Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.06 96.60 90.21 97.67 69.64 93.62 98.44 91.26


Total test records in report: 1603
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html
T1523 /workspace/coverage/cover_reg_top/16.i2c_intr_test.4140637723 Jun 06 02:42:12 PM PDT 24 Jun 06 02:42:15 PM PDT 24 41162470 ps
T93 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2999982734 Jun 06 02:41:28 PM PDT 24 Jun 06 02:41:30 PM PDT 24 74576845 ps
T1524 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3408994706 Jun 06 02:41:41 PM PDT 24 Jun 06 02:41:45 PM PDT 24 66952349 ps
T1525 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3421324189 Jun 06 02:41:44 PM PDT 24 Jun 06 02:41:48 PM PDT 24 104990006 ps
T1526 /workspace/coverage/cover_reg_top/42.i2c_intr_test.381664981 Jun 06 02:41:53 PM PDT 24 Jun 06 02:41:58 PM PDT 24 42404214 ps
T1527 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1421307743 Jun 06 02:41:26 PM PDT 24 Jun 06 02:41:30 PM PDT 24 865648725 ps
T94 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1825654261 Jun 06 02:41:28 PM PDT 24 Jun 06 02:41:31 PM PDT 24 27603832 ps
T1528 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2826076464 Jun 06 02:41:51 PM PDT 24 Jun 06 02:41:56 PM PDT 24 15622669 ps
T95 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1077535675 Jun 06 02:41:42 PM PDT 24 Jun 06 02:41:45 PM PDT 24 65955389 ps
T96 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3521116333 Jun 06 02:41:46 PM PDT 24 Jun 06 02:41:50 PM PDT 24 207739131 ps
T1529 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2664578051 Jun 06 02:41:30 PM PDT 24 Jun 06 02:41:34 PM PDT 24 83988896 ps
T1530 /workspace/coverage/cover_reg_top/19.i2c_intr_test.4010355095 Jun 06 02:41:48 PM PDT 24 Jun 06 02:41:52 PM PDT 24 38978539 ps
T1531 /workspace/coverage/cover_reg_top/45.i2c_intr_test.2638271337 Jun 06 02:41:55 PM PDT 24 Jun 06 02:42:00 PM PDT 24 46342054 ps
T97 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3787667865 Jun 06 02:41:29 PM PDT 24 Jun 06 02:41:32 PM PDT 24 361224503 ps
T183 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2613147436 Jun 06 02:41:48 PM PDT 24 Jun 06 02:41:55 PM PDT 24 315399275 ps
T1532 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2617622437 Jun 06 02:41:49 PM PDT 24 Jun 06 02:41:54 PM PDT 24 35010241 ps
T1533 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.109870540 Jun 06 02:41:28 PM PDT 24 Jun 06 02:41:30 PM PDT 24 83836063 ps
T138 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2182004822 Jun 06 02:41:31 PM PDT 24 Jun 06 02:41:34 PM PDT 24 29382246 ps
T1534 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1723110480 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:36 PM PDT 24 67990782 ps
T193 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3724358308 Jun 06 02:41:44 PM PDT 24 Jun 06 02:41:47 PM PDT 24 63894460 ps
T1535 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3108850256 Jun 06 02:41:43 PM PDT 24 Jun 06 02:41:47 PM PDT 24 30436494 ps
T1536 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.809655711 Jun 06 02:41:51 PM PDT 24 Jun 06 02:41:57 PM PDT 24 252908728 ps
T1537 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2583940135 Jun 06 02:41:50 PM PDT 24 Jun 06 02:41:54 PM PDT 24 28920608 ps
T1538 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1383760474 Jun 06 02:41:31 PM PDT 24 Jun 06 02:41:34 PM PDT 24 239943891 ps
T187 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3228847618 Jun 06 02:41:40 PM PDT 24 Jun 06 02:41:43 PM PDT 24 150811712 ps
T1539 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3905903489 Jun 06 02:41:34 PM PDT 24 Jun 06 02:41:37 PM PDT 24 120431322 ps
T1540 /workspace/coverage/cover_reg_top/34.i2c_intr_test.2960875312 Jun 06 02:41:59 PM PDT 24 Jun 06 02:42:03 PM PDT 24 37309397 ps
T1541 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3397076911 Jun 06 02:41:49 PM PDT 24 Jun 06 02:41:54 PM PDT 24 25046007 ps
T1542 /workspace/coverage/cover_reg_top/41.i2c_intr_test.956124539 Jun 06 02:41:48 PM PDT 24 Jun 06 02:41:52 PM PDT 24 51449950 ps
T188 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2481572130 Jun 06 02:41:27 PM PDT 24 Jun 06 02:41:31 PM PDT 24 251034280 ps
T1543 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.471360317 Jun 06 02:41:51 PM PDT 24 Jun 06 02:41:56 PM PDT 24 30080429 ps
T196 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3077082880 Jun 06 02:41:33 PM PDT 24 Jun 06 02:41:41 PM PDT 24 874177206 ps
T1544 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1093559683 Jun 06 02:41:42 PM PDT 24 Jun 06 02:41:45 PM PDT 24 105292340 ps
T1545 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3874738117 Jun 06 02:42:00 PM PDT 24 Jun 06 02:42:03 PM PDT 24 50989119 ps
T194 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.321075902 Jun 06 02:41:33 PM PDT 24 Jun 06 02:41:36 PM PDT 24 26856907 ps
T1546 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2737209428 Jun 06 02:41:31 PM PDT 24 Jun 06 02:41:36 PM PDT 24 806695470 ps
T1547 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.90747275 Jun 06 02:41:33 PM PDT 24 Jun 06 02:41:38 PM PDT 24 460061467 ps
T195 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3257095507 Jun 06 02:41:45 PM PDT 24 Jun 06 02:41:49 PM PDT 24 27997739 ps
T179 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3122823755 Jun 06 02:41:40 PM PDT 24 Jun 06 02:41:43 PM PDT 24 71570268 ps
T1548 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3214381995 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:36 PM PDT 24 133705504 ps
T200 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2279240954 Jun 06 02:41:30 PM PDT 24 Jun 06 02:41:33 PM PDT 24 16593545 ps
T1549 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1411528889 Jun 06 02:41:47 PM PDT 24 Jun 06 02:41:52 PM PDT 24 16820579 ps
T1550 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3331979484 Jun 06 02:41:39 PM PDT 24 Jun 06 02:41:41 PM PDT 24 81148941 ps
T1551 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1267648592 Jun 06 02:41:40 PM PDT 24 Jun 06 02:41:43 PM PDT 24 211818165 ps
T1552 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1528250816 Jun 06 02:41:28 PM PDT 24 Jun 06 02:41:37 PM PDT 24 23257302 ps
T1553 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3557001573 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:36 PM PDT 24 20062335 ps
T1554 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.437309628 Jun 06 02:41:29 PM PDT 24 Jun 06 02:41:32 PM PDT 24 65688185 ps
T1555 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.340174858 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:36 PM PDT 24 46857565 ps
T1556 /workspace/coverage/cover_reg_top/24.i2c_intr_test.3548712404 Jun 06 02:41:45 PM PDT 24 Jun 06 02:41:49 PM PDT 24 57403910 ps
T1557 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3033336855 Jun 06 02:41:30 PM PDT 24 Jun 06 02:41:34 PM PDT 24 81055331 ps
T1558 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1799559793 Jun 06 02:41:49 PM PDT 24 Jun 06 02:41:53 PM PDT 24 196901482 ps
T180 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2484797741 Jun 06 02:41:48 PM PDT 24 Jun 06 02:41:55 PM PDT 24 771368822 ps
T1559 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2605186018 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:35 PM PDT 24 118928582 ps
T1560 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1530575674 Jun 06 02:41:44 PM PDT 24 Jun 06 02:41:46 PM PDT 24 50409532 ps
T1561 /workspace/coverage/cover_reg_top/36.i2c_intr_test.3187720279 Jun 06 02:41:48 PM PDT 24 Jun 06 02:41:53 PM PDT 24 16280230 ps
T186 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2704716428 Jun 06 02:41:31 PM PDT 24 Jun 06 02:41:35 PM PDT 24 480400827 ps
T197 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3301135500 Jun 06 02:42:09 PM PDT 24 Jun 06 02:42:13 PM PDT 24 53683446 ps
T1562 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1028749249 Jun 06 02:41:40 PM PDT 24 Jun 06 02:41:42 PM PDT 24 24575111 ps
T1563 /workspace/coverage/cover_reg_top/49.i2c_intr_test.1887288197 Jun 06 02:41:57 PM PDT 24 Jun 06 02:42:01 PM PDT 24 48397351 ps
T1564 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.762960149 Jun 06 02:41:40 PM PDT 24 Jun 06 02:41:43 PM PDT 24 113588958 ps
T1565 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.707687601 Jun 06 02:41:50 PM PDT 24 Jun 06 02:41:56 PM PDT 24 127729896 ps
T1566 /workspace/coverage/cover_reg_top/27.i2c_intr_test.1011020296 Jun 06 02:41:49 PM PDT 24 Jun 06 02:41:53 PM PDT 24 37024674 ps
T1567 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1422390946 Jun 06 02:41:51 PM PDT 24 Jun 06 02:41:57 PM PDT 24 59504326 ps
T1568 /workspace/coverage/cover_reg_top/23.i2c_intr_test.2899550281 Jun 06 02:41:57 PM PDT 24 Jun 06 02:42:02 PM PDT 24 36365955 ps
T1569 /workspace/coverage/cover_reg_top/11.i2c_intr_test.2854047409 Jun 06 02:41:40 PM PDT 24 Jun 06 02:41:43 PM PDT 24 26012678 ps
T1570 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2597873820 Jun 06 02:41:42 PM PDT 24 Jun 06 02:41:45 PM PDT 24 86766714 ps
T1571 /workspace/coverage/cover_reg_top/30.i2c_intr_test.816456419 Jun 06 02:41:48 PM PDT 24 Jun 06 02:41:52 PM PDT 24 41111836 ps
T1572 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2687713095 Jun 06 02:41:31 PM PDT 24 Jun 06 02:41:34 PM PDT 24 55395976 ps
T1573 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3938048312 Jun 06 02:41:50 PM PDT 24 Jun 06 02:41:55 PM PDT 24 173915006 ps
T1574 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.804980718 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:36 PM PDT 24 52537324 ps
T1575 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4121201638 Jun 06 02:41:30 PM PDT 24 Jun 06 02:41:33 PM PDT 24 54213372 ps
T1576 /workspace/coverage/cover_reg_top/2.i2c_intr_test.2851075989 Jun 06 02:41:27 PM PDT 24 Jun 06 02:41:29 PM PDT 24 32112238 ps
T1577 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.804104848 Jun 06 02:41:41 PM PDT 24 Jun 06 02:41:44 PM PDT 24 359413894 ps
T1578 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.4108428829 Jun 06 02:41:29 PM PDT 24 Jun 06 02:41:38 PM PDT 24 2500293764 ps
T1579 /workspace/coverage/cover_reg_top/14.i2c_intr_test.1623695643 Jun 06 02:41:45 PM PDT 24 Jun 06 02:41:49 PM PDT 24 40398885 ps
T1580 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3606504443 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:35 PM PDT 24 53406631 ps
T1581 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1567886100 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:36 PM PDT 24 55331155 ps
T1582 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3536783254 Jun 06 02:41:28 PM PDT 24 Jun 06 02:41:31 PM PDT 24 73246726 ps
T1583 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1914795569 Jun 06 02:41:45 PM PDT 24 Jun 06 02:41:49 PM PDT 24 102438500 ps
T1584 /workspace/coverage/cover_reg_top/10.i2c_intr_test.2926398076 Jun 06 02:41:49 PM PDT 24 Jun 06 02:41:54 PM PDT 24 45922523 ps
T198 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2672543811 Jun 06 02:41:46 PM PDT 24 Jun 06 02:41:51 PM PDT 24 52512511 ps
T1585 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3699420866 Jun 06 02:41:31 PM PDT 24 Jun 06 02:41:35 PM PDT 24 19282304 ps
T199 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2038084609 Jun 06 02:41:34 PM PDT 24 Jun 06 02:41:37 PM PDT 24 24903551 ps
T1586 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2088658563 Jun 06 02:41:47 PM PDT 24 Jun 06 02:41:52 PM PDT 24 34772784 ps
T1587 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1033615967 Jun 06 02:41:50 PM PDT 24 Jun 06 02:41:55 PM PDT 24 57949916 ps
T1588 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.145058708 Jun 06 02:41:43 PM PDT 24 Jun 06 02:41:47 PM PDT 24 71831570 ps
T1589 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1593770191 Jun 06 02:41:29 PM PDT 24 Jun 06 02:41:37 PM PDT 24 881654664 ps
T1590 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1423405305 Jun 06 02:41:51 PM PDT 24 Jun 06 02:41:56 PM PDT 24 44882310 ps
T1591 /workspace/coverage/cover_reg_top/38.i2c_intr_test.579727507 Jun 06 02:41:51 PM PDT 24 Jun 06 02:41:56 PM PDT 24 20225928 ps
T1592 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3299845757 Jun 06 02:41:45 PM PDT 24 Jun 06 02:41:49 PM PDT 24 37460883 ps
T1593 /workspace/coverage/cover_reg_top/7.i2c_intr_test.3230208993 Jun 06 02:41:33 PM PDT 24 Jun 06 02:41:36 PM PDT 24 19311008 ps
T1594 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1767146027 Jun 06 02:41:30 PM PDT 24 Jun 06 02:41:33 PM PDT 24 59894346 ps
T1595 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3308567714 Jun 06 02:41:50 PM PDT 24 Jun 06 02:41:56 PM PDT 24 53687724 ps
T1596 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2841205953 Jun 06 02:41:27 PM PDT 24 Jun 06 02:41:32 PM PDT 24 535423062 ps
T1597 /workspace/coverage/cover_reg_top/6.i2c_intr_test.3218429850 Jun 06 02:41:28 PM PDT 24 Jun 06 02:41:30 PM PDT 24 40784465 ps
T1598 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.4133899853 Jun 06 02:41:27 PM PDT 24 Jun 06 02:41:29 PM PDT 24 87332959 ps
T1599 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2172868035 Jun 06 02:41:29 PM PDT 24 Jun 06 02:41:33 PM PDT 24 31425587 ps
T184 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.824435846 Jun 06 02:41:44 PM PDT 24 Jun 06 02:41:49 PM PDT 24 316953124 ps
T234 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2215324614 Jun 06 02:41:43 PM PDT 24 Jun 06 02:41:46 PM PDT 24 253709299 ps
T1600 /workspace/coverage/cover_reg_top/21.i2c_intr_test.1150630259 Jun 06 02:41:49 PM PDT 24 Jun 06 02:41:54 PM PDT 24 55125151 ps
T1601 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2887900296 Jun 06 02:41:20 PM PDT 24 Jun 06 02:41:24 PM PDT 24 263435015 ps
T1602 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2628696226 Jun 06 02:41:40 PM PDT 24 Jun 06 02:41:42 PM PDT 24 49589606 ps
T1603 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1516620530 Jun 06 02:41:32 PM PDT 24 Jun 06 02:41:36 PM PDT 24 26341938 ps

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3716802453
Short name T2
Test name
Test status
Simulation time 1586941085 ps
CPU time 17.69 seconds
Started Jun 06 02:49:15 PM PDT 24
Finished Jun 06 02:49:35 PM PDT 24
Peak memory 213240 kb
Host smart-a9c73417-5d94-4f24-898d-0095ed24cd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716802453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3716802453
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.1714351118
Short name T8
Test name
Test status
Simulation time 9138491408 ps
CPU time 11.23 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 02:49:16 PM PDT 24
Peak memory 213572 kb
Host smart-af31748c-ef05-425a-baef-c37bb97f269b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714351118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.1714351118
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1709957510
Short name T46
Test name
Test status
Simulation time 130670270948 ps
CPU time 1429.47 seconds
Started Jun 06 02:56:11 PM PDT 24
Finished Jun 06 03:20:04 PM PDT 24
Peak memory 1958352 kb
Host smart-f4ae3ada-0d3f-4741-ac4d-d30a1b1713e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709957510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1709957510
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1936461824
Short name T11
Test name
Test status
Simulation time 6379088676 ps
CPU time 4.46 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:22 PM PDT 24
Peak memory 213320 kb
Host smart-04ec0560-880e-4392-a0eb-7aaf66fe9e4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936461824 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1936461824
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.2860137116
Short name T88
Test name
Test status
Simulation time 577796477 ps
CPU time 2.49 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203928 kb
Host smart-fa4b4c16-4d67-4baf-b207-9144233f88ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860137116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.2860137116
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.1889738789
Short name T10
Test name
Test status
Simulation time 598917719 ps
CPU time 2.96 seconds
Started Jun 06 02:57:45 PM PDT 24
Finished Jun 06 02:57:53 PM PDT 24
Peak memory 213316 kb
Host smart-00b92c6a-2ec0-4879-8f06-3ee1bda93b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889738789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.1889738789
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_override.1858183071
Short name T125
Test name
Test status
Simulation time 45373020 ps
CPU time 0.63 seconds
Started Jun 06 02:57:21 PM PDT 24
Finished Jun 06 02:57:25 PM PDT 24
Peak memory 204696 kb
Host smart-2c790244-ea6d-4ef3-941e-1d7c95a0c5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858183071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1858183071
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.2567330775
Short name T86
Test name
Test status
Simulation time 10135806686 ps
CPU time 46.15 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:57:09 PM PDT 24
Peak memory 386188 kb
Host smart-00ebb0ec-4a78-4de1-8636-e0ab50cc572f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567330775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.2567330775
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.4228832541
Short name T177
Test name
Test status
Simulation time 49315183 ps
CPU time 2.31 seconds
Started Jun 06 02:41:41 PM PDT 24
Finished Jun 06 02:41:45 PM PDT 24
Peak memory 204056 kb
Host smart-6621a21f-7d96-4fd8-9819-a2edbd239241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228832541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.4228832541
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1790036536
Short name T41
Test name
Test status
Simulation time 3333899739 ps
CPU time 7.16 seconds
Started Jun 06 02:57:26 PM PDT 24
Finished Jun 06 02:57:39 PM PDT 24
Peak memory 205092 kb
Host smart-dec0813c-6181-4edf-a369-8c129e120c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790036536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1790036536
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3923387825
Short name T119
Test name
Test status
Simulation time 17226596 ps
CPU time 0.62 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:18 PM PDT 24
Peak memory 204760 kb
Host smart-1ee149c6-f62d-4170-9d29-80881f9a2f8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923387825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3923387825
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.3374794710
Short name T48
Test name
Test status
Simulation time 91568820098 ps
CPU time 388.69 seconds
Started Jun 06 02:55:42 PM PDT 24
Finished Jun 06 03:02:15 PM PDT 24
Peak memory 1264628 kb
Host smart-c47b873a-e533-4b00-bd7f-147196aea125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374794710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.3374794710
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2742347575
Short name T18
Test name
Test status
Simulation time 1538549577 ps
CPU time 20.49 seconds
Started Jun 06 02:55:20 PM PDT 24
Finished Jun 06 02:55:45 PM PDT 24
Peak memory 205052 kb
Host smart-0cc90840-2389-4e9e-9b1f-d20ae9e51240
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742347575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2742347575
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3413272011
Short name T139
Test name
Test status
Simulation time 19683395 ps
CPU time 0.75 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203716 kb
Host smart-41bb613a-3f21-477a-82b4-6304e9aad266
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413272011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3413272011
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1602719339
Short name T31
Test name
Test status
Simulation time 49873874262 ps
CPU time 1479.52 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 03:17:49 PM PDT 24
Peak memory 2305400 kb
Host smart-75e4a20f-dcfa-4e01-b475-6d1e368c1c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602719339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1602719339
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.116577280
Short name T16
Test name
Test status
Simulation time 24882257381 ps
CPU time 97.04 seconds
Started Jun 06 02:50:42 PM PDT 24
Finished Jun 06 02:52:21 PM PDT 24
Peak memory 1377108 kb
Host smart-cce1c6f4-6dae-4467-b8d6-aa442642b029
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116577280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.116577280
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2213343211
Short name T64
Test name
Test status
Simulation time 6568074965 ps
CPU time 8.18 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:54:20 PM PDT 24
Peak memory 215560 kb
Host smart-e49e59fe-941c-4252-8dba-3c6f719a64ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213343211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2213343211
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1629236725
Short name T162
Test name
Test status
Simulation time 64597901 ps
CPU time 0.92 seconds
Started Jun 06 02:48:54 PM PDT 24
Finished Jun 06 02:48:57 PM PDT 24
Peak memory 222968 kb
Host smart-b89fd4bb-67d3-42d8-ada8-c0d048d3668d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629236725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1629236725
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3951758996
Short name T52
Test name
Test status
Simulation time 176605191 ps
CPU time 0.88 seconds
Started Jun 06 02:51:15 PM PDT 24
Finished Jun 06 02:51:20 PM PDT 24
Peak memory 204560 kb
Host smart-28df8464-ca72-4a6a-b5c5-1d1c0c8c97b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951758996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3951758996
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.325481275
Short name T102
Test name
Test status
Simulation time 42709151311 ps
CPU time 1801.48 seconds
Started Jun 06 02:55:37 PM PDT 24
Finished Jun 06 03:25:44 PM PDT 24
Peak memory 4065508 kb
Host smart-12e7b90b-4ed0-4fb4-bf70-6383c3d1029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325481275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.325481275
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3643567396
Short name T250
Test name
Test status
Simulation time 6360383367 ps
CPU time 516.93 seconds
Started Jun 06 02:51:41 PM PDT 24
Finished Jun 06 03:00:20 PM PDT 24
Peak memory 1035276 kb
Host smart-e45282b0-a748-4bbb-bd33-da034841c7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643567396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3643567396
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.4012674832
Short name T67
Test name
Test status
Simulation time 48416463951 ps
CPU time 630.21 seconds
Started Jun 06 02:55:02 PM PDT 24
Finished Jun 06 03:05:38 PM PDT 24
Peak memory 1634880 kb
Host smart-610f71fa-5b0c-4aaa-9976-b98bd0bc918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012674832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.4012674832
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.1253549111
Short name T217
Test name
Test status
Simulation time 413670167 ps
CPU time 1.02 seconds
Started Jun 06 02:48:44 PM PDT 24
Finished Jun 06 02:48:46 PM PDT 24
Peak memory 204780 kb
Host smart-875d25a0-b0eb-4252-8fe1-429f696d50fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253549111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.1253549111
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1414921973
Short name T240
Test name
Test status
Simulation time 19823984084 ps
CPU time 1642.09 seconds
Started Jun 06 02:50:40 PM PDT 24
Finished Jun 06 03:18:04 PM PDT 24
Peak memory 4051704 kb
Host smart-8c823132-de5e-4122-bb17-cc77825c6b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414921973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1414921973
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.560849198
Short name T148
Test name
Test status
Simulation time 10216694276 ps
CPU time 34.32 seconds
Started Jun 06 02:52:02 PM PDT 24
Finished Jun 06 02:52:40 PM PDT 24
Peak memory 378016 kb
Host smart-3dd175a2-6b90-4401-b01c-2c775c929b91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560849198 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.560849198
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2084382040
Short name T211
Test name
Test status
Simulation time 123924027 ps
CPU time 6.78 seconds
Started Jun 06 02:51:17 PM PDT 24
Finished Jun 06 02:51:28 PM PDT 24
Peak memory 205036 kb
Host smart-933f2df0-2357-4852-b9bd-ed200462efb0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084382040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2084382040
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.453386962
Short name T109
Test name
Test status
Simulation time 16312158015 ps
CPU time 42.42 seconds
Started Jun 06 02:54:56 PM PDT 24
Finished Jun 06 02:55:45 PM PDT 24
Peak memory 383688 kb
Host smart-0f4de4d1-d789-4bed-bd63-8ef5b31fa149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453386962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.453386962
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.510019765
Short name T225
Test name
Test status
Simulation time 2995615031 ps
CPU time 2.68 seconds
Started Jun 06 02:48:54 PM PDT 24
Finished Jun 06 02:48:58 PM PDT 24
Peak memory 205132 kb
Host smart-505532ae-813f-4335-8d08-86fab42a208f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510019765 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.510019765
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.2616839358
Short name T213
Test name
Test status
Simulation time 83336556333 ps
CPU time 1483.74 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 03:15:56 PM PDT 24
Peak memory 4538444 kb
Host smart-3b06a229-b15d-49cd-8c7a-2d6bd6ae2d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616839358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.2616839358
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.179191881
Short name T260
Test name
Test status
Simulation time 4942044994 ps
CPU time 4.54 seconds
Started Jun 06 02:51:06 PM PDT 24
Finished Jun 06 02:51:14 PM PDT 24
Peak memory 205204 kb
Host smart-3fb2de96-64f9-4739-b068-f3017ec9924f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179191881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_intr_smoke.179191881
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.2538786640
Short name T103
Test name
Test status
Simulation time 13667402634 ps
CPU time 733.29 seconds
Started Jun 06 02:53:32 PM PDT 24
Finished Jun 06 03:05:48 PM PDT 24
Peak memory 3002064 kb
Host smart-842edab5-2305-4a82-a10b-ce8dad2fe2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538786640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2538786640
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3123380780
Short name T1086
Test name
Test status
Simulation time 2510138326 ps
CPU time 2.6 seconds
Started Jun 06 02:54:06 PM PDT 24
Finished Jun 06 02:54:12 PM PDT 24
Peak memory 205144 kb
Host smart-053408b2-a1b4-4ca1-a3bd-560c9670d2f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123380780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3123380780
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1690626242
Short name T59
Test name
Test status
Simulation time 2577469056 ps
CPU time 44.55 seconds
Started Jun 06 02:51:29 PM PDT 24
Finished Jun 06 02:52:15 PM PDT 24
Peak memory 448176 kb
Host smart-d8dbc16e-0fd2-4241-8087-70c1a91b3992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690626242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1690626242
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2481572130
Short name T188
Test name
Test status
Simulation time 251034280 ps
CPU time 2.34 seconds
Started Jun 06 02:41:27 PM PDT 24
Finished Jun 06 02:41:31 PM PDT 24
Peak memory 204008 kb
Host smart-d5044028-4fd7-41db-ad4d-f18a74ec4c9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481572130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2481572130
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.147841618
Short name T1225
Test name
Test status
Simulation time 10443467144 ps
CPU time 20.18 seconds
Started Jun 06 02:53:01 PM PDT 24
Finished Jun 06 02:53:23 PM PDT 24
Peak memory 342952 kb
Host smart-e6441b13-8c45-449d-bd2d-479285cf1353
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147841618 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_tx.147841618
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.2125217421
Short name T1507
Test name
Test status
Simulation time 19569824 ps
CPU time 0.66 seconds
Started Jun 06 02:41:46 PM PDT 24
Finished Jun 06 02:41:51 PM PDT 24
Peak memory 203640 kb
Host smart-f64652d1-ef10-430a-94fa-6a77df42f77c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125217421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.2125217421
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.3623180969
Short name T752
Test name
Test status
Simulation time 1211986493 ps
CPU time 2.29 seconds
Started Jun 06 02:51:28 PM PDT 24
Finished Jun 06 02:51:32 PM PDT 24
Peak memory 205124 kb
Host smart-176e1591-2413-4da2-b188-4611fc187fd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623180969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.3623180969
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.1672651864
Short name T691
Test name
Test status
Simulation time 4337596188 ps
CPU time 5.1 seconds
Started Jun 06 02:51:42 PM PDT 24
Finished Jun 06 02:51:49 PM PDT 24
Peak memory 206844 kb
Host smart-1b9bc1f2-4566-414e-aeb8-d90698ed7918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672651864 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.1672651864
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2375311413
Short name T243
Test name
Test status
Simulation time 17888122727 ps
CPU time 1710.63 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 03:20:31 PM PDT 24
Peak memory 1831800 kb
Host smart-2e141ca0-4e2d-440f-8999-8a32c8af2291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375311413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2375311413
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.1122985643
Short name T99
Test name
Test status
Simulation time 15168634288 ps
CPU time 892.75 seconds
Started Jun 06 02:52:18 PM PDT 24
Finished Jun 06 03:07:14 PM PDT 24
Peak memory 3171504 kb
Host smart-fb656662-6229-4143-a904-d5462d10f1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122985643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.1122985643
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3178624135
Short name T220
Test name
Test status
Simulation time 12021100785 ps
CPU time 35.93 seconds
Started Jun 06 02:49:17 PM PDT 24
Finished Jun 06 02:49:55 PM PDT 24
Peak memory 424292 kb
Host smart-4af00fb8-9df1-45b1-b663-7791a7c62909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178624135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3178624135
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1379374432
Short name T230
Test name
Test status
Simulation time 3477285481 ps
CPU time 33.95 seconds
Started Jun 06 02:53:01 PM PDT 24
Finished Jun 06 02:53:38 PM PDT 24
Peak memory 230348 kb
Host smart-9914256a-ee8c-4bf6-a057-ee4a36c27724
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379374432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1379374432
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2733710792
Short name T26
Test name
Test status
Simulation time 15500466695 ps
CPU time 184.7 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:55:37 PM PDT 24
Peak memory 2251044 kb
Host smart-d0b565a2-cc5d-4bc5-9d8c-28f25337bb07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733710792 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2733710792
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1134940506
Short name T174
Test name
Test status
Simulation time 259809218 ps
CPU time 2.5 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 203988 kb
Host smart-3d2b5c44-6773-4e82-9350-38b045bffc2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134940506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1134940506
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2704716428
Short name T186
Test name
Test status
Simulation time 480400827 ps
CPU time 2.28 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 204004 kb
Host smart-c03924ed-812b-49ec-84df-d997af711d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704716428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2704716428
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2791323428
Short name T182
Test name
Test status
Simulation time 203959916 ps
CPU time 1.37 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:32 PM PDT 24
Peak memory 203816 kb
Host smart-68416d53-518f-440b-91bf-0169fe22efdb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791323428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2791323428
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.3033336855
Short name T1557
Test name
Test status
Simulation time 81055331 ps
CPU time 1.44 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:34 PM PDT 24
Peak memory 203940 kb
Host smart-82626ed0-e13d-411c-876c-5821d5653fa7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033336855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.3033336855
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.2841205953
Short name T1596
Test name
Test status
Simulation time 535423062 ps
CPU time 3.35 seconds
Started Jun 06 02:41:27 PM PDT 24
Finished Jun 06 02:41:32 PM PDT 24
Peak memory 203988 kb
Host smart-6f6fe822-8913-472f-9e5e-9cea151834fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841205953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.2841205953
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2038084609
Short name T199
Test name
Test status
Simulation time 24903551 ps
CPU time 0.75 seconds
Started Jun 06 02:41:34 PM PDT 24
Finished Jun 06 02:41:37 PM PDT 24
Peak memory 203720 kb
Host smart-0e90c98d-8d18-4475-a0b1-a76510882836
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038084609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2038084609
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.1825654261
Short name T94
Test name
Test status
Simulation time 27603832 ps
CPU time 0.82 seconds
Started Jun 06 02:41:28 PM PDT 24
Finished Jun 06 02:41:31 PM PDT 24
Peak memory 203776 kb
Host smart-1ce53181-8083-426f-acc0-f3fc0c0430e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825654261 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.1825654261
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2887900296
Short name T1601
Test name
Test status
Simulation time 263435015 ps
CPU time 0.81 seconds
Started Jun 06 02:41:20 PM PDT 24
Finished Jun 06 02:41:24 PM PDT 24
Peak memory 203748 kb
Host smart-f1c75bbe-f34e-4548-9da0-2c853b3dc439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887900296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2887900296
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.4247819683
Short name T1500
Test name
Test status
Simulation time 14583386 ps
CPU time 0.67 seconds
Started Jun 06 02:41:16 PM PDT 24
Finished Jun 06 02:41:21 PM PDT 24
Peak memory 203688 kb
Host smart-d21e6550-b724-46ed-9b5c-6377b9501bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247819683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.4247819683
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2605186018
Short name T1559
Test name
Test status
Simulation time 118928582 ps
CPU time 0.84 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203696 kb
Host smart-3537bb96-c552-4d8b-b954-d471fc73817f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605186018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2605186018
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1887079772
Short name T1519
Test name
Test status
Simulation time 116161279 ps
CPU time 1.41 seconds
Started Jun 06 02:41:28 PM PDT 24
Finished Jun 06 02:41:31 PM PDT 24
Peak memory 204044 kb
Host smart-70efbbb7-888a-4ff8-9ab8-d52d5d89b1ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887079772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1887079772
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3743394656
Short name T1510
Test name
Test status
Simulation time 64402712 ps
CPU time 1.42 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:34 PM PDT 24
Peak memory 204024 kb
Host smart-df993d58-5068-4799-ab6f-eb9823e1f82f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743394656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3743394656
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.4108428829
Short name T1578
Test name
Test status
Simulation time 2500293764 ps
CPU time 6.6 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:38 PM PDT 24
Peak memory 203968 kb
Host smart-20774a0e-b548-469b-a795-f7f89ece11c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108428829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.4108428829
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2999982734
Short name T93
Test name
Test status
Simulation time 74576845 ps
CPU time 0.76 seconds
Started Jun 06 02:41:28 PM PDT 24
Finished Jun 06 02:41:30 PM PDT 24
Peak memory 203716 kb
Host smart-ba59349d-027e-4a11-9ff2-6a8599ef25c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999982734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2999982734
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.340174858
Short name T1555
Test name
Test status
Simulation time 46857565 ps
CPU time 0.81 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203784 kb
Host smart-91ef4e79-5905-4f83-a1a8-e6c53cba4a27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340174858 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.340174858
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3699420866
Short name T1585
Test name
Test status
Simulation time 19282304 ps
CPU time 0.68 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203660 kb
Host smart-c54620c0-6ca8-4212-bd7f-0a7dbe8f7b05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699420866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3699420866
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1528250816
Short name T1552
Test name
Test status
Simulation time 23257302 ps
CPU time 0.88 seconds
Started Jun 06 02:41:28 PM PDT 24
Finished Jun 06 02:41:37 PM PDT 24
Peak memory 203708 kb
Host smart-6a864454-e93d-4ffb-bdb6-8e5422e5b0fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528250816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1528250816
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.3787667865
Short name T97
Test name
Test status
Simulation time 361224503 ps
CPU time 1.27 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:32 PM PDT 24
Peak memory 203912 kb
Host smart-35c4d08c-bc32-4522-b462-304a93d0660a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787667865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.3787667865
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2664578051
Short name T1529
Test name
Test status
Simulation time 83988896 ps
CPU time 1.51 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:34 PM PDT 24
Peak memory 203972 kb
Host smart-1ef2aed6-4a1b-49b4-8e88-ac9f40ecf518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664578051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2664578051
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.3481845771
Short name T92
Test name
Test status
Simulation time 86389395 ps
CPU time 0.97 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:43 PM PDT 24
Peak memory 203796 kb
Host smart-1918dccb-50df-49e5-8cd8-614b1107fba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481845771 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.3481845771
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1567766893
Short name T192
Test name
Test status
Simulation time 18917393 ps
CPU time 0.69 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:47 PM PDT 24
Peak memory 203732 kb
Host smart-989de572-6829-4794-9fe6-84faeb4a8066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567766893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1567766893
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.2926398076
Short name T1584
Test name
Test status
Simulation time 45922523 ps
CPU time 0.7 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:41:54 PM PDT 24
Peak memory 203628 kb
Host smart-b9e73eab-8d30-4c10-b328-d515ac641720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926398076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.2926398076
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3465649191
Short name T1518
Test name
Test status
Simulation time 25913279 ps
CPU time 0.89 seconds
Started Jun 06 02:41:38 PM PDT 24
Finished Jun 06 02:41:40 PM PDT 24
Peak memory 203636 kb
Host smart-d72d7702-b1f9-42ae-945b-92b067de0b3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465649191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3465649191
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.2597873820
Short name T1570
Test name
Test status
Simulation time 86766714 ps
CPU time 1.78 seconds
Started Jun 06 02:41:42 PM PDT 24
Finished Jun 06 02:41:45 PM PDT 24
Peak memory 203948 kb
Host smart-1ab7801d-67b0-4dfa-a2d7-161843c57027
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597873820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.2597873820
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.824435846
Short name T184
Test name
Test status
Simulation time 316953124 ps
CPU time 2.21 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 203956 kb
Host smart-c260f09a-c9f1-4e5d-acd6-4cb6f6081815
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824435846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.824435846
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3576350172
Short name T140
Test name
Test status
Simulation time 68262131 ps
CPU time 0.97 seconds
Started Jun 06 02:41:43 PM PDT 24
Finished Jun 06 02:41:46 PM PDT 24
Peak memory 203756 kb
Host smart-774a883b-c0fa-4157-afc7-2a3c55557bc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576350172 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3576350172
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3077019492
Short name T191
Test name
Test status
Simulation time 32261366 ps
CPU time 0.71 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 203704 kb
Host smart-2bf07a06-f174-4553-821f-be914d3c0141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077019492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3077019492
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.2854047409
Short name T1569
Test name
Test status
Simulation time 26012678 ps
CPU time 0.72 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:43 PM PDT 24
Peak memory 203652 kb
Host smart-05294136-ede5-4231-94ce-de06ec252a72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854047409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.2854047409
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3733716678
Short name T1516
Test name
Test status
Simulation time 35238628 ps
CPU time 1.05 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:42 PM PDT 24
Peak memory 203796 kb
Host smart-2b59e074-ab9b-42b4-8fc7-d5b759018b14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733716678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3733716678
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.677723723
Short name T190
Test name
Test status
Simulation time 77848189 ps
CPU time 1.62 seconds
Started Jun 06 02:41:47 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 203944 kb
Host smart-12f09e5a-7b19-4ff4-a6ad-b50ea8fc01eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677723723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.677723723
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1028749249
Short name T1562
Test name
Test status
Simulation time 24575111 ps
CPU time 0.79 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:42 PM PDT 24
Peak memory 203740 kb
Host smart-b798dcac-915b-4815-854e-080bfef92181
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028749249 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1028749249
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3724358308
Short name T193
Test name
Test status
Simulation time 63894460 ps
CPU time 0.83 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:47 PM PDT 24
Peak memory 203732 kb
Host smart-9d230756-3e42-4ffb-ae1a-6f1a561eb09a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724358308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3724358308
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2462697722
Short name T1497
Test name
Test status
Simulation time 18019847 ps
CPU time 0.71 seconds
Started Jun 06 02:41:39 PM PDT 24
Finished Jun 06 02:41:40 PM PDT 24
Peak memory 203692 kb
Host smart-5d18b49e-320d-45bd-b756-c96e5285fba9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462697722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2462697722
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.272281171
Short name T205
Test name
Test status
Simulation time 88845746 ps
CPU time 0.82 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:42 PM PDT 24
Peak memory 203692 kb
Host smart-df0526ee-ec38-4aff-8ec0-45e598ab7577
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272281171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_ou
tstanding.272281171
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.707687601
Short name T1565
Test name
Test status
Simulation time 127729896 ps
CPU time 2.1 seconds
Started Jun 06 02:41:50 PM PDT 24
Finished Jun 06 02:41:56 PM PDT 24
Peak memory 204000 kb
Host smart-8be50bd4-3940-44d7-82e6-7df8f962c366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707687601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.707687601
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3299845757
Short name T1592
Test name
Test status
Simulation time 37460883 ps
CPU time 1.01 seconds
Started Jun 06 02:41:45 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 203776 kb
Host smart-c978e059-9701-43aa-9315-c3462e8c72ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299845757 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3299845757
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1914795569
Short name T1583
Test name
Test status
Simulation time 102438500 ps
CPU time 0.73 seconds
Started Jun 06 02:41:45 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 203720 kb
Host smart-83f5ed7d-8a4e-4ab7-9e39-a4b3b70e5d56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914795569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1914795569
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2076557992
Short name T1502
Test name
Test status
Simulation time 20895345 ps
CPU time 0.7 seconds
Started Jun 06 02:41:41 PM PDT 24
Finished Jun 06 02:41:44 PM PDT 24
Peak memory 203692 kb
Host smart-b7b0f292-1778-4039-aabb-fbc2e5160f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076557992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2076557992
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1496213067
Short name T202
Test name
Test status
Simulation time 501627289 ps
CPU time 1.24 seconds
Started Jun 06 02:41:52 PM PDT 24
Finished Jun 06 02:41:58 PM PDT 24
Peak memory 203912 kb
Host smart-974784f5-fe97-48ab-a0c9-8327f18da204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496213067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1496213067
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3408994706
Short name T1524
Test name
Test status
Simulation time 66952349 ps
CPU time 2.51 seconds
Started Jun 06 02:41:41 PM PDT 24
Finished Jun 06 02:41:45 PM PDT 24
Peak memory 204056 kb
Host smart-96268ba5-ba00-400c-9049-9e100adbf98f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408994706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3408994706
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.859014405
Short name T1513
Test name
Test status
Simulation time 25000852 ps
CPU time 0.83 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:43 PM PDT 24
Peak memory 203820 kb
Host smart-59013a10-85d8-444e-8847-8b181b71508c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859014405 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.859014405
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.1530575674
Short name T1560
Test name
Test status
Simulation time 50409532 ps
CPU time 0.73 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:46 PM PDT 24
Peak memory 203732 kb
Host smart-95b3391d-d1a1-4f74-b6cb-a467bb8c2c09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530575674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.1530575674
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.1623695643
Short name T1579
Test name
Test status
Simulation time 40398885 ps
CPU time 0.66 seconds
Started Jun 06 02:41:45 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 203652 kb
Host smart-667c5f0d-d097-4684-a77c-1ef703b2f444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623695643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.1623695643
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.471360317
Short name T1543
Test name
Test status
Simulation time 30080429 ps
CPU time 0.86 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:56 PM PDT 24
Peak memory 203680 kb
Host smart-0c60f224-b784-4e52-ac2e-518e5702dc3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471360317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_ou
tstanding.471360317
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3521116333
Short name T96
Test name
Test status
Simulation time 207739131 ps
CPU time 1.44 seconds
Started Jun 06 02:41:46 PM PDT 24
Finished Jun 06 02:41:50 PM PDT 24
Peak memory 204068 kb
Host smart-2d00cc81-3740-47de-a58b-5c6d34f1400d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521116333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3521116333
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.3406077782
Short name T173
Test name
Test status
Simulation time 1031690191 ps
CPU time 2.48 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 203952 kb
Host smart-b7cab29f-bbae-4bf6-8bd2-9e5234f4c318
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406077782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.3406077782
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3108850256
Short name T1535
Test name
Test status
Simulation time 30436494 ps
CPU time 1.31 seconds
Started Jun 06 02:41:43 PM PDT 24
Finished Jun 06 02:41:47 PM PDT 24
Peak memory 212200 kb
Host smart-741ee3ac-c009-4569-a4b7-0e279009cd5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108850256 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3108850256
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3257095507
Short name T195
Test name
Test status
Simulation time 27997739 ps
CPU time 0.77 seconds
Started Jun 06 02:41:45 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 203720 kb
Host smart-8780675e-6d2f-493a-9ba9-cb4ecce4b8ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257095507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3257095507
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.759610941
Short name T1512
Test name
Test status
Simulation time 27361571 ps
CPU time 0.7 seconds
Started Jun 06 02:41:39 PM PDT 24
Finished Jun 06 02:41:41 PM PDT 24
Peak memory 203624 kb
Host smart-e39ac44b-66fe-47d5-be58-a68fb52113f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759610941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.759610941
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1093559683
Short name T1544
Test name
Test status
Simulation time 105292340 ps
CPU time 1.23 seconds
Started Jun 06 02:41:42 PM PDT 24
Finished Jun 06 02:41:45 PM PDT 24
Peak memory 203940 kb
Host smart-4f95e1b0-ff8d-40d5-9e3b-01ab72b89f42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093559683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1093559683
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.3122823755
Short name T179
Test name
Test status
Simulation time 71570268 ps
CPU time 1.51 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:43 PM PDT 24
Peak memory 203992 kb
Host smart-fe944cb4-416c-4a9e-8968-9e0db36f5d73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122823755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.3122823755
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3331979484
Short name T1550
Test name
Test status
Simulation time 81148941 ps
CPU time 1.12 seconds
Started Jun 06 02:41:39 PM PDT 24
Finished Jun 06 02:41:41 PM PDT 24
Peak memory 203976 kb
Host smart-b9997874-444d-475a-9fb8-6359a11ee632
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331979484 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3331979484
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1422390946
Short name T1567
Test name
Test status
Simulation time 59504326 ps
CPU time 0.73 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:57 PM PDT 24
Peak memory 203676 kb
Host smart-7bb9fef3-5f2e-4fc6-af86-166c332f5fdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422390946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1422390946
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.4140637723
Short name T1523
Test name
Test status
Simulation time 41162470 ps
CPU time 0.69 seconds
Started Jun 06 02:42:12 PM PDT 24
Finished Jun 06 02:42:15 PM PDT 24
Peak memory 203612 kb
Host smart-16520e67-1cdc-4cf1-a640-4c0abe0a4e48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140637723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4140637723
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.396757868
Short name T90
Test name
Test status
Simulation time 463693931 ps
CPU time 1.18 seconds
Started Jun 06 02:41:41 PM PDT 24
Finished Jun 06 02:41:44 PM PDT 24
Peak memory 203964 kb
Host smart-7662013f-8778-4141-8d93-778467ec0632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396757868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_ou
tstanding.396757868
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1077535675
Short name T95
Test name
Test status
Simulation time 65955389 ps
CPU time 1.38 seconds
Started Jun 06 02:41:42 PM PDT 24
Finished Jun 06 02:41:45 PM PDT 24
Peak memory 204004 kb
Host smart-f6ff24e6-bb08-4a3c-a875-aec25f0dc0b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077535675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1077535675
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.2484797741
Short name T180
Test name
Test status
Simulation time 771368822 ps
CPU time 2.48 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:55 PM PDT 24
Peak memory 203972 kb
Host smart-ebebb28c-c863-47ed-b1ee-aa62371ae048
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484797741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.2484797741
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3421324189
Short name T1525
Test name
Test status
Simulation time 104990006 ps
CPU time 0.76 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:48 PM PDT 24
Peak memory 203780 kb
Host smart-7c60eda3-cb0d-48f8-8d0d-de84a2fbc852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421324189 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3421324189
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.4240205588
Short name T206
Test name
Test status
Simulation time 65843068 ps
CPU time 0.7 seconds
Started Jun 06 02:41:46 PM PDT 24
Finished Jun 06 02:41:50 PM PDT 24
Peak memory 203748 kb
Host smart-74b7e55b-4361-4178-a142-7feb436d28e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240205588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.4240205588
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.3859431399
Short name T1504
Test name
Test status
Simulation time 42202206 ps
CPU time 0.64 seconds
Started Jun 06 02:41:47 PM PDT 24
Finished Jun 06 02:41:51 PM PDT 24
Peak memory 203628 kb
Host smart-d10a2654-8801-454d-bf76-104b5ff8c520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859431399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.3859431399
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.1033615967
Short name T1587
Test name
Test status
Simulation time 57949916 ps
CPU time 0.84 seconds
Started Jun 06 02:41:50 PM PDT 24
Finished Jun 06 02:41:55 PM PDT 24
Peak memory 203680 kb
Host smart-b9937f17-25a8-4a24-a754-25364caeff83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033615967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.1033615967
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3308567714
Short name T1595
Test name
Test status
Simulation time 53687724 ps
CPU time 1.83 seconds
Started Jun 06 02:41:50 PM PDT 24
Finished Jun 06 02:41:56 PM PDT 24
Peak memory 204012 kb
Host smart-8e9cff58-9dc9-471d-8b86-b8eb2e403f66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308567714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3308567714
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2613147436
Short name T183
Test name
Test status
Simulation time 315399275 ps
CPU time 2.29 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:55 PM PDT 24
Peak memory 203980 kb
Host smart-82ccd001-d8a8-4cf4-b826-3b699a425583
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613147436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2613147436
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.3938048312
Short name T1573
Test name
Test status
Simulation time 173915006 ps
CPU time 0.93 seconds
Started Jun 06 02:41:50 PM PDT 24
Finished Jun 06 02:41:55 PM PDT 24
Peak memory 203804 kb
Host smart-4c108b11-a799-4766-b608-9f94a276bb69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938048312 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.3938048312
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.1423405305
Short name T1590
Test name
Test status
Simulation time 44882310 ps
CPU time 0.67 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:56 PM PDT 24
Peak memory 203716 kb
Host smart-0e4a1d12-8d91-413d-a602-11b827a945b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423405305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.1423405305
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.123288569
Short name T1521
Test name
Test status
Simulation time 32028424 ps
CPU time 0.64 seconds
Started Jun 06 02:41:50 PM PDT 24
Finished Jun 06 02:41:54 PM PDT 24
Peak memory 203672 kb
Host smart-22257d26-40dc-4561-864a-a7420adf3e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123288569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.123288569
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2886541761
Short name T201
Test name
Test status
Simulation time 56828416 ps
CPU time 1.24 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:57 PM PDT 24
Peak memory 203956 kb
Host smart-ff66792b-296c-49b3-bf0a-53befdfb1745
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886541761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2886541761
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.759949298
Short name T185
Test name
Test status
Simulation time 94295943 ps
CPU time 1.33 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:48 PM PDT 24
Peak memory 203988 kb
Host smart-37e63d4a-415e-4bf6-ba2a-f8957c160e12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759949298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.759949298
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.762960149
Short name T1564
Test name
Test status
Simulation time 113588958 ps
CPU time 1.52 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:43 PM PDT 24
Peak memory 212152 kb
Host smart-c3efc7ec-4b2f-4f26-8612-669fb925185b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762960149 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.762960149
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3397076911
Short name T1541
Test name
Test status
Simulation time 25046007 ps
CPU time 0.77 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:41:54 PM PDT 24
Peak memory 203684 kb
Host smart-850b4446-6c8a-46b4-af8d-0bb49f5e1cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397076911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3397076911
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.4010355095
Short name T1530
Test name
Test status
Simulation time 38978539 ps
CPU time 0.69 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 203672 kb
Host smart-47ca139d-a3ff-48e0-89cc-4b9ff02e5b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010355095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.4010355095
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.2617622437
Short name T1532
Test name
Test status
Simulation time 35010241 ps
CPU time 0.94 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:41:54 PM PDT 24
Peak memory 203736 kb
Host smart-ceb2e75e-8dc6-4d24-bf32-f9801c86f6f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617622437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.2617622437
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.809655711
Short name T1536
Test name
Test status
Simulation time 252908728 ps
CPU time 1.82 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:57 PM PDT 24
Peak memory 204000 kb
Host smart-0d597957-5486-4e00-882a-784469581785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809655711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.809655711
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.3228847618
Short name T187
Test name
Test status
Simulation time 150811712 ps
CPU time 1.55 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:43 PM PDT 24
Peak memory 203932 kb
Host smart-fc183896-a817-4d37-b4a7-a512e2bce9df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228847618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.3228847618
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.2662189341
Short name T1505
Test name
Test status
Simulation time 55343387 ps
CPU time 1.31 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203968 kb
Host smart-126ca50e-58dc-4b70-9207-e24d63f74afa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662189341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.2662189341
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.3077082880
Short name T196
Test name
Test status
Simulation time 874177206 ps
CPU time 5.88 seconds
Started Jun 06 02:41:33 PM PDT 24
Finished Jun 06 02:41:41 PM PDT 24
Peak memory 203904 kb
Host smart-1ae9ba7f-91a7-4bc7-a008-e4f0edfae91e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077082880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.3077082880
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.804980718
Short name T1574
Test name
Test status
Simulation time 52537324 ps
CPU time 0.72 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203724 kb
Host smart-53f577ae-acb2-4875-9cd5-b0d5891c78a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804980718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.804980718
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3536783254
Short name T1582
Test name
Test status
Simulation time 73246726 ps
CPU time 1.05 seconds
Started Jun 06 02:41:28 PM PDT 24
Finished Jun 06 02:41:31 PM PDT 24
Peak memory 203776 kb
Host smart-cff7518a-9324-49b1-82cb-312ab71fb070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536783254 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3536783254
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.2279240954
Short name T200
Test name
Test status
Simulation time 16593545 ps
CPU time 0.73 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:33 PM PDT 24
Peak memory 203684 kb
Host smart-6103a7d6-c8f5-42e4-8eff-87e341ab9335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279240954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.2279240954
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.2851075989
Short name T1576
Test name
Test status
Simulation time 32112238 ps
CPU time 0.67 seconds
Started Jun 06 02:41:27 PM PDT 24
Finished Jun 06 02:41:29 PM PDT 24
Peak memory 203624 kb
Host smart-9bcd85f2-1a63-42bb-a677-3c0f2265e88d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851075989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.2851075989
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.566478832
Short name T172
Test name
Test status
Simulation time 79070902 ps
CPU time 1.78 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:33 PM PDT 24
Peak memory 203996 kb
Host smart-65037a07-dd43-418b-8421-9c8afb13bd21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566478832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.566478832
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2826076464
Short name T1528
Test name
Test status
Simulation time 15622669 ps
CPU time 0.64 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:56 PM PDT 24
Peak memory 203688 kb
Host smart-65c39ab4-550f-4e94-aa7d-bdc2680296a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826076464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2826076464
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.1150630259
Short name T1600
Test name
Test status
Simulation time 55125151 ps
CPU time 0.68 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:41:54 PM PDT 24
Peak memory 203672 kb
Host smart-d55fb051-efcc-4299-ab4f-af10c15c992f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150630259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1150630259
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.1989183304
Short name T1495
Test name
Test status
Simulation time 31338548 ps
CPU time 0.63 seconds
Started Jun 06 02:41:41 PM PDT 24
Finished Jun 06 02:41:43 PM PDT 24
Peak memory 203636 kb
Host smart-2eb7736c-244b-42e9-9026-0f4346603f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989183304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.1989183304
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.2899550281
Short name T1568
Test name
Test status
Simulation time 36365955 ps
CPU time 0.66 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:02 PM PDT 24
Peak memory 203640 kb
Host smart-4fbe30cc-6946-4f49-8b21-fe1d606c1180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899550281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.2899550281
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.3548712404
Short name T1556
Test name
Test status
Simulation time 57403910 ps
CPU time 0.7 seconds
Started Jun 06 02:41:45 PM PDT 24
Finished Jun 06 02:41:49 PM PDT 24
Peak memory 203644 kb
Host smart-b9f6fa54-5b56-4432-8c91-af40c8c20b64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548712404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.3548712404
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.670693355
Short name T1506
Test name
Test status
Simulation time 64949366 ps
CPU time 0.66 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:42:00 PM PDT 24
Peak memory 203612 kb
Host smart-f3e29ede-daf0-464f-b7a1-19c38816cb09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670693355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.670693355
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2088658563
Short name T1586
Test name
Test status
Simulation time 34772784 ps
CPU time 0.64 seconds
Started Jun 06 02:41:47 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 203656 kb
Host smart-329cee94-61f9-4fc9-b56b-268a8ddf537c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088658563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2088658563
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.1011020296
Short name T1566
Test name
Test status
Simulation time 37024674 ps
CPU time 0.67 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:41:53 PM PDT 24
Peak memory 203588 kb
Host smart-cf9a7245-0a9a-4514-987f-1316c06e433c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011020296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.1011020296
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.795778806
Short name T115
Test name
Test status
Simulation time 20603024 ps
CPU time 0.7 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 203680 kb
Host smart-83d8d595-50bc-4b4c-92b5-5aaebf213928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795778806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.795778806
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.4005202081
Short name T1514
Test name
Test status
Simulation time 22395766 ps
CPU time 0.69 seconds
Started Jun 06 02:41:47 PM PDT 24
Finished Jun 06 02:41:51 PM PDT 24
Peak memory 203616 kb
Host smart-5c14f173-07b8-465d-bc6e-d364944e51d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005202081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4005202081
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.495918253
Short name T1508
Test name
Test status
Simulation time 63626923 ps
CPU time 1.41 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:34 PM PDT 24
Peak memory 203964 kb
Host smart-27d5727f-d86d-4c26-abcb-7d63ad8afc3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495918253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.495918253
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1421307743
Short name T1527
Test name
Test status
Simulation time 865648725 ps
CPU time 3.31 seconds
Started Jun 06 02:41:26 PM PDT 24
Finished Jun 06 02:41:30 PM PDT 24
Peak memory 203948 kb
Host smart-e5e03837-9c6b-44d1-8968-8b5d2236023d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421307743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1421307743
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3557001573
Short name T1553
Test name
Test status
Simulation time 20062335 ps
CPU time 0.77 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203712 kb
Host smart-db3a7e78-b27c-4255-8734-17b6c1657c84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557001573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3557001573
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.4133899853
Short name T1598
Test name
Test status
Simulation time 87332959 ps
CPU time 1.02 seconds
Started Jun 06 02:41:27 PM PDT 24
Finished Jun 06 02:41:29 PM PDT 24
Peak memory 203744 kb
Host smart-1fe15028-c088-45c5-8eaa-34d9dab68b79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133899853 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.4133899853
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.1804045132
Short name T91
Test name
Test status
Simulation time 96851339 ps
CPU time 0.66 seconds
Started Jun 06 02:41:27 PM PDT 24
Finished Jun 06 02:41:29 PM PDT 24
Peak memory 203816 kb
Host smart-a839e10d-5a1c-4bc1-b72b-0dc632adad80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804045132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.1804045132
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.1801757830
Short name T1503
Test name
Test status
Simulation time 22094531 ps
CPU time 0.66 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203636 kb
Host smart-2586f87d-da46-4251-8c81-cc8e7f7c5483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801757830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.1801757830
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3905903489
Short name T1539
Test name
Test status
Simulation time 120431322 ps
CPU time 1.15 seconds
Started Jun 06 02:41:34 PM PDT 24
Finished Jun 06 02:41:37 PM PDT 24
Peak memory 203932 kb
Host smart-4c12e4f8-48ec-4c41-823b-f77ffc65d29e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905903489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.3905903489
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1516620530
Short name T1603
Test name
Test status
Simulation time 26341938 ps
CPU time 1.23 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203996 kb
Host smart-a5125f52-dda8-4f01-99ef-af8626e51fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516620530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1516620530
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.816456419
Short name T1571
Test name
Test status
Simulation time 41111836 ps
CPU time 0.67 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 203684 kb
Host smart-d7416d27-b916-46d1-b5ab-118d05f31ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816456419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.816456419
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3672608095
Short name T1496
Test name
Test status
Simulation time 15166954 ps
CPU time 0.65 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:41:59 PM PDT 24
Peak memory 203628 kb
Host smart-62593414-15eb-458f-a6e3-1a919160acf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672608095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3672608095
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.1923000929
Short name T1499
Test name
Test status
Simulation time 43408338 ps
CPU time 0.65 seconds
Started Jun 06 02:41:54 PM PDT 24
Finished Jun 06 02:41:59 PM PDT 24
Peak memory 203668 kb
Host smart-87711e09-79b2-4b63-91b5-173a16bf99ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923000929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.1923000929
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.3818971569
Short name T1520
Test name
Test status
Simulation time 64630808 ps
CPU time 0.71 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:56 PM PDT 24
Peak memory 203648 kb
Host smart-3bf847d7-621c-41c7-a404-752b44c84221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818971569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.3818971569
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.2960875312
Short name T1540
Test name
Test status
Simulation time 37309397 ps
CPU time 0.64 seconds
Started Jun 06 02:41:59 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 203660 kb
Host smart-576fff1a-5e56-4c00-aa39-957364a335d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960875312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.2960875312
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2406936938
Short name T1515
Test name
Test status
Simulation time 19603687 ps
CPU time 0.68 seconds
Started Jun 06 02:41:46 PM PDT 24
Finished Jun 06 02:41:50 PM PDT 24
Peak memory 203720 kb
Host smart-8f502b17-2a16-4226-a85f-ee706ffe0de0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406936938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2406936938
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3187720279
Short name T1561
Test name
Test status
Simulation time 16280230 ps
CPU time 0.68 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:53 PM PDT 24
Peak memory 203664 kb
Host smart-4846fd09-8cf6-4810-8d21-36a8050994c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187720279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3187720279
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.986478603
Short name T1498
Test name
Test status
Simulation time 31805453 ps
CPU time 0.64 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:53 PM PDT 24
Peak memory 203616 kb
Host smart-a3283435-b773-4d6a-b8ed-154fd9db30cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986478603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.986478603
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.579727507
Short name T1591
Test name
Test status
Simulation time 20225928 ps
CPU time 0.64 seconds
Started Jun 06 02:41:51 PM PDT 24
Finished Jun 06 02:41:56 PM PDT 24
Peak memory 203628 kb
Host smart-50be5e93-0893-426b-963e-a2e0f7b58a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579727507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.579727507
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2172868035
Short name T1599
Test name
Test status
Simulation time 31425587 ps
CPU time 1.39 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:33 PM PDT 24
Peak memory 203976 kb
Host smart-aac48aa9-93ab-403f-8b74-54b88d4bd0d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172868035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2172868035
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1593770191
Short name T1589
Test name
Test status
Simulation time 881654664 ps
CPU time 6.11 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:37 PM PDT 24
Peak memory 203988 kb
Host smart-63932869-8395-4bfa-a131-54d491cb8fcc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593770191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1593770191
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.2182004822
Short name T138
Test name
Test status
Simulation time 29382246 ps
CPU time 0.78 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:34 PM PDT 24
Peak memory 203716 kb
Host smart-5f35ab44-4ada-4542-8a1b-e46ee83d73b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182004822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.2182004822
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3571701412
Short name T176
Test name
Test status
Simulation time 35821195 ps
CPU time 0.99 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:31 PM PDT 24
Peak memory 203812 kb
Host smart-3f973575-cf3c-41ad-8bd2-76b1a2ee0a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571701412 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3571701412
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.1767146027
Short name T1594
Test name
Test status
Simulation time 59894346 ps
CPU time 0.75 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:33 PM PDT 24
Peak memory 203684 kb
Host smart-193e0eef-4807-4e85-82aa-d400babfd7da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767146027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.1767146027
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.2416915453
Short name T1522
Test name
Test status
Simulation time 57619181 ps
CPU time 0.69 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:31 PM PDT 24
Peak memory 203640 kb
Host smart-9646032e-566f-4bf3-a39a-2f0169a8a445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416915453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2416915453
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.437309628
Short name T1554
Test name
Test status
Simulation time 65688185 ps
CPU time 0.86 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:32 PM PDT 24
Peak memory 203708 kb
Host smart-879e76c7-eedd-433a-9699-80fe87bdccb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437309628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.437309628
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.1567886100
Short name T1581
Test name
Test status
Simulation time 55331155 ps
CPU time 1.33 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 204060 kb
Host smart-69ce97c3-9f0b-4d29-8230-604cd294f4cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567886100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.1567886100
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.1191098106
Short name T175
Test name
Test status
Simulation time 269691831 ps
CPU time 1.54 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203940 kb
Host smart-7bd56f3e-8034-4b00-9666-4cab0b541ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191098106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.1191098106
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.184323348
Short name T1517
Test name
Test status
Simulation time 43272535 ps
CPU time 0.62 seconds
Started Jun 06 02:41:53 PM PDT 24
Finished Jun 06 02:41:58 PM PDT 24
Peak memory 203660 kb
Host smart-ada701aa-d850-455e-97b4-2b9f1c479eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184323348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.184323348
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.956124539
Short name T1542
Test name
Test status
Simulation time 51449950 ps
CPU time 0.66 seconds
Started Jun 06 02:41:48 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 203676 kb
Host smart-d4899f9d-851b-46ac-b414-bffa0457ec47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956124539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.956124539
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.381664981
Short name T1526
Test name
Test status
Simulation time 42404214 ps
CPU time 0.64 seconds
Started Jun 06 02:41:53 PM PDT 24
Finished Jun 06 02:41:58 PM PDT 24
Peak memory 203612 kb
Host smart-7d7af66e-cf7a-42b7-8f32-b0d981c3b2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381664981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.381664981
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3160098069
Short name T1501
Test name
Test status
Simulation time 63442795 ps
CPU time 0.66 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:42:00 PM PDT 24
Peak memory 203616 kb
Host smart-508db357-3816-4209-9c47-7af8560af3ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160098069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3160098069
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3874738117
Short name T1545
Test name
Test status
Simulation time 50989119 ps
CPU time 0.71 seconds
Started Jun 06 02:42:00 PM PDT 24
Finished Jun 06 02:42:03 PM PDT 24
Peak memory 203616 kb
Host smart-c1637545-4677-4e84-9cef-9e8758b96a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874738117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3874738117
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.2638271337
Short name T1531
Test name
Test status
Simulation time 46342054 ps
CPU time 0.68 seconds
Started Jun 06 02:41:55 PM PDT 24
Finished Jun 06 02:42:00 PM PDT 24
Peak memory 203612 kb
Host smart-a9121b7c-de34-4408-86d1-0fdc9f6d4acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638271337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.2638271337
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1799559793
Short name T1558
Test name
Test status
Simulation time 196901482 ps
CPU time 0.71 seconds
Started Jun 06 02:41:49 PM PDT 24
Finished Jun 06 02:41:53 PM PDT 24
Peak memory 203604 kb
Host smart-72d83542-4a45-4d9c-a8bf-941a6f34aec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799559793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1799559793
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1411528889
Short name T1549
Test name
Test status
Simulation time 16820579 ps
CPU time 0.74 seconds
Started Jun 06 02:41:47 PM PDT 24
Finished Jun 06 02:41:52 PM PDT 24
Peak memory 203672 kb
Host smart-6fc0a3f5-5f58-43f5-a053-0ad15305e90e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411528889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1411528889
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2583940135
Short name T1537
Test name
Test status
Simulation time 28920608 ps
CPU time 0.66 seconds
Started Jun 06 02:41:50 PM PDT 24
Finished Jun 06 02:41:54 PM PDT 24
Peak memory 203676 kb
Host smart-893be066-9ca9-48f3-8253-ff4f0c955037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583940135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2583940135
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.1887288197
Short name T1563
Test name
Test status
Simulation time 48397351 ps
CPU time 0.63 seconds
Started Jun 06 02:41:57 PM PDT 24
Finished Jun 06 02:42:01 PM PDT 24
Peak memory 203668 kb
Host smart-42004d1f-4633-4423-a07f-333ea7b4e2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887288197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.1887288197
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1723110480
Short name T1534
Test name
Test status
Simulation time 67990782 ps
CPU time 1.11 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203812 kb
Host smart-bcab6aff-87a9-46c6-bd27-cb6fe87a6d53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723110480 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.1723110480
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.174946455
Short name T89
Test name
Test status
Simulation time 112427231 ps
CPU time 0.79 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:33 PM PDT 24
Peak memory 203708 kb
Host smart-b8b80063-9dea-4174-9672-45417d90154d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174946455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.174946455
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3071787972
Short name T1509
Test name
Test status
Simulation time 29203242 ps
CPU time 0.67 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:34 PM PDT 24
Peak memory 203604 kb
Host smart-2015b4b5-9d86-4e6e-be62-475ba93fa006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071787972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3071787972
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1383760474
Short name T1538
Test name
Test status
Simulation time 239943891 ps
CPU time 0.83 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:34 PM PDT 24
Peak memory 203720 kb
Host smart-d77ac0f5-fff3-4064-a386-0a4c46e6802f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383760474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1383760474
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.2737209428
Short name T1546
Test name
Test status
Simulation time 806695470 ps
CPU time 2.42 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203964 kb
Host smart-b97cc9bb-86e6-4457-b438-19b1ed733ee7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737209428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.2737209428
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3738896201
Short name T181
Test name
Test status
Simulation time 624607077 ps
CPU time 2.08 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:32 PM PDT 24
Peak memory 203928 kb
Host smart-4a934092-7f67-466b-b31b-7bf260f6105c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738896201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3738896201
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.3606504443
Short name T1580
Test name
Test status
Simulation time 53406631 ps
CPU time 1.23 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203956 kb
Host smart-260d709e-f27e-40f2-9eed-430b8dc69824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606504443 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.3606504443
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2687713095
Short name T1572
Test name
Test status
Simulation time 55395976 ps
CPU time 0.67 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:34 PM PDT 24
Peak memory 203752 kb
Host smart-8a0a6158-1429-4adf-b1a7-5e1fe2712f57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687713095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2687713095
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3218429850
Short name T1597
Test name
Test status
Simulation time 40784465 ps
CPU time 0.67 seconds
Started Jun 06 02:41:28 PM PDT 24
Finished Jun 06 02:41:30 PM PDT 24
Peak memory 203664 kb
Host smart-c457bef5-ada0-45d7-a43a-3789c8db9ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218429850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3218429850
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1844218899
Short name T204
Test name
Test status
Simulation time 60489212 ps
CPU time 0.92 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203756 kb
Host smart-44425ef3-64c1-497b-b462-a0840b87f9f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844218899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1844218899
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.3214381995
Short name T1548
Test name
Test status
Simulation time 133705504 ps
CPU time 1.21 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 204000 kb
Host smart-84c6c713-a7a8-46e6-9e34-88fd09ecd721
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214381995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.3214381995
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3868650541
Short name T189
Test name
Test status
Simulation time 122169235 ps
CPU time 1.01 seconds
Started Jun 06 02:41:31 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203784 kb
Host smart-0585f12f-aea0-4a13-94d0-13ef53517233
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868650541 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3868650541
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.321075902
Short name T194
Test name
Test status
Simulation time 26856907 ps
CPU time 0.69 seconds
Started Jun 06 02:41:33 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203708 kb
Host smart-ecf917bd-856a-46e2-a3ae-9f1a8fbc94c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321075902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.321075902
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3230208993
Short name T1593
Test name
Test status
Simulation time 19311008 ps
CPU time 0.68 seconds
Started Jun 06 02:41:33 PM PDT 24
Finished Jun 06 02:41:36 PM PDT 24
Peak memory 203636 kb
Host smart-de709faf-065b-4dcf-8282-07598ff4db2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230208993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3230208993
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.4121201638
Short name T1575
Test name
Test status
Simulation time 54213372 ps
CPU time 1.19 seconds
Started Jun 06 02:41:30 PM PDT 24
Finished Jun 06 02:41:33 PM PDT 24
Peak memory 203892 kb
Host smart-da99be96-8c1c-42be-9bde-b85409279c4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121201638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.4121201638
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.90747275
Short name T1547
Test name
Test status
Simulation time 460061467 ps
CPU time 2.17 seconds
Started Jun 06 02:41:33 PM PDT 24
Finished Jun 06 02:41:38 PM PDT 24
Peak memory 204016 kb
Host smart-4fb0eb27-04f4-4fe5-8202-32821f2c2dd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90747275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.90747275
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.109870540
Short name T1533
Test name
Test status
Simulation time 83836063 ps
CPU time 1.48 seconds
Started Jun 06 02:41:28 PM PDT 24
Finished Jun 06 02:41:30 PM PDT 24
Peak memory 203956 kb
Host smart-be8e5c39-1493-44e6-88b9-3d204396f335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109870540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.109870540
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.804104848
Short name T1577
Test name
Test status
Simulation time 359413894 ps
CPU time 0.79 seconds
Started Jun 06 02:41:41 PM PDT 24
Finished Jun 06 02:41:44 PM PDT 24
Peak memory 203760 kb
Host smart-67ffaf55-e046-4071-abe0-64a1d75d9cb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804104848 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.804104848
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.2672543811
Short name T198
Test name
Test status
Simulation time 52512511 ps
CPU time 0.78 seconds
Started Jun 06 02:41:46 PM PDT 24
Finished Jun 06 02:41:51 PM PDT 24
Peak memory 203692 kb
Host smart-f3e109f7-1966-4f1a-8045-635ed974682f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672543811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.2672543811
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1767854346
Short name T1511
Test name
Test status
Simulation time 42138685 ps
CPU time 0.68 seconds
Started Jun 06 02:41:32 PM PDT 24
Finished Jun 06 02:41:35 PM PDT 24
Peak memory 203684 kb
Host smart-d9a0c27e-5cd4-4609-94ca-ec31e20433cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767854346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1767854346
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.1267648592
Short name T1551
Test name
Test status
Simulation time 211818165 ps
CPU time 1.21 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:43 PM PDT 24
Peak memory 203928 kb
Host smart-4fb9fe8a-0dcc-41cc-bf48-158b8763e4c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267648592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.1267648592
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1578642428
Short name T157
Test name
Test status
Simulation time 201982242 ps
CPU time 2.31 seconds
Started Jun 06 02:41:29 PM PDT 24
Finished Jun 06 02:41:33 PM PDT 24
Peak memory 203988 kb
Host smart-3c759617-e6e8-4563-bb7f-a4b71ca95006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578642428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1578642428
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3824586496
Short name T178
Test name
Test status
Simulation time 29714071 ps
CPU time 1.25 seconds
Started Jun 06 02:41:44 PM PDT 24
Finished Jun 06 02:41:48 PM PDT 24
Peak memory 212228 kb
Host smart-80e353ec-285e-4214-8d3b-9aff48240256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824586496 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3824586496
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.3301135500
Short name T197
Test name
Test status
Simulation time 53683446 ps
CPU time 0.69 seconds
Started Jun 06 02:42:09 PM PDT 24
Finished Jun 06 02:42:13 PM PDT 24
Peak memory 203692 kb
Host smart-43ae3371-75e6-4ddc-b2b1-12ba9bbce0c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301135500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.3301135500
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2628696226
Short name T1602
Test name
Test status
Simulation time 49589606 ps
CPU time 0.73 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:42 PM PDT 24
Peak memory 203600 kb
Host smart-186dfad2-60d9-4de4-adfe-0a4c6e710e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628696226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2628696226
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.3021176850
Short name T203
Test name
Test status
Simulation time 33526745 ps
CPU time 0.88 seconds
Started Jun 06 02:41:40 PM PDT 24
Finished Jun 06 02:41:42 PM PDT 24
Peak memory 203948 kb
Host smart-114c6cef-87aa-41bf-872d-aa4267e3264c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021176850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.3021176850
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.145058708
Short name T1588
Test name
Test status
Simulation time 71831570 ps
CPU time 1.52 seconds
Started Jun 06 02:41:43 PM PDT 24
Finished Jun 06 02:41:47 PM PDT 24
Peak memory 203952 kb
Host smart-b82a6989-2faf-47d9-ac57-6e0f68badd72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145058708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.145058708
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2215324614
Short name T234
Test name
Test status
Simulation time 253709299 ps
CPU time 1.47 seconds
Started Jun 06 02:41:43 PM PDT 24
Finished Jun 06 02:41:46 PM PDT 24
Peak memory 203940 kb
Host smart-73b65311-e6b9-4733-bff5-22a69eb479a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215324614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2215324614
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3748627050
Short name T494
Test name
Test status
Simulation time 194931664 ps
CPU time 0.61 seconds
Started Jun 06 02:48:54 PM PDT 24
Finished Jun 06 02:48:56 PM PDT 24
Peak memory 204728 kb
Host smart-f43600bf-b720-4d3d-b8ce-ec511e4f57a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748627050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3748627050
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.3307268575
Short name T767
Test name
Test status
Simulation time 384654287 ps
CPU time 2.59 seconds
Started Jun 06 02:48:38 PM PDT 24
Finished Jun 06 02:48:42 PM PDT 24
Peak memory 213348 kb
Host smart-e251a620-4b5a-43f4-933f-be884ab897d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307268575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.3307268575
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.2439700919
Short name T1018
Test name
Test status
Simulation time 191107327 ps
CPU time 9.61 seconds
Started Jun 06 02:48:39 PM PDT 24
Finished Jun 06 02:48:50 PM PDT 24
Peak memory 238856 kb
Host smart-6292b74e-6a30-4c56-9b2d-2859b4d30a57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439700919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.2439700919
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2517607391
Short name T389
Test name
Test status
Simulation time 5615851690 ps
CPU time 53.27 seconds
Started Jun 06 02:48:36 PM PDT 24
Finished Jun 06 02:49:31 PM PDT 24
Peak memory 583656 kb
Host smart-4a4a3478-b12d-4ec4-abb1-183468331601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517607391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2517607391
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.2556603617
Short name T352
Test name
Test status
Simulation time 4725059510 ps
CPU time 79.17 seconds
Started Jun 06 02:48:45 PM PDT 24
Finished Jun 06 02:50:05 PM PDT 24
Peak memory 732864 kb
Host smart-793ba4a7-4f30-4db7-8620-79d647cadec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556603617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.2556603617
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1385079797
Short name T840
Test name
Test status
Simulation time 180031231 ps
CPU time 4.56 seconds
Started Jun 06 02:48:46 PM PDT 24
Finished Jun 06 02:48:51 PM PDT 24
Peak memory 205048 kb
Host smart-6b810576-a74b-48b5-bee4-dca19024bd7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385079797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1385079797
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.255416914
Short name T906
Test name
Test status
Simulation time 38022868537 ps
CPU time 353.3 seconds
Started Jun 06 02:48:41 PM PDT 24
Finished Jun 06 02:54:36 PM PDT 24
Peak memory 1242108 kb
Host smart-b2355679-8d71-4c28-bef3-37784723c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255416914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.255416914
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3639817267
Short name T625
Test name
Test status
Simulation time 459347581 ps
CPU time 7.6 seconds
Started Jun 06 02:48:57 PM PDT 24
Finished Jun 06 02:49:05 PM PDT 24
Peak memory 205064 kb
Host smart-e0cbb30a-45d8-43d6-97f8-ac5260a4f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639817267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3639817267
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.1039187982
Short name T787
Test name
Test status
Simulation time 1894179818 ps
CPU time 84.14 seconds
Started Jun 06 02:48:56 PM PDT 24
Finished Jun 06 02:50:21 PM PDT 24
Peak memory 332528 kb
Host smart-d5e0a152-205c-49e9-abec-95898778fbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039187982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.1039187982
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.2356310532
Short name T549
Test name
Test status
Simulation time 24355445 ps
CPU time 0.65 seconds
Started Jun 06 02:48:34 PM PDT 24
Finished Jun 06 02:48:37 PM PDT 24
Peak memory 204704 kb
Host smart-b47c61ac-4f7a-42ff-b47a-d8af9c7a5f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356310532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2356310532
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1902417287
Short name T595
Test name
Test status
Simulation time 24517175950 ps
CPU time 69.33 seconds
Started Jun 06 02:48:35 PM PDT 24
Finished Jun 06 02:49:47 PM PDT 24
Peak memory 205200 kb
Host smart-b4fc2e75-c780-43fe-9f2a-f716230c4cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902417287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1902417287
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.3073173266
Short name T1140
Test name
Test status
Simulation time 1894306134 ps
CPU time 93.19 seconds
Started Jun 06 02:48:39 PM PDT 24
Finished Jun 06 02:50:14 PM PDT 24
Peak memory 372904 kb
Host smart-6327ae43-1eef-4e2d-b7fe-2c3c83b9f389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073173266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.3073173266
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3974482215
Short name T1042
Test name
Test status
Simulation time 20753950640 ps
CPU time 406.25 seconds
Started Jun 06 02:48:42 PM PDT 24
Finished Jun 06 02:55:29 PM PDT 24
Peak memory 1329236 kb
Host smart-65bfe08c-cdf3-41b9-8d18-ed774490eea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974482215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3974482215
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.3713369528
Short name T1399
Test name
Test status
Simulation time 614052401 ps
CPU time 12.23 seconds
Started Jun 06 02:48:40 PM PDT 24
Finished Jun 06 02:48:54 PM PDT 24
Peak memory 221128 kb
Host smart-3a2f02bf-79a7-415c-942c-d7d26ca78c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713369528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.3713369528
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.3970428907
Short name T728
Test name
Test status
Simulation time 10300303434 ps
CPU time 4.05 seconds
Started Jun 06 02:48:43 PM PDT 24
Finished Jun 06 02:48:48 PM PDT 24
Peak memory 205200 kb
Host smart-15166f96-73c8-4bb7-8a2b-d90290ee5645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970428907 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.3970428907
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.3051189671
Short name T1482
Test name
Test status
Simulation time 10137608631 ps
CPU time 12.59 seconds
Started Jun 06 02:48:45 PM PDT 24
Finished Jun 06 02:48:59 PM PDT 24
Peak memory 250700 kb
Host smart-5fc795d7-efae-4846-988a-f45db9d29022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051189671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.3051189671
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.294993620
Short name T335
Test name
Test status
Simulation time 10352452936 ps
CPU time 15.72 seconds
Started Jun 06 02:48:44 PM PDT 24
Finished Jun 06 02:49:01 PM PDT 24
Peak memory 319600 kb
Host smart-66d09252-ef76-485a-9b23-669afc5bcac9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294993620 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.294993620
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.1412478109
Short name T475
Test name
Test status
Simulation time 1040215684 ps
CPU time 3.72 seconds
Started Jun 06 02:48:54 PM PDT 24
Finished Jun 06 02:49:00 PM PDT 24
Peak memory 205108 kb
Host smart-36663b21-5075-45ec-817e-2d1c9cf7b67f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412478109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.1412478109
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.3869374732
Short name T15
Test name
Test status
Simulation time 4151610261 ps
CPU time 10.86 seconds
Started Jun 06 02:48:37 PM PDT 24
Finished Jun 06 02:48:49 PM PDT 24
Peak memory 213524 kb
Host smart-4cb9a7ab-2570-42ca-befc-47b405ec80c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869374732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3869374732
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.3415298208
Short name T732
Test name
Test status
Simulation time 889764754 ps
CPU time 2.74 seconds
Started Jun 06 02:48:47 PM PDT 24
Finished Jun 06 02:48:51 PM PDT 24
Peak memory 205072 kb
Host smart-75de2262-a6b5-41a7-b139-0ee17b27a682
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415298208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.3415298208
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.771865586
Short name T407
Test name
Test status
Simulation time 2538144311 ps
CPU time 6.21 seconds
Started Jun 06 02:48:43 PM PDT 24
Finished Jun 06 02:48:50 PM PDT 24
Peak memory 215464 kb
Host smart-a64f7563-2bfc-416f-8b37-118c77d2f50c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771865586 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.771865586
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.194504246
Short name T1294
Test name
Test status
Simulation time 5622241343 ps
CPU time 4.2 seconds
Started Jun 06 02:48:46 PM PDT 24
Finished Jun 06 02:48:51 PM PDT 24
Peak memory 205168 kb
Host smart-1b2a46d7-c040-4222-93ae-dc088ba7f44d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194504246 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.194504246
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.3633250040
Short name T1243
Test name
Test status
Simulation time 3458406581 ps
CPU time 28.35 seconds
Started Jun 06 02:48:39 PM PDT 24
Finished Jun 06 02:49:08 PM PDT 24
Peak memory 205124 kb
Host smart-68c73d98-6da3-46f9-ab30-f5810c39a02f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633250040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.3633250040
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.4027069857
Short name T514
Test name
Test status
Simulation time 8459375900 ps
CPU time 25.68 seconds
Started Jun 06 02:48:43 PM PDT 24
Finished Jun 06 02:49:10 PM PDT 24
Peak memory 228948 kb
Host smart-acfad32a-9d2d-43a4-a987-15fca58e2f9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027069857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.4027069857
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2976219165
Short name T1493
Test name
Test status
Simulation time 27265514007 ps
CPU time 129.52 seconds
Started Jun 06 02:48:38 PM PDT 24
Finished Jun 06 02:50:49 PM PDT 24
Peak memory 1848436 kb
Host smart-859f3f7a-382a-4a08-a47f-f9d4d411e4d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976219165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2976219165
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1275008838
Short name T231
Test name
Test status
Simulation time 16722824451 ps
CPU time 251.32 seconds
Started Jun 06 02:48:43 PM PDT 24
Finished Jun 06 02:52:56 PM PDT 24
Peak memory 2039320 kb
Host smart-17a2999a-4251-4338-bbf6-06303756d6ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275008838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1275008838
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1468133371
Short name T996
Test name
Test status
Simulation time 3433845119 ps
CPU time 8.6 seconds
Started Jun 06 02:48:47 PM PDT 24
Finished Jun 06 02:48:56 PM PDT 24
Peak memory 221448 kb
Host smart-ca989a11-51b3-4848-9a65-29409924a291
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468133371 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1468133371
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.4263975823
Short name T1467
Test name
Test status
Simulation time 1218457448 ps
CPU time 16.74 seconds
Started Jun 06 02:48:55 PM PDT 24
Finished Jun 06 02:49:13 PM PDT 24
Peak memory 205088 kb
Host smart-079fb85d-1b3a-49fa-a754-5b8d0ff9b4a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263975823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.4263975823
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.3993106545
Short name T415
Test name
Test status
Simulation time 33629546 ps
CPU time 0.61 seconds
Started Jun 06 02:49:05 PM PDT 24
Finished Jun 06 02:49:07 PM PDT 24
Peak memory 204704 kb
Host smart-3a404115-ed16-4ba4-a649-7b4d9c934ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993106545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3993106545
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2768527672
Short name T756
Test name
Test status
Simulation time 338288708 ps
CPU time 2.63 seconds
Started Jun 06 02:49:03 PM PDT 24
Finished Jun 06 02:49:07 PM PDT 24
Peak memory 213288 kb
Host smart-0b17bdbc-8c9e-478c-892c-931efb14410b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768527672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2768527672
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.1604810080
Short name T279
Test name
Test status
Simulation time 295337281 ps
CPU time 15.96 seconds
Started Jun 06 02:48:56 PM PDT 24
Finished Jun 06 02:49:13 PM PDT 24
Peak memory 267208 kb
Host smart-5fcd807d-1b90-420a-bb62-1e9227ef6d38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604810080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.1604810080
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.303932085
Short name T1406
Test name
Test status
Simulation time 2022031987 ps
CPU time 63.72 seconds
Started Jun 06 02:48:57 PM PDT 24
Finished Jun 06 02:50:01 PM PDT 24
Peak memory 687656 kb
Host smart-dbcbca8d-43b6-48d2-93be-884b825bb352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303932085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.303932085
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.3159672833
Short name T447
Test name
Test status
Simulation time 2319228441 ps
CPU time 74.11 seconds
Started Jun 06 02:48:55 PM PDT 24
Finished Jun 06 02:50:11 PM PDT 24
Peak memory 756372 kb
Host smart-432d0f9d-8080-45f4-97e1-4c371bb51369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159672833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.3159672833
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.4013756456
Short name T672
Test name
Test status
Simulation time 317757749 ps
CPU time 0.96 seconds
Started Jun 06 02:48:53 PM PDT 24
Finished Jun 06 02:48:55 PM PDT 24
Peak memory 204960 kb
Host smart-38cb9fbc-6fb9-40e4-b249-ac34f11589d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013756456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.4013756456
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.4054989484
Short name T1231
Test name
Test status
Simulation time 774922474 ps
CPU time 4.27 seconds
Started Jun 06 02:48:54 PM PDT 24
Finished Jun 06 02:49:00 PM PDT 24
Peak memory 230344 kb
Host smart-bdc983ef-2de3-4390-8de9-8b54213d054d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054989484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
4054989484
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.107542949
Short name T671
Test name
Test status
Simulation time 5498592520 ps
CPU time 466.89 seconds
Started Jun 06 02:48:56 PM PDT 24
Finished Jun 06 02:56:44 PM PDT 24
Peak memory 1544708 kb
Host smart-18fddcec-42e4-4390-aa7e-e6b636e777f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107542949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.107542949
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.2536536627
Short name T1171
Test name
Test status
Simulation time 746964460 ps
CPU time 5.77 seconds
Started Jun 06 02:49:03 PM PDT 24
Finished Jun 06 02:49:10 PM PDT 24
Peak memory 205064 kb
Host smart-b9c98701-ea09-4db5-b9d9-20a8c9f59620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536536627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.2536536627
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.353282580
Short name T28
Test name
Test status
Simulation time 1773172444 ps
CPU time 72.67 seconds
Started Jun 06 02:49:06 PM PDT 24
Finished Jun 06 02:50:20 PM PDT 24
Peak memory 277380 kb
Host smart-41ce4627-7d13-447f-b1a0-7f24dea322c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353282580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.353282580
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.532636313
Short name T127
Test name
Test status
Simulation time 21279019 ps
CPU time 0.7 seconds
Started Jun 06 02:48:54 PM PDT 24
Finished Jun 06 02:48:56 PM PDT 24
Peak memory 204964 kb
Host smart-52ab7629-891d-46eb-a766-6d2af18d56b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532636313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.532636313
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.188594935
Short name T388
Test name
Test status
Simulation time 545777420 ps
CPU time 22.35 seconds
Started Jun 06 02:48:54 PM PDT 24
Finished Jun 06 02:49:18 PM PDT 24
Peak memory 229576 kb
Host smart-388ffcf1-27e7-4d7d-b8b2-1eb82028ffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188594935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.188594935
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.1796683515
Short name T1241
Test name
Test status
Simulation time 2933683937 ps
CPU time 21.25 seconds
Started Jun 06 02:48:53 PM PDT 24
Finished Jun 06 02:49:15 PM PDT 24
Peak memory 307384 kb
Host smart-d5c17827-4a74-41f6-bde9-c92e1c0f114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796683515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1796683515
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.1304527093
Short name T242
Test name
Test status
Simulation time 86390625405 ps
CPU time 412.74 seconds
Started Jun 06 02:49:02 PM PDT 24
Finished Jun 06 02:55:56 PM PDT 24
Peak memory 1549232 kb
Host smart-f39e076e-4212-4d8a-afbc-d66a0beb2977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304527093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.1304527093
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.874367113
Short name T850
Test name
Test status
Simulation time 796654365 ps
CPU time 12.56 seconds
Started Jun 06 02:48:54 PM PDT 24
Finished Jun 06 02:49:08 PM PDT 24
Peak memory 221068 kb
Host smart-bea21493-888c-4ee6-a07d-6ef204def947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874367113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.874367113
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1475671456
Short name T161
Test name
Test status
Simulation time 54733767 ps
CPU time 0.87 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 02:49:06 PM PDT 24
Peak memory 221988 kb
Host smart-f7d6ef23-fd98-4f96-aa34-9e3e306a22c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475671456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1475671456
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3640254752
Short name T557
Test name
Test status
Simulation time 549220008 ps
CPU time 2.77 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 02:49:09 PM PDT 24
Peak memory 205100 kb
Host smart-5c6046a7-5656-4c5b-80f9-dfc9706b5aab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640254752 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3640254752
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2768474839
Short name T1435
Test name
Test status
Simulation time 10125269700 ps
CPU time 45.1 seconds
Started Jun 06 02:49:05 PM PDT 24
Finished Jun 06 02:49:51 PM PDT 24
Peak memory 323092 kb
Host smart-71c7e026-6714-44b2-ab91-3f4b03161913
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768474839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2768474839
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.3744884527
Short name T77
Test name
Test status
Simulation time 10305988359 ps
CPU time 14.35 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 02:49:19 PM PDT 24
Peak memory 283008 kb
Host smart-a911174c-792f-42d8-870b-e3fec9560c30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744884527 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.3744884527
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.3393827261
Short name T1330
Test name
Test status
Simulation time 2112491168 ps
CPU time 2.71 seconds
Started Jun 06 02:49:06 PM PDT 24
Finished Jun 06 02:49:09 PM PDT 24
Peak memory 205012 kb
Host smart-83b36d74-77e4-42f8-986c-aa6e08824a2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393827261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.3393827261
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.3089053505
Short name T364
Test name
Test status
Simulation time 1533210000 ps
CPU time 1.82 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 02:49:07 PM PDT 24
Peak memory 205072 kb
Host smart-2e531031-e757-495c-8038-9afe62f649f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089053505 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.3089053505
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.4180130460
Short name T1255
Test name
Test status
Simulation time 1144387296 ps
CPU time 2.44 seconds
Started Jun 06 02:49:05 PM PDT 24
Finished Jun 06 02:49:08 PM PDT 24
Peak memory 205056 kb
Host smart-dd97cefa-3081-436c-8838-f5b3f770b9d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180130460 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.4180130460
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2977141634
Short name T1213
Test name
Test status
Simulation time 3565766859 ps
CPU time 4.7 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 02:49:10 PM PDT 24
Peak memory 208940 kb
Host smart-51282ae5-3b5f-42f4-9580-7a8ba07f433a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977141634 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2977141634
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2132595487
Short name T1465
Test name
Test status
Simulation time 27412293562 ps
CPU time 92.6 seconds
Started Jun 06 02:49:03 PM PDT 24
Finished Jun 06 02:50:37 PM PDT 24
Peak memory 1668320 kb
Host smart-ae0990ac-7ef6-4bc9-a839-0e7ba9d9001b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132595487 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2132595487
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3332978417
Short name T1334
Test name
Test status
Simulation time 4642715334 ps
CPU time 45.75 seconds
Started Jun 06 02:49:03 PM PDT 24
Finished Jun 06 02:49:50 PM PDT 24
Peak memory 205196 kb
Host smart-5cc7c81f-6495-44fc-a014-6b3262097858
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332978417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3332978417
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1887074301
Short name T562
Test name
Test status
Simulation time 5127338538 ps
CPU time 28.33 seconds
Started Jun 06 02:49:03 PM PDT 24
Finished Jun 06 02:49:33 PM PDT 24
Peak memory 221052 kb
Host smart-949d6ae6-eaf3-4a4f-b0f0-3199b03672df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887074301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1887074301
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.1916596141
Short name T952
Test name
Test status
Simulation time 19162695183 ps
CPU time 21.33 seconds
Started Jun 06 02:49:05 PM PDT 24
Finished Jun 06 02:49:27 PM PDT 24
Peak memory 205196 kb
Host smart-d94488db-b297-49ae-9917-404604c1b08c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916596141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.1916596141
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3537752087
Short name T455
Test name
Test status
Simulation time 30432992477 ps
CPU time 933.58 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 03:04:39 PM PDT 24
Peak memory 3914696 kb
Host smart-00b2135a-3df0-490c-808d-5d776dfb94b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537752087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3537752087
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1202655373
Short name T709
Test name
Test status
Simulation time 1427698707 ps
CPU time 8.17 seconds
Started Jun 06 02:49:02 PM PDT 24
Finished Jun 06 02:49:12 PM PDT 24
Peak memory 221340 kb
Host smart-81f39d03-acab-48f3-9e33-ca0da9543eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202655373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1202655373
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.34715854
Short name T117
Test name
Test status
Simulation time 1063225619 ps
CPU time 19.95 seconds
Started Jun 06 02:49:03 PM PDT 24
Finished Jun 06 02:49:24 PM PDT 24
Peak memory 205076 kb
Host smart-519b9ad9-4e28-45f6-830a-d05e60d4c625
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34715854 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.34715854
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.3282675244
Short name T722
Test name
Test status
Simulation time 19029851 ps
CPU time 0.67 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:13 PM PDT 24
Peak memory 204728 kb
Host smart-57aa67fe-9c7d-4ac8-8660-6555583cefc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282675244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.3282675244
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.2608553163
Short name T432
Test name
Test status
Simulation time 159063371 ps
CPU time 5.84 seconds
Started Jun 06 02:50:57 PM PDT 24
Finished Jun 06 02:51:04 PM PDT 24
Peak memory 221328 kb
Host smart-e05e40fa-d67f-459b-a1dd-047576ccd1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608553163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.2608553163
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1979040744
Short name T488
Test name
Test status
Simulation time 2125044250 ps
CPU time 10.24 seconds
Started Jun 06 02:50:59 PM PDT 24
Finished Jun 06 02:51:11 PM PDT 24
Peak memory 328308 kb
Host smart-c6bd3d9b-9fd7-4291-91d9-f9ec08ad1a65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979040744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1979040744
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.728863439
Short name T1273
Test name
Test status
Simulation time 1724681899 ps
CPU time 42.52 seconds
Started Jun 06 02:51:01 PM PDT 24
Finished Jun 06 02:51:45 PM PDT 24
Peak memory 459352 kb
Host smart-07b2e3fe-edc1-4827-a499-245d094f8afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728863439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.728863439
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.373084654
Short name T663
Test name
Test status
Simulation time 2184031118 ps
CPU time 166.24 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:53:46 PM PDT 24
Peak memory 700524 kb
Host smart-dd7a7769-5b6d-470c-91f5-a18ae489c5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373084654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.373084654
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3217422800
Short name T629
Test name
Test status
Simulation time 439486703 ps
CPU time 1.13 seconds
Started Jun 06 02:51:02 PM PDT 24
Finished Jun 06 02:51:05 PM PDT 24
Peak memory 205020 kb
Host smart-508ca07a-e3ea-4e05-8c69-704a0d0c5ed0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217422800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3217422800
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.759480807
Short name T925
Test name
Test status
Simulation time 1469082204 ps
CPU time 4.07 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:51:04 PM PDT 24
Peak memory 205084 kb
Host smart-ca5052ef-f947-42dd-be06-39aea82508ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759480807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx.
759480807
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2232448732
Short name T100
Test name
Test status
Simulation time 4352910369 ps
CPU time 110.18 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:52:50 PM PDT 24
Peak memory 1263424 kb
Host smart-e3fde94a-9215-45bd-93d9-753302105018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232448732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2232448732
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2686196525
Short name T166
Test name
Test status
Simulation time 359759928 ps
CPU time 5.95 seconds
Started Jun 06 02:51:06 PM PDT 24
Finished Jun 06 02:51:15 PM PDT 24
Peak memory 204984 kb
Host smart-07c5a446-7dbb-4b2b-bcd7-fffa8d56560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686196525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2686196525
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.1918569168
Short name T496
Test name
Test status
Simulation time 1668517914 ps
CPU time 28.38 seconds
Started Jun 06 02:51:08 PM PDT 24
Finished Jun 06 02:51:39 PM PDT 24
Peak memory 261940 kb
Host smart-2be2f86c-d8c8-41f8-a8c8-13b398e7502c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918569168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.1918569168
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.2174396939
Short name T739
Test name
Test status
Simulation time 14939933 ps
CPU time 0.67 seconds
Started Jun 06 02:51:02 PM PDT 24
Finished Jun 06 02:51:05 PM PDT 24
Peak memory 204696 kb
Host smart-bc48b3ae-f3dc-4ee0-8e92-113d96c317fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174396939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2174396939
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.686136305
Short name T286
Test name
Test status
Simulation time 7171995269 ps
CPU time 26.33 seconds
Started Jun 06 02:51:00 PM PDT 24
Finished Jun 06 02:51:28 PM PDT 24
Peak memory 205204 kb
Host smart-e2691a3e-c154-471d-9bc8-a303655ebcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686136305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.686136305
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2976079404
Short name T923
Test name
Test status
Simulation time 3265498662 ps
CPU time 34.38 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:51:34 PM PDT 24
Peak memory 365816 kb
Host smart-355853b9-a6c0-4c7a-b50d-f9dd7289eb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976079404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2976079404
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.663239467
Short name T912
Test name
Test status
Simulation time 26148916946 ps
CPU time 1215.45 seconds
Started Jun 06 02:51:00 PM PDT 24
Finished Jun 06 03:11:18 PM PDT 24
Peak memory 1667680 kb
Host smart-6354c20a-2aeb-4ec7-9177-830df8b05ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663239467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.663239467
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1041304179
Short name T241
Test name
Test status
Simulation time 1881907314 ps
CPU time 16.75 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:51:16 PM PDT 24
Peak memory 229672 kb
Host smart-2c3f2c37-deec-42be-a0f7-e79eff364287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041304179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1041304179
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3736003410
Short name T1065
Test name
Test status
Simulation time 4754810356 ps
CPU time 6.17 seconds
Started Jun 06 02:51:07 PM PDT 24
Finished Jun 06 02:51:16 PM PDT 24
Peak memory 214528 kb
Host smart-26c21af4-5493-4364-a1fb-94fec9ff5aa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736003410 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3736003410
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1230445655
Short name T822
Test name
Test status
Simulation time 10157437081 ps
CPU time 25.61 seconds
Started Jun 06 02:51:07 PM PDT 24
Finished Jun 06 02:51:36 PM PDT 24
Peak memory 283636 kb
Host smart-01f2c012-50e9-437a-bdf6-9d684e1068e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230445655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1230445655
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.4205705355
Short name T932
Test name
Test status
Simulation time 10432824280 ps
CPU time 5.35 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:18 PM PDT 24
Peak memory 228776 kb
Host smart-4fb0538c-b63f-438d-88f7-cf04fb6d32bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205705355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.4205705355
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.3638830710
Short name T828
Test name
Test status
Simulation time 1580034954 ps
CPU time 4.79 seconds
Started Jun 06 02:51:06 PM PDT 24
Finished Jun 06 02:51:14 PM PDT 24
Peak memory 205072 kb
Host smart-318a5d63-05fb-46c9-818e-c1329b210384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638830710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.3638830710
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.3581455349
Short name T931
Test name
Test status
Simulation time 1088349146 ps
CPU time 1.9 seconds
Started Jun 06 02:51:07 PM PDT 24
Finished Jun 06 02:51:12 PM PDT 24
Peak memory 205120 kb
Host smart-50876515-cb27-49ed-b602-e0e4d7116818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581455349 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.3581455349
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.1706315904
Short name T339
Test name
Test status
Simulation time 1467924463 ps
CPU time 2.76 seconds
Started Jun 06 02:51:07 PM PDT 24
Finished Jun 06 02:51:13 PM PDT 24
Peak memory 205100 kb
Host smart-b204fac4-def7-4254-98d9-65a801b2d09b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706315904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.1706315904
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.1407251338
Short name T969
Test name
Test status
Simulation time 4808867017 ps
CPU time 5.79 seconds
Started Jun 06 02:51:06 PM PDT 24
Finished Jun 06 02:51:15 PM PDT 24
Peak memory 213388 kb
Host smart-4e8f3bb9-163b-488d-b428-9f8fdad64d87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407251338 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.1407251338
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.464039930
Short name T674
Test name
Test status
Simulation time 10767933580 ps
CPU time 7.07 seconds
Started Jun 06 02:51:06 PM PDT 24
Finished Jun 06 02:51:16 PM PDT 24
Peak memory 234236 kb
Host smart-e60da802-c469-4b7a-b67a-ac24850d4f5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464039930 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.464039930
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2174221594
Short name T1284
Test name
Test status
Simulation time 3595871227 ps
CPU time 34.1 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:51:34 PM PDT 24
Peak memory 205168 kb
Host smart-05b8a8b4-b8e0-4be7-96f0-3e535ebc0225
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174221594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2174221594
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.1507671602
Short name T443
Test name
Test status
Simulation time 980399994 ps
CPU time 42.72 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:51:42 PM PDT 24
Peak memory 205132 kb
Host smart-bf48e151-7266-4425-9f15-875feb7d2f18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507671602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.1507671602
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.2570822899
Short name T1327
Test name
Test status
Simulation time 9777243855 ps
CPU time 11.47 seconds
Started Jun 06 02:50:57 PM PDT 24
Finished Jun 06 02:51:10 PM PDT 24
Peak memory 205064 kb
Host smart-3f9eeaca-dfd7-463e-9e07-3c4ec75cc48e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570822899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.2570822899
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2786325238
Short name T750
Test name
Test status
Simulation time 14086647826 ps
CPU time 233.07 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:54:53 PM PDT 24
Peak memory 1755584 kb
Host smart-806b4842-b60e-4232-9cbd-a6a5dda874e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786325238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2786325238
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3575030745
Short name T325
Test name
Test status
Simulation time 2419307651 ps
CPU time 6.83 seconds
Started Jun 06 02:51:08 PM PDT 24
Finished Jun 06 02:51:18 PM PDT 24
Peak memory 213380 kb
Host smart-2f3369c7-51cb-4b27-8497-e510455f1490
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575030745 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3575030745
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.322146016
Short name T1100
Test name
Test status
Simulation time 1049094187 ps
CPU time 18.81 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:32 PM PDT 24
Peak memory 205116 kb
Host smart-b620fb33-f2ef-40f5-a853-522e577b8f01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322146016 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.322146016
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1857165994
Short name T163
Test name
Test status
Simulation time 30068352 ps
CPU time 0.61 seconds
Started Jun 06 02:51:17 PM PDT 24
Finished Jun 06 02:51:22 PM PDT 24
Peak memory 204684 kb
Host smart-94de4238-c215-4685-a387-8e3b4c5f16b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857165994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1857165994
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.860636275
Short name T686
Test name
Test status
Simulation time 224175641 ps
CPU time 1.87 seconds
Started Jun 06 02:51:07 PM PDT 24
Finished Jun 06 02:51:12 PM PDT 24
Peak memory 213344 kb
Host smart-cd50e68d-3865-4083-a227-0fad903f17b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860636275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.860636275
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.1622553815
Short name T1020
Test name
Test status
Simulation time 218431430 ps
CPU time 10.91 seconds
Started Jun 06 02:51:08 PM PDT 24
Finished Jun 06 02:51:22 PM PDT 24
Peak memory 240812 kb
Host smart-d6e6fafe-324d-44f7-b193-1575edb03075
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622553815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.1622553815
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.894863277
Short name T624
Test name
Test status
Simulation time 4890459918 ps
CPU time 96.98 seconds
Started Jun 06 02:51:07 PM PDT 24
Finished Jun 06 02:52:46 PM PDT 24
Peak memory 494804 kb
Host smart-3d72902e-94e2-4d5b-9d16-b492aef64d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894863277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.894863277
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.461160066
Short name T1415
Test name
Test status
Simulation time 3207309949 ps
CPU time 186.75 seconds
Started Jun 06 02:51:07 PM PDT 24
Finished Jun 06 02:54:17 PM PDT 24
Peak memory 697200 kb
Host smart-d3e0f2c1-6366-4c3c-b064-21fc89519471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461160066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.461160066
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.48649837
Short name T900
Test name
Test status
Simulation time 120726456 ps
CPU time 1 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:13 PM PDT 24
Peak memory 204732 kb
Host smart-17e2498e-dc21-4540-938c-99aa34ed3979
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48649837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_fmt
.48649837
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.78190205
Short name T1474
Test name
Test status
Simulation time 1352315541 ps
CPU time 4.77 seconds
Started Jun 06 02:51:10 PM PDT 24
Finished Jun 06 02:51:19 PM PDT 24
Peak memory 232580 kb
Host smart-32a05edd-d014-4c65-89e6-b3aaf9abd295
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78190205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.78190205
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.3595021836
Short name T1272
Test name
Test status
Simulation time 3484529264 ps
CPU time 241.88 seconds
Started Jun 06 02:51:07 PM PDT 24
Finished Jun 06 02:55:11 PM PDT 24
Peak memory 967100 kb
Host smart-46e41dfa-3214-46f5-974e-3dd7bc279d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595021836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.3595021836
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.606357038
Short name T1286
Test name
Test status
Simulation time 398379399 ps
CPU time 14.46 seconds
Started Jun 06 02:51:16 PM PDT 24
Finished Jun 06 02:51:34 PM PDT 24
Peak memory 204812 kb
Host smart-5c07dbbe-cbd2-4d1f-b598-ec71441ed618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606357038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.606357038
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3390787102
Short name T605
Test name
Test status
Simulation time 2525813243 ps
CPU time 59.01 seconds
Started Jun 06 02:51:15 PM PDT 24
Finished Jun 06 02:52:18 PM PDT 24
Peak memory 315020 kb
Host smart-d61c969a-2a38-46dc-9def-041e18b2d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390787102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3390787102
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.1766960043
Short name T1174
Test name
Test status
Simulation time 47971474 ps
CPU time 0.65 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:13 PM PDT 24
Peak memory 204700 kb
Host smart-4ca9e7e6-d6c8-4ca9-af30-9d0d7de5293d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766960043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1766960043
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.3392866930
Short name T677
Test name
Test status
Simulation time 12491978798 ps
CPU time 319.88 seconds
Started Jun 06 02:51:08 PM PDT 24
Finished Jun 06 02:56:32 PM PDT 24
Peak memory 1275232 kb
Host smart-4fdc4411-997d-4c3b-96e7-9c1fa0269521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392866930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.3392866930
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2804120636
Short name T977
Test name
Test status
Simulation time 7623378882 ps
CPU time 31.36 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:43 PM PDT 24
Peak memory 331812 kb
Host smart-30d67667-4fd7-4c0f-98ad-cac879c24eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804120636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2804120636
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1426779313
Short name T533
Test name
Test status
Simulation time 9553140544 ps
CPU time 32.31 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:45 PM PDT 24
Peak memory 213392 kb
Host smart-fde7d728-ba45-4676-8596-d814ba72638f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426779313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1426779313
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1856153874
Short name T310
Test name
Test status
Simulation time 1392691816 ps
CPU time 3.52 seconds
Started Jun 06 02:51:17 PM PDT 24
Finished Jun 06 02:51:25 PM PDT 24
Peak memory 205120 kb
Host smart-50fa7e44-21db-4631-bb12-ebc616da9623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856153874 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1856153874
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.835802985
Short name T1359
Test name
Test status
Simulation time 10105541511 ps
CPU time 45.81 seconds
Started Jun 06 02:51:15 PM PDT 24
Finished Jun 06 02:52:05 PM PDT 24
Peak memory 334316 kb
Host smart-285e0968-e211-4fa1-bfe1-74a24c067c58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835802985 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.835802985
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.3786680373
Short name T76
Test name
Test status
Simulation time 10071977518 ps
CPU time 76.59 seconds
Started Jun 06 02:51:16 PM PDT 24
Finished Jun 06 02:52:37 PM PDT 24
Peak memory 483196 kb
Host smart-36e2d724-3b7c-4bc9-99ac-105bf99fd525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786680373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.3786680373
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.1468957913
Short name T1070
Test name
Test status
Simulation time 1097288194 ps
CPU time 5.38 seconds
Started Jun 06 02:51:18 PM PDT 24
Finished Jun 06 02:51:28 PM PDT 24
Peak memory 205068 kb
Host smart-292cc6a0-a7a8-4ede-8723-119a1f9aef01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468957913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.1468957913
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.132569760
Short name T1321
Test name
Test status
Simulation time 1026215612 ps
CPU time 4.77 seconds
Started Jun 06 02:51:17 PM PDT 24
Finished Jun 06 02:51:26 PM PDT 24
Peak memory 205128 kb
Host smart-b5078243-a9d1-4eea-a977-478d4d128490
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132569760 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.132569760
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.1665137437
Short name T1367
Test name
Test status
Simulation time 411467745 ps
CPU time 2.77 seconds
Started Jun 06 02:51:14 PM PDT 24
Finished Jun 06 02:51:20 PM PDT 24
Peak memory 205092 kb
Host smart-ee676134-3998-4947-92d1-e68a3e9a0b89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665137437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.1665137437
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3587301913
Short name T804
Test name
Test status
Simulation time 15651912136 ps
CPU time 325.36 seconds
Started Jun 06 02:51:16 PM PDT 24
Finished Jun 06 02:56:46 PM PDT 24
Peak memory 3915216 kb
Host smart-35f2f434-5f5f-416b-bbfd-bb9c805758b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587301913 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3587301913
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2300648269
Short name T370
Test name
Test status
Simulation time 16035909821 ps
CPU time 33.03 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:46 PM PDT 24
Peak memory 205156 kb
Host smart-2e90bebd-7152-42f3-ac13-df257fce4284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300648269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2300648269
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.568955030
Short name T895
Test name
Test status
Simulation time 1984680507 ps
CPU time 9.15 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 02:51:22 PM PDT 24
Peak memory 205188 kb
Host smart-0372f206-1bc3-471a-a45b-2c7ddf463d51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568955030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_rd.568955030
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.3443858798
Short name T1006
Test name
Test status
Simulation time 48751758602 ps
CPU time 37.22 seconds
Started Jun 06 02:51:06 PM PDT 24
Finished Jun 06 02:51:45 PM PDT 24
Peak memory 705224 kb
Host smart-0b7157ef-262d-4333-9f20-0d2059dcf471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443858798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.3443858798
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.315167164
Short name T3
Test name
Test status
Simulation time 28734760829 ps
CPU time 786.5 seconds
Started Jun 06 02:51:09 PM PDT 24
Finished Jun 06 03:04:19 PM PDT 24
Peak memory 3438088 kb
Host smart-6ad553a9-5fd0-4b3e-a833-4cfc3e2e8cdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315167164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_t
arget_stretch.315167164
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.768629858
Short name T1220
Test name
Test status
Simulation time 1223374512 ps
CPU time 7.04 seconds
Started Jun 06 02:51:16 PM PDT 24
Finished Jun 06 02:51:27 PM PDT 24
Peak memory 211972 kb
Host smart-c9b0a9fa-db06-4a10-8c2e-246f8f48afed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768629858 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.768629858
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.369625775
Short name T1388
Test name
Test status
Simulation time 1031180755 ps
CPU time 19.04 seconds
Started Jun 06 02:51:16 PM PDT 24
Finished Jun 06 02:51:39 PM PDT 24
Peak memory 205096 kb
Host smart-35c756f6-96e0-47bf-88c3-43e4e817b4e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369625775 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.369625775
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.956156946
Short name T1218
Test name
Test status
Simulation time 33001833 ps
CPU time 0.61 seconds
Started Jun 06 02:51:26 PM PDT 24
Finished Jun 06 02:51:28 PM PDT 24
Peak memory 204764 kb
Host smart-5049db2d-5ce5-450f-874b-580828cdc30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956156946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.956156946
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2061787169
Short name T44
Test name
Test status
Simulation time 346837002 ps
CPU time 2.73 seconds
Started Jun 06 02:51:18 PM PDT 24
Finished Jun 06 02:51:25 PM PDT 24
Peak memory 213312 kb
Host smart-28decc07-a859-409b-848d-c1b9df7688c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061787169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2061787169
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.245700488
Short name T980
Test name
Test status
Simulation time 839218915 ps
CPU time 9.63 seconds
Started Jun 06 02:51:15 PM PDT 24
Finished Jun 06 02:51:29 PM PDT 24
Peak memory 227412 kb
Host smart-90ed8b1a-c39a-4322-a500-1cdc1f9890e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245700488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.245700488
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1336513703
Short name T1013
Test name
Test status
Simulation time 11167113131 ps
CPU time 128.59 seconds
Started Jun 06 02:51:15 PM PDT 24
Finished Jun 06 02:53:27 PM PDT 24
Peak memory 602000 kb
Host smart-106c7b4e-c011-404f-8ff8-b115d03d1c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336513703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1336513703
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.628069154
Short name T436
Test name
Test status
Simulation time 5346510857 ps
CPU time 102.05 seconds
Started Jun 06 02:51:17 PM PDT 24
Finished Jun 06 02:53:03 PM PDT 24
Peak memory 778048 kb
Host smart-137339a9-fb8a-4eda-8785-a090a8a12349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628069154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.628069154
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2620964918
Short name T860
Test name
Test status
Simulation time 3794870313 ps
CPU time 270.07 seconds
Started Jun 06 02:51:14 PM PDT 24
Finished Jun 06 02:55:48 PM PDT 24
Peak memory 1052640 kb
Host smart-bbd8a981-57ea-4460-adbe-6e9daa0acfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620964918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2620964918
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.3204418713
Short name T1410
Test name
Test status
Simulation time 389090692 ps
CPU time 5.07 seconds
Started Jun 06 02:51:26 PM PDT 24
Finished Jun 06 02:51:33 PM PDT 24
Peak memory 205040 kb
Host smart-f3ed1cd4-339c-4a92-9144-e8dc3ad1b9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204418713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.3204418713
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.2951079644
Short name T917
Test name
Test status
Simulation time 49909482 ps
CPU time 0.73 seconds
Started Jun 06 02:51:16 PM PDT 24
Finished Jun 06 02:51:21 PM PDT 24
Peak memory 204956 kb
Host smart-ae7f00e2-4bee-49e9-b706-049580f0708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951079644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2951079644
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.3564163107
Short name T1340
Test name
Test status
Simulation time 7252763350 ps
CPU time 21.99 seconds
Started Jun 06 02:51:22 PM PDT 24
Finished Jun 06 02:51:46 PM PDT 24
Peak memory 229572 kb
Host smart-f7b5dee6-784a-4725-a6ce-6a26a5fe9e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564163107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.3564163107
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.4042176117
Short name T844
Test name
Test status
Simulation time 8035413967 ps
CPU time 37.71 seconds
Started Jun 06 02:51:21 PM PDT 24
Finished Jun 06 02:52:01 PM PDT 24
Peak memory 414460 kb
Host smart-ba4ad578-dc71-4b88-9c3c-602c65e84dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042176117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.4042176117
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.4242052016
Short name T256
Test name
Test status
Simulation time 60086589092 ps
CPU time 1801.19 seconds
Started Jun 06 02:51:24 PM PDT 24
Finished Jun 06 03:21:27 PM PDT 24
Peak memory 2635404 kb
Host smart-c8b1b69f-b35c-49f1-a2e0-831ea8f26480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242052016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.4242052016
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.1138775249
Short name T948
Test name
Test status
Simulation time 744484968 ps
CPU time 15.08 seconds
Started Jun 06 02:51:22 PM PDT 24
Finished Jun 06 02:51:39 PM PDT 24
Peak memory 221332 kb
Host smart-97da01dc-3be0-4c66-b00a-d35af07a386c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138775249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.1138775249
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3577780392
Short name T1182
Test name
Test status
Simulation time 1944928035 ps
CPU time 4.91 seconds
Started Jun 06 02:51:29 PM PDT 24
Finished Jun 06 02:51:35 PM PDT 24
Peak memory 213496 kb
Host smart-38846632-fd0e-4e84-8311-26c8ef120d8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577780392 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3577780392
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.2181793982
Short name T372
Test name
Test status
Simulation time 10099470218 ps
CPU time 46.13 seconds
Started Jun 06 02:51:24 PM PDT 24
Finished Jun 06 02:52:12 PM PDT 24
Peak memory 348644 kb
Host smart-7fb043be-f2f8-43e6-b59d-bcc778e28b76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181793982 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.2181793982
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3036148067
Short name T1120
Test name
Test status
Simulation time 10179779401 ps
CPU time 10.82 seconds
Started Jun 06 02:51:25 PM PDT 24
Finished Jun 06 02:51:38 PM PDT 24
Peak memory 267360 kb
Host smart-902539f6-7b3c-442f-b0f1-e174ef922ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036148067 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.3036148067
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.2139921811
Short name T679
Test name
Test status
Simulation time 1833799296 ps
CPU time 2.71 seconds
Started Jun 06 02:51:27 PM PDT 24
Finished Jun 06 02:51:32 PM PDT 24
Peak memory 205052 kb
Host smart-2d3eb34d-f04a-419b-8621-9d0ea8b83a55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139921811 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.2139921811
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.795001695
Short name T236
Test name
Test status
Simulation time 1076529727 ps
CPU time 6.15 seconds
Started Jun 06 02:51:28 PM PDT 24
Finished Jun 06 02:51:36 PM PDT 24
Peak memory 205072 kb
Host smart-edc5dc93-c982-4a3c-94af-fe97d82a9eea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795001695 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.795001695
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.4224444450
Short name T705
Test name
Test status
Simulation time 816255890 ps
CPU time 4.55 seconds
Started Jun 06 02:51:23 PM PDT 24
Finished Jun 06 02:51:29 PM PDT 24
Peak memory 205032 kb
Host smart-5bef07d2-b534-436b-b749-74a890e48986
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224444450 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.4224444450
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1910691732
Short name T919
Test name
Test status
Simulation time 22760184292 ps
CPU time 497.47 seconds
Started Jun 06 02:51:24 PM PDT 24
Finished Jun 06 02:59:44 PM PDT 24
Peak memory 5241164 kb
Host smart-2df5719b-5feb-4dbe-8008-a7fb9873d701
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910691732 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1910691732
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3119754840
Short name T1
Test name
Test status
Simulation time 1937849325 ps
CPU time 12.69 seconds
Started Jun 06 02:51:23 PM PDT 24
Finished Jun 06 02:51:37 PM PDT 24
Peak memory 205036 kb
Host smart-bf0af794-b7fb-492a-a794-bf695161dd2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119754840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3119754840
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.1570014903
Short name T511
Test name
Test status
Simulation time 568127125 ps
CPU time 24.71 seconds
Started Jun 06 02:51:24 PM PDT 24
Finished Jun 06 02:51:51 PM PDT 24
Peak memory 205024 kb
Host smart-fdf496e7-1a50-4c7d-9382-50bc1aeb208c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570014903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.1570014903
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.1645771735
Short name T781
Test name
Test status
Simulation time 29458974307 ps
CPU time 74.5 seconds
Started Jun 06 02:51:25 PM PDT 24
Finished Jun 06 02:52:41 PM PDT 24
Peak memory 1186964 kb
Host smart-fb4ccab4-515c-42c3-87db-23ff0bbfc38f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645771735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.1645771735
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.58389196
Short name T1285
Test name
Test status
Simulation time 3236283564 ps
CPU time 8.47 seconds
Started Jun 06 02:51:26 PM PDT 24
Finished Jun 06 02:51:36 PM PDT 24
Peak memory 212432 kb
Host smart-8a7eab72-165d-45e0-b1ee-445b91a39e99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58389196 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_timeout.58389196
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.2299776649
Short name T521
Test name
Test status
Simulation time 1038326102 ps
CPU time 19.76 seconds
Started Jun 06 02:51:24 PM PDT 24
Finished Jun 06 02:51:46 PM PDT 24
Peak memory 205096 kb
Host smart-47cc30be-2f60-4b04-9293-741d03df13d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299776649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.2299776649
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2020366030
Short name T1211
Test name
Test status
Simulation time 15540949 ps
CPU time 0.68 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:51:39 PM PDT 24
Peak memory 204740 kb
Host smart-3cbbb32f-ea99-4e9a-b4e8-f9a3f3f3e9f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020366030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2020366030
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3747572710
Short name T845
Test name
Test status
Simulation time 650560173 ps
CPU time 2.13 seconds
Started Jun 06 02:51:32 PM PDT 24
Finished Jun 06 02:51:37 PM PDT 24
Peak memory 213252 kb
Host smart-98ac776e-827d-46b1-a7e3-4d8350d1b04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747572710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3747572710
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.4275430991
Short name T265
Test name
Test status
Simulation time 319011379 ps
CPU time 16.46 seconds
Started Jun 06 02:51:35 PM PDT 24
Finished Jun 06 02:51:55 PM PDT 24
Peak memory 249876 kb
Host smart-f51148ba-fbe3-441f-ab81-310fb581c2ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275430991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.4275430991
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.850580174
Short name T1078
Test name
Test status
Simulation time 11691092388 ps
CPU time 218.7 seconds
Started Jun 06 02:51:33 PM PDT 24
Finished Jun 06 02:55:15 PM PDT 24
Peak memory 812868 kb
Host smart-c3d9d8c9-a27b-474e-9f45-6e87beb31204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850580174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.850580174
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3448836558
Short name T1299
Test name
Test status
Simulation time 2312435313 ps
CPU time 182.98 seconds
Started Jun 06 02:51:29 PM PDT 24
Finished Jun 06 02:54:33 PM PDT 24
Peak memory 780428 kb
Host smart-9f987574-3ec6-4c65-b249-e011ce5b67d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448836558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3448836558
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2019588353
Short name T1451
Test name
Test status
Simulation time 510176404 ps
CPU time 1.1 seconds
Started Jun 06 02:51:35 PM PDT 24
Finished Jun 06 02:51:40 PM PDT 24
Peak memory 204968 kb
Host smart-9cbccda0-8583-46a2-8432-9fd375651b5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019588353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2019588353
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.495921516
Short name T1254
Test name
Test status
Simulation time 165811873 ps
CPU time 4.61 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:51:43 PM PDT 24
Peak memory 233736 kb
Host smart-23bb6e7b-3b44-4d2c-a91a-39b12631110d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495921516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx.
495921516
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.1300754404
Short name T1398
Test name
Test status
Simulation time 18401734927 ps
CPU time 108.43 seconds
Started Jun 06 02:51:26 PM PDT 24
Finished Jun 06 02:53:17 PM PDT 24
Peak memory 1225436 kb
Host smart-ce8db41d-f06f-4df8-8b4c-4cc79faf0e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300754404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.1300754404
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.2311432462
Short name T918
Test name
Test status
Simulation time 588995948 ps
CPU time 7.44 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:51:46 PM PDT 24
Peak memory 204956 kb
Host smart-f04a6fdd-64c4-4feb-a2a9-97bfad7d60f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311432462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2311432462
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.126556131
Short name T538
Test name
Test status
Simulation time 1758689489 ps
CPU time 33.87 seconds
Started Jun 06 02:51:36 PM PDT 24
Finished Jun 06 02:52:13 PM PDT 24
Peak memory 331788 kb
Host smart-80364db1-f547-4488-b424-ad82a6ebf174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126556131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.126556131
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.4207003680
Short name T534
Test name
Test status
Simulation time 75293127 ps
CPU time 0.74 seconds
Started Jun 06 02:51:29 PM PDT 24
Finished Jun 06 02:51:31 PM PDT 24
Peak memory 204720 kb
Host smart-2d41bbc1-075b-43c7-a3f7-94d530d587e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207003680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.4207003680
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.1450592016
Short name T951
Test name
Test status
Simulation time 27483962600 ps
CPU time 20.6 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:51:58 PM PDT 24
Peak memory 213312 kb
Host smart-6a41fc52-14d1-4c04-b85d-888ebcc7434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450592016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.1450592016
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2190325257
Short name T753
Test name
Test status
Simulation time 3111145481 ps
CPU time 26.14 seconds
Started Jun 06 02:51:25 PM PDT 24
Finished Jun 06 02:51:53 PM PDT 24
Peak memory 362844 kb
Host smart-b20cb83e-3fa8-4dac-b0fa-e271f158aac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190325257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2190325257
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.1653102038
Short name T1434
Test name
Test status
Simulation time 58377769118 ps
CPU time 1408.55 seconds
Started Jun 06 02:51:30 PM PDT 24
Finished Jun 06 03:15:01 PM PDT 24
Peak memory 1678608 kb
Host smart-1a48f399-c229-429d-a523-cc4003a4b0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653102038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.1653102038
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3723462384
Short name T867
Test name
Test status
Simulation time 1328864917 ps
CPU time 12.4 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:51:50 PM PDT 24
Peak memory 214264 kb
Host smart-26492823-c3f0-4367-a0ca-915e1bf1b93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723462384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3723462384
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3197773031
Short name T1197
Test name
Test status
Simulation time 564308944 ps
CPU time 2.87 seconds
Started Jun 06 02:51:47 PM PDT 24
Finished Jun 06 02:51:52 PM PDT 24
Peak memory 205088 kb
Host smart-a13be111-deb6-40a2-9a34-d34373a76e46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197773031 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3197773031
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.4049429251
Short name T371
Test name
Test status
Simulation time 10085603216 ps
CPU time 22.38 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:52:01 PM PDT 24
Peak memory 284784 kb
Host smart-da434ff3-be22-4c9f-8e89-2c32d28260f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049429251 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.4049429251
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.1283378697
Short name T569
Test name
Test status
Simulation time 10712033159 ps
CPU time 7.61 seconds
Started Jun 06 02:51:33 PM PDT 24
Finished Jun 06 02:51:45 PM PDT 24
Peak memory 254084 kb
Host smart-7a156cb5-bb61-49bc-bf57-be7165d08136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283378697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.1283378697
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.2235691395
Short name T608
Test name
Test status
Simulation time 1099115138 ps
CPU time 5.47 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:51:43 PM PDT 24
Peak memory 205116 kb
Host smart-6e267d7b-87d6-4c0e-be5d-fbb7ef5d0fdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235691395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.2235691395
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.149531034
Short name T401
Test name
Test status
Simulation time 1288475660 ps
CPU time 2 seconds
Started Jun 06 02:51:31 PM PDT 24
Finished Jun 06 02:51:35 PM PDT 24
Peak memory 205108 kb
Host smart-d87f1355-2402-47e1-b5e2-3369b04f1ce3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149531034 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.149531034
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_hrst.1097047645
Short name T349
Test name
Test status
Simulation time 497627130 ps
CPU time 2.76 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:51:41 PM PDT 24
Peak memory 205204 kb
Host smart-ba494aab-80cd-4241-aff8-613364172219
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097047645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_hrst.1097047645
Directory /workspace/13.i2c_target_hrst/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2729147248
Short name T1239
Test name
Test status
Simulation time 2574694663 ps
CPU time 7.46 seconds
Started Jun 06 02:51:32 PM PDT 24
Finished Jun 06 02:51:42 PM PDT 24
Peak memory 211688 kb
Host smart-1eb498d3-0ac5-4ae7-86e0-c434d8848bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729147248 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2729147248
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.3261714849
Short name T905
Test name
Test status
Simulation time 20174934934 ps
CPU time 428.54 seconds
Started Jun 06 02:51:33 PM PDT 24
Finished Jun 06 02:58:45 PM PDT 24
Peak memory 4672280 kb
Host smart-9cd43c20-b060-4267-950f-4d3f993d23d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261714849 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.3261714849
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.1647339837
Short name T1122
Test name
Test status
Simulation time 1675235647 ps
CPU time 10.71 seconds
Started Jun 06 02:51:32 PM PDT 24
Finished Jun 06 02:51:45 PM PDT 24
Peak memory 205020 kb
Host smart-05a840e0-84c3-42ea-aeaf-75cc684cd987
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647339837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.1647339837
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.3112335939
Short name T698
Test name
Test status
Simulation time 3155159812 ps
CPU time 22.9 seconds
Started Jun 06 02:51:33 PM PDT 24
Finished Jun 06 02:52:00 PM PDT 24
Peak memory 226928 kb
Host smart-a8a230b8-fab8-4293-adf4-ea3e65d16d18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112335939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.3112335939
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.3850628124
Short name T1312
Test name
Test status
Simulation time 16259932384 ps
CPU time 17.63 seconds
Started Jun 06 02:51:35 PM PDT 24
Finished Jun 06 02:51:56 PM PDT 24
Peak memory 205116 kb
Host smart-93360d11-fe5b-42e1-b79e-98a972b429dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850628124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.3850628124
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.4158335552
Short name T1300
Test name
Test status
Simulation time 7837702476 ps
CPU time 59.58 seconds
Started Jun 06 02:51:33 PM PDT 24
Finished Jun 06 02:52:36 PM PDT 24
Peak memory 926172 kb
Host smart-6d29ec5b-e78b-4356-ab69-58678ae73406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158335552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.4158335552
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.3426077383
Short name T377
Test name
Test status
Simulation time 1588098807 ps
CPU time 7.28 seconds
Started Jun 06 02:51:33 PM PDT 24
Finished Jun 06 02:51:44 PM PDT 24
Peak memory 218512 kb
Host smart-82bf4831-3b6a-4182-8965-fe73b6fc286d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426077383 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.3426077383
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.694755290
Short name T1237
Test name
Test status
Simulation time 1120002782 ps
CPU time 16.19 seconds
Started Jun 06 02:51:35 PM PDT 24
Finished Jun 06 02:51:55 PM PDT 24
Peak memory 205056 kb
Host smart-563f2f70-2469-44c3-b768-01e71595a67e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694755290 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.694755290
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.2041628165
Short name T609
Test name
Test status
Simulation time 15755837 ps
CPU time 0.63 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:51:54 PM PDT 24
Peak memory 204624 kb
Host smart-49fe1cc2-b261-44fd-abe2-301a6a6f3bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041628165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.2041628165
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2740994515
Short name T361
Test name
Test status
Simulation time 247694991 ps
CPU time 2.68 seconds
Started Jun 06 02:51:43 PM PDT 24
Finished Jun 06 02:51:48 PM PDT 24
Peak memory 213312 kb
Host smart-f4fc3c6b-6a4f-40d0-8125-23e95585b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740994515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2740994515
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.4228656907
Short name T1270
Test name
Test status
Simulation time 421123426 ps
CPU time 8.06 seconds
Started Jun 06 02:51:41 PM PDT 24
Finished Jun 06 02:51:52 PM PDT 24
Peak memory 289652 kb
Host smart-d63d3205-b341-4bae-805b-0847a7ce2fd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228656907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.4228656907
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.108690350
Short name T922
Test name
Test status
Simulation time 5814169222 ps
CPU time 47.8 seconds
Started Jun 06 02:51:41 PM PDT 24
Finished Jun 06 02:52:31 PM PDT 24
Peak memory 553412 kb
Host smart-9b0fd7cc-f1f7-44b7-ade3-8aec82fb8274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108690350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.108690350
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3159625440
Short name T901
Test name
Test status
Simulation time 5830677840 ps
CPU time 39.27 seconds
Started Jun 06 02:51:34 PM PDT 24
Finished Jun 06 02:52:16 PM PDT 24
Peak memory 499764 kb
Host smart-46f7b7b0-f64f-487f-bf1f-ffda6b65c897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159625440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3159625440
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.3876563027
Short name T214
Test name
Test status
Simulation time 100582006 ps
CPU time 0.93 seconds
Started Jun 06 02:51:32 PM PDT 24
Finished Jun 06 02:51:35 PM PDT 24
Peak memory 204772 kb
Host smart-d1f99df0-c3d4-4577-b42d-94d38decfe8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876563027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.3876563027
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.1604308402
Short name T1450
Test name
Test status
Simulation time 395483161 ps
CPU time 5.53 seconds
Started Jun 06 02:51:49 PM PDT 24
Finished Jun 06 02:51:57 PM PDT 24
Peak memory 243736 kb
Host smart-387ecaf2-278d-4bf7-bddf-466374c840be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604308402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.1604308402
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.3282993841
Short name T1258
Test name
Test status
Simulation time 22162669356 ps
CPU time 181.78 seconds
Started Jun 06 02:51:35 PM PDT 24
Finished Jun 06 02:54:41 PM PDT 24
Peak memory 1501668 kb
Host smart-4faf377e-7cce-463a-b4cb-557b7399ba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282993841 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.3282993841
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.2033018142
Short name T602
Test name
Test status
Simulation time 674645867 ps
CPU time 10.76 seconds
Started Jun 06 02:51:51 PM PDT 24
Finished Jun 06 02:52:05 PM PDT 24
Peak memory 205064 kb
Host smart-99f8f70b-ec83-46ec-bb4e-1f8ff690ee20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033018142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.2033018142
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.3115461995
Short name T264
Test name
Test status
Simulation time 12594243324 ps
CPU time 28.31 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:52:21 PM PDT 24
Peak memory 340776 kb
Host smart-053a3fc2-3b0e-4cac-ba1f-72ef202cf6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115461995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.3115461995
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3276509475
Short name T805
Test name
Test status
Simulation time 19781958 ps
CPU time 0.65 seconds
Started Jun 06 02:51:32 PM PDT 24
Finished Jun 06 02:51:36 PM PDT 24
Peak memory 204708 kb
Host smart-62310d95-7f53-4b76-be58-0c4afbb5d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276509475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3276509475
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1991388982
Short name T737
Test name
Test status
Simulation time 7327264194 ps
CPU time 45.18 seconds
Started Jun 06 02:51:41 PM PDT 24
Finished Jun 06 02:52:29 PM PDT 24
Peak memory 551772 kb
Host smart-667df705-9f0d-4cf0-b45d-025811c15e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991388982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1991388982
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3938296647
Short name T1338
Test name
Test status
Simulation time 19544063739 ps
CPU time 29.38 seconds
Started Jun 06 02:51:32 PM PDT 24
Finished Jun 06 02:52:04 PM PDT 24
Peak memory 282372 kb
Host smart-bef36a99-8f44-4700-ae34-1282f1156875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938296647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3938296647
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.2359866863
Short name T423
Test name
Test status
Simulation time 2631596932 ps
CPU time 29.08 seconds
Started Jun 06 02:51:42 PM PDT 24
Finished Jun 06 02:52:13 PM PDT 24
Peak memory 213380 kb
Host smart-6562d8f7-b835-4207-9359-26a96e6ef9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359866863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.2359866863
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1053422865
Short name T1328
Test name
Test status
Simulation time 1034708086 ps
CPU time 1.75 seconds
Started Jun 06 02:51:48 PM PDT 24
Finished Jun 06 02:51:52 PM PDT 24
Peak memory 205080 kb
Host smart-5094eb66-2308-4670-b8ed-74455c9e5d05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053422865 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1053422865
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2146687876
Short name T894
Test name
Test status
Simulation time 10073185694 ps
CPU time 38.8 seconds
Started Jun 06 02:51:47 PM PDT 24
Finished Jun 06 02:52:28 PM PDT 24
Peak memory 317520 kb
Host smart-3064fdae-53da-4b29-9c5f-8dd442e1e750
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146687876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2146687876
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.3679322069
Short name T1389
Test name
Test status
Simulation time 10427090320 ps
CPU time 16.32 seconds
Started Jun 06 02:51:44 PM PDT 24
Finished Jun 06 02:52:03 PM PDT 24
Peak memory 321368 kb
Host smart-bfd9b0f1-8105-4c75-928d-6cce3f983995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679322069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.3679322069
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.431556278
Short name T221
Test name
Test status
Simulation time 1131013164 ps
CPU time 1.66 seconds
Started Jun 06 02:51:48 PM PDT 24
Finished Jun 06 02:51:52 PM PDT 24
Peak memory 205124 kb
Host smart-e708abee-7043-4526-9d66-d94c93d3239b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431556278 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.431556278
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.105686045
Short name T235
Test name
Test status
Simulation time 1106693462 ps
CPU time 1.17 seconds
Started Jun 06 02:51:49 PM PDT 24
Finished Jun 06 02:51:53 PM PDT 24
Peak memory 204844 kb
Host smart-400354ea-4d15-4b84-b28b-6505d7a7a795
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105686045 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.105686045
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.3905981495
Short name T1318
Test name
Test status
Simulation time 1652422210 ps
CPU time 3.19 seconds
Started Jun 06 02:51:49 PM PDT 24
Finished Jun 06 02:51:55 PM PDT 24
Peak memory 205084 kb
Host smart-cf6f2403-6c10-4ff8-90aa-15136eabfca7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905981495 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.3905981495
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.3866127202
Short name T1353
Test name
Test status
Simulation time 4436730268 ps
CPU time 16.92 seconds
Started Jun 06 02:51:42 PM PDT 24
Finished Jun 06 02:52:02 PM PDT 24
Peak memory 666292 kb
Host smart-0624fe51-8075-4c4f-846f-2cb3755a0871
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866127202 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.3866127202
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.915017025
Short name T306
Test name
Test status
Simulation time 5649947185 ps
CPU time 12.03 seconds
Started Jun 06 02:51:45 PM PDT 24
Finished Jun 06 02:52:00 PM PDT 24
Peak memory 205296 kb
Host smart-9ed8fd14-a762-4e88-9ff7-2656206c5b11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915017025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.915017025
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.494080855
Short name T271
Test name
Test status
Simulation time 1548678806 ps
CPU time 68.29 seconds
Started Jun 06 02:51:41 PM PDT 24
Finished Jun 06 02:52:52 PM PDT 24
Peak memory 208068 kb
Host smart-3834fb94-3a2b-4ee6-a655-5cf3ee7fb3b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494080855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.494080855
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.731409452
Short name T1209
Test name
Test status
Simulation time 28124929885 ps
CPU time 5.81 seconds
Started Jun 06 02:51:41 PM PDT 24
Finished Jun 06 02:51:49 PM PDT 24
Peak memory 205112 kb
Host smart-a02a9556-d5c3-4c8d-a1da-dcf1aa6d8f23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731409452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_wr.731409452
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.729473137
Short name T1346
Test name
Test status
Simulation time 21508689991 ps
CPU time 99.03 seconds
Started Jun 06 02:51:40 PM PDT 24
Finished Jun 06 02:53:22 PM PDT 24
Peak memory 485920 kb
Host smart-5fb085b3-d29d-4799-84ae-ebb406a9e006
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729473137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_t
arget_stretch.729473137
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2768044022
Short name T354
Test name
Test status
Simulation time 6480561386 ps
CPU time 8.17 seconds
Started Jun 06 02:51:41 PM PDT 24
Finished Jun 06 02:51:52 PM PDT 24
Peak memory 220032 kb
Host smart-6878f699-7b8e-44c0-a2af-5ca32178daa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768044022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2768044022
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.1321050848
Short name T1290
Test name
Test status
Simulation time 1040195280 ps
CPU time 16.36 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:52:10 PM PDT 24
Peak memory 205092 kb
Host smart-36b33a81-3fca-4e58-88ca-8725813c31c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321050848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.1321050848
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.2644577560
Short name T1361
Test name
Test status
Simulation time 136797535 ps
CPU time 0.63 seconds
Started Jun 06 02:51:57 PM PDT 24
Finished Jun 06 02:52:00 PM PDT 24
Peak memory 204712 kb
Host smart-625c1a01-fca6-4206-9113-800f00f966e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644577560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.2644577560
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.1244031944
Short name T778
Test name
Test status
Simulation time 98482194 ps
CPU time 2.34 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:51:56 PM PDT 24
Peak memory 213108 kb
Host smart-e8385f5f-b717-4e40-9e7e-f947b29b33d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244031944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.1244031944
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.442825541
Short name T1293
Test name
Test status
Simulation time 1783920197 ps
CPU time 8.02 seconds
Started Jun 06 02:51:49 PM PDT 24
Finished Jun 06 02:52:00 PM PDT 24
Peak memory 298596 kb
Host smart-a3344c3d-8faf-4739-9f5c-fffecbcdb461
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442825541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_empt
y.442825541
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.42396547
Short name T38
Test name
Test status
Simulation time 21091593839 ps
CPU time 89.19 seconds
Started Jun 06 02:51:51 PM PDT 24
Finished Jun 06 02:53:23 PM PDT 24
Peak memory 837348 kb
Host smart-f70994fa-1e05-4ff8-9b50-af327538dfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42396547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.42396547
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.1321534863
Short name T985
Test name
Test status
Simulation time 1373845222 ps
CPU time 99.35 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:53:32 PM PDT 24
Peak memory 519692 kb
Host smart-ebef55f4-7439-4d60-836c-294b3b138723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321534863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.1321534863
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1528739309
Short name T1319
Test name
Test status
Simulation time 517088534 ps
CPU time 1.08 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:51:53 PM PDT 24
Peak memory 204932 kb
Host smart-f58871e5-8d91-4ebc-a293-e713dd08e3cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528739309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1528739309
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1915471613
Short name T670
Test name
Test status
Simulation time 186174996 ps
CPU time 10.43 seconds
Started Jun 06 02:51:49 PM PDT 24
Finished Jun 06 02:52:02 PM PDT 24
Peak memory 236704 kb
Host smart-48d8b2ef-111f-495e-93e8-4a445de0a8d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915471613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1915471613
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3613529575
Short name T1271
Test name
Test status
Simulation time 58308121770 ps
CPU time 267.33 seconds
Started Jun 06 02:51:49 PM PDT 24
Finished Jun 06 02:56:19 PM PDT 24
Peak memory 1074844 kb
Host smart-46086d54-7c64-4e35-a482-50b105851904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613529575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3613529575
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.3089630423
Short name T1421
Test name
Test status
Simulation time 1435113348 ps
CPU time 13.68 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 02:52:14 PM PDT 24
Peak memory 205072 kb
Host smart-9e425f18-0b3f-4bf1-a38e-387bc0cddacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089630423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.3089630423
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.3167344819
Short name T771
Test name
Test status
Simulation time 2538690183 ps
CPU time 59.9 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:53:01 PM PDT 24
Peak memory 324520 kb
Host smart-f26e3bf6-983a-4ab6-856f-07b953f0ddc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167344819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.3167344819
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.4119821497
Short name T738
Test name
Test status
Simulation time 27772049 ps
CPU time 0.68 seconds
Started Jun 06 02:51:51 PM PDT 24
Finished Jun 06 02:51:54 PM PDT 24
Peak memory 204704 kb
Host smart-da59c91d-27f5-474f-9ac7-bf139b40cced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119821497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.4119821497
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3529599796
Short name T1134
Test name
Test status
Simulation time 6556477592 ps
CPU time 90.37 seconds
Started Jun 06 02:51:53 PM PDT 24
Finished Jun 06 02:53:26 PM PDT 24
Peak memory 246904 kb
Host smart-d60ed25b-e08e-45c6-b2a3-7a2bb20a25f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529599796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3529599796
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.504315618
Short name T812
Test name
Test status
Simulation time 1250288928 ps
CPU time 57.22 seconds
Started Jun 06 02:51:52 PM PDT 24
Finished Jun 06 02:52:52 PM PDT 24
Peak memory 296124 kb
Host smart-c2c5cae6-1fc6-499f-acda-8fbd967d8f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504315618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.504315618
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.1207122675
Short name T1262
Test name
Test status
Simulation time 57853257656 ps
CPU time 363.46 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:57:56 PM PDT 24
Peak memory 1022292 kb
Host smart-562408f4-68c6-4db0-a3ef-d331dbcf015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207122675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.1207122675
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.654148422
Short name T380
Test name
Test status
Simulation time 684656112 ps
CPU time 11.77 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:52:04 PM PDT 24
Peak memory 213316 kb
Host smart-9b03d68e-4d1b-42f1-b3f9-7f3ee15f7a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654148422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.654148422
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3653478888
Short name T744
Test name
Test status
Simulation time 1402808362 ps
CPU time 3.46 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 02:52:05 PM PDT 24
Peak memory 205052 kb
Host smart-4d1633e2-8892-4324-afcf-afc16dfb5a74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653478888 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3653478888
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.1555599528
Short name T796
Test name
Test status
Simulation time 10107612054 ps
CPU time 48.02 seconds
Started Jun 06 02:52:10 PM PDT 24
Finished Jun 06 02:53:00 PM PDT 24
Peak memory 372332 kb
Host smart-84aa10bd-b821-4699-a86b-a0933d564ad2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555599528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.1555599528
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.3187019122
Short name T1008
Test name
Test status
Simulation time 2148315329 ps
CPU time 2.64 seconds
Started Jun 06 02:52:00 PM PDT 24
Finished Jun 06 02:52:06 PM PDT 24
Peak memory 205160 kb
Host smart-14ca0442-4305-41cb-9d6a-7919ea7ea0c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187019122 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.3187019122
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.2523186595
Short name T604
Test name
Test status
Simulation time 1129772756 ps
CPU time 5.67 seconds
Started Jun 06 02:51:57 PM PDT 24
Finished Jun 06 02:52:05 PM PDT 24
Peak memory 205132 kb
Host smart-71e8abec-bbac-4bf6-bece-33a772e2fe68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523186595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.2523186595
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.660879401
Short name T974
Test name
Test status
Simulation time 1713141198 ps
CPU time 2.92 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:52:05 PM PDT 24
Peak memory 205120 kb
Host smart-cb5244a0-9d28-4260-a809-67c44462b1a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660879401 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.i2c_target_hrst.660879401
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.3101411228
Short name T281
Test name
Test status
Simulation time 465393759 ps
CPU time 3.03 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:51:56 PM PDT 24
Peak memory 205144 kb
Host smart-4089f31c-5eea-4948-8620-cdc52331b354
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101411228 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.3101411228
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.1417117794
Short name T499
Test name
Test status
Simulation time 22370998872 ps
CPU time 486.7 seconds
Started Jun 06 02:51:49 PM PDT 24
Finished Jun 06 02:59:59 PM PDT 24
Peak memory 5218804 kb
Host smart-7786a623-8f5e-4f91-a756-5c11fa5e29c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417117794 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.1417117794
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3743553798
Short name T666
Test name
Test status
Simulation time 6232803114 ps
CPU time 20.21 seconds
Started Jun 06 02:51:51 PM PDT 24
Finished Jun 06 02:52:15 PM PDT 24
Peak memory 205168 kb
Host smart-1c5aa9b9-e400-4dd0-803d-586db9f2867b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743553798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3743553798
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1063919147
Short name T1263
Test name
Test status
Simulation time 3812386444 ps
CPU time 42.5 seconds
Started Jun 06 02:51:49 PM PDT 24
Finished Jun 06 02:52:34 PM PDT 24
Peak memory 205176 kb
Host smart-5b53e3cc-49ba-4204-abf3-3e61a81937c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063919147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1063919147
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1096276829
Short name T1054
Test name
Test status
Simulation time 31532277481 ps
CPU time 245.23 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:55:58 PM PDT 24
Peak memory 2927276 kb
Host smart-ab7958c3-9b08-4f70-aa5b-5c92fadb3d4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096276829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1096276829
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.384064130
Short name T854
Test name
Test status
Simulation time 25109131413 ps
CPU time 170.58 seconds
Started Jun 06 02:51:50 PM PDT 24
Finished Jun 06 02:54:43 PM PDT 24
Peak memory 1474884 kb
Host smart-e23a3516-db55-4b5d-81ed-e697722f1ebf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384064130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.384064130
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3203222549
Short name T627
Test name
Test status
Simulation time 2028192064 ps
CPU time 7.52 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 02:52:08 PM PDT 24
Peak memory 220260 kb
Host smart-6085638c-f77d-420d-a0c2-7d8b4ef32872
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203222549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3203222549
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.2327130795
Short name T337
Test name
Test status
Simulation time 1096532576 ps
CPU time 20.51 seconds
Started Jun 06 02:52:11 PM PDT 24
Finished Jun 06 02:52:34 PM PDT 24
Peak memory 205080 kb
Host smart-7e80ce58-bea9-48e5-9231-368b57fb0e55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327130795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.2327130795
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1634058151
Short name T1040
Test name
Test status
Simulation time 36612957 ps
CPU time 0.62 seconds
Started Jun 06 02:52:07 PM PDT 24
Finished Jun 06 02:52:10 PM PDT 24
Peak memory 204764 kb
Host smart-22a5da81-e9f6-408b-bd50-6e3e88f830a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634058151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1634058151
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.906914884
Short name T1236
Test name
Test status
Simulation time 137278638 ps
CPU time 2.64 seconds
Started Jun 06 02:51:57 PM PDT 24
Finished Jun 06 02:52:02 PM PDT 24
Peak memory 213336 kb
Host smart-55afe0b9-adbd-44ac-9434-2cb41859143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906914884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.906914884
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.1670919354
Short name T450
Test name
Test status
Simulation time 406901259 ps
CPU time 5.77 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:52:08 PM PDT 24
Peak memory 268836 kb
Host smart-cf8568ab-cc9d-4b05-a0f3-39d293e5e706
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670919354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.1670919354
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1059145559
Short name T72
Test name
Test status
Simulation time 6677028825 ps
CPU time 110.96 seconds
Started Jun 06 02:51:56 PM PDT 24
Finished Jun 06 02:53:50 PM PDT 24
Peak memory 579096 kb
Host smart-b6c32914-5545-4ee9-a91d-c0b35046eeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059145559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1059145559
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.386273252
Short name T1196
Test name
Test status
Simulation time 1861077245 ps
CPU time 58.86 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 02:53:00 PM PDT 24
Peak memory 584428 kb
Host smart-4a9c3d2b-170b-4d6a-b12a-29e6dfb71a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386273252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.386273252
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.846222975
Short name T54
Test name
Test status
Simulation time 193777299 ps
CPU time 0.97 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:52:03 PM PDT 24
Peak memory 204756 kb
Host smart-5ad3c841-7b02-47e0-a91b-c96b483fc35f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846222975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.846222975
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.70475848
Short name T212
Test name
Test status
Simulation time 166565095 ps
CPU time 3.91 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:52:05 PM PDT 24
Peak memory 230132 kb
Host smart-0ef4f82a-328c-4d58-a8c4-0bff1ca8ee54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70475848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx.70475848
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.644807933
Short name T857
Test name
Test status
Simulation time 10175428163 ps
CPU time 443.11 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 02:59:23 PM PDT 24
Peak memory 1481260 kb
Host smart-6ebdbd19-e39b-4163-9e40-878ea36b4a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644807933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.644807933
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.602026817
Short name T575
Test name
Test status
Simulation time 2592171007 ps
CPU time 25.73 seconds
Started Jun 06 02:52:12 PM PDT 24
Finished Jun 06 02:52:40 PM PDT 24
Peak memory 205088 kb
Host smart-fb79806c-e62d-4ab9-b4b0-f42fdeddebe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602026817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.602026817
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.1046572546
Short name T360
Test name
Test status
Simulation time 2519869845 ps
CPU time 106.12 seconds
Started Jun 06 02:52:09 PM PDT 24
Finished Jun 06 02:53:57 PM PDT 24
Peak memory 334560 kb
Host smart-d0ca4f77-bff3-40c3-9221-c914496b4192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046572546 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.1046572546
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.936619410
Short name T1113
Test name
Test status
Simulation time 98933711 ps
CPU time 0.7 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:52:02 PM PDT 24
Peak memory 204764 kb
Host smart-f215947e-6d78-4f08-bdb5-0359f76e57b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936619410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.936619410
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.4213135871
Short name T61
Test name
Test status
Simulation time 7932132792 ps
CPU time 200.31 seconds
Started Jun 06 02:51:57 PM PDT 24
Finished Jun 06 02:55:20 PM PDT 24
Peak memory 1189060 kb
Host smart-a72c6fc9-0910-40f2-a6f7-6e50b6186897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213135871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.4213135871
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.415219824
Short name T785
Test name
Test status
Simulation time 2009567300 ps
CPU time 108.2 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:53:50 PM PDT 24
Peak memory 462320 kb
Host smart-9d9d1ec0-0a61-496c-a32e-efd9f7671f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415219824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.415219824
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.4170809753
Short name T579
Test name
Test status
Simulation time 3492983827 ps
CPU time 8.82 seconds
Started Jun 06 02:51:57 PM PDT 24
Finished Jun 06 02:52:09 PM PDT 24
Peak memory 213548 kb
Host smart-0ebdb2f4-b6f4-4c38-8ab9-47dab79ea025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170809753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.4170809753
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.3929512523
Short name T269
Test name
Test status
Simulation time 1392786842 ps
CPU time 3.87 seconds
Started Jun 06 02:52:08 PM PDT 24
Finished Jun 06 02:52:14 PM PDT 24
Peak memory 205152 kb
Host smart-5eb96231-ea58-403f-ad3c-7dbe40acd460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929512523 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.3929512523
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.218670606
Short name T814
Test name
Test status
Simulation time 10300621350 ps
CPU time 23.26 seconds
Started Jun 06 02:52:09 PM PDT 24
Finished Jun 06 02:52:34 PM PDT 24
Peak memory 263664 kb
Host smart-134ec5fe-b20f-491d-8a48-df94f0b749aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218670606 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_acq.218670606
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.785537738
Short name T913
Test name
Test status
Simulation time 10567676831 ps
CPU time 18.44 seconds
Started Jun 06 02:52:10 PM PDT 24
Finished Jun 06 02:52:31 PM PDT 24
Peak memory 306184 kb
Host smart-f3626e9e-c253-4aa1-9f48-048ade509d85
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785537738 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.i2c_target_fifo_reset_tx.785537738
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.117627040
Short name T1464
Test name
Test status
Simulation time 1049486131 ps
CPU time 2.79 seconds
Started Jun 06 02:52:08 PM PDT 24
Finished Jun 06 02:52:13 PM PDT 24
Peak memory 205108 kb
Host smart-440bd9b6-d0f1-4947-a7b7-618ae1128f95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117627040 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.117627040
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.3193017468
Short name T309
Test name
Test status
Simulation time 2476128602 ps
CPU time 1.18 seconds
Started Jun 06 02:52:08 PM PDT 24
Finished Jun 06 02:52:12 PM PDT 24
Peak memory 204940 kb
Host smart-47bc3989-d646-4b51-aaee-c03c7cb48d4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193017468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.3193017468
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.4241282238
Short name T751
Test name
Test status
Simulation time 829147407 ps
CPU time 2.59 seconds
Started Jun 06 02:52:11 PM PDT 24
Finished Jun 06 02:52:16 PM PDT 24
Peak memory 205248 kb
Host smart-25f2fbfc-2359-4434-b2c4-5bab1f2af0f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241282238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.4241282238
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.17179980
Short name T1448
Test name
Test status
Simulation time 1192790157 ps
CPU time 6.17 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 02:52:06 PM PDT 24
Peak memory 213264 kb
Host smart-053f3776-34ee-42bb-9f45-2f8d61c9926f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17179980 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_intr_smoke.17179980
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.3947653183
Short name T400
Test name
Test status
Simulation time 5247673319 ps
CPU time 16.43 seconds
Started Jun 06 02:52:02 PM PDT 24
Finished Jun 06 02:52:22 PM PDT 24
Peak memory 645332 kb
Host smart-986fa1fa-3313-4a3c-a241-675a0aa80953
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947653183 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.3947653183
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3740874495
Short name T946
Test name
Test status
Simulation time 3324806520 ps
CPU time 12.63 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:52:14 PM PDT 24
Peak memory 205192 kb
Host smart-68288368-9936-4990-b274-866a299d3e47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740874495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3740874495
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2368703945
Short name T824
Test name
Test status
Simulation time 488304123 ps
CPU time 19.51 seconds
Started Jun 06 02:51:59 PM PDT 24
Finished Jun 06 02:52:21 PM PDT 24
Peak memory 205056 kb
Host smart-1e90e1ba-9c0e-4dbe-9e6a-6fb231ba7baf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368703945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2368703945
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1731498340
Short name T643
Test name
Test status
Simulation time 20573398501 ps
CPU time 8.87 seconds
Started Jun 06 02:52:02 PM PDT 24
Finished Jun 06 02:52:13 PM PDT 24
Peak memory 205056 kb
Host smart-a6a67781-6e3c-4566-8308-8b72f0374ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731498340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1731498340
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1164180070
Short name T1016
Test name
Test status
Simulation time 18801967543 ps
CPU time 3554.31 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 03:51:16 PM PDT 24
Peak memory 4438392 kb
Host smart-700ed743-f446-4284-8890-4c7651453202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164180070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1164180070
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3117513071
Short name T641
Test name
Test status
Simulation time 8976283632 ps
CPU time 7.55 seconds
Started Jun 06 02:51:58 PM PDT 24
Finished Jun 06 02:52:08 PM PDT 24
Peak memory 220440 kb
Host smart-2239e738-52e7-4249-bfd7-c242fa889b73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117513071 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3117513071
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.319352587
Short name T708
Test name
Test status
Simulation time 1072154559 ps
CPU time 20.03 seconds
Started Jun 06 02:52:08 PM PDT 24
Finished Jun 06 02:52:31 PM PDT 24
Peak memory 205108 kb
Host smart-e1799302-5e5b-42c8-afbf-d4aa7a8373f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319352587 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.319352587
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.364974928
Short name T170
Test name
Test status
Simulation time 33530721 ps
CPU time 0.61 seconds
Started Jun 06 02:52:17 PM PDT 24
Finished Jun 06 02:52:21 PM PDT 24
Peak memory 204696 kb
Host smart-c3a9f735-f0f7-436d-a3dd-6660a27d0166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364974928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.364974928
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3854716116
Short name T463
Test name
Test status
Simulation time 394012124 ps
CPU time 1.5 seconds
Started Jun 06 02:52:08 PM PDT 24
Finished Jun 06 02:52:12 PM PDT 24
Peak memory 213356 kb
Host smart-2221e560-865b-4ac4-b18b-e2a14c84cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854716116 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3854716116
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.3835681220
Short name T45
Test name
Test status
Simulation time 404541995 ps
CPU time 21.28 seconds
Started Jun 06 02:52:10 PM PDT 24
Finished Jun 06 02:52:33 PM PDT 24
Peak memory 291116 kb
Host smart-c9b20a89-ad21-4fe6-ad62-174f7053682f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835681220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.3835681220
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2579415345
Short name T508
Test name
Test status
Simulation time 3368376662 ps
CPU time 53.42 seconds
Started Jun 06 02:52:10 PM PDT 24
Finished Jun 06 02:53:06 PM PDT 24
Peak memory 625488 kb
Host smart-53d63015-d6d7-4284-a19e-c922d4ba4172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579415345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2579415345
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.1164433344
Short name T333
Test name
Test status
Simulation time 10702777437 ps
CPU time 93.98 seconds
Started Jun 06 02:52:07 PM PDT 24
Finished Jun 06 02:53:44 PM PDT 24
Peak memory 789456 kb
Host smart-38966470-1f8a-4d3c-b643-7e59b096346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164433344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.1164433344
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1637207504
Short name T341
Test name
Test status
Simulation time 230317449 ps
CPU time 0.94 seconds
Started Jun 06 02:52:11 PM PDT 24
Finished Jun 06 02:52:14 PM PDT 24
Peak memory 204800 kb
Host smart-02d13a98-ecc3-46d5-9d4d-353dce7ea7f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637207504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1637207504
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.448690322
Short name T1408
Test name
Test status
Simulation time 743779834 ps
CPU time 4.68 seconds
Started Jun 06 02:52:09 PM PDT 24
Finished Jun 06 02:52:16 PM PDT 24
Peak memory 204980 kb
Host smart-e4a2a0bc-ed90-4ce0-b8e2-5cd5ecbb125f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448690322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx.
448690322
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2923256094
Short name T829
Test name
Test status
Simulation time 32000323591 ps
CPU time 158.79 seconds
Started Jun 06 02:52:06 PM PDT 24
Finished Jun 06 02:54:47 PM PDT 24
Peak memory 1589176 kb
Host smart-0fd89a53-d90e-4d66-a535-0d55897f9b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923256094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2923256094
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.720714734
Short name T574
Test name
Test status
Simulation time 478659089 ps
CPU time 7.29 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:52:30 PM PDT 24
Peak memory 205028 kb
Host smart-a54fda72-9971-4eea-ad65-8505ea968e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720714734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.720714734
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2978553376
Short name T1310
Test name
Test status
Simulation time 2287069075 ps
CPU time 115.61 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:54:18 PM PDT 24
Peak memory 379340 kb
Host smart-231b85df-fccd-4275-b9a7-5bf13672c289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978553376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2978553376
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.3812677796
Short name T129
Test name
Test status
Simulation time 88782719 ps
CPU time 0.65 seconds
Started Jun 06 02:52:07 PM PDT 24
Finished Jun 06 02:52:11 PM PDT 24
Peak memory 204716 kb
Host smart-1376c2b4-e670-436e-a175-8a4fbd89a41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812677796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.3812677796
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.3726367741
Short name T646
Test name
Test status
Simulation time 25182139900 ps
CPU time 116.72 seconds
Started Jun 06 02:52:06 PM PDT 24
Finished Jun 06 02:54:05 PM PDT 24
Peak memory 215288 kb
Host smart-6e4f4dbf-bfe8-4ad6-998a-dc8492608553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726367741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.3726367741
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3929187318
Short name T885
Test name
Test status
Simulation time 8021117218 ps
CPU time 100.45 seconds
Started Jun 06 02:52:11 PM PDT 24
Finished Jun 06 02:53:53 PM PDT 24
Peak memory 368204 kb
Host smart-ff97538f-1d68-4e4b-8334-2990c8983fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929187318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3929187318
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2501287777
Short name T594
Test name
Test status
Simulation time 1712874082 ps
CPU time 16.54 seconds
Started Jun 06 02:52:09 PM PDT 24
Finished Jun 06 02:52:28 PM PDT 24
Peak memory 221088 kb
Host smart-00402c1a-6770-4f56-84ef-647a25b9c0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501287777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2501287777
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.580458926
Short name T964
Test name
Test status
Simulation time 601074062 ps
CPU time 3.25 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:52:26 PM PDT 24
Peak memory 205096 kb
Host smart-1e7f242d-3e95-4e6d-be59-0685df4f2e5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580458926 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.580458926
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2933597996
Short name T1045
Test name
Test status
Simulation time 10125435263 ps
CPU time 14.58 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:52:36 PM PDT 24
Peak memory 251356 kb
Host smart-c2078ec7-95ed-4553-b0f3-953defce10e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933597996 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2933597996
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.860468782
Short name T167
Test name
Test status
Simulation time 10179499827 ps
CPU time 70.01 seconds
Started Jun 06 02:52:22 PM PDT 24
Finished Jun 06 02:53:34 PM PDT 24
Peak memory 492264 kb
Host smart-653f02a2-4f27-4f7a-b6b6-223186046241
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860468782 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.860468782
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.1882058216
Short name T222
Test name
Test status
Simulation time 1409430986 ps
CPU time 5.25 seconds
Started Jun 06 02:52:18 PM PDT 24
Finished Jun 06 02:52:27 PM PDT 24
Peak memory 205148 kb
Host smart-d4bb679e-9442-416b-8557-9ce84e4e0d80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882058216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.1882058216
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.4087470617
Short name T965
Test name
Test status
Simulation time 1045659785 ps
CPU time 2.65 seconds
Started Jun 06 02:52:20 PM PDT 24
Finished Jun 06 02:52:26 PM PDT 24
Peak memory 205060 kb
Host smart-fcc1c176-b486-4c49-a5bb-8e3839c12200
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087470617 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.4087470617
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.3683960606
Short name T759
Test name
Test status
Simulation time 460499534 ps
CPU time 2.8 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:52:25 PM PDT 24
Peak memory 205040 kb
Host smart-68d44ff2-b103-443c-9a35-a96ce2466466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683960606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.3683960606
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.344943569
Short name T1242
Test name
Test status
Simulation time 1069266128 ps
CPU time 6.68 seconds
Started Jun 06 02:52:18 PM PDT 24
Finished Jun 06 02:52:28 PM PDT 24
Peak memory 213336 kb
Host smart-03fffa72-8c62-4203-a0f4-963d54d69358
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344943569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_intr_smoke.344943569
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2104415000
Short name T847
Test name
Test status
Simulation time 19522986409 ps
CPU time 47.36 seconds
Started Jun 06 02:52:18 PM PDT 24
Finished Jun 06 02:53:09 PM PDT 24
Peak memory 822428 kb
Host smart-40a0a263-7a34-4fde-817a-02a728f156e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104415000 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2104415000
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3983304002
Short name T1041
Test name
Test status
Simulation time 599902382 ps
CPU time 22.42 seconds
Started Jun 06 02:52:09 PM PDT 24
Finished Jun 06 02:52:33 PM PDT 24
Peak memory 205000 kb
Host smart-ef65d716-faf7-43c6-909a-875f8a3fe65a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983304002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3983304002
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.108873951
Short name T1475
Test name
Test status
Simulation time 952078133 ps
CPU time 18.17 seconds
Started Jun 06 02:52:09 PM PDT 24
Finished Jun 06 02:52:29 PM PDT 24
Peak memory 215840 kb
Host smart-5368bc13-4f98-405d-becc-530177878ec5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108873951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.108873951
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.523631291
Short name T1490
Test name
Test status
Simulation time 63236977997 ps
CPU time 1129.8 seconds
Started Jun 06 02:52:09 PM PDT 24
Finished Jun 06 03:11:01 PM PDT 24
Peak memory 7213040 kb
Host smart-ee4c6a1d-73ad-4934-b131-307f8fb65ad1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523631291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.523631291
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.693080373
Short name T434
Test name
Test status
Simulation time 17640669070 ps
CPU time 976.78 seconds
Started Jun 06 02:52:11 PM PDT 24
Finished Jun 06 03:08:30 PM PDT 24
Peak memory 4303116 kb
Host smart-4200442d-8eba-461e-bd99-170f9e5e1889
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693080373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_t
arget_stretch.693080373
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.4263129443
Short name T1247
Test name
Test status
Simulation time 6974281151 ps
CPU time 7.85 seconds
Started Jun 06 02:52:20 PM PDT 24
Finished Jun 06 02:52:31 PM PDT 24
Peak memory 221448 kb
Host smart-fcdb5a2a-c311-495b-9d0f-234758d4aab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263129443 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.4263129443
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.2144704065
Short name T710
Test name
Test status
Simulation time 1281820817 ps
CPU time 15.84 seconds
Started Jun 06 02:52:18 PM PDT 24
Finished Jun 06 02:52:37 PM PDT 24
Peak memory 205080 kb
Host smart-5a085324-625a-4a50-a216-ecbc30450682
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144704065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2144704065
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.1942859151
Short name T837
Test name
Test status
Simulation time 44934295 ps
CPU time 0.61 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:52:34 PM PDT 24
Peak memory 204744 kb
Host smart-e5408934-f906-4410-ba51-26f21b7ad308
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942859151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.1942859151
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3905699488
Short name T653
Test name
Test status
Simulation time 153761118 ps
CPU time 1.49 seconds
Started Jun 06 02:52:25 PM PDT 24
Finished Jun 06 02:52:28 PM PDT 24
Peak memory 213284 kb
Host smart-03e75f68-f702-4798-bd78-9b71aaf8a1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905699488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3905699488
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1887696535
Short name T1302
Test name
Test status
Simulation time 391469144 ps
CPU time 8.37 seconds
Started Jun 06 02:52:17 PM PDT 24
Finished Jun 06 02:52:29 PM PDT 24
Peak memory 275568 kb
Host smart-54b51039-61dc-48ca-b0c5-5e8c78e44c47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887696535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1887696535
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.3273176912
Short name T846
Test name
Test status
Simulation time 2084476711 ps
CPU time 164.94 seconds
Started Jun 06 02:52:22 PM PDT 24
Finished Jun 06 02:55:09 PM PDT 24
Peak memory 699956 kb
Host smart-d93061e0-97dc-4f4f-adfb-40f6449fd968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273176912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.3273176912
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2744798476
Short name T1048
Test name
Test status
Simulation time 7320817850 ps
CPU time 146.35 seconds
Started Jun 06 02:52:20 PM PDT 24
Finished Jun 06 02:54:50 PM PDT 24
Peak memory 660996 kb
Host smart-3c333053-536c-4b61-ba76-f0f67863d3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744798476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2744798476
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.3972021025
Short name T567
Test name
Test status
Simulation time 154672419 ps
CPU time 1.08 seconds
Started Jun 06 02:52:17 PM PDT 24
Finished Jun 06 02:52:21 PM PDT 24
Peak memory 204764 kb
Host smart-2a65ea31-f49f-47d8-9190-d3b750f5315d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972021025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.3972021025
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1242765377
Short name T169
Test name
Test status
Simulation time 751964164 ps
CPU time 10.02 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:52:32 PM PDT 24
Peak memory 204936 kb
Host smart-d010ebbf-ae92-49e7-94de-8403a06587ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242765377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1242765377
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.953812864
Short name T648
Test name
Test status
Simulation time 3618244697 ps
CPU time 290.21 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:57:13 PM PDT 24
Peak memory 1102240 kb
Host smart-d268cb7d-922d-434f-b708-ae59918b42bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953812864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.953812864
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.489678547
Short name T820
Test name
Test status
Simulation time 1967565747 ps
CPU time 4.9 seconds
Started Jun 06 02:52:28 PM PDT 24
Finished Jun 06 02:52:36 PM PDT 24
Peak memory 204988 kb
Host smart-45338f00-43de-4094-8a30-cd26249a51b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489678547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.489678547
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.3244953499
Short name T1261
Test name
Test status
Simulation time 2222306014 ps
CPU time 96.81 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:54:09 PM PDT 24
Peak memory 302040 kb
Host smart-16d9ffdd-f283-4e36-a1d1-806588e867f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244953499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3244953499
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.571965487
Short name T1005
Test name
Test status
Simulation time 48556563 ps
CPU time 0.64 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:52:24 PM PDT 24
Peak memory 204668 kb
Host smart-3ea09383-2290-45c3-a2f0-b2688e520665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571965487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.571965487
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.2967065176
Short name T735
Test name
Test status
Simulation time 5778361169 ps
CPU time 32.87 seconds
Started Jun 06 02:52:19 PM PDT 24
Finished Jun 06 02:52:55 PM PDT 24
Peak memory 267472 kb
Host smart-9d2c84f4-4a34-44b1-85d5-878ff17740ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967065176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2967065176
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3727112043
Short name T975
Test name
Test status
Simulation time 4723639856 ps
CPU time 38.42 seconds
Started Jun 06 02:52:20 PM PDT 24
Finished Jun 06 02:53:02 PM PDT 24
Peak memory 477596 kb
Host smart-fcfd3096-76ab-4aeb-b417-7cb5e918ad83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727112043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3727112043
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.83161008
Short name T137
Test name
Test status
Simulation time 4041956917 ps
CPU time 16.81 seconds
Started Jun 06 02:52:20 PM PDT 24
Finished Jun 06 02:52:40 PM PDT 24
Peak memory 229832 kb
Host smart-d19a151e-4b10-440e-83e3-2458f5101b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83161008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.83161008
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3446669324
Short name T788
Test name
Test status
Simulation time 679937464 ps
CPU time 3.31 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:52:35 PM PDT 24
Peak memory 205308 kb
Host smart-d575d7a6-861b-40fc-97bb-2906b127ac88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446669324 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3446669324
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3554983528
Short name T768
Test name
Test status
Simulation time 10247437967 ps
CPU time 14 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:52:46 PM PDT 24
Peak memory 250132 kb
Host smart-77d81778-5643-4711-bc80-746761e358b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554983528 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3554983528
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.2807156033
Short name T640
Test name
Test status
Simulation time 10435900270 ps
CPU time 16.8 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:52:50 PM PDT 24
Peak memory 323016 kb
Host smart-97d5af7b-5bc4-463a-a981-8571c0e52808
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807156033 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.2807156033
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.528130002
Short name T1082
Test name
Test status
Simulation time 1550695533 ps
CPU time 2.68 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:52:34 PM PDT 24
Peak memory 205108 kb
Host smart-3ae7ae22-3d0c-4984-b737-1983f33a3ca6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528130002 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.528130002
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.3395592005
Short name T696
Test name
Test status
Simulation time 1847570088 ps
CPU time 1.05 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:52:34 PM PDT 24
Peak memory 204908 kb
Host smart-9f931e34-41b9-44f9-9629-dbd0cefe2873
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395592005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.3395592005
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2524382406
Short name T1405
Test name
Test status
Simulation time 472986755 ps
CPU time 2.11 seconds
Started Jun 06 02:52:28 PM PDT 24
Finished Jun 06 02:52:33 PM PDT 24
Peak memory 205068 kb
Host smart-2bd0d123-eefc-467a-892c-a6db097f8c34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524382406 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2524382406
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2613144069
Short name T391
Test name
Test status
Simulation time 596963786 ps
CPU time 3.37 seconds
Started Jun 06 02:52:27 PM PDT 24
Finished Jun 06 02:52:33 PM PDT 24
Peak memory 205088 kb
Host smart-21213f15-cd7d-43e9-a1f4-93bea9f81a3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613144069 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2613144069
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2253593980
Short name T1125
Test name
Test status
Simulation time 4085625095 ps
CPU time 17.22 seconds
Started Jun 06 02:52:17 PM PDT 24
Finished Jun 06 02:52:38 PM PDT 24
Peak memory 205180 kb
Host smart-c1698773-849a-4148-86d0-836ab4e16dca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253593980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2253593980
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.2665710714
Short name T274
Test name
Test status
Simulation time 802908377 ps
CPU time 15.8 seconds
Started Jun 06 02:52:28 PM PDT 24
Finished Jun 06 02:52:47 PM PDT 24
Peak memory 205056 kb
Host smart-f62ec7cc-ecec-40a8-bb7d-651296533355
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665710714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.2665710714
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.995095832
Short name T1117
Test name
Test status
Simulation time 64916922692 ps
CPU time 258.25 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:56:51 PM PDT 24
Peak memory 2576360 kb
Host smart-f6b9e829-343f-4307-a115-9aeea15389ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995095832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.995095832
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2266154372
Short name T639
Test name
Test status
Simulation time 31061447833 ps
CPU time 289.63 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:57:22 PM PDT 24
Peak memory 1998604 kb
Host smart-2da9afe3-1a88-4438-a12a-491b395cf5a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266154372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2266154372
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.746864401
Short name T345
Test name
Test status
Simulation time 2371455925 ps
CPU time 6.42 seconds
Started Jun 06 02:52:28 PM PDT 24
Finished Jun 06 02:52:37 PM PDT 24
Peak memory 210044 kb
Host smart-618fb1ba-3ba2-4d0d-a223-1d1c6bd492ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746864401 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_timeout.746864401
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.3988878561
Short name T1455
Test name
Test status
Simulation time 1070204941 ps
CPU time 16.21 seconds
Started Jun 06 02:52:31 PM PDT 24
Finished Jun 06 02:52:51 PM PDT 24
Peak memory 205040 kb
Host smart-0a835ac0-8720-411d-9eea-bda9a0dadb34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988878561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.3988878561
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2809396683
Short name T858
Test name
Test status
Simulation time 16907917 ps
CPU time 0.6 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:53:09 PM PDT 24
Peak memory 204692 kb
Host smart-58dc2d43-2fbe-4473-abcb-ed73ee9b4aaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809396683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2809396683
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.867917382
Short name T800
Test name
Test status
Simulation time 474800639 ps
CPU time 9.4 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:52:43 PM PDT 24
Peak memory 269212 kb
Host smart-80f79786-9fd1-4db6-b286-7a045612a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867917382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.867917382
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.3557651214
Short name T1253
Test name
Test status
Simulation time 344173057 ps
CPU time 7.95 seconds
Started Jun 06 02:52:31 PM PDT 24
Finished Jun 06 02:52:42 PM PDT 24
Peak memory 273888 kb
Host smart-c5736238-c993-49c4-ba1c-06c809ab44d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557651214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.3557651214
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.3702554302
Short name T1333
Test name
Test status
Simulation time 1355920389 ps
CPU time 92.67 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:54:07 PM PDT 24
Peak memory 541256 kb
Host smart-6256fd83-6baa-40b6-a3b5-98c9c80cc5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702554302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.3702554302
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.1715184773
Short name T1183
Test name
Test status
Simulation time 2690456731 ps
CPU time 35.62 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:53:08 PM PDT 24
Peak memory 325448 kb
Host smart-e5fc98c2-e3e6-468e-b3d3-9f89b17d96e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715184773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.1715184773
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.3445677842
Short name T658
Test name
Test status
Simulation time 104102630 ps
CPU time 0.96 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:52:35 PM PDT 24
Peak memory 204760 kb
Host smart-b6be1025-8599-4a12-bb9b-1fbdf49235e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445677842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.3445677842
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.902183811
Short name T1336
Test name
Test status
Simulation time 164549109 ps
CPU time 3.67 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:52:35 PM PDT 24
Peak memory 205020 kb
Host smart-6f5fcb77-ef4d-4261-96bb-25def7746bf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902183811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
902183811
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3263488171
Short name T1169
Test name
Test status
Simulation time 3650820595 ps
CPU time 86.54 seconds
Started Jun 06 02:52:28 PM PDT 24
Finished Jun 06 02:53:58 PM PDT 24
Peak memory 1092132 kb
Host smart-7f8aff06-6dcf-4c6b-b2fc-18b008f8ca67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263488171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3263488171
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.3548708342
Short name T39
Test name
Test status
Simulation time 534598110 ps
CPU time 3.25 seconds
Started Jun 06 02:53:03 PM PDT 24
Finished Jun 06 02:53:10 PM PDT 24
Peak memory 205140 kb
Host smart-af2a0ea5-047b-4a60-b36c-15144394a509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548708342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.3548708342
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2795553712
Short name T613
Test name
Test status
Simulation time 8036554697 ps
CPU time 96.73 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:54:41 PM PDT 24
Peak memory 332836 kb
Host smart-eacb4b46-bc1d-4140-a999-a4ac664c395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795553712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2795553712
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.2400579706
Short name T1203
Test name
Test status
Simulation time 28717304 ps
CPU time 0.66 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:52:33 PM PDT 24
Peak memory 204700 kb
Host smart-5416d09d-6fd0-4040-837e-46a0fd2f2171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400579706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.2400579706
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.2129895836
Short name T1295
Test name
Test status
Simulation time 25719241552 ps
CPU time 140.64 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 02:54:52 PM PDT 24
Peak memory 1239924 kb
Host smart-0080505b-5034-4088-8d4b-31b756279a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129895836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.2129895836
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1927680888
Short name T532
Test name
Test status
Simulation time 13963428403 ps
CPU time 74.61 seconds
Started Jun 06 02:52:28 PM PDT 24
Finished Jun 06 02:53:45 PM PDT 24
Peak memory 382000 kb
Host smart-c110b2e6-5e74-4244-896c-b3b8d21d3832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927680888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1927680888
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.1491459048
Short name T1024
Test name
Test status
Simulation time 10858625311 ps
CPU time 411.63 seconds
Started Jun 06 02:52:27 PM PDT 24
Finished Jun 06 02:59:21 PM PDT 24
Peak memory 1285008 kb
Host smart-05547f8e-15c0-4a7c-992e-4353d35717cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491459048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.1491459048
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.1569705517
Short name T1364
Test name
Test status
Simulation time 1021707910 ps
CPU time 10.1 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:52:44 PM PDT 24
Peak memory 213280 kb
Host smart-1b3f5d73-5cb6-43b5-b28c-6196c2334b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569705517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.1569705517
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.2046780441
Short name T660
Test name
Test status
Simulation time 467082778 ps
CPU time 2.75 seconds
Started Jun 06 02:53:01 PM PDT 24
Finished Jun 06 02:53:06 PM PDT 24
Peak memory 205120 kb
Host smart-345181a2-57de-431e-807f-f3fb75b9f180
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046780441 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.2046780441
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1767441795
Short name T1424
Test name
Test status
Simulation time 10461488606 ps
CPU time 8.27 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:52:41 PM PDT 24
Peak memory 222396 kb
Host smart-8ce8be73-5aff-4669-a1cc-6c34ef653f23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767441795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1767441795
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.1362013733
Short name T681
Test name
Test status
Simulation time 1095587592 ps
CPU time 2.53 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:53:08 PM PDT 24
Peak memory 205032 kb
Host smart-566156e4-7373-4da2-918f-a452f2a01cfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362013733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.1362013733
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.2983996314
Short name T424
Test name
Test status
Simulation time 1517424854 ps
CPU time 1.31 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:53:07 PM PDT 24
Peak memory 204904 kb
Host smart-48d6608d-2b5a-4595-ac31-bb982f6674cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983996314 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.2983996314
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.517076717
Short name T296
Test name
Test status
Simulation time 2373610914 ps
CPU time 2.97 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:53:09 PM PDT 24
Peak memory 205180 kb
Host smart-8b2e946c-5df9-4140-9948-e4bdaeb852c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517076717 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.i2c_target_hrst.517076717
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.226358963
Short name T808
Test name
Test status
Simulation time 1287813244 ps
CPU time 3.83 seconds
Started Jun 06 02:52:27 PM PDT 24
Finished Jun 06 02:52:33 PM PDT 24
Peak memory 205136 kb
Host smart-378af9fc-a7bb-47f1-9d8f-9d097d956adf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226358963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.226358963
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.4166925475
Short name T971
Test name
Test status
Simulation time 17864260048 ps
CPU time 43.85 seconds
Started Jun 06 02:52:31 PM PDT 24
Finished Jun 06 02:53:18 PM PDT 24
Peak memory 1026632 kb
Host smart-5d0dfd24-b977-4690-b041-07072f38b25e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166925475 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.4166925475
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.104999181
Short name T1283
Test name
Test status
Simulation time 4039097167 ps
CPU time 15.7 seconds
Started Jun 06 02:52:31 PM PDT 24
Finished Jun 06 02:52:51 PM PDT 24
Peak memory 205120 kb
Host smart-1e2fe316-d253-49e6-8b93-297db78d1bc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104999181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.104999181
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.2975710618
Short name T1077
Test name
Test status
Simulation time 6298597000 ps
CPU time 10.08 seconds
Started Jun 06 02:52:30 PM PDT 24
Finished Jun 06 02:52:44 PM PDT 24
Peak memory 207576 kb
Host smart-99eff0d6-2c80-4ed0-ab2d-05563189d455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975710618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.2975710618
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3431082581
Short name T232
Test name
Test status
Simulation time 54467316405 ps
CPU time 458.81 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 03:00:11 PM PDT 24
Peak memory 4221832 kb
Host smart-0a0c187a-4d10-47f5-b3a9-d29310805a23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431082581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3431082581
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.2456341384
Short name T474
Test name
Test status
Simulation time 24430719061 ps
CPU time 1411.42 seconds
Started Jun 06 02:52:29 PM PDT 24
Finished Jun 06 03:16:04 PM PDT 24
Peak memory 5932540 kb
Host smart-ca4a27d9-3879-457c-8cea-42167c1fdfa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456341384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.2456341384
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2564954174
Short name T976
Test name
Test status
Simulation time 1508685977 ps
CPU time 8.17 seconds
Started Jun 06 02:52:31 PM PDT 24
Finished Jun 06 02:52:43 PM PDT 24
Peak memory 213316 kb
Host smart-383e1945-4390-44b0-8c9b-d515da185879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564954174 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2564954174
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.2860263468
Short name T1439
Test name
Test status
Simulation time 1097854951 ps
CPU time 16.82 seconds
Started Jun 06 02:53:01 PM PDT 24
Finished Jun 06 02:53:21 PM PDT 24
Peak memory 205092 kb
Host smart-b77eff3e-e044-4c9a-8a4f-01615ba271f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860263468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.2860263468
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.2696896943
Short name T726
Test name
Test status
Simulation time 36999846 ps
CPU time 0.6 seconds
Started Jun 06 02:49:29 PM PDT 24
Finished Jun 06 02:49:32 PM PDT 24
Peak memory 204700 kb
Host smart-09f7890e-a75d-423c-8560-29400ccf7dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696896943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.2696896943
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.161224985
Short name T47
Test name
Test status
Simulation time 498268616 ps
CPU time 8.84 seconds
Started Jun 06 02:49:12 PM PDT 24
Finished Jun 06 02:49:22 PM PDT 24
Peak memory 213256 kb
Host smart-e4e9dd59-0839-49b7-9dd4-bfaa57c0f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161224985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.161224985
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.1170321940
Short name T435
Test name
Test status
Simulation time 484850974 ps
CPU time 10.06 seconds
Started Jun 06 02:49:14 PM PDT 24
Finished Jun 06 02:49:26 PM PDT 24
Peak memory 297348 kb
Host smart-a7dcd89e-05b2-40e1-92d1-e88509471111
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170321940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.1170321940
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3229503144
Short name T1480
Test name
Test status
Simulation time 1960485042 ps
CPU time 68.53 seconds
Started Jun 06 02:49:13 PM PDT 24
Finished Jun 06 02:50:23 PM PDT 24
Peak memory 642240 kb
Host smart-6c660f31-59f3-48ce-9256-0e802bf1739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229503144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3229503144
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.989507093
Short name T1206
Test name
Test status
Simulation time 2383131215 ps
CPU time 87.05 seconds
Started Jun 06 02:49:17 PM PDT 24
Finished Jun 06 02:50:46 PM PDT 24
Peak memory 746340 kb
Host smart-3147b9e6-6ee7-4636-aafe-c1e84be5aaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989507093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.989507093
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.816938915
Short name T839
Test name
Test status
Simulation time 2044238203 ps
CPU time 1 seconds
Started Jun 06 02:49:14 PM PDT 24
Finished Jun 06 02:49:17 PM PDT 24
Peak memory 204756 kb
Host smart-9393a4b9-a2a7-49b3-904c-fe2b0a9c6b7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816938915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.816938915
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3820046638
Short name T1288
Test name
Test status
Simulation time 249324255 ps
CPU time 13.4 seconds
Started Jun 06 02:49:15 PM PDT 24
Finished Jun 06 02:49:31 PM PDT 24
Peak memory 205020 kb
Host smart-457b12dc-045e-4e4e-be16-51e6b98f3cc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820046638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3820046638
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.291031658
Short name T1060
Test name
Test status
Simulation time 26412607759 ps
CPU time 104.48 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 02:50:50 PM PDT 24
Peak memory 1192556 kb
Host smart-0ada2c92-e1c0-42ef-8ddf-62c5cd7c2732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291031658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.291031658
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3451834311
Short name T1192
Test name
Test status
Simulation time 279934351 ps
CPU time 3.69 seconds
Started Jun 06 02:49:12 PM PDT 24
Finished Jun 06 02:49:17 PM PDT 24
Peak memory 204980 kb
Host smart-20b23eaf-35af-4114-9482-76b46d828cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451834311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3451834311
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_override.43442029
Short name T355
Test name
Test status
Simulation time 37888970 ps
CPU time 0.66 seconds
Started Jun 06 02:49:06 PM PDT 24
Finished Jun 06 02:49:08 PM PDT 24
Peak memory 204780 kb
Host smart-623e2c76-4cab-4f87-889d-7abb755d06e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43442029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.43442029
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1335857214
Short name T1141
Test name
Test status
Simulation time 7403369666 ps
CPU time 97.37 seconds
Started Jun 06 02:49:13 PM PDT 24
Finished Jun 06 02:50:52 PM PDT 24
Peak memory 1037900 kb
Host smart-a279db63-9100-44c0-a377-5cf6c834f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335857214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1335857214
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3478303159
Short name T1379
Test name
Test status
Simulation time 1164625132 ps
CPU time 56.79 seconds
Started Jun 06 02:49:04 PM PDT 24
Finished Jun 06 02:50:02 PM PDT 24
Peak memory 310540 kb
Host smart-1c1b5d98-535a-4b17-a554-bffc08069fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478303159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3478303159
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.302974365
Short name T253
Test name
Test status
Simulation time 31095682221 ps
CPU time 2136.91 seconds
Started Jun 06 02:49:12 PM PDT 24
Finished Jun 06 03:24:51 PM PDT 24
Peak memory 2749056 kb
Host smart-3a3ec813-fbf6-4162-aee7-bb8b6aca0862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302974365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.302974365
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.3392763639
Short name T159
Test name
Test status
Simulation time 210969911 ps
CPU time 0.95 seconds
Started Jun 06 02:49:23 PM PDT 24
Finished Jun 06 02:49:25 PM PDT 24
Peak memory 222960 kb
Host smart-8aa6aab2-d9c0-4e19-93f1-a759b1c59194
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392763639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.3392763639
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.791000179
Short name T1011
Test name
Test status
Simulation time 1168598943 ps
CPU time 2.89 seconds
Started Jun 06 02:49:17 PM PDT 24
Finished Jun 06 02:49:21 PM PDT 24
Peak memory 205064 kb
Host smart-15c8ad34-2f66-4362-809e-95f26f7540a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791000179 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.791000179
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.3983701441
Short name T74
Test name
Test status
Simulation time 10122865295 ps
CPU time 54.11 seconds
Started Jun 06 02:49:16 PM PDT 24
Finished Jun 06 02:50:12 PM PDT 24
Peak memory 324324 kb
Host smart-431b2bc5-a289-40b9-ac90-f66c3e0b5141
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983701441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.3983701441
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1797275633
Short name T979
Test name
Test status
Simulation time 10618178340 ps
CPU time 14.9 seconds
Started Jun 06 02:49:15 PM PDT 24
Finished Jun 06 02:49:32 PM PDT 24
Peak memory 304564 kb
Host smart-b4dd39d8-5b9f-4848-a441-d77a389d7c62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797275633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1797275633
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.2367578553
Short name T1259
Test name
Test status
Simulation time 2127997173 ps
CPU time 2.78 seconds
Started Jun 06 02:49:12 PM PDT 24
Finished Jun 06 02:49:17 PM PDT 24
Peak memory 205008 kb
Host smart-e005704e-9c7d-4d79-8536-205fd37b391e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367578553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.2367578553
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.148352943
Short name T1224
Test name
Test status
Simulation time 1083094322 ps
CPU time 2.03 seconds
Started Jun 06 02:49:22 PM PDT 24
Finished Jun 06 02:49:25 PM PDT 24
Peak memory 205056 kb
Host smart-000c1093-e4ba-4539-8f62-87b99fdc7105
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148352943 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.148352943
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.2502234940
Short name T1265
Test name
Test status
Simulation time 1526066262 ps
CPU time 2.27 seconds
Started Jun 06 02:49:11 PM PDT 24
Finished Jun 06 02:49:14 PM PDT 24
Peak memory 205068 kb
Host smart-9d2d34ee-3487-4395-bf45-03049e9716c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502234940 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.2502234940
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2972626478
Short name T1080
Test name
Test status
Simulation time 17192100295 ps
CPU time 4.82 seconds
Started Jun 06 02:49:13 PM PDT 24
Finished Jun 06 02:49:19 PM PDT 24
Peak memory 205176 kb
Host smart-d1b48aa4-932e-4e13-bee4-306620d4f32a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972626478 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2972626478
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2106235817
Short name T1003
Test name
Test status
Simulation time 17900094931 ps
CPU time 54.63 seconds
Started Jun 06 02:49:15 PM PDT 24
Finished Jun 06 02:50:12 PM PDT 24
Peak memory 868544 kb
Host smart-a11d9dc7-de14-41b2-9d19-8c26fea4f343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106235817 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2106235817
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1372862413
Short name T1217
Test name
Test status
Simulation time 14243642670 ps
CPU time 20.34 seconds
Started Jun 06 02:49:12 PM PDT 24
Finished Jun 06 02:49:33 PM PDT 24
Peak memory 205180 kb
Host smart-3717a1d1-5e17-47b3-946a-9f0a82b06bc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372862413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1372862413
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1162096461
Short name T716
Test name
Test status
Simulation time 1821521191 ps
CPU time 29.53 seconds
Started Jun 06 02:49:17 PM PDT 24
Finished Jun 06 02:49:48 PM PDT 24
Peak memory 231208 kb
Host smart-c0f54f94-d657-4910-8d99-80089291e923
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162096461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1162096461
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.630953602
Short name T431
Test name
Test status
Simulation time 8372931755 ps
CPU time 15.11 seconds
Started Jun 06 02:49:14 PM PDT 24
Finished Jun 06 02:49:32 PM PDT 24
Peak memory 205052 kb
Host smart-0efd6648-bcaf-402d-a2a3-9b4844fa1f89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630953602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_wr.630953602
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.1377022883
Short name T1357
Test name
Test status
Simulation time 26190933437 ps
CPU time 486.08 seconds
Started Jun 06 02:49:13 PM PDT 24
Finished Jun 06 02:57:21 PM PDT 24
Peak memory 1487460 kb
Host smart-3915cf07-9dff-43e8-a596-edad5cc9c1b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377022883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.1377022883
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.565726012
Short name T440
Test name
Test status
Simulation time 4336338283 ps
CPU time 6.6 seconds
Started Jun 06 02:49:14 PM PDT 24
Finished Jun 06 02:49:23 PM PDT 24
Peak memory 221324 kb
Host smart-a2635c7a-d25d-4682-a7a4-1bae9274d766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565726012 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_timeout.565726012
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.3494969846
Short name T1355
Test name
Test status
Simulation time 1209429523 ps
CPU time 17.72 seconds
Started Jun 06 02:49:25 PM PDT 24
Finished Jun 06 02:49:43 PM PDT 24
Peak memory 205040 kb
Host smart-4fb0af05-77ef-4135-ba52-cb0073455d42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494969846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.3494969846
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1801258760
Short name T1313
Test name
Test status
Simulation time 16294775 ps
CPU time 0.63 seconds
Started Jun 06 02:53:04 PM PDT 24
Finished Jun 06 02:53:09 PM PDT 24
Peak memory 204796 kb
Host smart-54dd7fc9-6ccd-4f01-a2b2-e9db523d0a79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801258760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1801258760
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.1533286319
Short name T866
Test name
Test status
Simulation time 101616298 ps
CPU time 1.89 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:53:07 PM PDT 24
Peak memory 213492 kb
Host smart-1d66bd08-5519-4be3-96e0-d17e7cc897dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533286319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.1533286319
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3024180594
Short name T136
Test name
Test status
Simulation time 402669375 ps
CPU time 7.26 seconds
Started Jun 06 02:53:04 PM PDT 24
Finished Jun 06 02:53:15 PM PDT 24
Peak memory 288496 kb
Host smart-fe5e0de9-84e2-4de2-9bad-72881c17667c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024180594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3024180594
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3877730597
Short name T43
Test name
Test status
Simulation time 1818809661 ps
CPU time 131.36 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:55:20 PM PDT 24
Peak memory 656544 kb
Host smart-33a45057-c1d0-40f5-964f-770c565b9540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877730597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3877730597
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2539161296
Short name T742
Test name
Test status
Simulation time 1398612512 ps
CPU time 41.38 seconds
Started Jun 06 02:53:04 PM PDT 24
Finished Jun 06 02:53:49 PM PDT 24
Peak memory 443076 kb
Host smart-7f15170a-ab8e-4d1f-a400-c6920df83659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539161296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2539161296
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.1631771057
Short name T563
Test name
Test status
Simulation time 161547266 ps
CPU time 1.11 seconds
Started Jun 06 02:53:03 PM PDT 24
Finished Jun 06 02:53:08 PM PDT 24
Peak memory 204796 kb
Host smart-ef7b08dc-f28e-4b20-ad6c-0dd0344a86b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631771057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.1631771057
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.1891762185
Short name T551
Test name
Test status
Simulation time 279611952 ps
CPU time 3.33 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:53:09 PM PDT 24
Peak memory 224332 kb
Host smart-a32524a1-bc91-4dea-8918-5d07675b0b1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891762185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.1891762185
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.2413712385
Short name T1167
Test name
Test status
Simulation time 20308517733 ps
CPU time 181.88 seconds
Started Jun 06 02:53:03 PM PDT 24
Finished Jun 06 02:56:08 PM PDT 24
Peak memory 1498408 kb
Host smart-a4c81e5a-99cc-453e-8460-973eec5fac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413712385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.2413712385
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.2963587944
Short name T1264
Test name
Test status
Simulation time 1170959396 ps
CPU time 9.65 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:53:20 PM PDT 24
Peak memory 205044 kb
Host smart-8d9648c3-c128-4374-8210-c95d4996721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963587944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.2963587944
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3559564860
Short name T58
Test name
Test status
Simulation time 11996413230 ps
CPU time 54.48 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:54:03 PM PDT 24
Peak memory 334684 kb
Host smart-7b36bfed-6b0a-425a-a2ed-56e71de96cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559564860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3559564860
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.1096860885
Short name T983
Test name
Test status
Simulation time 61544242 ps
CPU time 0.65 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:53:06 PM PDT 24
Peak memory 204760 kb
Host smart-9f6df34e-dafb-45a2-8816-a2278cb51b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096860885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1096860885
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.217972697
Short name T33
Test name
Test status
Simulation time 6723595159 ps
CPU time 282.08 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:57:47 PM PDT 24
Peak memory 205260 kb
Host smart-0a6b8b8d-0b8e-486e-9071-a3da746271eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217972697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.217972697
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.4291575673
Short name T369
Test name
Test status
Simulation time 5354212576 ps
CPU time 20.27 seconds
Started Jun 06 02:53:03 PM PDT 24
Finished Jun 06 02:53:26 PM PDT 24
Peak memory 321168 kb
Host smart-586fb802-b72f-4dcf-b8a4-ecc16acd1944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291575673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.4291575673
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3027637817
Short name T49
Test name
Test status
Simulation time 146548846849 ps
CPU time 367.7 seconds
Started Jun 06 02:53:01 PM PDT 24
Finished Jun 06 02:59:12 PM PDT 24
Peak memory 1572356 kb
Host smart-78efa5e3-2903-4813-b722-fdd9eeadabfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027637817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3027637817
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3154721880
Short name T1012
Test name
Test status
Simulation time 7723403968 ps
CPU time 14.1 seconds
Started Jun 06 02:53:04 PM PDT 24
Finished Jun 06 02:53:22 PM PDT 24
Peak memory 219796 kb
Host smart-bab5a81a-a4d0-44f7-a326-a4a37f918292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154721880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3154721880
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3260478788
Short name T1032
Test name
Test status
Simulation time 2853791506 ps
CPU time 4.04 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:53:13 PM PDT 24
Peak memory 213380 kb
Host smart-66e52cc9-9272-43a1-a572-16bf04faf026
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260478788 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3260478788
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.1012077287
Short name T970
Test name
Test status
Simulation time 10233043745 ps
CPU time 47.3 seconds
Started Jun 06 02:53:04 PM PDT 24
Finished Jun 06 02:53:55 PM PDT 24
Peak memory 365320 kb
Host smart-e6859316-bee2-477b-90d4-07022a0003fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012077287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.1012077287
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.4128048598
Short name T412
Test name
Test status
Simulation time 10336657190 ps
CPU time 11.09 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:53:20 PM PDT 24
Peak memory 274892 kb
Host smart-22def1cd-69aa-442b-a766-850658a4b6a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128048598 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.4128048598
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.2310880993
Short name T1443
Test name
Test status
Simulation time 1474893377 ps
CPU time 2.09 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:53:11 PM PDT 24
Peak memory 205140 kb
Host smart-e85d619f-5946-4c31-a7c1-617a1789a672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310880993 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.2310880993
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.647650792
Short name T782
Test name
Test status
Simulation time 1081632535 ps
CPU time 5.57 seconds
Started Jun 06 02:53:03 PM PDT 24
Finished Jun 06 02:53:12 PM PDT 24
Peak memory 205152 kb
Host smart-0b66df81-514c-4bf4-ab62-25201ab0fee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647650792 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.647650792
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2983348795
Short name T1230
Test name
Test status
Simulation time 1656195321 ps
CPU time 2.57 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:53:12 PM PDT 24
Peak memory 205076 kb
Host smart-0b14a0d5-3b2a-4137-8762-bf251cf57b8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983348795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2983348795
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.3989838626
Short name T743
Test name
Test status
Simulation time 1324345500 ps
CPU time 6.64 seconds
Started Jun 06 02:53:04 PM PDT 24
Finished Jun 06 02:53:14 PM PDT 24
Peak memory 218704 kb
Host smart-40e828f7-8366-4ac7-8cec-c2ac13da2601
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989838626 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.3989838626
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.190317497
Short name T1301
Test name
Test status
Simulation time 18257674850 ps
CPU time 33.36 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:53:39 PM PDT 24
Peak memory 646012 kb
Host smart-548bdc36-dfb9-4d04-9d72-6b61b8b93290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190317497 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.190317497
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.4095468972
Short name T1478
Test name
Test status
Simulation time 4353331421 ps
CPU time 9.38 seconds
Started Jun 06 02:53:01 PM PDT 24
Finished Jun 06 02:53:14 PM PDT 24
Peak memory 205120 kb
Host smart-a58b0932-6aee-4297-947b-2de5de11fa29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095468972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.4095468972
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.3946512692
Short name T365
Test name
Test status
Simulation time 8772377470 ps
CPU time 5.21 seconds
Started Jun 06 02:53:03 PM PDT 24
Finished Jun 06 02:53:11 PM PDT 24
Peak memory 205080 kb
Host smart-95518f7c-2f89-4094-9c44-ebd27f90804d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946512692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.3946512692
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.2852861369
Short name T935
Test name
Test status
Simulation time 5634980699 ps
CPU time 36.06 seconds
Started Jun 06 02:53:03 PM PDT 24
Finished Jun 06 02:53:42 PM PDT 24
Peak memory 814708 kb
Host smart-14236f60-f62c-4347-8985-b7e37a19edc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852861369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.2852861369
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1771615073
Short name T1138
Test name
Test status
Simulation time 1134392396 ps
CPU time 7.14 seconds
Started Jun 06 02:53:01 PM PDT 24
Finished Jun 06 02:53:11 PM PDT 24
Peak memory 221404 kb
Host smart-dcfff2d8-c29a-4281-9a40-15716ebb78e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771615073 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1771615073
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.1027124364
Short name T1462
Test name
Test status
Simulation time 2503238876 ps
CPU time 29.74 seconds
Started Jun 06 02:53:04 PM PDT 24
Finished Jun 06 02:53:38 PM PDT 24
Peak memory 205120 kb
Host smart-edcf03af-f780-4ba8-ad4f-363248366d8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027124364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.1027124364
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2251945352
Short name T541
Test name
Test status
Simulation time 16488564 ps
CPU time 0.64 seconds
Started Jun 06 02:53:12 PM PDT 24
Finished Jun 06 02:53:16 PM PDT 24
Peak memory 204764 kb
Host smart-a1248e0a-fe7e-41f8-a66e-9cd292aa073f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251945352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2251945352
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.133109301
Short name T1172
Test name
Test status
Simulation time 83059064 ps
CPU time 1.24 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:53:11 PM PDT 24
Peak memory 213284 kb
Host smart-a9a31cda-57e4-41c0-87ce-b647fa65a216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133109301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.133109301
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.490022624
Short name T1486
Test name
Test status
Simulation time 594680236 ps
CPU time 6.61 seconds
Started Jun 06 02:53:07 PM PDT 24
Finished Jun 06 02:53:17 PM PDT 24
Peak memory 267904 kb
Host smart-5f09870d-8d7a-425c-86a7-76da890f2400
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490022624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_empt
y.490022624
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3066623464
Short name T1067
Test name
Test status
Simulation time 3497354580 ps
CPU time 103.77 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:54:54 PM PDT 24
Peak memory 501968 kb
Host smart-378f79f2-3028-420f-ade1-6082230e8297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066623464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3066623464
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.4084037281
Short name T1222
Test name
Test status
Simulation time 8335721606 ps
CPU time 90.51 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:54:41 PM PDT 24
Peak memory 785452 kb
Host smart-32a8c204-497f-4e6c-acc1-372ddd23b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084037281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.4084037281
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.4029769054
Short name T955
Test name
Test status
Simulation time 209528203 ps
CPU time 0.81 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:53:11 PM PDT 24
Peak memory 204724 kb
Host smart-890990aa-0e9f-4f45-8738-4b0d2220ed6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029769054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.4029769054
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.424542513
Short name T1371
Test name
Test status
Simulation time 171141656 ps
CPU time 3.31 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:53:14 PM PDT 24
Peak memory 205024 kb
Host smart-32bea6e1-7db8-42b2-8757-614fdaaba1fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424542513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.
424542513
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.217027414
Short name T445
Test name
Test status
Simulation time 9410406079 ps
CPU time 152.41 seconds
Started Jun 06 02:53:07 PM PDT 24
Finished Jun 06 02:55:44 PM PDT 24
Peak memory 746344 kb
Host smart-8dfd2e9a-a2d1-4efa-a99a-be2b2c5bac09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217027414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.217027414
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.2612123165
Short name T362
Test name
Test status
Simulation time 739842273 ps
CPU time 5.84 seconds
Started Jun 06 02:53:12 PM PDT 24
Finished Jun 06 02:53:20 PM PDT 24
Peak memory 205028 kb
Host smart-89613b43-3424-4dac-abd2-c311096997bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612123165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.2612123165
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.2911439762
Short name T50
Test name
Test status
Simulation time 6496763023 ps
CPU time 31.37 seconds
Started Jun 06 02:53:10 PM PDT 24
Finished Jun 06 02:53:45 PM PDT 24
Peak memory 344284 kb
Host smart-ede86f6b-3d03-44ad-a3ff-d6a4d12fbaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911439762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2911439762
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.4196132162
Short name T938
Test name
Test status
Simulation time 30698648 ps
CPU time 0.66 seconds
Started Jun 06 02:53:07 PM PDT 24
Finished Jun 06 02:53:12 PM PDT 24
Peak memory 204720 kb
Host smart-c3d7266d-f636-4f4e-9d27-21ec45e4d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196132162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.4196132162
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.964033523
Short name T1468
Test name
Test status
Simulation time 1624684679 ps
CPU time 20.61 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:53:31 PM PDT 24
Peak memory 252328 kb
Host smart-ad3fdf4a-0673-48e3-b888-13fcfcf11c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964033523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.964033523
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.2312265145
Short name T593
Test name
Test status
Simulation time 1510657072 ps
CPU time 69.23 seconds
Started Jun 06 02:53:07 PM PDT 24
Finished Jun 06 02:54:20 PM PDT 24
Peak memory 350992 kb
Host smart-2bdb93a9-1ad0-4f3c-a5df-8c29a0794b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312265145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.2312265145
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3973011851
Short name T244
Test name
Test status
Simulation time 687819004 ps
CPU time 31.75 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 02:53:41 PM PDT 24
Peak memory 213292 kb
Host smart-8590b196-3fbe-4554-ab87-28eb9f09e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973011851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3973011851
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.1043551873
Short name T1306
Test name
Test status
Simulation time 685272817 ps
CPU time 4.14 seconds
Started Jun 06 02:53:11 PM PDT 24
Finished Jun 06 02:53:18 PM PDT 24
Peak memory 213276 kb
Host smart-ff29a8c8-8c05-496f-8cd8-b0d548839c02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043551873 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.1043551873
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2853435244
Short name T596
Test name
Test status
Simulation time 10322484460 ps
CPU time 10.36 seconds
Started Jun 06 02:53:07 PM PDT 24
Finished Jun 06 02:53:21 PM PDT 24
Peak memory 248508 kb
Host smart-ad017911-b234-4ae4-9767-5e3a7fed3079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853435244 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2853435244
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.1779968306
Short name T543
Test name
Test status
Simulation time 10239838395 ps
CPU time 8.8 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:26 PM PDT 24
Peak memory 266588 kb
Host smart-68f8e194-4b79-48fc-947d-1597c1df5446
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779968306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.1779968306
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.3825135046
Short name T17
Test name
Test status
Simulation time 1351278006 ps
CPU time 6.05 seconds
Started Jun 06 02:53:11 PM PDT 24
Finished Jun 06 02:53:21 PM PDT 24
Peak memory 205136 kb
Host smart-2855fceb-08a7-42b6-89a0-0fc99168e931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825135046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.3825135046
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.3937956162
Short name T1289
Test name
Test status
Simulation time 1086093368 ps
CPU time 1.8 seconds
Started Jun 06 02:53:12 PM PDT 24
Finished Jun 06 02:53:18 PM PDT 24
Peak memory 205156 kb
Host smart-0cc6d42e-bf07-4281-a610-e737eed0e2b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937956162 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.3937956162
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3712628919
Short name T340
Test name
Test status
Simulation time 5645580740 ps
CPU time 2.38 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:20 PM PDT 24
Peak memory 205060 kb
Host smart-591cb3ae-f684-46bd-93a0-f49d5ddb129f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712628919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3712628919
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1429302899
Short name T446
Test name
Test status
Simulation time 1089882918 ps
CPU time 6.43 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:53:17 PM PDT 24
Peak memory 217828 kb
Host smart-1fdc8d88-eb6e-4de8-9e08-b25ec4351302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429302899 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1429302899
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2477651481
Short name T554
Test name
Test status
Simulation time 18262492882 ps
CPU time 276.81 seconds
Started Jun 06 02:53:07 PM PDT 24
Finished Jun 06 02:57:48 PM PDT 24
Peak memory 3016832 kb
Host smart-841a4e15-79f5-41d0-b66f-bc5ecf837994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477651481 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2477651481
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.824769347
Short name T1245
Test name
Test status
Simulation time 3794946145 ps
CPU time 29.77 seconds
Started Jun 06 02:53:07 PM PDT 24
Finished Jun 06 02:53:41 PM PDT 24
Peak memory 205056 kb
Host smart-47bd79e9-ec65-41be-8aff-3e0fd2021aee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824769347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.824769347
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.34542290
Short name T656
Test name
Test status
Simulation time 984936678 ps
CPU time 18.92 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:53:30 PM PDT 24
Peak memory 211260 kb
Host smart-ae6ca143-718a-4963-9fa2-d5d01ad91fa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34542290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stress_rd.34542290
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.2374909282
Short name T1246
Test name
Test status
Simulation time 67423143618 ps
CPU time 707.93 seconds
Started Jun 06 02:53:05 PM PDT 24
Finished Jun 06 03:04:58 PM PDT 24
Peak memory 5412848 kb
Host smart-26871c56-0b0a-4e03-b702-9a9afe21a134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374909282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.2374909282
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2075422887
Short name T568
Test name
Test status
Simulation time 1474638225 ps
CPU time 6.89 seconds
Started Jun 06 02:53:06 PM PDT 24
Finished Jun 06 02:53:17 PM PDT 24
Peak memory 213312 kb
Host smart-0db64e09-65e1-4af7-8365-7bc30c3c7bdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075422887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2075422887
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.3055835906
Short name T1116
Test name
Test status
Simulation time 1051763361 ps
CPU time 20.04 seconds
Started Jun 06 02:53:12 PM PDT 24
Finished Jun 06 02:53:35 PM PDT 24
Peak memory 205068 kb
Host smart-92896d9b-2057-4701-a036-f5d001c9ec86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055835906 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.3055835906
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2947783924
Short name T989
Test name
Test status
Simulation time 444904686 ps
CPU time 1.77 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:19 PM PDT 24
Peak memory 213336 kb
Host smart-d78f2250-5ae6-4439-817c-441b65f2264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947783924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2947783924
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.3971698831
Short name T819
Test name
Test status
Simulation time 448364242 ps
CPU time 9.48 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:53:32 PM PDT 24
Peak memory 269028 kb
Host smart-1df9ceba-2c9c-497a-a84c-62fae6e20081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971698831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.3971698831
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.118315452
Short name T615
Test name
Test status
Simulation time 1903736618 ps
CPU time 66.29 seconds
Started Jun 06 02:53:10 PM PDT 24
Finished Jun 06 02:54:19 PM PDT 24
Peak memory 669240 kb
Host smart-a7ae52fb-ccd0-4b09-ab8c-f390ab38a1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118315452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.118315452
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2045581668
Short name T777
Test name
Test status
Simulation time 7623325162 ps
CPU time 109.21 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:55:07 PM PDT 24
Peak memory 549544 kb
Host smart-008fd656-e998-47bb-b7fa-941ec83ccf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045581668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2045581668
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3403097262
Short name T53
Test name
Test status
Simulation time 323776685 ps
CPU time 0.86 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:18 PM PDT 24
Peak memory 204728 kb
Host smart-46e27867-2ec7-4448-a7bf-6d08ffd9f0d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403097262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3403097262
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2491633296
Short name T546
Test name
Test status
Simulation time 376142772 ps
CPU time 5.85 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:53:28 PM PDT 24
Peak memory 240784 kb
Host smart-7e17fba7-24ac-49bf-bf84-392a93421a92
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491633296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2491633296
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.4062766695
Short name T762
Test name
Test status
Simulation time 16971036154 ps
CPU time 128.18 seconds
Started Jun 06 02:53:13 PM PDT 24
Finished Jun 06 02:55:24 PM PDT 24
Peak memory 1153248 kb
Host smart-ca9f618b-02a1-4062-9da6-37a73fef5fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062766695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4062766695
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.489257585
Short name T223
Test name
Test status
Simulation time 3242673257 ps
CPU time 21.81 seconds
Started Jun 06 02:53:02 PM PDT 24
Finished Jun 06 02:53:27 PM PDT 24
Peak memory 205132 kb
Host smart-139faacc-a126-42bb-a618-2e109d274b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489257585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.489257585
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.312537613
Short name T1268
Test name
Test status
Simulation time 1398221396 ps
CPU time 28.35 seconds
Started Jun 06 02:53:13 PM PDT 24
Finished Jun 06 02:53:45 PM PDT 24
Peak memory 376924 kb
Host smart-f6cf915e-5e77-4fee-9331-37df59847aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312537613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.312537613
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2502352354
Short name T1046
Test name
Test status
Simulation time 41714481 ps
CPU time 0.64 seconds
Started Jun 06 02:53:13 PM PDT 24
Finished Jun 06 02:53:17 PM PDT 24
Peak memory 204732 kb
Host smart-aaeaf1de-ab65-4fd7-b329-b533086b059a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502352354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2502352354
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1961830723
Short name T403
Test name
Test status
Simulation time 24020635826 ps
CPU time 117.84 seconds
Started Jun 06 02:53:13 PM PDT 24
Finished Jun 06 02:55:14 PM PDT 24
Peak memory 205128 kb
Host smart-85931736-fbb0-4a46-8905-75ac855eceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961830723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1961830723
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.1035695885
Short name T1341
Test name
Test status
Simulation time 6966758658 ps
CPU time 36.85 seconds
Started Jun 06 02:53:11 PM PDT 24
Finished Jun 06 02:53:51 PM PDT 24
Peak memory 406228 kb
Host smart-b4071486-c574-4b17-9b07-120dc52a48fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035695885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.1035695885
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.2378436781
Short name T1109
Test name
Test status
Simulation time 2384195704 ps
CPU time 10.84 seconds
Started Jun 06 02:53:10 PM PDT 24
Finished Jun 06 02:53:24 PM PDT 24
Peak memory 213416 kb
Host smart-daac0e3f-7240-4295-8b66-84297d9b3713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378436781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.2378436781
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2735458633
Short name T770
Test name
Test status
Simulation time 10652784083 ps
CPU time 11.3 seconds
Started Jun 06 02:53:13 PM PDT 24
Finished Jun 06 02:53:27 PM PDT 24
Peak memory 250196 kb
Host smart-84fc4796-3195-4ca8-8a66-3f5a9706f4d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735458633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2735458633
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2721925308
Short name T501
Test name
Test status
Simulation time 10191356381 ps
CPU time 71.53 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:54:29 PM PDT 24
Peak memory 575860 kb
Host smart-df18b2f9-9842-44d4-a585-21a8f43efc7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721925308 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2721925308
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.30463898
Short name T886
Test name
Test status
Simulation time 1517945184 ps
CPU time 4.16 seconds
Started Jun 06 02:53:15 PM PDT 24
Finished Jun 06 02:53:23 PM PDT 24
Peak memory 205124 kb
Host smart-306622b8-bc82-44fa-a99b-505566b675ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30463898 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.30463898
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.4105569979
Short name T1027
Test name
Test status
Simulation time 1148364854 ps
CPU time 5.48 seconds
Started Jun 06 02:53:18 PM PDT 24
Finished Jun 06 02:53:28 PM PDT 24
Peak memory 205244 kb
Host smart-2eded0fc-4a36-45e4-8579-84046a078d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105569979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.4105569979
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2538743463
Short name T792
Test name
Test status
Simulation time 1808928885 ps
CPU time 2.77 seconds
Started Jun 06 02:53:16 PM PDT 24
Finished Jun 06 02:53:22 PM PDT 24
Peak memory 205096 kb
Host smart-6baac85a-a0dc-433c-9f46-25dc4193a528
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538743463 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2538743463
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.870282268
Short name T899
Test name
Test status
Simulation time 1382823738 ps
CPU time 4.18 seconds
Started Jun 06 02:53:15 PM PDT 24
Finished Jun 06 02:53:23 PM PDT 24
Peak memory 205048 kb
Host smart-03f36b70-ae1d-4874-97da-f2f5bc4ceb0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870282268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_intr_smoke.870282268
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1041860046
Short name T764
Test name
Test status
Simulation time 5542833435 ps
CPU time 2.67 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:20 PM PDT 24
Peak memory 205156 kb
Host smart-f12e17dd-5b67-4719-bd68-78f3a3392953
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041860046 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1041860046
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.751059923
Short name T481
Test name
Test status
Simulation time 1683661928 ps
CPU time 33.89 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:51 PM PDT 24
Peak memory 205140 kb
Host smart-096b2197-64ee-4393-96e7-782ad9bf2d51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751059923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.751059923
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_all.1197604843
Short name T1191
Test name
Test status
Simulation time 43722072466 ps
CPU time 1580.58 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 03:19:44 PM PDT 24
Peak memory 6845624 kb
Host smart-ff7b5e47-1618-451a-9c64-3f1fc3e334aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197604843 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.i2c_target_stress_all.1197604843
Directory /workspace/22.i2c_target_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.403743644
Short name T1195
Test name
Test status
Simulation time 306734408 ps
CPU time 5.88 seconds
Started Jun 06 02:53:14 PM PDT 24
Finished Jun 06 02:53:23 PM PDT 24
Peak memory 205080 kb
Host smart-5a5bf5a5-31f3-40f7-bba0-50ca349100d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403743644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_rd.403743644
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.3602164417
Short name T1058
Test name
Test status
Simulation time 39842099880 ps
CPU time 200.47 seconds
Started Jun 06 02:53:13 PM PDT 24
Finished Jun 06 02:56:37 PM PDT 24
Peak memory 2570244 kb
Host smart-5dee581d-c84e-4463-afdd-4fc18d5bd640
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602164417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.3602164417
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.1977104341
Short name T834
Test name
Test status
Simulation time 24692517369 ps
CPU time 1629.44 seconds
Started Jun 06 02:53:12 PM PDT 24
Finished Jun 06 03:20:25 PM PDT 24
Peak memory 3028844 kb
Host smart-a886fff1-a3d8-48eb-9e3f-8102ea1f50bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977104341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.1977104341
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.305730137
Short name T390
Test name
Test status
Simulation time 17580240069 ps
CPU time 7.58 seconds
Started Jun 06 02:53:13 PM PDT 24
Finished Jun 06 02:53:24 PM PDT 24
Peak memory 219420 kb
Host smart-b2cf0d6c-d86e-4dab-bc9a-30cc51f23b0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305730137 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.305730137
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.3571950477
Short name T1185
Test name
Test status
Simulation time 1052445992 ps
CPU time 16.37 seconds
Started Jun 06 02:53:15 PM PDT 24
Finished Jun 06 02:53:34 PM PDT 24
Peak memory 205032 kb
Host smart-d9190053-0b58-45fe-b3fd-d316aed149b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571950477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.3571950477
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2254985824
Short name T479
Test name
Test status
Simulation time 41242960 ps
CPU time 0.62 seconds
Started Jun 06 02:53:27 PM PDT 24
Finished Jun 06 02:53:29 PM PDT 24
Peak memory 204704 kb
Host smart-b936ea7f-cf60-4f5b-87c7-c3ccc4a33f05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254985824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2254985824
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.1970783611
Short name T707
Test name
Test status
Simulation time 344014024 ps
CPU time 6.22 seconds
Started Jun 06 02:53:21 PM PDT 24
Finished Jun 06 02:53:31 PM PDT 24
Peak memory 234740 kb
Host smart-ddfdaf12-7cab-4def-84bb-88940c9a70f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970783611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.1970783611
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2672332019
Short name T692
Test name
Test status
Simulation time 256326698 ps
CPU time 13.07 seconds
Started Jun 06 02:53:18 PM PDT 24
Finished Jun 06 02:53:35 PM PDT 24
Peak memory 255580 kb
Host smart-05bfb080-2b0c-408d-9157-c2517f9d0f33
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672332019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2672332019
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.674786857
Short name T659
Test name
Test status
Simulation time 5279414064 ps
CPU time 102.74 seconds
Started Jun 06 02:53:20 PM PDT 24
Finished Jun 06 02:55:06 PM PDT 24
Peak memory 849068 kb
Host smart-5811a111-59cf-4841-90af-037d6776a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674786857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.674786857
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3637400714
Short name T1021
Test name
Test status
Simulation time 3986349423 ps
CPU time 146.15 seconds
Started Jun 06 02:53:15 PM PDT 24
Finished Jun 06 02:55:44 PM PDT 24
Peak memory 654344 kb
Host smart-9deda4e5-5ebd-4d24-9f2f-1e4436b0c5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637400714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3637400714
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1122884461
Short name T402
Test name
Test status
Simulation time 79259575 ps
CPU time 0.86 seconds
Started Jun 06 02:53:15 PM PDT 24
Finished Jun 06 02:53:20 PM PDT 24
Peak memory 204776 kb
Host smart-b40d1404-fe3d-4f65-a4d3-6c1e072b09cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122884461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1122884461
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.3521442868
Short name T1103
Test name
Test status
Simulation time 3026007873 ps
CPU time 5.47 seconds
Started Jun 06 02:53:17 PM PDT 24
Finished Jun 06 02:53:26 PM PDT 24
Peak memory 205084 kb
Host smart-e3671d7e-48a8-4a9d-8283-409bd7419d9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521442868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.3521442868
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.32876986
Short name T104
Test name
Test status
Simulation time 53652149747 ps
CPU time 60.46 seconds
Started Jun 06 02:53:18 PM PDT 24
Finished Jun 06 02:54:23 PM PDT 24
Peak memory 843680 kb
Host smart-31adb493-6ea6-47ba-a59d-89c4d17c6c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32876986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.32876986
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.2343735230
Short name T702
Test name
Test status
Simulation time 2009817467 ps
CPU time 5.92 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:53:29 PM PDT 24
Peak memory 204960 kb
Host smart-cd2e4dd9-0f3d-4ea2-9520-af4429d86497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343735230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.2343735230
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.1412927485
Short name T1129
Test name
Test status
Simulation time 1420380716 ps
CPU time 22.89 seconds
Started Jun 06 02:53:27 PM PDT 24
Finished Jun 06 02:53:52 PM PDT 24
Peak memory 343912 kb
Host smart-24848894-c5d3-4fa0-966f-4de62d1b7c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412927485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.1412927485
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.4254000944
Short name T131
Test name
Test status
Simulation time 18968876 ps
CPU time 0.67 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:53:23 PM PDT 24
Peak memory 204964 kb
Host smart-f9e89563-608a-423f-854b-d7cc3b58e2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254000944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.4254000944
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.390455636
Short name T55
Test name
Test status
Simulation time 516523596 ps
CPU time 22.39 seconds
Started Jun 06 02:53:17 PM PDT 24
Finished Jun 06 02:53:43 PM PDT 24
Peak memory 257888 kb
Host smart-f5c1876a-b92e-4a67-a84a-fe8661501ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390455636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.390455636
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1990221519
Short name T396
Test name
Test status
Simulation time 1302611251 ps
CPU time 24.98 seconds
Started Jun 06 02:53:13 PM PDT 24
Finished Jun 06 02:53:41 PM PDT 24
Peak memory 276772 kb
Host smart-2a3d26f5-c8dc-469e-a654-a8d33c602b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990221519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1990221519
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.3535932598
Short name T123
Test name
Test status
Simulation time 12140693892 ps
CPU time 775.01 seconds
Started Jun 06 02:53:26 PM PDT 24
Finished Jun 06 03:06:23 PM PDT 24
Peak memory 2477120 kb
Host smart-62bad4d5-ec2c-45af-b831-80339b173963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535932598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.3535932598
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.174786157
Short name T1017
Test name
Test status
Simulation time 693638124 ps
CPU time 23.71 seconds
Started Jun 06 02:53:21 PM PDT 24
Finished Jun 06 02:53:48 PM PDT 24
Peak memory 213316 kb
Host smart-889c21b1-f5d0-4ac9-ae91-c78ae231f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174786157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.174786157
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1936823605
Short name T711
Test name
Test status
Simulation time 482616451 ps
CPU time 2.87 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:53:26 PM PDT 24
Peak memory 205116 kb
Host smart-2a7dd187-ec01-439a-a71f-d15ad34cc573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936823605 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1936823605
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2215604973
Short name T1489
Test name
Test status
Simulation time 10193116130 ps
CPU time 24.91 seconds
Started Jun 06 02:53:22 PM PDT 24
Finished Jun 06 02:53:50 PM PDT 24
Peak memory 319816 kb
Host smart-56fcb88a-bf9b-40f1-8274-fa43aabea0cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215604973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2215604973
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.94973216
Short name T1348
Test name
Test status
Simulation time 10468732234 ps
CPU time 23.66 seconds
Started Jun 06 02:53:22 PM PDT 24
Finished Jun 06 02:53:49 PM PDT 24
Peak memory 341772 kb
Host smart-9be93ddf-e7fc-42a5-a08b-5c5ba22471b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94973216 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.i2c_target_fifo_reset_tx.94973216
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.1347847005
Short name T1423
Test name
Test status
Simulation time 1163334964 ps
CPU time 3.85 seconds
Started Jun 06 02:53:24 PM PDT 24
Finished Jun 06 02:53:31 PM PDT 24
Peak memory 205048 kb
Host smart-794bd8ce-fae1-4805-8b5e-aca139802e3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347847005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.1347847005
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.2761746578
Short name T898
Test name
Test status
Simulation time 1407436698 ps
CPU time 2.17 seconds
Started Jun 06 02:53:20 PM PDT 24
Finished Jun 06 02:53:26 PM PDT 24
Peak memory 205108 kb
Host smart-8da63fbf-4f33-41ef-84ec-cb9c004447fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761746578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.2761746578
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.1847787545
Short name T229
Test name
Test status
Simulation time 924859759 ps
CPU time 2.79 seconds
Started Jun 06 02:53:22 PM PDT 24
Finished Jun 06 02:53:28 PM PDT 24
Peak memory 205024 kb
Host smart-e7d13d14-1846-4b27-a0df-9d2c51909d18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847787545 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.1847787545
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.876406268
Short name T715
Test name
Test status
Simulation time 987719957 ps
CPU time 5.11 seconds
Started Jun 06 02:53:21 PM PDT 24
Finished Jun 06 02:53:29 PM PDT 24
Peak memory 205140 kb
Host smart-1f95350c-ff62-4fb0-b1ac-70d02f142b6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876406268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_intr_smoke.876406268
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.2797757142
Short name T1317
Test name
Test status
Simulation time 9595499988 ps
CPU time 11.97 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:53:34 PM PDT 24
Peak memory 313084 kb
Host smart-2203e98d-5478-4155-bf29-716e71a63434
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797757142 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.2797757142
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.1667963709
Short name T1229
Test name
Test status
Simulation time 3312446265 ps
CPU time 57.82 seconds
Started Jun 06 02:53:27 PM PDT 24
Finished Jun 06 02:54:27 PM PDT 24
Peak memory 205148 kb
Host smart-491cafff-6185-4b8f-b928-79e1f7ba6019
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667963709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.1667963709
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.2942375340
Short name T1407
Test name
Test status
Simulation time 981370694 ps
CPU time 17.64 seconds
Started Jun 06 02:53:22 PM PDT 24
Finished Jun 06 02:53:43 PM PDT 24
Peak memory 211032 kb
Host smart-64f23765-5327-40f2-b1ef-7dd7b9d1a264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942375340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.2942375340
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.290923107
Short name T910
Test name
Test status
Simulation time 8411244469 ps
CPU time 9.5 seconds
Started Jun 06 02:53:22 PM PDT 24
Finished Jun 06 02:53:35 PM PDT 24
Peak memory 205108 kb
Host smart-ec47ab14-f84d-4ad0-8f33-e0240fef72d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290923107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_wr.290923107
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2633178869
Short name T374
Test name
Test status
Simulation time 23441681662 ps
CPU time 1135.95 seconds
Started Jun 06 02:53:22 PM PDT 24
Finished Jun 06 03:12:21 PM PDT 24
Peak memory 2409104 kb
Host smart-4f26cebf-487f-4b6a-8a3a-f2a4073d34ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633178869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2633178869
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3771837012
Short name T524
Test name
Test status
Simulation time 1095796841 ps
CPU time 6.97 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:53:30 PM PDT 24
Peak memory 213352 kb
Host smart-80392bee-1aeb-4cc5-8699-55c8a0bcc962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771837012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3771837012
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.2565624241
Short name T20
Test name
Test status
Simulation time 1041730041 ps
CPU time 17.83 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:53:40 PM PDT 24
Peak memory 205100 kb
Host smart-b825122c-2c64-4624-99d6-474286062b5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565624241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.2565624241
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.2687457383
Short name T80
Test name
Test status
Simulation time 65140053 ps
CPU time 0.62 seconds
Started Jun 06 02:53:31 PM PDT 24
Finished Jun 06 02:53:35 PM PDT 24
Peak memory 204740 kb
Host smart-4ec026c9-a1cc-421a-86da-37fb80addc3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687457383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.2687457383
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.4153861659
Short name T851
Test name
Test status
Simulation time 185593532 ps
CPU time 1.45 seconds
Started Jun 06 02:53:27 PM PDT 24
Finished Jun 06 02:53:31 PM PDT 24
Peak memory 216836 kb
Host smart-057300da-6f8d-4af1-b89c-ad85bc37006a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153861659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.4153861659
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3535724939
Short name T863
Test name
Test status
Simulation time 1272078089 ps
CPU time 7.12 seconds
Started Jun 06 02:53:24 PM PDT 24
Finished Jun 06 02:53:33 PM PDT 24
Peak memory 227904 kb
Host smart-2071efb8-3195-47b1-8c42-f5a9e68248c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535724939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3535724939
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.448927886
Short name T908
Test name
Test status
Simulation time 2588940492 ps
CPU time 186.53 seconds
Started Jun 06 02:53:26 PM PDT 24
Finished Jun 06 02:56:35 PM PDT 24
Peak memory 794420 kb
Host smart-82823349-2998-439c-9f9b-647e2e2c4d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448927886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.448927886
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1045341962
Short name T831
Test name
Test status
Simulation time 3977976119 ps
CPU time 62.67 seconds
Started Jun 06 02:53:28 PM PDT 24
Finished Jun 06 02:54:33 PM PDT 24
Peak memory 649056 kb
Host smart-f7150ff7-dfa0-4e0c-b17d-869fd8d86283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045341962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1045341962
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.873396769
Short name T676
Test name
Test status
Simulation time 505452500 ps
CPU time 1.02 seconds
Started Jun 06 02:53:26 PM PDT 24
Finished Jun 06 02:53:30 PM PDT 24
Peak memory 204752 kb
Host smart-06cc62ca-fcbf-4c10-8c89-082fb6eb967a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873396769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.873396769
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.2599131359
Short name T1414
Test name
Test status
Simulation time 280214942 ps
CPU time 2.97 seconds
Started Jun 06 02:53:23 PM PDT 24
Finished Jun 06 02:53:28 PM PDT 24
Peak memory 205068 kb
Host smart-c73a05d3-af50-4e66-906c-d27f70b8a9dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599131359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.2599131359
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2870799681
Short name T1135
Test name
Test status
Simulation time 15643023555 ps
CPU time 64.69 seconds
Started Jun 06 02:53:23 PM PDT 24
Finished Jun 06 02:54:31 PM PDT 24
Peak memory 846660 kb
Host smart-4c2de12e-0303-4528-9458-a6c460966edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870799681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2870799681
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.3263437190
Short name T1210
Test name
Test status
Simulation time 298569169 ps
CPU time 6.26 seconds
Started Jun 06 02:53:32 PM PDT 24
Finished Jun 06 02:53:42 PM PDT 24
Peak memory 205084 kb
Host smart-0168d76b-a9b1-4456-a1b2-341bb4b0a455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263437190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.3263437190
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1475396366
Short name T257
Test name
Test status
Simulation time 1308222049 ps
CPU time 27.17 seconds
Started Jun 06 02:53:27 PM PDT 24
Finished Jun 06 02:53:56 PM PDT 24
Peak memory 356328 kb
Host smart-4195122d-c60f-4fcb-b3b4-3995d4115494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475396366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1475396366
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.2162634062
Short name T1460
Test name
Test status
Simulation time 28488549 ps
CPU time 0.7 seconds
Started Jun 06 02:53:23 PM PDT 24
Finished Jun 06 02:53:26 PM PDT 24
Peak memory 204712 kb
Host smart-13670b7b-039a-4029-b084-7125e622d5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162634062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2162634062
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.2092811764
Short name T999
Test name
Test status
Simulation time 5330548894 ps
CPU time 21.93 seconds
Started Jun 06 02:53:22 PM PDT 24
Finished Jun 06 02:53:47 PM PDT 24
Peak memory 229500 kb
Host smart-32969894-bd50-41d8-8db3-fc1af34d38fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092811764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.2092811764
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2399220133
Short name T1477
Test name
Test status
Simulation time 6829493979 ps
CPU time 72.58 seconds
Started Jun 06 02:53:19 PM PDT 24
Finished Jun 06 02:54:35 PM PDT 24
Peak memory 273872 kb
Host smart-bedc40d2-5fff-4890-87d8-999c897c9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399220133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2399220133
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.1687637676
Short name T471
Test name
Test status
Simulation time 1674662530 ps
CPU time 8.27 seconds
Started Jun 06 02:53:32 PM PDT 24
Finished Jun 06 02:53:44 PM PDT 24
Peak memory 213336 kb
Host smart-5f82cd5e-442a-4820-ab19-7bf878b97c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687637676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1687637676
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.977029542
Short name T725
Test name
Test status
Simulation time 12909993277 ps
CPU time 4.33 seconds
Started Jun 06 02:53:24 PM PDT 24
Finished Jun 06 02:53:30 PM PDT 24
Peak memory 213420 kb
Host smart-b2b7d4b6-401b-4e32-ac30-6208e5f3b119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977029542 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.977029542
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1415723038
Short name T69
Test name
Test status
Simulation time 10318554670 ps
CPU time 12.94 seconds
Started Jun 06 02:53:33 PM PDT 24
Finished Jun 06 02:53:50 PM PDT 24
Peak memory 242408 kb
Host smart-57df74b6-1463-4ff6-8519-4ecd50efb2c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415723038 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1415723038
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2729123667
Short name T761
Test name
Test status
Simulation time 10074233512 ps
CPU time 80.38 seconds
Started Jun 06 02:53:33 PM PDT 24
Finished Jun 06 02:54:58 PM PDT 24
Peak memory 642196 kb
Host smart-f0552769-1a74-42c9-8c39-d7aea6272696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729123667 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2729123667
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.4291289756
Short name T1376
Test name
Test status
Simulation time 3349068207 ps
CPU time 2.21 seconds
Started Jun 06 02:53:33 PM PDT 24
Finished Jun 06 02:53:40 PM PDT 24
Peak memory 205108 kb
Host smart-f33e188e-425e-4976-977b-87937f431faa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291289756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.4291289756
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.2046077081
Short name T468
Test name
Test status
Simulation time 1691315063 ps
CPU time 2.59 seconds
Started Jun 06 02:53:26 PM PDT 24
Finished Jun 06 02:53:31 PM PDT 24
Peak memory 205128 kb
Host smart-eed2fb23-9b9d-430a-8941-6b5a1188b202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046077081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.2046077081
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.215789465
Short name T1184
Test name
Test status
Simulation time 1883512899 ps
CPU time 2.53 seconds
Started Jun 06 02:53:25 PM PDT 24
Finished Jun 06 02:53:30 PM PDT 24
Peak memory 205060 kb
Host smart-62340627-0aa8-4f34-a3b1-7b5d084fc4e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215789465 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.215789465
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2179121058
Short name T394
Test name
Test status
Simulation time 1165780795 ps
CPU time 4.67 seconds
Started Jun 06 02:53:27 PM PDT 24
Finished Jun 06 02:53:34 PM PDT 24
Peak memory 205060 kb
Host smart-81a6b2b9-7e87-4c4b-ba36-0ea9308bbfca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179121058 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2179121058
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.243166875
Short name T1114
Test name
Test status
Simulation time 16816432690 ps
CPU time 59 seconds
Started Jun 06 02:53:25 PM PDT 24
Finished Jun 06 02:54:26 PM PDT 24
Peak memory 1239916 kb
Host smart-cc9a27a1-f7e0-4fb5-b597-fb2f220dd75d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243166875 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.243166875
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.698940849
Short name T875
Test name
Test status
Simulation time 2778747429 ps
CPU time 50.86 seconds
Started Jun 06 02:53:25 PM PDT 24
Finished Jun 06 02:54:19 PM PDT 24
Peak memory 205196 kb
Host smart-8cfaafd4-4dda-451e-a6de-b13e5fc2f647
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698940849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.698940849
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.870743326
Short name T760
Test name
Test status
Simulation time 1093591626 ps
CPU time 15.97 seconds
Started Jun 06 02:53:33 PM PDT 24
Finished Jun 06 02:53:53 PM PDT 24
Peak memory 219240 kb
Host smart-504c7bd1-3ca2-4a41-8c3e-947d123d8bd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870743326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.870743326
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3979717319
Short name T868
Test name
Test status
Simulation time 46684531386 ps
CPU time 595.18 seconds
Started Jun 06 02:53:27 PM PDT 24
Finished Jun 06 03:03:25 PM PDT 24
Peak memory 4392628 kb
Host smart-6a6d829b-46ea-490e-9d26-82c0f412e653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979717319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3979717319
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.183490661
Short name T1164
Test name
Test status
Simulation time 8633560145 ps
CPU time 47.16 seconds
Started Jun 06 02:53:27 PM PDT 24
Finished Jun 06 02:54:16 PM PDT 24
Peak memory 642888 kb
Host smart-2cb56b4e-b57d-4e14-91d8-d90a2d4b2ab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183490661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stretch.183490661
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2408351963
Short name T684
Test name
Test status
Simulation time 6199836876 ps
CPU time 7.65 seconds
Started Jun 06 02:53:33 PM PDT 24
Finished Jun 06 02:53:45 PM PDT 24
Peak memory 213364 kb
Host smart-7bf804f6-f1f2-4d47-96bc-095a08186ec6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408351963 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2408351963
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.146861280
Short name T491
Test name
Test status
Simulation time 1310206539 ps
CPU time 17.3 seconds
Started Jun 06 02:53:33 PM PDT 24
Finished Jun 06 02:53:54 PM PDT 24
Peak memory 205064 kb
Host smart-c6bbbe1a-94cc-4cf0-a8fe-96d075bcf1a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146861280 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.146861280
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.1769010098
Short name T586
Test name
Test status
Simulation time 28492612 ps
CPU time 0.63 seconds
Started Jun 06 02:53:48 PM PDT 24
Finished Jun 06 02:53:52 PM PDT 24
Peak memory 204688 kb
Host smart-34b0cba3-2875-4c7e-b1ea-23dd390b12cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769010098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.1769010098
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.1096340598
Short name T1014
Test name
Test status
Simulation time 291325989 ps
CPU time 2.25 seconds
Started Jun 06 02:53:31 PM PDT 24
Finished Jun 06 02:53:36 PM PDT 24
Peak memory 213348 kb
Host smart-cba3632e-ed4b-429e-bc5b-8e3b9227e8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096340598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.1096340598
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2361442377
Short name T1157
Test name
Test status
Simulation time 7790119575 ps
CPU time 9.21 seconds
Started Jun 06 02:53:34 PM PDT 24
Finished Jun 06 02:53:47 PM PDT 24
Peak memory 294520 kb
Host smart-0cce3066-41f4-41a0-923a-2e2d446e97c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361442377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2361442377
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2340657941
Short name T284
Test name
Test status
Simulation time 8696627349 ps
CPU time 156.64 seconds
Started Jun 06 02:53:34 PM PDT 24
Finished Jun 06 02:56:15 PM PDT 24
Peak memory 726024 kb
Host smart-382884af-48c9-4f6d-b050-0cecacb5f5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340657941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2340657941
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.2887239049
Short name T865
Test name
Test status
Simulation time 2211062833 ps
CPU time 182.16 seconds
Started Jun 06 02:53:32 PM PDT 24
Finished Jun 06 02:56:38 PM PDT 24
Peak memory 746192 kb
Host smart-7a84907e-1af9-4a21-8fd0-4a954dca2123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887239049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.2887239049
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1425242510
Short name T453
Test name
Test status
Simulation time 422894497 ps
CPU time 1.02 seconds
Started Jun 06 02:53:35 PM PDT 24
Finished Jun 06 02:53:39 PM PDT 24
Peak memory 204928 kb
Host smart-436544b9-7ff7-4746-93a2-9be307f7b581
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425242510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1425242510
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3435524612
Short name T1456
Test name
Test status
Simulation time 521996967 ps
CPU time 7.82 seconds
Started Jun 06 02:53:30 PM PDT 24
Finished Jun 06 02:53:41 PM PDT 24
Peak memory 226612 kb
Host smart-1f0b9d58-d6ca-4acd-8383-5d8fd1086b99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435524612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3435524612
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.354929953
Short name T1487
Test name
Test status
Simulation time 5164962922 ps
CPU time 167.52 seconds
Started Jun 06 02:53:34 PM PDT 24
Finished Jun 06 02:56:26 PM PDT 24
Peak memory 1455276 kb
Host smart-25dd6bb6-8f20-4bef-b9f2-60bd04f26133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354929953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.354929953
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2151980325
Short name T685
Test name
Test status
Simulation time 337198115 ps
CPU time 4.44 seconds
Started Jun 06 02:53:46 PM PDT 24
Finished Jun 06 02:53:54 PM PDT 24
Peak memory 205052 kb
Host smart-223618ed-27f1-432f-960b-577126a547ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151980325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2151980325
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.4033660428
Short name T1463
Test name
Test status
Simulation time 1801207434 ps
CPU time 95.79 seconds
Started Jun 06 02:53:39 PM PDT 24
Finished Jun 06 02:55:18 PM PDT 24
Peak memory 438896 kb
Host smart-e45318c1-745f-4750-8ef6-c7b62fa907f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033660428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.4033660428
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2075711150
Short name T1119
Test name
Test status
Simulation time 20543037 ps
CPU time 0.66 seconds
Started Jun 06 02:53:31 PM PDT 24
Finished Jun 06 02:53:34 PM PDT 24
Peak memory 204688 kb
Host smart-b6f3e71f-2004-4ae4-932c-1b55f3304873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075711150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2075711150
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.4073678020
Short name T1010
Test name
Test status
Simulation time 4443999928 ps
CPU time 21.94 seconds
Started Jun 06 02:53:30 PM PDT 24
Finished Jun 06 02:53:55 PM PDT 24
Peak memory 205220 kb
Host smart-63bd6c5d-5680-44fd-9533-2659df1ea82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073678020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.4073678020
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.4173785844
Short name T740
Test name
Test status
Simulation time 11687773899 ps
CPU time 27.49 seconds
Started Jun 06 02:53:33 PM PDT 24
Finished Jun 06 02:54:04 PM PDT 24
Peak memory 297624 kb
Host smart-4abdd5a3-af90-497d-95eb-539a103bab92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173785844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.4173785844
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.4192746264
Short name T1190
Test name
Test status
Simulation time 74305914057 ps
CPU time 1449.13 seconds
Started Jun 06 02:53:33 PM PDT 24
Finished Jun 06 03:17:46 PM PDT 24
Peak memory 2442988 kb
Host smart-fefd14b0-857c-425e-bb78-33f9b1fac8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192746264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.4192746264
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1729541306
Short name T283
Test name
Test status
Simulation time 645490654 ps
CPU time 25.66 seconds
Started Jun 06 02:53:32 PM PDT 24
Finished Jun 06 02:54:01 PM PDT 24
Peak memory 213244 kb
Host smart-f87c0927-c0b8-4bb1-836d-e9f60ab6a92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729541306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1729541306
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.10569297
Short name T504
Test name
Test status
Simulation time 901064055 ps
CPU time 4.71 seconds
Started Jun 06 02:53:38 PM PDT 24
Finished Jun 06 02:53:46 PM PDT 24
Peak memory 213344 kb
Host smart-be4474e5-7683-4fc7-b735-258d2b63b551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10569297 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_bad_addr.10569297
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.4018436241
Short name T1227
Test name
Test status
Simulation time 10155488192 ps
CPU time 47.22 seconds
Started Jun 06 02:53:39 PM PDT 24
Finished Jun 06 02:54:30 PM PDT 24
Peak memory 355568 kb
Host smart-1b69ac47-0b8f-4477-a3f7-654d1c911fb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018436241 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.4018436241
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2448963790
Short name T472
Test name
Test status
Simulation time 10490507281 ps
CPU time 7.91 seconds
Started Jun 06 02:53:40 PM PDT 24
Finished Jun 06 02:53:52 PM PDT 24
Peak memory 244992 kb
Host smart-a8c226f9-2881-4d99-b12d-e84bd5009637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448963790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2448963790
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.301486115
Short name T619
Test name
Test status
Simulation time 1505541084 ps
CPU time 7.08 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:54:00 PM PDT 24
Peak memory 205080 kb
Host smart-e2ba97eb-8130-4dbd-9906-225985856fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301486115 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.301486115
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.3416820529
Short name T1391
Test name
Test status
Simulation time 1122866521 ps
CPU time 5.68 seconds
Started Jun 06 02:53:48 PM PDT 24
Finished Jun 06 02:53:58 PM PDT 24
Peak memory 205048 kb
Host smart-4688a6cb-c8f4-47bd-90a2-43e898b45d3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416820529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.3416820529
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.2309260379
Short name T628
Test name
Test status
Simulation time 385895741 ps
CPU time 2.68 seconds
Started Jun 06 02:53:40 PM PDT 24
Finished Jun 06 02:53:46 PM PDT 24
Peak memory 205056 kb
Host smart-c358b581-a26a-487a-9762-68a1284aaa71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309260379 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.2309260379
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.332440236
Short name T879
Test name
Test status
Simulation time 8821489345 ps
CPU time 5.98 seconds
Started Jun 06 02:53:31 PM PDT 24
Finished Jun 06 02:53:39 PM PDT 24
Peak memory 211432 kb
Host smart-9fd38f65-4342-49fd-aa51-41a23d594bdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332440236 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.332440236
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.126452204
Short name T416
Test name
Test status
Simulation time 7650300612 ps
CPU time 5.51 seconds
Started Jun 06 02:53:32 PM PDT 24
Finished Jun 06 02:53:41 PM PDT 24
Peak memory 205224 kb
Host smart-d3f5141d-8c71-4df1-9971-0027e2adc9ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126452204 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.126452204
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2684975765
Short name T650
Test name
Test status
Simulation time 5889118751 ps
CPU time 15.21 seconds
Started Jun 06 02:53:29 PM PDT 24
Finished Jun 06 02:53:46 PM PDT 24
Peak memory 205132 kb
Host smart-09ec001c-3b89-4088-a5fe-0ac7f772af48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684975765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2684975765
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.2051949819
Short name T1108
Test name
Test status
Simulation time 1594305702 ps
CPU time 14.09 seconds
Started Jun 06 02:53:32 PM PDT 24
Finished Jun 06 02:53:50 PM PDT 24
Peak memory 216624 kb
Host smart-e9ed3205-c791-45f7-a5fb-3f8a0f95ce3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051949819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.2051949819
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3208947770
Short name T580
Test name
Test status
Simulation time 28222851095 ps
CPU time 101.53 seconds
Started Jun 06 02:53:29 PM PDT 24
Finished Jun 06 02:55:13 PM PDT 24
Peak memory 1562968 kb
Host smart-f1445a1d-4d39-4ab2-8e06-5090e57d0b06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208947770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3208947770
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1059780066
Short name T1081
Test name
Test status
Simulation time 7913325284 ps
CPU time 24.54 seconds
Started Jun 06 02:53:29 PM PDT 24
Finished Jun 06 02:53:56 PM PDT 24
Peak memory 500772 kb
Host smart-bec4bfa8-0601-4b8e-868e-43d57dc41f0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059780066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1059780066
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.850585524
Short name T168
Test name
Test status
Simulation time 1327227143 ps
CPU time 7.92 seconds
Started Jun 06 02:53:42 PM PDT 24
Finished Jun 06 02:53:54 PM PDT 24
Peak memory 211404 kb
Host smart-eae78939-07c7-436c-b9f7-93214b5cb183
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850585524 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.850585524
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.2460826167
Short name T1115
Test name
Test status
Simulation time 1039760780 ps
CPU time 19.72 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:54:13 PM PDT 24
Peak memory 205092 kb
Host smart-49f27c9d-4237-4ba2-b572-c67a7351b507
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460826167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2460826167
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.985498667
Short name T861
Test name
Test status
Simulation time 42516733 ps
CPU time 0.63 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:54:03 PM PDT 24
Peak memory 204800 kb
Host smart-cec697a0-cec3-453e-bf6f-a701451917dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985498667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.985498667
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.2520962376
Short name T1287
Test name
Test status
Simulation time 239947834 ps
CPU time 1.66 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:53:54 PM PDT 24
Peak memory 213312 kb
Host smart-59a97981-79fb-4aed-915e-ef23a93e1f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520962376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.2520962376
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.910022389
Short name T1297
Test name
Test status
Simulation time 1509209364 ps
CPU time 19.14 seconds
Started Jun 06 02:53:53 PM PDT 24
Finished Jun 06 02:54:16 PM PDT 24
Peak memory 280444 kb
Host smart-d9c44b52-3bb4-4064-875e-ac4856b01776
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910022389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.910022389
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1599788276
Short name T786
Test name
Test status
Simulation time 20404914188 ps
CPU time 116.34 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:55:49 PM PDT 24
Peak memory 577932 kb
Host smart-de921854-ee9a-4d5f-90c6-456f02021f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599788276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1599788276
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.3760218603
Short name T392
Test name
Test status
Simulation time 10708254994 ps
CPU time 97.92 seconds
Started Jun 06 02:53:48 PM PDT 24
Finished Jun 06 02:55:30 PM PDT 24
Peak memory 873776 kb
Host smart-b8190134-68d1-4785-9add-d0402db19c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760218603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.3760218603
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.2908999365
Short name T874
Test name
Test status
Simulation time 187495092 ps
CPU time 0.95 seconds
Started Jun 06 02:53:48 PM PDT 24
Finished Jun 06 02:53:53 PM PDT 24
Peak memory 204728 kb
Host smart-52b68ac9-17cc-48ae-9a5b-536827a42143
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908999365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.2908999365
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3441475523
Short name T1280
Test name
Test status
Simulation time 1028662718 ps
CPU time 9.21 seconds
Started Jun 06 02:53:50 PM PDT 24
Finished Jun 06 02:54:03 PM PDT 24
Peak memory 231824 kb
Host smart-6ca16c77-17f4-4735-9e26-190f6c5ed18f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441475523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3441475523
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.2551732515
Short name T351
Test name
Test status
Simulation time 9241457282 ps
CPU time 148.67 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:56:21 PM PDT 24
Peak memory 1308472 kb
Host smart-b39d82b5-2b38-4fe9-b893-92982028bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551732515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.2551732515
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3430034636
Short name T990
Test name
Test status
Simulation time 1046205835 ps
CPU time 8.37 seconds
Started Jun 06 02:53:57 PM PDT 24
Finished Jun 06 02:54:08 PM PDT 24
Peak memory 205120 kb
Host smart-05abbd26-88a0-4155-968d-f260dba32ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430034636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3430034636
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.2243939149
Short name T1320
Test name
Test status
Simulation time 5452302135 ps
CPU time 23.04 seconds
Started Jun 06 02:54:00 PM PDT 24
Finished Jun 06 02:54:26 PM PDT 24
Peak memory 308952 kb
Host smart-f544fe1b-25ee-4854-ae1d-a1f82ab012b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243939149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.2243939149
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2749527586
Short name T714
Test name
Test status
Simulation time 15364266 ps
CPU time 0.71 seconds
Started Jun 06 02:53:48 PM PDT 24
Finished Jun 06 02:53:52 PM PDT 24
Peak memory 204776 kb
Host smart-29b98b9b-7140-4633-99bb-b0f303607eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749527586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2749527586
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.2258425958
Short name T920
Test name
Test status
Simulation time 2865767844 ps
CPU time 7.34 seconds
Started Jun 06 02:53:50 PM PDT 24
Finished Jun 06 02:54:01 PM PDT 24
Peak memory 229376 kb
Host smart-2605e928-6327-45c0-9df3-06bda24c7604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258425958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.2258425958
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1798277392
Short name T1378
Test name
Test status
Simulation time 1571881905 ps
CPU time 28.12 seconds
Started Jun 06 02:53:50 PM PDT 24
Finished Jun 06 02:54:22 PM PDT 24
Peak memory 381392 kb
Host smart-33aaf802-c928-4f9d-b770-58b5e06bf83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798277392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1798277392
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.2626977959
Short name T114
Test name
Test status
Simulation time 6091315137 ps
CPU time 144.63 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:56:17 PM PDT 24
Peak memory 808540 kb
Host smart-747d5735-325e-40c9-9fd1-24cc7a19a249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626977959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.2626977959
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.3418276002
Short name T1039
Test name
Test status
Simulation time 1117598836 ps
CPU time 45.06 seconds
Started Jun 06 02:53:48 PM PDT 24
Finished Jun 06 02:54:36 PM PDT 24
Peak memory 213312 kb
Host smart-4ebecaba-f428-4ec5-8447-f4446d1ffbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418276002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.3418276002
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.1212722667
Short name T27
Test name
Test status
Simulation time 2606082802 ps
CPU time 3.93 seconds
Started Jun 06 02:53:58 PM PDT 24
Finished Jun 06 02:54:05 PM PDT 24
Peak memory 213392 kb
Host smart-5122bf14-b70e-47fe-94a9-5c1cf04b0741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212722667 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.1212722667
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.656006471
Short name T772
Test name
Test status
Simulation time 10149748461 ps
CPU time 13.48 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:54:06 PM PDT 24
Peak memory 244528 kb
Host smart-416703bf-91ad-4ed2-9438-56607b98b759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656006471 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_acq.656006471
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.2862940605
Short name T597
Test name
Test status
Simulation time 10178484087 ps
CPU time 17.33 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:54:10 PM PDT 24
Peak memory 326484 kb
Host smart-29edbbae-5d99-4be1-b7aa-549ef24781d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862940605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.2862940605
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.1290014303
Short name T1420
Test name
Test status
Simulation time 2782220398 ps
CPU time 3.52 seconds
Started Jun 06 02:53:58 PM PDT 24
Finished Jun 06 02:54:04 PM PDT 24
Peak memory 205172 kb
Host smart-c7e56c2c-bd3a-42ca-be87-2f1f42c297e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290014303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1290014303
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.2302640058
Short name T1316
Test name
Test status
Simulation time 1099814761 ps
CPU time 4.95 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:54:07 PM PDT 24
Peak memory 205052 kb
Host smart-b6dfd022-6c81-45ad-b8a4-43c987d0afa9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302640058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.2302640058
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1077896740
Short name T690
Test name
Test status
Simulation time 1888919318 ps
CPU time 2.46 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:54:04 PM PDT 24
Peak memory 205104 kb
Host smart-1254ae52-5434-42f7-8484-de47bb56f086
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077896740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1077896740
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3460620733
Short name T332
Test name
Test status
Simulation time 2307523525 ps
CPU time 6.43 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:54:00 PM PDT 24
Peak memory 218708 kb
Host smart-cbcad53e-174a-477b-a8d6-a72305a3948d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460620733 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3460620733
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1712479668
Short name T527
Test name
Test status
Simulation time 11067597851 ps
CPU time 64.85 seconds
Started Jun 06 02:53:54 PM PDT 24
Finished Jun 06 02:55:02 PM PDT 24
Peak memory 1117892 kb
Host smart-2db5441d-2c03-4691-88e8-a8d16bd25508
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712479668 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1712479668
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2901304099
Short name T1240
Test name
Test status
Simulation time 2047608901 ps
CPU time 48.33 seconds
Started Jun 06 02:53:50 PM PDT 24
Finished Jun 06 02:54:42 PM PDT 24
Peak memory 205036 kb
Host smart-223e77c6-8aaa-4131-ba8a-e8f4ff3fc851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901304099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2901304099
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1403722799
Short name T528
Test name
Test status
Simulation time 2088782798 ps
CPU time 22.16 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:54:15 PM PDT 24
Peak memory 205064 kb
Host smart-e65528a8-4917-4edf-aa08-7aa4170888c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403722799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1403722799
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.847662298
Short name T22
Test name
Test status
Simulation time 37665038402 ps
CPU time 496.4 seconds
Started Jun 06 02:53:48 PM PDT 24
Finished Jun 06 03:02:08 PM PDT 24
Peak memory 4515296 kb
Host smart-d78e8576-7224-4196-a21d-7b89a69b9764
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847662298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.847662298
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.3283471405
Short name T519
Test name
Test status
Simulation time 19207236647 ps
CPU time 451.68 seconds
Started Jun 06 02:53:50 PM PDT 24
Finished Jun 06 03:01:25 PM PDT 24
Peak memory 1312008 kb
Host smart-9acad5a9-5ce9-4bb6-91a4-aee1115faefa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283471405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.3283471405
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.664108839
Short name T1052
Test name
Test status
Simulation time 5648390048 ps
CPU time 7.32 seconds
Started Jun 06 02:53:49 PM PDT 24
Finished Jun 06 02:54:00 PM PDT 24
Peak memory 217004 kb
Host smart-a5d39d7d-f4ab-4b30-bf42-46e91ceb58a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664108839 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_timeout.664108839
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.3131617452
Short name T467
Test name
Test status
Simulation time 1155446404 ps
CPU time 15.46 seconds
Started Jun 06 02:54:01 PM PDT 24
Finished Jun 06 02:54:20 PM PDT 24
Peak memory 205056 kb
Host smart-8cfd985a-b2da-4c02-83e7-0b24f969dae3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131617452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.3131617452
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.1708982502
Short name T156
Test name
Test status
Simulation time 17688589 ps
CPU time 0.62 seconds
Started Jun 06 02:54:09 PM PDT 24
Finished Jun 06 02:54:14 PM PDT 24
Peak memory 204704 kb
Host smart-53c575f5-4e98-439f-817d-9819057a9af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708982502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.1708982502
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.3775358617
Short name T487
Test name
Test status
Simulation time 338461292 ps
CPU time 6.53 seconds
Started Jun 06 02:54:23 PM PDT 24
Finished Jun 06 02:54:33 PM PDT 24
Peak memory 275840 kb
Host smart-91e9c44a-1b8f-4521-a0c0-8d42cc3f1074
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775358617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.3775358617
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3207393443
Short name T741
Test name
Test status
Simulation time 2872241603 ps
CPU time 46.68 seconds
Started Jun 06 02:54:00 PM PDT 24
Finished Jun 06 02:54:50 PM PDT 24
Peak memory 539196 kb
Host smart-4f5948d7-5437-4ae7-9838-49f37a0f3a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207393443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3207393443
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3598830237
Short name T293
Test name
Test status
Simulation time 8143862490 ps
CPU time 56.69 seconds
Started Jun 06 02:54:00 PM PDT 24
Finished Jun 06 02:55:01 PM PDT 24
Peak memory 640228 kb
Host smart-54351439-d14f-4371-8900-c865ab96e0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598830237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3598830237
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.830762592
Short name T811
Test name
Test status
Simulation time 451568601 ps
CPU time 1.1 seconds
Started Jun 06 02:53:58 PM PDT 24
Finished Jun 06 02:54:03 PM PDT 24
Peak memory 204916 kb
Host smart-d0427192-a938-447c-b5e4-b375a8efe48b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830762592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.830762592
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.2542015047
Short name T516
Test name
Test status
Simulation time 379064076 ps
CPU time 3.22 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:54:06 PM PDT 24
Peak memory 205016 kb
Host smart-097b20c5-995d-4009-a094-ebe9ba25b5c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542015047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.2542015047
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1888681216
Short name T1139
Test name
Test status
Simulation time 4547850004 ps
CPU time 330.89 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:59:33 PM PDT 24
Peak memory 1187088 kb
Host smart-10aebdfb-1199-4f33-bf2f-ae4a119e6300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888681216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1888681216
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2142829500
Short name T821
Test name
Test status
Simulation time 327274053 ps
CPU time 13.5 seconds
Started Jun 06 02:54:07 PM PDT 24
Finished Jun 06 02:54:24 PM PDT 24
Peak memory 205024 kb
Host smart-abe6265e-d486-4e34-91d1-8c167dfb4fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142829500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2142829500
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1050065570
Short name T649
Test name
Test status
Simulation time 1758315904 ps
CPU time 79.74 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:55:31 PM PDT 24
Peak memory 343680 kb
Host smart-3c9dbbec-41b2-46ed-a866-eedcb3542979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050065570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1050065570
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.4078121052
Short name T263
Test name
Test status
Simulation time 69027593 ps
CPU time 0.69 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:54:04 PM PDT 24
Peak memory 204696 kb
Host smart-abe809ce-2f2b-4fa3-adce-f79fad94e13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078121052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.4078121052
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2690558860
Short name T669
Test name
Test status
Simulation time 5485046644 ps
CPU time 95.63 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:55:38 PM PDT 24
Peak memory 670752 kb
Host smart-da061a73-4e6d-49f9-a2bd-ae998f8b585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690558860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2690558860
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3358582411
Short name T292
Test name
Test status
Simulation time 3196541987 ps
CPU time 25.02 seconds
Started Jun 06 02:54:00 PM PDT 24
Finished Jun 06 02:54:29 PM PDT 24
Peak memory 347944 kb
Host smart-2a078b24-3ad3-4954-a3da-cad4c07be1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358582411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3358582411
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.2190551594
Short name T255
Test name
Test status
Simulation time 18415220593 ps
CPU time 864.64 seconds
Started Jun 06 02:54:03 PM PDT 24
Finished Jun 06 03:08:30 PM PDT 24
Peak memory 2432004 kb
Host smart-af479632-b5c8-459a-99f4-0a4c22047fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190551594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.2190551594
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3875454967
Short name T1238
Test name
Test status
Simulation time 1953209308 ps
CPU time 22.42 seconds
Started Jun 06 02:54:00 PM PDT 24
Finished Jun 06 02:54:26 PM PDT 24
Peak memory 213280 kb
Host smart-86c67318-f43a-400d-b8e3-2334aba8c3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875454967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3875454967
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2430296750
Short name T1396
Test name
Test status
Simulation time 990877958 ps
CPU time 4.4 seconds
Started Jun 06 02:54:00 PM PDT 24
Finished Jun 06 02:54:08 PM PDT 24
Peak memory 205132 kb
Host smart-d29564e6-39fd-4ea6-b232-ad8eebeea7e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430296750 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2430296750
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.1020748448
Short name T665
Test name
Test status
Simulation time 10161220966 ps
CPU time 11.68 seconds
Started Jun 06 02:54:02 PM PDT 24
Finished Jun 06 02:54:17 PM PDT 24
Peak memory 244944 kb
Host smart-a1055735-6739-438b-8bdb-d4a1692b6eff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020748448 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.1020748448
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3305400502
Short name T456
Test name
Test status
Simulation time 10122036752 ps
CPU time 20.63 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:54:23 PM PDT 24
Peak memory 297088 kb
Host smart-58fd342a-5a81-48ca-aa07-5292960e8ae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305400502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3305400502
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.3754270208
Short name T936
Test name
Test status
Simulation time 1431267015 ps
CPU time 6.05 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:54:20 PM PDT 24
Peak memory 204884 kb
Host smart-9183dc9e-fc93-441b-b9f2-f9b597913488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754270208 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.3754270208
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.2569466864
Short name T576
Test name
Test status
Simulation time 1081934584 ps
CPU time 5.92 seconds
Started Jun 06 02:54:07 PM PDT 24
Finished Jun 06 02:54:17 PM PDT 24
Peak memory 205056 kb
Host smart-455bb27f-8c90-4652-9bf9-5283c33c0f5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569466864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.2569466864
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.653365471
Short name T266
Test name
Test status
Simulation time 1413491618 ps
CPU time 3.88 seconds
Started Jun 06 02:54:02 PM PDT 24
Finished Jun 06 02:54:09 PM PDT 24
Peak memory 205108 kb
Host smart-1918faf8-90ed-4af8-8c04-cb17856974bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653365471 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_intr_smoke.653365471
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.487030352
Short name T1232
Test name
Test status
Simulation time 22263959422 ps
CPU time 63.98 seconds
Started Jun 06 02:54:03 PM PDT 24
Finished Jun 06 02:55:10 PM PDT 24
Peak memory 1305508 kb
Host smart-74dc1587-70a7-44dd-a2cd-bdfb43830b74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487030352 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.487030352
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.870276510
Short name T644
Test name
Test status
Simulation time 821773154 ps
CPU time 29.92 seconds
Started Jun 06 02:53:59 PM PDT 24
Finished Jun 06 02:54:33 PM PDT 24
Peak memory 205068 kb
Host smart-64c7c1bc-0833-47b9-874f-95e8a5326c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870276510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.870276510
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.1606926326
Short name T924
Test name
Test status
Simulation time 733531998 ps
CPU time 5.95 seconds
Started Jun 06 02:54:00 PM PDT 24
Finished Jun 06 02:54:09 PM PDT 24
Peak memory 205052 kb
Host smart-5dd3703b-21bc-4a0c-a0ad-6de7602c3e80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606926326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.1606926326
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2037221170
Short name T350
Test name
Test status
Simulation time 58737076939 ps
CPU time 1663.55 seconds
Started Jun 06 02:54:03 PM PDT 24
Finished Jun 06 03:21:50 PM PDT 24
Peak memory 9868380 kb
Host smart-8d153049-2a1d-4da9-8c0f-0cd02df74d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037221170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2037221170
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2957307424
Short name T799
Test name
Test status
Simulation time 16504743395 ps
CPU time 455.14 seconds
Started Jun 06 02:54:01 PM PDT 24
Finished Jun 06 03:01:40 PM PDT 24
Peak memory 2921916 kb
Host smart-7c8b7417-10bf-442f-ba0f-5a63aec2b49b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957307424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2957307424
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.294490513
Short name T566
Test name
Test status
Simulation time 4900950159 ps
CPU time 7.14 seconds
Started Jun 06 02:54:04 PM PDT 24
Finished Jun 06 02:54:14 PM PDT 24
Peak memory 213372 kb
Host smart-5fcfd882-8a34-43d5-879a-86795db8e962
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294490513 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_timeout.294490513
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.2000703984
Short name T1354
Test name
Test status
Simulation time 1163356314 ps
CPU time 17.93 seconds
Started Jun 06 02:54:06 PM PDT 24
Finished Jun 06 02:54:27 PM PDT 24
Peak memory 205036 kb
Host smart-6e5ad9df-540d-4b9f-b648-a7cf197dd8e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000703984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.2000703984
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2283692511
Short name T1121
Test name
Test status
Simulation time 17033046 ps
CPU time 0.62 seconds
Started Jun 06 02:54:11 PM PDT 24
Finished Jun 06 02:54:16 PM PDT 24
Peak memory 204728 kb
Host smart-07479f5c-5bad-4d87-bfab-37de28ea49c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283692511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2283692511
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.2906874675
Short name T688
Test name
Test status
Simulation time 471263883 ps
CPU time 3.73 seconds
Started Jun 06 02:54:07 PM PDT 24
Finished Jun 06 02:54:14 PM PDT 24
Peak memory 216840 kb
Host smart-d65e49bd-9386-4c5b-ab73-528b3db203d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906874675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.2906874675
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.3670384443
Short name T395
Test name
Test status
Simulation time 1409239727 ps
CPU time 17.83 seconds
Started Jun 06 02:54:07 PM PDT 24
Finished Jun 06 02:54:29 PM PDT 24
Peak memory 264884 kb
Host smart-91e82534-d12a-4ec9-a781-925de8991300
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670384443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.3670384443
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.796654459
Short name T614
Test name
Test status
Simulation time 4660025405 ps
CPU time 78.53 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:55:32 PM PDT 24
Peak memory 763568 kb
Host smart-8f3dda6e-dc59-40fe-a20b-879c2c2584ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796654459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.796654459
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.48448426
Short name T1072
Test name
Test status
Simulation time 3711928277 ps
CPU time 134.94 seconds
Started Jun 06 02:54:09 PM PDT 24
Finished Jun 06 02:56:28 PM PDT 24
Peak memory 620052 kb
Host smart-ca1ae011-70c7-4df8-9ab2-9d4fa4815efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48448426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.48448426
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.693184764
Short name T1189
Test name
Test status
Simulation time 95124523 ps
CPU time 0.96 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:54:12 PM PDT 24
Peak memory 204752 kb
Host smart-c9bbfa16-8a7b-4132-ab01-e057b09ffb0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693184764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_fm
t.693184764
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.3039140875
Short name T1411
Test name
Test status
Simulation time 209819636 ps
CPU time 4.57 seconds
Started Jun 06 02:54:11 PM PDT 24
Finished Jun 06 02:54:19 PM PDT 24
Peak memory 204980 kb
Host smart-aa54f4b4-f59f-4078-a72a-65c4012f9deb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039140875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.3039140875
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1318488650
Short name T927
Test name
Test status
Simulation time 22834090930 ps
CPU time 161.83 seconds
Started Jun 06 02:54:09 PM PDT 24
Finished Jun 06 02:56:55 PM PDT 24
Peak memory 1599180 kb
Host smart-ec6136e0-bf6d-4cf5-bda5-0bb899ad57c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318488650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1318488650
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.884494900
Short name T967
Test name
Test status
Simulation time 450853530 ps
CPU time 7.63 seconds
Started Jun 06 02:54:09 PM PDT 24
Finished Jun 06 02:54:20 PM PDT 24
Peak memory 204980 kb
Host smart-2e604cd9-bf70-4897-bab3-26804402eb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884494900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.884494900
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.3231618281
Short name T736
Test name
Test status
Simulation time 987307474 ps
CPU time 15.86 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:54:27 PM PDT 24
Peak memory 276972 kb
Host smart-32b7504c-d72d-4fa1-b648-ef58efb7cfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231618281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.3231618281
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1897164231
Short name T907
Test name
Test status
Simulation time 38216258 ps
CPU time 0.66 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:54:14 PM PDT 24
Peak memory 204884 kb
Host smart-a9488bfd-8414-46ad-b198-9bd3421e5fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897164231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1897164231
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.641890531
Short name T1392
Test name
Test status
Simulation time 48906715730 ps
CPU time 318.44 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:59:30 PM PDT 24
Peak memory 844816 kb
Host smart-9347a227-30ad-40ae-be7b-b3d69b690ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641890531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.641890531
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2618210552
Short name T81
Test name
Test status
Simulation time 1270200821 ps
CPU time 24.18 seconds
Started Jun 06 02:54:07 PM PDT 24
Finished Jun 06 02:54:34 PM PDT 24
Peak memory 296220 kb
Host smart-62a72972-f5cc-4b1b-9cac-bb939ae2aef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618210552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2618210552
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.2135771293
Short name T673
Test name
Test status
Simulation time 29257111810 ps
CPU time 747.48 seconds
Started Jun 06 02:54:09 PM PDT 24
Finished Jun 06 03:06:40 PM PDT 24
Peak memory 2172068 kb
Host smart-33ba8dc6-6d1b-4127-9c24-53f7ddd32361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135771293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.2135771293
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2229369434
Short name T275
Test name
Test status
Simulation time 803310845 ps
CPU time 6.66 seconds
Started Jun 06 02:54:07 PM PDT 24
Finished Jun 06 02:54:17 PM PDT 24
Peak memory 213296 kb
Host smart-b8a93cbc-9d73-4b58-9672-5db286e6aebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229369434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2229369434
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.3393877968
Short name T273
Test name
Test status
Simulation time 329679644 ps
CPU time 2.18 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:54:14 PM PDT 24
Peak memory 205080 kb
Host smart-4a26dd48-1c90-4d2d-a43b-4e385147c98d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393877968 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.3393877968
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.4242004907
Short name T1133
Test name
Test status
Simulation time 10213638318 ps
CPU time 13.75 seconds
Started Jun 06 02:54:09 PM PDT 24
Finished Jun 06 02:54:26 PM PDT 24
Peak memory 245360 kb
Host smart-383267da-59b3-4fe3-be62-36046a1a81c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242004907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.4242004907
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.4070224011
Short name T1470
Test name
Test status
Simulation time 10274801808 ps
CPU time 33.31 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:54:48 PM PDT 24
Peak memory 370488 kb
Host smart-95dd0cf5-ecf5-4ae9-834c-017840a0fb96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070224011 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.4070224011
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.2579642110
Short name T1438
Test name
Test status
Simulation time 1059737940 ps
CPU time 2.87 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:54:15 PM PDT 24
Peak memory 205048 kb
Host smart-e65f77c5-91a3-4e23-9172-59ccbcfc120a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579642110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.2579642110
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.2702267665
Short name T1457
Test name
Test status
Simulation time 1044473684 ps
CPU time 5.56 seconds
Started Jun 06 02:54:09 PM PDT 24
Finished Jun 06 02:54:18 PM PDT 24
Peak memory 205044 kb
Host smart-91644ad3-48fe-48aa-8a9e-6334e29e3687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702267665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.2702267665
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2333086553
Short name T1001
Test name
Test status
Simulation time 1689877463 ps
CPU time 2.66 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:54:17 PM PDT 24
Peak memory 205048 kb
Host smart-c641abe2-77f7-48a8-983f-ee287f35e0ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333086553 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2333086553
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.251535322
Short name T357
Test name
Test status
Simulation time 14046355908 ps
CPU time 7.01 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:54:21 PM PDT 24
Peak memory 213376 kb
Host smart-25bb1032-bd85-431c-9386-78a573e24fa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251535322 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_intr_smoke.251535322
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.3066852823
Short name T687
Test name
Test status
Simulation time 5560676412 ps
CPU time 3.1 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:54:17 PM PDT 24
Peak memory 205112 kb
Host smart-466120b8-d885-4fa7-8085-724f23155e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066852823 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.3066852823
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.3474575035
Short name T747
Test name
Test status
Simulation time 5543166987 ps
CPU time 46.74 seconds
Started Jun 06 02:54:07 PM PDT 24
Finished Jun 06 02:54:57 PM PDT 24
Peak memory 205176 kb
Host smart-798d7803-0f39-4c5d-ba8c-de71b150fa54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474575035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.3474575035
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.3270820042
Short name T135
Test name
Test status
Simulation time 7734902516 ps
CPU time 14.07 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:54:27 PM PDT 24
Peak memory 211792 kb
Host smart-fa3866ec-ec2c-45b5-8827-eab05451a24b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270820042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.3270820042
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1135827789
Short name T1394
Test name
Test status
Simulation time 21995437452 ps
CPU time 23.52 seconds
Started Jun 06 02:54:12 PM PDT 24
Finished Jun 06 02:54:39 PM PDT 24
Peak memory 295600 kb
Host smart-36a1ecbc-ee5c-4525-a505-c3de36d1c1be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135827789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1135827789
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3490236490
Short name T313
Test name
Test status
Simulation time 5582042681 ps
CPU time 18.27 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:54:30 PM PDT 24
Peak memory 360708 kb
Host smart-ecd45961-14bc-4c7e-bee1-ac1ec0bbde6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490236490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3490236490
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.3560108087
Short name T870
Test name
Test status
Simulation time 1052579177 ps
CPU time 19.99 seconds
Started Jun 06 02:54:11 PM PDT 24
Finished Jun 06 02:54:35 PM PDT 24
Peak memory 205080 kb
Host smart-abdf90cd-b1ae-4a46-8030-b3a581cf2553
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560108087 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.3560108087
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.4053756965
Short name T1162
Test name
Test status
Simulation time 19011876 ps
CPU time 0.62 seconds
Started Jun 06 02:54:24 PM PDT 24
Finished Jun 06 02:54:28 PM PDT 24
Peak memory 204736 kb
Host smart-5bacbd80-3285-4a05-90d2-379af13c3ec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053756965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.4053756965
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.961190345
Short name T873
Test name
Test status
Simulation time 50425379 ps
CPU time 1.98 seconds
Started Jun 06 02:54:23 PM PDT 24
Finished Jun 06 02:54:27 PM PDT 24
Peak memory 213320 kb
Host smart-d08e646b-c8d6-4fb3-9ea0-d8e485db5ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961190345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.961190345
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.1244754447
Short name T953
Test name
Test status
Simulation time 222066152 ps
CPU time 11.89 seconds
Started Jun 06 02:54:09 PM PDT 24
Finished Jun 06 02:54:25 PM PDT 24
Peak memory 247432 kb
Host smart-6ce0ee53-9f45-483c-b208-029d22d2b556
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244754447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.1244754447
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.2628532103
Short name T37
Test name
Test status
Simulation time 6855743980 ps
CPU time 102.53 seconds
Started Jun 06 02:54:24 PM PDT 24
Finished Jun 06 02:56:10 PM PDT 24
Peak memory 479396 kb
Host smart-324cb1a8-1347-4519-9bba-0a9766f6f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628532103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.2628532103
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.203076981
Short name T386
Test name
Test status
Simulation time 1998228610 ps
CPU time 56.11 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:55:10 PM PDT 24
Peak memory 674272 kb
Host smart-ed56fc80-373d-4d4a-8300-52c196e8e187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203076981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.203076981
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.3573416336
Short name T1110
Test name
Test status
Simulation time 373571092 ps
CPU time 1.01 seconds
Started Jun 06 02:54:11 PM PDT 24
Finished Jun 06 02:54:16 PM PDT 24
Peak memory 204976 kb
Host smart-61b6e6db-9d63-4753-98a1-398f61be350e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573416336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.3573416336
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.151825497
Short name T449
Test name
Test status
Simulation time 140586498 ps
CPU time 7.2 seconds
Started Jun 06 02:54:08 PM PDT 24
Finished Jun 06 02:54:19 PM PDT 24
Peak memory 205052 kb
Host smart-afcef837-af0b-4459-b7f1-9f025c7562b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151825497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
151825497
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3914047082
Short name T98
Test name
Test status
Simulation time 11927542742 ps
CPU time 74.77 seconds
Started Jun 06 02:54:10 PM PDT 24
Finished Jun 06 02:55:29 PM PDT 24
Peak memory 945352 kb
Host smart-54d4e1a0-5d17-49ab-908a-964e3698a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914047082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3914047082
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3283335456
Short name T1062
Test name
Test status
Simulation time 407778581 ps
CPU time 6.57 seconds
Started Jun 06 02:54:25 PM PDT 24
Finished Jun 06 02:54:36 PM PDT 24
Peak memory 205108 kb
Host smart-1f9f318e-bc10-4d18-98aa-4fd6d27c364c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283335456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3283335456
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.1440791503
Short name T461
Test name
Test status
Simulation time 2046709684 ps
CPU time 89 seconds
Started Jun 06 02:54:25 PM PDT 24
Finished Jun 06 02:55:58 PM PDT 24
Peak memory 334144 kb
Host smart-797dce79-7611-46b3-a9e8-378d05a3ec59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440791503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.1440791503
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.1844335303
Short name T826
Test name
Test status
Simulation time 187523777 ps
CPU time 0.69 seconds
Started Jun 06 02:54:12 PM PDT 24
Finished Jun 06 02:54:16 PM PDT 24
Peak memory 204960 kb
Host smart-f5c9b5c4-d0df-40ca-99ce-edcbc61c3d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844335303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.1844335303
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.280962318
Short name T267
Test name
Test status
Simulation time 5370930315 ps
CPU time 48.07 seconds
Started Jun 06 02:54:23 PM PDT 24
Finished Jun 06 02:55:15 PM PDT 24
Peak memory 230060 kb
Host smart-b0554d54-59e8-4b07-93ed-33af0661a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280962318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.280962318
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.1589284742
Short name T634
Test name
Test status
Simulation time 11627538542 ps
CPU time 75.86 seconds
Started Jun 06 02:54:12 PM PDT 24
Finished Jun 06 02:55:31 PM PDT 24
Peak memory 331976 kb
Host smart-00bc7856-35e4-4405-a18d-7971812173c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589284742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.1589284742
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.2848562357
Short name T1360
Test name
Test status
Simulation time 166312620114 ps
CPU time 256.83 seconds
Started Jun 06 02:54:22 PM PDT 24
Finished Jun 06 02:58:41 PM PDT 24
Peak memory 1350816 kb
Host smart-f7aaf371-6377-4089-a72e-89aa05990465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848562357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2848562357
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.3262079335
Short name T816
Test name
Test status
Simulation time 2600013287 ps
CPU time 30.24 seconds
Started Jun 06 02:54:23 PM PDT 24
Finished Jun 06 02:54:57 PM PDT 24
Peak memory 213396 kb
Host smart-93c0eaa4-c322-4d14-9a9f-7a4f725ead70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262079335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.3262079335
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.287522584
Short name T299
Test name
Test status
Simulation time 3442165785 ps
CPU time 3.77 seconds
Started Jun 06 02:54:24 PM PDT 24
Finished Jun 06 02:54:31 PM PDT 24
Peak memory 213396 kb
Host smart-6f64d21e-bd4e-40b4-b698-945709e664b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287522584 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.287522584
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.3875737480
Short name T1050
Test name
Test status
Simulation time 10421741200 ps
CPU time 12.49 seconds
Started Jun 06 02:54:24 PM PDT 24
Finished Jun 06 02:54:40 PM PDT 24
Peak memory 257600 kb
Host smart-05256910-5021-4895-a8e8-ee8d1fbff824
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875737480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.3875737480
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.940331619
Short name T209
Test name
Test status
Simulation time 10315320706 ps
CPU time 36.1 seconds
Started Jun 06 02:54:25 PM PDT 24
Finished Jun 06 02:55:05 PM PDT 24
Peak memory 461832 kb
Host smart-35fb59c8-ab7a-4b9f-9ff9-4babd8da90d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940331619 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.940331619
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.312065962
Short name T1491
Test name
Test status
Simulation time 1274943290 ps
CPU time 6.56 seconds
Started Jun 06 02:54:27 PM PDT 24
Finished Jun 06 02:54:38 PM PDT 24
Peak memory 205076 kb
Host smart-4ce0f54b-e695-4f9c-b32d-f2f2c5d2a2f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312065962 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.312065962
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2758838453
Short name T667
Test name
Test status
Simulation time 1558201483 ps
CPU time 2.37 seconds
Started Jun 06 02:54:25 PM PDT 24
Finished Jun 06 02:54:31 PM PDT 24
Peak memory 204960 kb
Host smart-c32c803e-a7bf-4fcd-868b-912d126b21d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758838453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2758838453
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.2824979839
Short name T1166
Test name
Test status
Simulation time 1481420813 ps
CPU time 2.44 seconds
Started Jun 06 02:54:27 PM PDT 24
Finished Jun 06 02:54:34 PM PDT 24
Peak memory 205084 kb
Host smart-51a34395-2d54-47e2-a28f-5ce840b728ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824979839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_hrst.2824979839
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.3105418793
Short name T657
Test name
Test status
Simulation time 1115608236 ps
CPU time 5.21 seconds
Started Jun 06 02:54:26 PM PDT 24
Finished Jun 06 02:54:36 PM PDT 24
Peak memory 205036 kb
Host smart-07c1e682-53da-4f6c-8b99-d24bd194dc9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105418793 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.3105418793
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2872648345
Short name T706
Test name
Test status
Simulation time 2892519573 ps
CPU time 4.15 seconds
Started Jun 06 02:54:23 PM PDT 24
Finished Jun 06 02:54:31 PM PDT 24
Peak memory 205132 kb
Host smart-ba9d0e41-06af-49a6-9d5e-5038fa53dc65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872648345 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2872648345
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.3628759923
Short name T118
Test name
Test status
Simulation time 656150874 ps
CPU time 9.35 seconds
Started Jun 06 02:54:20 PM PDT 24
Finished Jun 06 02:54:32 PM PDT 24
Peak memory 205056 kb
Host smart-16c3ce6b-cdd8-4bdb-8972-e4a4ec101bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628759923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.3628759923
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.196622219
Short name T171
Test name
Test status
Simulation time 5338722810 ps
CPU time 23.62 seconds
Started Jun 06 02:54:24 PM PDT 24
Finished Jun 06 02:54:52 PM PDT 24
Peak memory 219164 kb
Host smart-1858c213-be40-43ff-90e4-d5bfe4e0712b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196622219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.196622219
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.95585484
Short name T880
Test name
Test status
Simulation time 62277472175 ps
CPU time 25.17 seconds
Started Jun 06 02:54:21 PM PDT 24
Finished Jun 06 02:54:49 PM PDT 24
Peak memory 488028 kb
Host smart-7ccf2e29-63eb-4232-90c6-9b907838ce94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95585484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stress_wr.95585484
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.4157888308
Short name T259
Test name
Test status
Simulation time 5678315084 ps
CPU time 18.55 seconds
Started Jun 06 02:54:23 PM PDT 24
Finished Jun 06 02:54:45 PM PDT 24
Peak memory 362252 kb
Host smart-ac09c1c8-5867-4584-89a2-0a2d224f2946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157888308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.4157888308
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1671666224
Short name T164
Test name
Test status
Simulation time 4631461217 ps
CPU time 6.65 seconds
Started Jun 06 02:54:23 PM PDT 24
Finished Jun 06 02:54:33 PM PDT 24
Peak memory 205168 kb
Host smart-0aec79c4-55a6-4ffc-ab55-5c9b085c3496
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671666224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1671666224
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.3080044767
Short name T1187
Test name
Test status
Simulation time 1282151248 ps
CPU time 16.77 seconds
Started Jun 06 02:54:23 PM PDT 24
Finished Jun 06 02:54:43 PM PDT 24
Peak memory 205028 kb
Host smart-cfbeb21c-ef0f-4ca4-8fa9-8ed6241f1ed4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080044767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3080044767
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3262125804
Short name T939
Test name
Test status
Simulation time 33184897 ps
CPU time 0.64 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:01 PM PDT 24
Peak memory 204800 kb
Host smart-3f3c9172-a1dd-4821-b80a-22811349a3a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262125804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3262125804
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3263164948
Short name T621
Test name
Test status
Simulation time 321746052 ps
CPU time 5.03 seconds
Started Jun 06 02:49:28 PM PDT 24
Finished Jun 06 02:49:34 PM PDT 24
Peak memory 213372 kb
Host smart-e8520da6-f8f8-43f1-81de-d54fe140f151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263164948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3263164948
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1677653409
Short name T82
Test name
Test status
Simulation time 234084374 ps
CPU time 2.65 seconds
Started Jun 06 02:49:28 PM PDT 24
Finished Jun 06 02:49:32 PM PDT 24
Peak memory 215392 kb
Host smart-ca4693e4-f113-4adb-838f-e9e943dde9d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677653409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1677653409
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3970953641
Short name T1324
Test name
Test status
Simulation time 3086312460 ps
CPU time 35.97 seconds
Started Jun 06 02:49:28 PM PDT 24
Finished Jun 06 02:50:05 PM PDT 24
Peak memory 439488 kb
Host smart-8114449c-0178-42e4-8229-110ca9996cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970953641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3970953641
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.3632563399
Short name T426
Test name
Test status
Simulation time 23034372372 ps
CPU time 82.15 seconds
Started Jun 06 02:49:29 PM PDT 24
Finished Jun 06 02:50:54 PM PDT 24
Peak memory 675952 kb
Host smart-5b6e1d24-23ef-4e97-aa28-5829b29508fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632563399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3632563399
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.2347273516
Short name T304
Test name
Test status
Simulation time 618021764 ps
CPU time 1.19 seconds
Started Jun 06 02:49:27 PM PDT 24
Finished Jun 06 02:49:29 PM PDT 24
Peak memory 204936 kb
Host smart-2af9d392-4c7b-4e1e-b1cc-7c776977a298
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347273516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.2347273516
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3970377294
Short name T1176
Test name
Test status
Simulation time 220449126 ps
CPU time 13.23 seconds
Started Jun 06 02:49:29 PM PDT 24
Finished Jun 06 02:49:44 PM PDT 24
Peak memory 249312 kb
Host smart-57e67673-dd8c-487d-b684-519816f2041a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970377294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3970377294
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2107162672
Short name T1492
Test name
Test status
Simulation time 3437982861 ps
CPU time 250.64 seconds
Started Jun 06 02:49:29 PM PDT 24
Finished Jun 06 02:53:42 PM PDT 24
Peak memory 1012284 kb
Host smart-b3f72a85-0758-4be6-8fe1-fcfa1e64027f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107162672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2107162672
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3032335130
Short name T1303
Test name
Test status
Simulation time 1245471553 ps
CPU time 5.09 seconds
Started Jun 06 02:50:00 PM PDT 24
Finished Jun 06 02:50:07 PM PDT 24
Peak memory 205108 kb
Host smart-5d69d4fa-3c59-43eb-afc8-765a8accb5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032335130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3032335130
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.4253577467
Short name T1019
Test name
Test status
Simulation time 7212972051 ps
CPU time 47.08 seconds
Started Jun 06 02:49:58 PM PDT 24
Finished Jun 06 02:50:47 PM PDT 24
Peak memory 478972 kb
Host smart-595234c4-c345-4619-bba5-8b8588a707ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253577467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.4253577467
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.3220924918
Short name T328
Test name
Test status
Simulation time 40432129 ps
CPU time 0.63 seconds
Started Jun 06 02:49:29 PM PDT 24
Finished Jun 06 02:49:32 PM PDT 24
Peak memory 204668 kb
Host smart-f2bd6f11-7f68-43a0-b3bd-03104dcac632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220924918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.3220924918
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.2176763669
Short name T302
Test name
Test status
Simulation time 268341095 ps
CPU time 3.2 seconds
Started Jun 06 02:49:28 PM PDT 24
Finished Jun 06 02:49:33 PM PDT 24
Peak memory 229524 kb
Host smart-c2cd0afc-3554-4adc-94ff-879c9ef7d1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176763669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.2176763669
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2106428863
Short name T1212
Test name
Test status
Simulation time 1335325312 ps
CPU time 26.76 seconds
Started Jun 06 02:49:30 PM PDT 24
Finished Jun 06 02:49:59 PM PDT 24
Peak memory 364424 kb
Host smart-d2ad6526-cda0-4c81-a8b2-c36e8d00b861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106428863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2106428863
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.959824548
Short name T536
Test name
Test status
Simulation time 176604099046 ps
CPU time 516.88 seconds
Started Jun 06 02:49:28 PM PDT 24
Finished Jun 06 02:58:07 PM PDT 24
Peak memory 2148856 kb
Host smart-18ec5f41-b487-41c0-bdf5-265f0da3f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959824548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.959824548
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3480674933
Short name T1199
Test name
Test status
Simulation time 1960943679 ps
CPU time 43.79 seconds
Started Jun 06 02:49:30 PM PDT 24
Finished Jun 06 02:50:16 PM PDT 24
Peak memory 221512 kb
Host smart-6b34cc86-263c-4adc-b053-75ff52f0de6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480674933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3480674933
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.59074683
Short name T160
Test name
Test status
Simulation time 60127625 ps
CPU time 0.95 seconds
Started Jun 06 02:49:58 PM PDT 24
Finished Jun 06 02:50:01 PM PDT 24
Peak memory 223068 kb
Host smart-ee069743-afcc-422f-92c4-b871ad459fc2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59074683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.59074683
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.487567285
Short name T1090
Test name
Test status
Simulation time 2063398658 ps
CPU time 4.6 seconds
Started Jun 06 02:49:58 PM PDT 24
Finished Jun 06 02:50:05 PM PDT 24
Peak memory 205148 kb
Host smart-20488478-186e-417c-a8af-0fcd442e78b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487567285 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.487567285
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3306062135
Short name T71
Test name
Test status
Simulation time 10106359699 ps
CPU time 40.68 seconds
Started Jun 06 02:49:29 PM PDT 24
Finished Jun 06 02:50:12 PM PDT 24
Peak memory 347676 kb
Host smart-9f154468-3c1f-4158-ae4b-85df283d67ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306062135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3306062135
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.1991393568
Short name T1037
Test name
Test status
Simulation time 10132074264 ps
CPU time 65.48 seconds
Started Jun 06 02:49:56 PM PDT 24
Finished Jun 06 02:51:03 PM PDT 24
Peak memory 601672 kb
Host smart-8b71526f-92b2-45c5-9678-71aef67faa73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991393568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.1991393568
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.3143738069
Short name T466
Test name
Test status
Simulation time 1454850921 ps
CPU time 6.88 seconds
Started Jun 06 02:50:01 PM PDT 24
Finished Jun 06 02:50:09 PM PDT 24
Peak memory 205108 kb
Host smart-6fec56bb-1ece-411c-9f46-3185e4b9da7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143738069 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.3143738069
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.1004349366
Short name T321
Test name
Test status
Simulation time 1037990327 ps
CPU time 6.14 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:07 PM PDT 24
Peak memory 205044 kb
Host smart-d7cb034d-b918-496c-9ffd-a32873eaffdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004349366 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1004349366
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1887235298
Short name T7
Test name
Test status
Simulation time 615245485 ps
CPU time 3.42 seconds
Started Jun 06 02:50:02 PM PDT 24
Finished Jun 06 02:50:07 PM PDT 24
Peak memory 205020 kb
Host smart-5de7adfe-bf2e-4938-9804-b39f36f7c6ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887235298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1887235298
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3717445503
Short name T1397
Test name
Test status
Simulation time 1008157162 ps
CPU time 5.06 seconds
Started Jun 06 02:49:30 PM PDT 24
Finished Jun 06 02:49:37 PM PDT 24
Peak memory 205056 kb
Host smart-9ac02a73-4c39-41c9-a49e-7922abe363eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717445503 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3717445503
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3910059305
Short name T79
Test name
Test status
Simulation time 13438309390 ps
CPU time 4.23 seconds
Started Jun 06 02:49:29 PM PDT 24
Finished Jun 06 02:49:36 PM PDT 24
Peak memory 205144 kb
Host smart-c767812d-2ff0-4143-8527-1d9192e6be88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910059305 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3910059305
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.24514891
Short name T553
Test name
Test status
Simulation time 3282972167 ps
CPU time 12.93 seconds
Started Jun 06 02:49:28 PM PDT 24
Finished Jun 06 02:49:43 PM PDT 24
Peak memory 205136 kb
Host smart-af2b27f6-2d54-4120-af63-5318a06d26e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24514891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_targe
t_smoke.24514891
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.469858318
Short name T1035
Test name
Test status
Simulation time 11627185156 ps
CPU time 73.03 seconds
Started Jun 06 02:49:29 PM PDT 24
Finished Jun 06 02:50:43 PM PDT 24
Peak memory 208328 kb
Host smart-7105f16b-edad-4f79-ab58-940c46ca583c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469858318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.469858318
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2530583572
Short name T1136
Test name
Test status
Simulation time 60581877280 ps
CPU time 1795.29 seconds
Started Jun 06 02:49:28 PM PDT 24
Finished Jun 06 03:19:25 PM PDT 24
Peak memory 10061824 kb
Host smart-9224f255-33c9-411b-92e2-4e4ce682f702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530583572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2530583572
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2865593002
Short name T724
Test name
Test status
Simulation time 13950747104 ps
CPU time 572.25 seconds
Started Jun 06 02:49:30 PM PDT 24
Finished Jun 06 02:59:05 PM PDT 24
Peak memory 1661500 kb
Host smart-cfd625b4-ed24-49e4-bfec-67edaacc3124
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865593002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2865593002
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.4234349283
Short name T375
Test name
Test status
Simulation time 5407075397 ps
CPU time 7.36 seconds
Started Jun 06 02:49:28 PM PDT 24
Finished Jun 06 02:49:37 PM PDT 24
Peak memory 217876 kb
Host smart-8055e6cd-0078-44d9-8fe1-90c8cb338ffe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234349283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.4234349283
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.3074978926
Short name T774
Test name
Test status
Simulation time 1077264998 ps
CPU time 16.82 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:17 PM PDT 24
Peak memory 205064 kb
Host smart-de46060a-deda-443f-8edf-522498f342ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074978926 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.3074978926
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.2818843332
Short name T356
Test name
Test status
Simulation time 90797520 ps
CPU time 0.58 seconds
Started Jun 06 02:54:44 PM PDT 24
Finished Jun 06 02:54:52 PM PDT 24
Peak memory 204752 kb
Host smart-50d7d7f4-45d4-4d19-b938-5c833e749d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818843332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.2818843332
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.2118149022
Short name T287
Test name
Test status
Simulation time 486221435 ps
CPU time 3.43 seconds
Started Jun 06 02:54:29 PM PDT 24
Finished Jun 06 02:54:37 PM PDT 24
Peak memory 232604 kb
Host smart-3be8c354-daac-46e2-9133-42f4ae454508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118149022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.2118149022
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1312556015
Short name T1304
Test name
Test status
Simulation time 442272877 ps
CPU time 9.62 seconds
Started Jun 06 02:54:28 PM PDT 24
Finished Jun 06 02:54:43 PM PDT 24
Peak memory 296116 kb
Host smart-06972406-96af-451d-b3d7-3a2c167046aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312556015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1312556015
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.64635753
Short name T893
Test name
Test status
Simulation time 43980851076 ps
CPU time 111.57 seconds
Started Jun 06 02:54:24 PM PDT 24
Finished Jun 06 02:56:19 PM PDT 24
Peak memory 843320 kb
Host smart-52c496be-30c5-4839-b05f-26fca75aec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64635753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.64635753
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.1167011372
Short name T1452
Test name
Test status
Simulation time 7733081881 ps
CPU time 65.66 seconds
Started Jun 06 02:54:27 PM PDT 24
Finished Jun 06 02:55:37 PM PDT 24
Peak memory 631568 kb
Host smart-45543627-33e3-448f-b1eb-de7af8c56fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167011372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.1167011372
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3586984862
Short name T683
Test name
Test status
Simulation time 276187835 ps
CPU time 1.06 seconds
Started Jun 06 02:54:26 PM PDT 24
Finished Jun 06 02:54:32 PM PDT 24
Peak memory 204768 kb
Host smart-d5c23dd9-d253-426c-90a6-7164f0b817f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586984862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3586984862
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2765950633
Short name T473
Test name
Test status
Simulation time 152170898 ps
CPU time 8.68 seconds
Started Jun 06 02:54:28 PM PDT 24
Finished Jun 06 02:54:42 PM PDT 24
Peak memory 231228 kb
Host smart-75d8def7-8405-4a6d-890c-2bd5aeb13586
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765950633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2765950633
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.2373024800
Short name T1332
Test name
Test status
Simulation time 9954173859 ps
CPU time 130.28 seconds
Started Jun 06 02:54:29 PM PDT 24
Finished Jun 06 02:56:44 PM PDT 24
Peak memory 1339780 kb
Host smart-f8ff91a0-5eb2-4ee9-a9ac-2b9a7494b7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373024800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.2373024800
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.4079658002
Short name T1390
Test name
Test status
Simulation time 653853493 ps
CPU time 5.33 seconds
Started Jun 06 02:54:32 PM PDT 24
Finished Jun 06 02:54:42 PM PDT 24
Peak memory 204968 kb
Host smart-29d94ec1-274c-4a42-93ca-539dc59cbaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079658002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.4079658002
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.3059279194
Short name T1107
Test name
Test status
Simulation time 1544412171 ps
CPU time 65.39 seconds
Started Jun 06 02:54:44 PM PDT 24
Finished Jun 06 02:55:57 PM PDT 24
Peak memory 335476 kb
Host smart-734a3b82-2016-4607-98a4-f0199661ada4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059279194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.3059279194
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.504888348
Short name T700
Test name
Test status
Simulation time 15639962 ps
CPU time 0.66 seconds
Started Jun 06 02:54:25 PM PDT 24
Finished Jun 06 02:54:30 PM PDT 24
Peak memory 204736 kb
Host smart-3283fc53-9b17-4ee1-b99b-1f98f247ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504888348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.504888348
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2583670338
Short name T387
Test name
Test status
Simulation time 12268041999 ps
CPU time 64.08 seconds
Started Jun 06 02:54:26 PM PDT 24
Finished Jun 06 02:55:35 PM PDT 24
Peak memory 573360 kb
Host smart-2ee314d5-3a7e-437e-9ed1-6f94b81e3954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583670338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2583670338
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2368205465
Short name T680
Test name
Test status
Simulation time 1824942404 ps
CPU time 30.05 seconds
Started Jun 06 02:54:25 PM PDT 24
Finished Jun 06 02:54:59 PM PDT 24
Peak memory 364748 kb
Host smart-fc6b5e80-370e-4b08-b1b1-6cc1deb4d7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368205465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2368205465
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2790361605
Short name T68
Test name
Test status
Simulation time 101160130761 ps
CPU time 458.39 seconds
Started Jun 06 02:54:34 PM PDT 24
Finished Jun 06 03:02:17 PM PDT 24
Peak memory 979104 kb
Host smart-ac81d2b2-3f82-4b82-9e24-64670f75d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790361605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2790361605
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.2693389273
Short name T245
Test name
Test status
Simulation time 916037408 ps
CPU time 14.5 seconds
Started Jun 06 02:54:30 PM PDT 24
Finished Jun 06 02:54:49 PM PDT 24
Peak memory 221552 kb
Host smart-f8f37512-5b31-4725-a040-72dfcf96db5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693389273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.2693389273
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.3767019212
Short name T12
Test name
Test status
Simulation time 3587144003 ps
CPU time 3.95 seconds
Started Jun 06 02:54:35 PM PDT 24
Finished Jun 06 02:54:45 PM PDT 24
Peak memory 205104 kb
Host smart-102a5ba7-1fcd-4dfd-b472-b1503643bc94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767019212 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.3767019212
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2901397373
Short name T780
Test name
Test status
Simulation time 10117487414 ps
CPU time 23.22 seconds
Started Jun 06 02:54:33 PM PDT 24
Finished Jun 06 02:55:01 PM PDT 24
Peak memory 270432 kb
Host smart-a7798e7d-088d-465d-8598-fbea6ef51980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901397373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2901397373
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2037303624
Short name T1351
Test name
Test status
Simulation time 10444716798 ps
CPU time 5.84 seconds
Started Jun 06 02:54:35 PM PDT 24
Finished Jun 06 02:54:46 PM PDT 24
Peak memory 240844 kb
Host smart-71e85be5-1e14-4d9c-a126-749013b29749
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037303624 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2037303624
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.1055453968
Short name T1429
Test name
Test status
Simulation time 4845236862 ps
CPU time 2.82 seconds
Started Jun 06 02:54:32 PM PDT 24
Finished Jun 06 02:54:40 PM PDT 24
Peak memory 205192 kb
Host smart-b67d7654-c50a-42cb-a5a7-1088e20c2a84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055453968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.1055453968
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.3421128954
Short name T1425
Test name
Test status
Simulation time 1423088553 ps
CPU time 2.65 seconds
Started Jun 06 02:54:35 PM PDT 24
Finished Jun 06 02:54:43 PM PDT 24
Peak memory 205124 kb
Host smart-ca09d5eb-4e36-490f-bcfd-4ac4541d237c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421128954 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.3421128954
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.1657446904
Short name T382
Test name
Test status
Simulation time 715486137 ps
CPU time 2.33 seconds
Started Jun 06 02:54:32 PM PDT 24
Finished Jun 06 02:54:39 PM PDT 24
Peak memory 205032 kb
Host smart-723bd820-9b82-44f1-b5dc-a9c3eafd9a5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657446904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.1657446904
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1488684698
Short name T891
Test name
Test status
Simulation time 752919008 ps
CPU time 3.94 seconds
Started Jun 06 02:54:34 PM PDT 24
Finished Jun 06 02:54:42 PM PDT 24
Peak memory 206320 kb
Host smart-e245f47b-3fb8-45e5-95f4-1b72e1a30bd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488684698 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1488684698
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.2888300803
Short name T1275
Test name
Test status
Simulation time 29050153395 ps
CPU time 242.96 seconds
Started Jun 06 02:54:41 PM PDT 24
Finished Jun 06 02:58:51 PM PDT 24
Peak memory 3288384 kb
Host smart-2a140416-5360-4ce4-907f-f538ea31603e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888300803 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.2888300803
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.262627939
Short name T988
Test name
Test status
Simulation time 1444804449 ps
CPU time 12.5 seconds
Started Jun 06 02:54:44 PM PDT 24
Finished Jun 06 02:55:04 PM PDT 24
Peak memory 205052 kb
Host smart-10b1812a-5700-483c-94bd-e244503bf49d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262627939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.262627939
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3949138791
Short name T425
Test name
Test status
Simulation time 7231056724 ps
CPU time 28.24 seconds
Started Jun 06 02:54:31 PM PDT 24
Finished Jun 06 02:55:04 PM PDT 24
Peak memory 234344 kb
Host smart-058fd0e7-daef-4656-938f-9457201bddc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949138791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3949138791
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.3693243478
Short name T165
Test name
Test status
Simulation time 20824849008 ps
CPU time 22.56 seconds
Started Jun 06 02:54:41 PM PDT 24
Finished Jun 06 02:55:11 PM PDT 24
Peak memory 205028 kb
Host smart-ac2884ee-df5b-4534-bb54-6877a950d623
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693243478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.3693243478
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1070484888
Short name T590
Test name
Test status
Simulation time 2058802252 ps
CPU time 6.52 seconds
Started Jun 06 02:54:34 PM PDT 24
Finished Jun 06 02:54:46 PM PDT 24
Peak memory 211828 kb
Host smart-16f3f635-d2dc-497a-8f7d-e3ee0eb8ced1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070484888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1070484888
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.3908616432
Short name T430
Test name
Test status
Simulation time 1068700612 ps
CPU time 15.92 seconds
Started Jun 06 02:54:39 PM PDT 24
Finished Jun 06 02:55:02 PM PDT 24
Peak memory 205052 kb
Host smart-a58afba0-e1ae-4d40-9c35-ad04b3a18327
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908616432 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.3908616432
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.41916740
Short name T462
Test name
Test status
Simulation time 16312002 ps
CPU time 0.64 seconds
Started Jun 06 02:54:46 PM PDT 24
Finished Jun 06 02:54:54 PM PDT 24
Peak memory 204760 kb
Host smart-be731395-797e-4965-bd7f-a46f01b75bb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41916740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.41916740
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3758041077
Short name T1095
Test name
Test status
Simulation time 388511943 ps
CPU time 6.08 seconds
Started Jun 06 02:54:34 PM PDT 24
Finished Jun 06 02:54:45 PM PDT 24
Peak memory 262148 kb
Host smart-98cf8ad6-fe29-49f2-9839-696fc807aef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758041077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3758041077
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.633719602
Short name T606
Test name
Test status
Simulation time 1498547310 ps
CPU time 18.15 seconds
Started Jun 06 02:54:34 PM PDT 24
Finished Jun 06 02:54:57 PM PDT 24
Peak memory 275700 kb
Host smart-b0b68545-061f-44cb-a56d-f721f633796d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633719602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.633719602
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.544215197
Short name T56
Test name
Test status
Simulation time 1918477214 ps
CPU time 140.63 seconds
Started Jun 06 02:54:40 PM PDT 24
Finished Jun 06 02:57:08 PM PDT 24
Peak memory 674280 kb
Host smart-86dad20f-0069-4515-b165-cf47ba78e649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544215197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.544215197
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3198380241
Short name T587
Test name
Test status
Simulation time 5516299381 ps
CPU time 92.39 seconds
Started Jun 06 02:54:33 PM PDT 24
Finished Jun 06 02:56:10 PM PDT 24
Peak memory 877724 kb
Host smart-94c45419-4efe-4be7-acfc-1e0d631eaf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198380241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3198380241
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.3859683301
Short name T358
Test name
Test status
Simulation time 132746472 ps
CPU time 1.11 seconds
Started Jun 06 02:54:45 PM PDT 24
Finished Jun 06 02:54:54 PM PDT 24
Peak memory 205020 kb
Host smart-56e90217-0610-4915-a29e-5d8610eec8ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859683301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.3859683301
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2136789334
Short name T876
Test name
Test status
Simulation time 564592083 ps
CPU time 6.1 seconds
Started Jun 06 02:54:32 PM PDT 24
Finished Jun 06 02:54:43 PM PDT 24
Peak memory 219292 kb
Host smart-5f7f61dc-cf51-486b-a3d7-39ed3828c4f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136789334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2136789334
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.3172283286
Short name T108
Test name
Test status
Simulation time 18954484885 ps
CPU time 378.77 seconds
Started Jun 06 02:54:41 PM PDT 24
Finished Jun 06 03:01:07 PM PDT 24
Peak memory 1338416 kb
Host smart-a50537af-f600-4040-a47e-41b5ef56dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172283286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.3172283286
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.295571241
Short name T859
Test name
Test status
Simulation time 1088735347 ps
CPU time 22.66 seconds
Started Jun 06 02:54:42 PM PDT 24
Finished Jun 06 02:55:12 PM PDT 24
Peak memory 205088 kb
Host smart-a4401ab0-c595-4e13-8a87-c0c990c7fdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295571241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.295571241
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_override.51401331
Short name T1279
Test name
Test status
Simulation time 15626559 ps
CPU time 0.64 seconds
Started Jun 06 02:54:32 PM PDT 24
Finished Jun 06 02:54:37 PM PDT 24
Peak memory 204700 kb
Host smart-900378b4-1325-4578-bbfe-d623b06846c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51401331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.51401331
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1405854771
Short name T1154
Test name
Test status
Simulation time 1276890302 ps
CPU time 51.26 seconds
Started Jun 06 02:54:36 PM PDT 24
Finished Jun 06 02:55:33 PM PDT 24
Peak memory 216012 kb
Host smart-3f731513-b048-42a1-96e3-7a58b56e1a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405854771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1405854771
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1693785611
Short name T1233
Test name
Test status
Simulation time 2493938822 ps
CPU time 59.44 seconds
Started Jun 06 02:54:53 PM PDT 24
Finished Jun 06 02:55:59 PM PDT 24
Peak memory 299800 kb
Host smart-50f64c09-3b47-4669-85ee-32e222952a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693785611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1693785611
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.886080117
Short name T6
Test name
Test status
Simulation time 543844774 ps
CPU time 8.15 seconds
Started Jun 06 02:54:33 PM PDT 24
Finished Jun 06 02:54:46 PM PDT 24
Peak memory 216544 kb
Host smart-dc0c2d5c-4a8e-4922-8408-9fc425ffb6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886080117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.886080117
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.1800818770
Short name T24
Test name
Test status
Simulation time 1757425938 ps
CPU time 4.48 seconds
Started Jun 06 02:54:36 PM PDT 24
Finished Jun 06 02:54:47 PM PDT 24
Peak memory 205160 kb
Host smart-165b7ced-56b2-458c-b0ab-589ed056671e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800818770 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.1800818770
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3829136361
Short name T486
Test name
Test status
Simulation time 10122981230 ps
CPU time 49.29 seconds
Started Jun 06 02:54:34 PM PDT 24
Finished Jun 06 02:55:29 PM PDT 24
Peak memory 317344 kb
Host smart-e6ee7336-12f0-4cb3-aca4-2abc81f20cb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829136361 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3829136361
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1336588612
Short name T1476
Test name
Test status
Simulation time 10338520312 ps
CPU time 35.08 seconds
Started Jun 06 02:54:31 PM PDT 24
Finished Jun 06 02:55:11 PM PDT 24
Peak memory 476528 kb
Host smart-ef622659-d731-4032-b804-9e99ec868063
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336588612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1336588612
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.3622726009
Short name T540
Test name
Test status
Simulation time 1336209171 ps
CPU time 1.82 seconds
Started Jun 06 02:54:56 PM PDT 24
Finished Jun 06 02:55:05 PM PDT 24
Peak memory 204952 kb
Host smart-2ac186d9-323a-43d0-b6d5-dd0b2cce8114
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622726009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.3622726009
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.3494211767
Short name T106
Test name
Test status
Simulation time 1319005502 ps
CPU time 2.1 seconds
Started Jun 06 02:54:42 PM PDT 24
Finished Jun 06 02:54:52 PM PDT 24
Peak memory 205104 kb
Host smart-07c34a3b-defe-4129-8d31-e3241d26e2e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494211767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.3494211767
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.1773452863
Short name T564
Test name
Test status
Simulation time 628590837 ps
CPU time 2.87 seconds
Started Jun 06 02:54:41 PM PDT 24
Finished Jun 06 02:54:51 PM PDT 24
Peak memory 205084 kb
Host smart-d458d2a3-1079-48de-87e8-b58de27d6ba5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773452863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 31.i2c_target_hrst.1773452863
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.3205358264
Short name T1249
Test name
Test status
Simulation time 4113208873 ps
CPU time 5.72 seconds
Started Jun 06 02:54:35 PM PDT 24
Finished Jun 06 02:54:46 PM PDT 24
Peak memory 213372 kb
Host smart-07a4c084-6f64-4818-af58-580176475573
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205358264 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.3205358264
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1121141011
Short name T233
Test name
Test status
Simulation time 14034879310 ps
CPU time 211.65 seconds
Started Jun 06 02:54:32 PM PDT 24
Finished Jun 06 02:58:09 PM PDT 24
Peak memory 2926912 kb
Host smart-4c2e3798-9603-4b35-aacb-37a1890d495d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121141011 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1121141011
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.1442060769
Short name T87
Test name
Test status
Simulation time 4824129192 ps
CPU time 18.12 seconds
Started Jun 06 02:54:35 PM PDT 24
Finished Jun 06 02:54:58 PM PDT 24
Peak memory 205152 kb
Host smart-e81ac252-c339-4e95-91f5-8d826a9eadbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442060769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.1442060769
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2571601954
Short name T301
Test name
Test status
Simulation time 394630106 ps
CPU time 4.99 seconds
Started Jun 06 02:54:40 PM PDT 24
Finished Jun 06 02:54:52 PM PDT 24
Peak memory 205092 kb
Host smart-5e46edeb-6c01-4d57-85c4-298042696a8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571601954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2571601954
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3220197729
Short name T307
Test name
Test status
Simulation time 9962255920 ps
CPU time 2.34 seconds
Started Jun 06 02:54:45 PM PDT 24
Finished Jun 06 02:54:54 PM PDT 24
Peak memory 205160 kb
Host smart-27597904-3f1c-4123-8e7e-51f2fd4641ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220197729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3220197729
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2639163182
Short name T1002
Test name
Test status
Simulation time 12436057906 ps
CPU time 728.79 seconds
Started Jun 06 02:54:44 PM PDT 24
Finished Jun 06 03:07:00 PM PDT 24
Peak memory 3184428 kb
Host smart-54c40b71-519b-40e4-861e-8ea01bf5de69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639163182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2639163182
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3444220404
Short name T295
Test name
Test status
Simulation time 1212986891 ps
CPU time 7.09 seconds
Started Jun 06 02:54:44 PM PDT 24
Finished Jun 06 02:54:58 PM PDT 24
Peak memory 205140 kb
Host smart-505afb2d-c991-4ce0-892f-cf1ae76d1f1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444220404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3444220404
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.2035494438
Short name T547
Test name
Test status
Simulation time 1031482598 ps
CPU time 19.67 seconds
Started Jun 06 02:54:42 PM PDT 24
Finished Jun 06 02:55:09 PM PDT 24
Peak memory 205052 kb
Host smart-fca3fbd2-900a-4c2d-81db-731a6f9f9da4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035494438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2035494438
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.2560345461
Short name T950
Test name
Test status
Simulation time 48748641 ps
CPU time 0.61 seconds
Started Jun 06 02:54:50 PM PDT 24
Finished Jun 06 02:54:58 PM PDT 24
Peak memory 204728 kb
Host smart-897cc70e-5fff-4153-b404-218882b24a9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560345461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.2560345461
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.855930147
Short name T34
Test name
Test status
Simulation time 249288924 ps
CPU time 2.53 seconds
Started Jun 06 02:54:55 PM PDT 24
Finished Jun 06 02:55:05 PM PDT 24
Peak memory 233400 kb
Host smart-db3ad097-af26-405f-9d94-f817e028f4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855930147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.855930147
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.543052095
Short name T329
Test name
Test status
Simulation time 276078114 ps
CPU time 13.71 seconds
Started Jun 06 02:54:42 PM PDT 24
Finished Jun 06 02:55:04 PM PDT 24
Peak memory 240968 kb
Host smart-b9ee9dc1-1b96-4096-a520-46ea47d95cec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543052095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.543052095
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2654996761
Short name T66
Test name
Test status
Simulation time 10905541501 ps
CPU time 95.39 seconds
Started Jun 06 02:54:41 PM PDT 24
Finished Jun 06 02:56:24 PM PDT 24
Peak memory 858832 kb
Host smart-b17cfff2-3dea-4f4d-bf5f-7c34e7e0d7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654996761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2654996761
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.382662504
Short name T288
Test name
Test status
Simulation time 15893481511 ps
CPU time 45.66 seconds
Started Jun 06 02:54:39 PM PDT 24
Finished Jun 06 02:55:32 PM PDT 24
Peak memory 525524 kb
Host smart-1f528536-929a-417a-8305-0effc0d9d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382662504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.382662504
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3506359534
Short name T884
Test name
Test status
Simulation time 504813218 ps
CPU time 0.93 seconds
Started Jun 06 02:54:40 PM PDT 24
Finished Jun 06 02:54:47 PM PDT 24
Peak memory 204736 kb
Host smart-b10fbc7e-e082-48c2-9488-cd97ebc8f537
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506359534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3506359534
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3924198364
Short name T947
Test name
Test status
Simulation time 159039818 ps
CPU time 9.39 seconds
Started Jun 06 02:54:55 PM PDT 24
Finished Jun 06 02:55:11 PM PDT 24
Peak memory 233876 kb
Host smart-cbba8a8c-65ff-466d-8fff-32a5a6662940
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924198364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3924198364
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.116302663
Short name T1473
Test name
Test status
Simulation time 9310728469 ps
CPU time 344.09 seconds
Started Jun 06 02:54:40 PM PDT 24
Finished Jun 06 03:00:32 PM PDT 24
Peak memory 1261936 kb
Host smart-494801ee-6db1-44ca-88cb-a409b5a34544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116302663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.116302663
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.116800606
Short name T718
Test name
Test status
Simulation time 433029277 ps
CPU time 5.34 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:55:02 PM PDT 24
Peak memory 205040 kb
Host smart-5765c9ca-a8e2-40fb-8f8c-1d96d28561ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116800606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.116800606
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.463335784
Short name T383
Test name
Test status
Simulation time 6332064720 ps
CPU time 74.49 seconds
Started Jun 06 02:54:46 PM PDT 24
Finished Jun 06 02:56:08 PM PDT 24
Peak memory 330008 kb
Host smart-20b39268-6fbf-40d9-bcad-ab652c388470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463335784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.463335784
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.1562765085
Short name T346
Test name
Test status
Simulation time 27067697 ps
CPU time 0.67 seconds
Started Jun 06 02:54:42 PM PDT 24
Finished Jun 06 02:54:50 PM PDT 24
Peak memory 204652 kb
Host smart-13281c8d-19d3-4f6f-a43e-f7133becd118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562765085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1562765085
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.2534536981
Short name T1153
Test name
Test status
Simulation time 7083217941 ps
CPU time 50.35 seconds
Started Jun 06 02:54:43 PM PDT 24
Finished Jun 06 02:55:40 PM PDT 24
Peak memory 613840 kb
Host smart-5f3e3609-940f-4316-bfee-0ceb3edb61d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534536981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.2534536981
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2493836278
Short name T1372
Test name
Test status
Simulation time 2269596213 ps
CPU time 44.84 seconds
Started Jun 06 02:54:40 PM PDT 24
Finished Jun 06 02:55:32 PM PDT 24
Peak memory 353608 kb
Host smart-44dad1c8-905d-4523-bae0-2f9f0b5eaad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493836278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2493836278
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.736451103
Short name T1193
Test name
Test status
Simulation time 655844779 ps
CPU time 28.2 seconds
Started Jun 06 02:54:56 PM PDT 24
Finished Jun 06 02:55:31 PM PDT 24
Peak memory 213288 kb
Host smart-dc00b321-f96a-427f-b186-e91357e35104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736451103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.736451103
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.2879081327
Short name T312
Test name
Test status
Simulation time 479818354 ps
CPU time 2.81 seconds
Started Jun 06 02:54:41 PM PDT 24
Finished Jun 06 02:54:51 PM PDT 24
Peak memory 205156 kb
Host smart-bbcf4109-6d47-4caf-a7ba-3b7833cb73d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879081327 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.2879081327
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.621623540
Short name T1088
Test name
Test status
Simulation time 10222196754 ps
CPU time 11.73 seconds
Started Jun 06 02:54:41 PM PDT 24
Finished Jun 06 02:55:00 PM PDT 24
Peak memory 268616 kb
Host smart-5080026f-5e89-4eeb-8839-32d03472bdc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621623540 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.621623540
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.1465650796
Short name T1363
Test name
Test status
Simulation time 10790557651 ps
CPU time 9.46 seconds
Started Jun 06 02:54:42 PM PDT 24
Finished Jun 06 02:54:59 PM PDT 24
Peak memory 276160 kb
Host smart-8feb7a3d-8138-49ee-9539-264255f51ede
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465650796 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.1465650796
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.2809565232
Short name T903
Test name
Test status
Simulation time 1322995169 ps
CPU time 5.71 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:55:01 PM PDT 24
Peak memory 205052 kb
Host smart-d643514e-9f5e-42f8-bee6-b0641e1b1e9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809565232 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.2809565232
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.3386430788
Short name T490
Test name
Test status
Simulation time 1185217323 ps
CPU time 3.26 seconds
Started Jun 06 02:54:48 PM PDT 24
Finished Jun 06 02:54:58 PM PDT 24
Peak memory 205036 kb
Host smart-706ff684-71e9-40ae-8692-718367a025f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386430788 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.3386430788
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.2110952345
Short name T1061
Test name
Test status
Simulation time 7066640041 ps
CPU time 3.15 seconds
Started Jun 06 02:54:41 PM PDT 24
Finished Jun 06 02:54:51 PM PDT 24
Peak memory 205188 kb
Host smart-b923bd35-834e-495d-9a9a-2528e32ae99f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110952345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_hrst.2110952345
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.85233397
Short name T1307
Test name
Test status
Simulation time 7669910526 ps
CPU time 8.16 seconds
Started Jun 06 02:54:45 PM PDT 24
Finished Jun 06 02:55:01 PM PDT 24
Peak memory 205176 kb
Host smart-ab0e37af-1d15-4b61-86f8-57a0fa2b2fce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85233397 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 32.i2c_target_intr_smoke.85233397
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1158478078
Short name T1214
Test name
Test status
Simulation time 27727143915 ps
CPU time 17.78 seconds
Started Jun 06 02:54:46 PM PDT 24
Finished Jun 06 02:55:11 PM PDT 24
Peak memory 517884 kb
Host smart-a2092c5a-0875-4af7-9dc0-3ccca7d4693a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158478078 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1158478078
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.2078632495
Short name T1369
Test name
Test status
Simulation time 1866689226 ps
CPU time 13.08 seconds
Started Jun 06 02:54:56 PM PDT 24
Finished Jun 06 02:55:16 PM PDT 24
Peak memory 205076 kb
Host smart-00822415-204e-411c-9c92-dd381354380f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078632495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.2078632495
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.4070972630
Short name T507
Test name
Test status
Simulation time 4089754845 ps
CPU time 44.86 seconds
Started Jun 06 02:54:40 PM PDT 24
Finished Jun 06 02:55:32 PM PDT 24
Peak memory 206216 kb
Host smart-e94db47f-00e6-4016-bb93-e62b278ae2db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070972630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.4070972630
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.242686361
Short name T633
Test name
Test status
Simulation time 40607989409 ps
CPU time 71.44 seconds
Started Jun 06 02:54:40 PM PDT 24
Finished Jun 06 02:55:59 PM PDT 24
Peak memory 1286044 kb
Host smart-a828964e-2eca-448a-be11-1c62a1c9c411
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242686361 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c
_target_stress_wr.242686361
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.757677815
Short name T1219
Test name
Test status
Simulation time 8107836547 ps
CPU time 16.09 seconds
Started Jun 06 02:54:46 PM PDT 24
Finished Jun 06 02:55:09 PM PDT 24
Peak memory 360972 kb
Host smart-8cf937ab-1dab-422c-8f03-1b11cd394ae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757677815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_t
arget_stretch.757677815
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.1132980735
Short name T493
Test name
Test status
Simulation time 1233287836 ps
CPU time 7.15 seconds
Started Jun 06 02:54:54 PM PDT 24
Finished Jun 06 02:55:08 PM PDT 24
Peak memory 205104 kb
Host smart-6baf8d01-52e9-4225-9270-d94aa55c3129
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132980735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.1132980735
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.745067551
Short name T719
Test name
Test status
Simulation time 1131838919 ps
CPU time 18 seconds
Started Jun 06 02:54:51 PM PDT 24
Finished Jun 06 02:55:15 PM PDT 24
Peak memory 205136 kb
Host smart-57673299-ad43-450f-bb7e-06c087bb871d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745067551 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.745067551
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.842983984
Short name T155
Test name
Test status
Simulation time 27711440 ps
CPU time 0.67 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:55:06 PM PDT 24
Peak memory 204740 kb
Host smart-4fd494f9-08bf-4469-8c9a-3dbc2b4ec0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842983984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.842983984
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.4136245739
Short name T1102
Test name
Test status
Simulation time 474345596 ps
CPU time 1.99 seconds
Started Jun 06 02:54:50 PM PDT 24
Finished Jun 06 02:54:58 PM PDT 24
Peak memory 213364 kb
Host smart-3bd90f83-7016-4c4f-952a-a20ac759bab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136245739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.4136245739
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.486207966
Short name T1004
Test name
Test status
Simulation time 1003475461 ps
CPU time 24.85 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:55:21 PM PDT 24
Peak memory 293520 kb
Host smart-9db74a63-4985-42e3-aa08-8bcc92b68d90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486207966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.486207966
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2679435385
Short name T522
Test name
Test status
Simulation time 2523780624 ps
CPU time 76.62 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:56:12 PM PDT 24
Peak memory 634800 kb
Host smart-dffb2127-8f42-4053-b3e2-fa6a4befb2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679435385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2679435385
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.385622483
Short name T635
Test name
Test status
Simulation time 23292557390 ps
CPU time 155.98 seconds
Started Jun 06 02:54:56 PM PDT 24
Finished Jun 06 02:57:39 PM PDT 24
Peak memory 675848 kb
Host smart-80c26859-c6fb-472b-8b6f-68e3bd5f06ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385622483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.385622483
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.2037964988
Short name T652
Test name
Test status
Simulation time 463290577 ps
CPU time 0.87 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:54:57 PM PDT 24
Peak memory 204784 kb
Host smart-55f6ad53-c242-43a9-8c1a-a7de8ba4616c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037964988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.2037964988
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2184343211
Short name T1308
Test name
Test status
Simulation time 245342098 ps
CPU time 7.8 seconds
Started Jun 06 02:54:50 PM PDT 24
Finished Jun 06 02:55:04 PM PDT 24
Peak memory 226392 kb
Host smart-4a933832-fdc3-4a1b-9514-ac90a3dd0e80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184343211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2184343211
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.306594493
Short name T246
Test name
Test status
Simulation time 3289787548 ps
CPU time 235.63 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:58:52 PM PDT 24
Peak memory 971864 kb
Host smart-e5b93390-adaf-4de6-b955-7b9558854d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306594493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.306594493
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.12816854
Short name T1296
Test name
Test status
Simulation time 4084391142 ps
CPU time 15.12 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:55:20 PM PDT 24
Peak memory 205120 kb
Host smart-9dcbabf0-2cda-4e57-ab53-b697484deb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12816854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.12816854
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.4084266340
Short name T30
Test name
Test status
Simulation time 3321898236 ps
CPU time 31 seconds
Started Jun 06 02:55:00 PM PDT 24
Finished Jun 06 02:55:37 PM PDT 24
Peak memory 331140 kb
Host smart-f4985dfb-903a-4fd5-85dc-0388373c2563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084266340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.4084266340
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3155504408
Short name T84
Test name
Test status
Simulation time 16295754 ps
CPU time 0.66 seconds
Started Jun 06 02:54:52 PM PDT 24
Finished Jun 06 02:54:59 PM PDT 24
Peak memory 204692 kb
Host smart-5ef8e4f4-0835-425b-ae6c-57cbddca8c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155504408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3155504408
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.2354901169
Short name T458
Test name
Test status
Simulation time 26968251825 ps
CPU time 1115.46 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 03:13:32 PM PDT 24
Peak memory 213376 kb
Host smart-9494c608-b5c6-4b62-8e56-2750f84fa91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354901169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2354901169
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2596120611
Short name T437
Test name
Test status
Simulation time 22449064305 ps
CPU time 34.71 seconds
Started Jun 06 02:54:50 PM PDT 24
Finished Jun 06 02:55:32 PM PDT 24
Peak memory 323096 kb
Host smart-93cbdd53-f967-4cbd-b383-d699d00d3e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596120611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2596120611
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.1366348042
Short name T478
Test name
Test status
Simulation time 7950149293 ps
CPU time 14.82 seconds
Started Jun 06 02:54:50 PM PDT 24
Finished Jun 06 02:55:11 PM PDT 24
Peak memory 221576 kb
Host smart-34365b2c-cf8c-4ce0-80d7-a8dc90336f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366348042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.1366348042
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.966873812
Short name T442
Test name
Test status
Simulation time 1133130678 ps
CPU time 2.07 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:54:58 PM PDT 24
Peak memory 205124 kb
Host smart-8b65f6f8-4d14-482d-971a-f4c45b7d223c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966873812 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.966873812
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3740662281
Short name T794
Test name
Test status
Simulation time 10193035245 ps
CPU time 24.4 seconds
Started Jun 06 02:54:50 PM PDT 24
Finished Jun 06 02:55:21 PM PDT 24
Peak memory 299132 kb
Host smart-6eebec7e-7371-4b75-8d48-4cf97b2f9f7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740662281 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3740662281
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1035908027
Short name T1165
Test name
Test status
Simulation time 10623678790 ps
CPU time 21.49 seconds
Started Jun 06 02:54:53 PM PDT 24
Finished Jun 06 02:55:21 PM PDT 24
Peak memory 335388 kb
Host smart-d9c21ee8-56d6-4c94-b4b6-d46be18b9a24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035908027 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1035908027
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.305026807
Short name T1051
Test name
Test status
Simulation time 2020205881 ps
CPU time 3.02 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:55:08 PM PDT 24
Peak memory 205288 kb
Host smart-9e8e8a7c-cba1-4191-9ed1-9781d517d6c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305026807 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.305026807
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.4174072778
Short name T1030
Test name
Test status
Simulation time 1066965536 ps
CPU time 5.7 seconds
Started Jun 06 02:55:03 PM PDT 24
Finished Jun 06 02:55:16 PM PDT 24
Peak memory 205056 kb
Host smart-bdddaf26-160c-4c87-b256-60f04c033282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174072778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.4174072778
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2272946620
Short name T773
Test name
Test status
Simulation time 1677728590 ps
CPU time 2.57 seconds
Started Jun 06 02:55:03 PM PDT 24
Finished Jun 06 02:55:13 PM PDT 24
Peak memory 205012 kb
Host smart-3a5efa01-34cc-4c33-823f-63ea8b45bbd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272946620 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2272946620
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.3832061805
Short name T835
Test name
Test status
Simulation time 1121807092 ps
CPU time 6.54 seconds
Started Jun 06 02:54:52 PM PDT 24
Finished Jun 06 02:55:05 PM PDT 24
Peak memory 207876 kb
Host smart-7302d9b4-89e2-4107-b220-4ba367d93024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832061805 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.3832061805
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.479737417
Short name T585
Test name
Test status
Simulation time 10147168051 ps
CPU time 172.03 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:57:48 PM PDT 24
Peak memory 2607236 kb
Host smart-c9235875-2be8-4b8c-bbac-5f0cd302fcf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479737417 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.479737417
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.3183738363
Short name T1292
Test name
Test status
Simulation time 5660546359 ps
CPU time 18.52 seconds
Started Jun 06 02:54:56 PM PDT 24
Finished Jun 06 02:55:21 PM PDT 24
Peak memory 205192 kb
Host smart-04c4b604-86ba-47b1-ac86-b06e89b9119a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183738363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.3183738363
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3727057398
Short name T1056
Test name
Test status
Simulation time 920287062 ps
CPU time 9.23 seconds
Started Jun 06 02:54:54 PM PDT 24
Finished Jun 06 02:55:10 PM PDT 24
Peak memory 205084 kb
Host smart-189ff162-f5ab-4d8c-921f-a52b65727bc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727057398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3727057398
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.581035719
Short name T959
Test name
Test status
Simulation time 53902582119 ps
CPU time 529.34 seconds
Started Jun 06 02:54:55 PM PDT 24
Finished Jun 06 03:03:52 PM PDT 24
Peak memory 4293824 kb
Host smart-9fca5e31-0773-4c51-beea-30a412271304
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581035719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_wr.581035719
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.207649840
Short name T142
Test name
Test status
Simulation time 40836881007 ps
CPU time 124.66 seconds
Started Jun 06 02:54:49 PM PDT 24
Finished Jun 06 02:57:00 PM PDT 24
Peak memory 547604 kb
Host smart-39062bc8-e1bc-42f2-bccf-de5cd5f3f1a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207649840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_t
arget_stretch.207649840
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3248421581
Short name T843
Test name
Test status
Simulation time 1341524506 ps
CPU time 7.02 seconds
Started Jun 06 02:54:56 PM PDT 24
Finished Jun 06 02:55:10 PM PDT 24
Peak memory 214388 kb
Host smart-2c5be434-1229-4b34-b226-14e35ae39c91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248421581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3248421581
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.2150179708
Short name T1356
Test name
Test status
Simulation time 1070151049 ps
CPU time 15.87 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:55:21 PM PDT 24
Peak memory 205028 kb
Host smart-35dffb4a-7a6c-4b90-bc01-5632a86f2715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150179708 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.2150179708
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2580985749
Short name T513
Test name
Test status
Simulation time 19056525 ps
CPU time 0.65 seconds
Started Jun 06 02:55:08 PM PDT 24
Finished Jun 06 02:55:16 PM PDT 24
Peak memory 204684 kb
Host smart-053693dd-7736-4ae5-b84f-d152b2ddbfab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580985749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2580985749
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.4210931187
Short name T272
Test name
Test status
Simulation time 397507519 ps
CPU time 3.22 seconds
Started Jun 06 02:55:00 PM PDT 24
Finished Jun 06 02:55:09 PM PDT 24
Peak memory 216392 kb
Host smart-308e63c4-c21a-4c93-b744-56b819e9f6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210931187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.4210931187
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1779946307
Short name T1015
Test name
Test status
Simulation time 356300646 ps
CPU time 7.73 seconds
Started Jun 06 02:55:01 PM PDT 24
Finished Jun 06 02:55:15 PM PDT 24
Peak memory 277232 kb
Host smart-9390aa5e-81a8-449d-8ec1-94c54768602e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779946307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1779946307
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.1798481795
Short name T465
Test name
Test status
Simulation time 2962016774 ps
CPU time 230.88 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:58:56 PM PDT 24
Peak memory 909904 kb
Host smart-d472a517-d010-4839-9494-f361168cd8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798481795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.1798481795
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3755995836
Short name T110
Test name
Test status
Simulation time 2410810741 ps
CPU time 73.59 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:56:19 PM PDT 24
Peak memory 772420 kb
Host smart-60a452ce-faa9-432c-bf30-7895e7aadd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755995836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3755995836
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.786909007
Short name T617
Test name
Test status
Simulation time 147475961 ps
CPU time 0.83 seconds
Started Jun 06 02:55:01 PM PDT 24
Finished Jun 06 02:55:08 PM PDT 24
Peak memory 204776 kb
Host smart-c42fd905-8352-43b2-b29e-6f361f743e77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786909007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_fm
t.786909007
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.609845210
Short name T363
Test name
Test status
Simulation time 168441153 ps
CPU time 4.61 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:55:09 PM PDT 24
Peak memory 236040 kb
Host smart-3c18f940-a521-4ff2-8567-b2a483147bba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609845210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
609845210
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3999499059
Short name T730
Test name
Test status
Simulation time 5128668066 ps
CPU time 142.38 seconds
Started Jun 06 02:55:01 PM PDT 24
Finished Jun 06 02:57:29 PM PDT 24
Peak memory 1406564 kb
Host smart-09ab05c9-edd0-4063-a049-7cb78926def5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999499059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3999499059
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.333694536
Short name T224
Test name
Test status
Simulation time 1109302157 ps
CPU time 8.55 seconds
Started Jun 06 02:55:08 PM PDT 24
Finished Jun 06 02:55:24 PM PDT 24
Peak memory 204972 kb
Host smart-65a8cadd-7d9e-4c31-9b2b-b949c7287cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333694536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.333694536
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.1199566307
Short name T802
Test name
Test status
Simulation time 7007535454 ps
CPU time 25.11 seconds
Started Jun 06 02:55:10 PM PDT 24
Finished Jun 06 02:55:42 PM PDT 24
Peak memory 300172 kb
Host smart-1be6c6f5-9a0a-4ac6-b29c-3de3eded212c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199566307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.1199566307
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1884563660
Short name T1252
Test name
Test status
Simulation time 29593010 ps
CPU time 0.7 seconds
Started Jun 06 02:55:01 PM PDT 24
Finished Jun 06 02:55:08 PM PDT 24
Peak memory 204744 kb
Host smart-abf82186-89eb-4de5-b213-ddae0b6f2388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884563660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1884563660
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.556291987
Short name T638
Test name
Test status
Simulation time 3544102384 ps
CPU time 36.29 seconds
Started Jun 06 02:55:02 PM PDT 24
Finished Jun 06 02:55:44 PM PDT 24
Peak memory 205200 kb
Host smart-d69ec90c-3bd9-4e38-b089-bc6ad6d59557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556291987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.556291987
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.3997874479
Short name T1436
Test name
Test status
Simulation time 1521960543 ps
CPU time 74.39 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:56:20 PM PDT 24
Peak memory 332912 kb
Host smart-fa404f99-cb9d-4a9f-92c9-0fdb2635b725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997874479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.3997874479
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.2912168912
Short name T258
Test name
Test status
Simulation time 3793123294 ps
CPU time 15.32 seconds
Started Jun 06 02:55:00 PM PDT 24
Finished Jun 06 02:55:21 PM PDT 24
Peak memory 229812 kb
Host smart-2900f547-ea75-49b0-846b-e1b37345ab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912168912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.2912168912
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1917923229
Short name T1066
Test name
Test status
Simulation time 1615912037 ps
CPU time 4.19 seconds
Started Jun 06 02:55:10 PM PDT 24
Finished Jun 06 02:55:20 PM PDT 24
Peak memory 205116 kb
Host smart-b37511d6-2db7-49ef-be88-c03d2ffa6463
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917923229 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1917923229
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.3538666498
Short name T143
Test name
Test status
Simulation time 10154105024 ps
CPU time 9.37 seconds
Started Jun 06 02:55:08 PM PDT 24
Finished Jun 06 02:55:24 PM PDT 24
Peak memory 223664 kb
Host smart-37f0e88a-dd63-4685-92b8-6e6cb523c670
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538666498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.3538666498
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1673682577
Short name T70
Test name
Test status
Simulation time 10122065520 ps
CPU time 72.48 seconds
Started Jun 06 02:55:07 PM PDT 24
Finished Jun 06 02:56:27 PM PDT 24
Peak memory 613368 kb
Host smart-c9157ae3-24b6-4afb-a18a-4cdd3e746688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673682577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1673682577
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.41973893
Short name T324
Test name
Test status
Simulation time 1129256915 ps
CPU time 5.71 seconds
Started Jun 06 02:55:08 PM PDT 24
Finished Jun 06 02:55:21 PM PDT 24
Peak memory 205056 kb
Host smart-37a0197b-0672-4fd8-9d99-fd388b0d9e51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41973893 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.41973893
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.2525509466
Short name T1202
Test name
Test status
Simulation time 1153189244 ps
CPU time 6.1 seconds
Started Jun 06 02:55:31 PM PDT 24
Finished Jun 06 02:55:42 PM PDT 24
Peak memory 205144 kb
Host smart-e941ff66-65fd-4b74-bbdf-19e3b0a2b1eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525509466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.2525509466
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2077185696
Short name T1430
Test name
Test status
Simulation time 1837306043 ps
CPU time 3.12 seconds
Started Jun 06 02:55:08 PM PDT 24
Finished Jun 06 02:55:18 PM PDT 24
Peak memory 205104 kb
Host smart-a31319f3-5c83-4619-9fdf-36aebfce150b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077185696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2077185696
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2436954321
Short name T600
Test name
Test status
Simulation time 18421637796 ps
CPU time 7.02 seconds
Started Jun 06 02:55:00 PM PDT 24
Finished Jun 06 02:55:13 PM PDT 24
Peak memory 209916 kb
Host smart-1a36242a-192b-4c69-8af9-737e9b7f4cb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436954321 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2436954321
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.1360004100
Short name T537
Test name
Test status
Simulation time 27918882587 ps
CPU time 91.16 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:56:37 PM PDT 24
Peak memory 1605232 kb
Host smart-8452ef80-4abf-4bbc-bcbb-3f44ac708c03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360004100 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.1360004100
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.820427279
Short name T1466
Test name
Test status
Simulation time 2987005900 ps
CPU time 39.29 seconds
Started Jun 06 02:55:00 PM PDT 24
Finished Jun 06 02:55:45 PM PDT 24
Peak memory 205140 kb
Host smart-5464119c-f0b7-4caa-8781-6c0539191ad8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820427279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_tar
get_smoke.820427279
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2169825582
Short name T1118
Test name
Test status
Simulation time 887061862 ps
CPU time 14.78 seconds
Started Jun 06 02:55:04 PM PDT 24
Finished Jun 06 02:55:26 PM PDT 24
Peak memory 221768 kb
Host smart-bc1b38df-0f36-42f3-b1cb-65a408ead54e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169825582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2169825582
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.3840941643
Short name T512
Test name
Test status
Simulation time 26353838567 ps
CPU time 19.23 seconds
Started Jun 06 02:54:59 PM PDT 24
Finished Jun 06 02:55:24 PM PDT 24
Peak memory 419052 kb
Host smart-5c9d65cb-e774-4f83-a240-c16e628b4e89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840941643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.3840941643
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.3656006539
Short name T289
Test name
Test status
Simulation time 14411151240 ps
CPU time 2094.13 seconds
Started Jun 06 02:55:07 PM PDT 24
Finished Jun 06 03:30:09 PM PDT 24
Peak memory 3474248 kb
Host smart-269f6c06-c604-43a8-965e-b5b94fcff1cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656006539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.3656006539
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1911456714
Short name T765
Test name
Test status
Simulation time 1294518637 ps
CPU time 6.71 seconds
Started Jun 06 02:55:07 PM PDT 24
Finished Jun 06 02:55:21 PM PDT 24
Peak memory 210460 kb
Host smart-b19c4644-b333-40aa-96e0-a41898991747
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911456714 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1911456714
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.191181706
Short name T817
Test name
Test status
Simulation time 1134632903 ps
CPU time 14.67 seconds
Started Jun 06 02:55:10 PM PDT 24
Finished Jun 06 02:55:31 PM PDT 24
Peak memory 205056 kb
Host smart-6e1f4922-0dbe-4346-bb55-3e00ae782a89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191181706 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.191181706
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.35421719
Short name T1344
Test name
Test status
Simulation time 20420468 ps
CPU time 0.66 seconds
Started Jun 06 02:55:20 PM PDT 24
Finished Jun 06 02:55:26 PM PDT 24
Peak memory 204720 kb
Host smart-b4335661-c633-4583-a9bf-d6d128263089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35421719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.35421719
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2151660874
Short name T1445
Test name
Test status
Simulation time 167727519 ps
CPU time 1.8 seconds
Started Jun 06 02:55:08 PM PDT 24
Finished Jun 06 02:55:16 PM PDT 24
Peak memory 213268 kb
Host smart-5bedd454-b6f2-4b32-a8bb-6e6ebeb497b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151660874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2151660874
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1959598543
Short name T838
Test name
Test status
Simulation time 922379252 ps
CPU time 10.14 seconds
Started Jun 06 02:55:10 PM PDT 24
Finished Jun 06 02:55:26 PM PDT 24
Peak memory 303568 kb
Host smart-796505bd-c194-4bf5-b1ec-0c945b382104
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959598543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1959598543
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.997709646
Short name T1194
Test name
Test status
Simulation time 11540063375 ps
CPU time 112.2 seconds
Started Jun 06 02:55:07 PM PDT 24
Finished Jun 06 02:57:06 PM PDT 24
Peak memory 807240 kb
Host smart-bc2d3d56-6252-41f1-ad7f-806f9af44ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997709646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.997709646
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2700832965
Short name T911
Test name
Test status
Simulation time 2728700014 ps
CPU time 78.04 seconds
Started Jun 06 02:55:21 PM PDT 24
Finished Jun 06 02:56:45 PM PDT 24
Peak memory 742936 kb
Host smart-54b334fd-a07b-4303-b519-83b9c8635889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700832965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2700832965
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.3894367673
Short name T1326
Test name
Test status
Simulation time 133264644 ps
CPU time 1.07 seconds
Started Jun 06 02:55:09 PM PDT 24
Finished Jun 06 02:55:17 PM PDT 24
Peak memory 204752 kb
Host smart-cef5097a-cfe7-432c-90e9-04809ec7a853
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894367673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.3894367673
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.4234859931
Short name T121
Test name
Test status
Simulation time 222687331 ps
CPU time 5.37 seconds
Started Jun 06 02:55:07 PM PDT 24
Finished Jun 06 02:55:19 PM PDT 24
Peak memory 246164 kb
Host smart-0451afb3-6b67-44fd-8293-9d5d161d7c9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234859931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.4234859931
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.4283591244
Short name T503
Test name
Test status
Simulation time 4219955972 ps
CPU time 296.37 seconds
Started Jun 06 02:55:09 PM PDT 24
Finished Jun 06 03:00:12 PM PDT 24
Peak memory 1158068 kb
Host smart-a3597a40-bef4-49ab-809b-f09ab12271c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283591244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.4283591244
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1869878303
Short name T1144
Test name
Test status
Simulation time 1698160452 ps
CPU time 7.64 seconds
Started Jun 06 02:55:20 PM PDT 24
Finished Jun 06 02:55:33 PM PDT 24
Peak memory 205004 kb
Host smart-88ef5dc9-5861-4180-bb3d-854ba7b21cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869878303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1869878303
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.1689556073
Short name T584
Test name
Test status
Simulation time 3908076067 ps
CPU time 29.81 seconds
Started Jun 06 02:55:23 PM PDT 24
Finished Jun 06 02:55:58 PM PDT 24
Peak memory 305416 kb
Host smart-b938e929-c0d7-4b69-9d3f-14aa6705c45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689556073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.1689556073
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3487133847
Short name T981
Test name
Test status
Simulation time 29199342 ps
CPU time 0.7 seconds
Started Jun 06 02:55:07 PM PDT 24
Finished Jun 06 02:55:15 PM PDT 24
Peak memory 204900 kb
Host smart-4e7f83f8-7f2e-466b-93cd-9c1ff541ce9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487133847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3487133847
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.2895842771
Short name T1000
Test name
Test status
Simulation time 7381369424 ps
CPU time 163.33 seconds
Started Jun 06 02:55:08 PM PDT 24
Finished Jun 06 02:57:58 PM PDT 24
Peak memory 1273548 kb
Host smart-f882e983-d3a9-48c1-b58a-70540aa78a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895842771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.2895842771
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2246082707
Short name T890
Test name
Test status
Simulation time 7275492874 ps
CPU time 86.58 seconds
Started Jun 06 02:55:10 PM PDT 24
Finished Jun 06 02:56:43 PM PDT 24
Peak memory 367112 kb
Host smart-f7eac914-5800-4feb-af1c-12297cce21b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246082707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2246082707
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.390046168
Short name T248
Test name
Test status
Simulation time 28005449202 ps
CPU time 1653.73 seconds
Started Jun 06 02:55:07 PM PDT 24
Finished Jun 06 03:22:48 PM PDT 24
Peak memory 2168268 kb
Host smart-c18022d0-efab-4bca-ac13-ffa7d46b47e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390046168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.390046168
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.2867440228
Short name T300
Test name
Test status
Simulation time 545054628 ps
CPU time 9.7 seconds
Started Jun 06 02:55:10 PM PDT 24
Finished Jun 06 02:55:26 PM PDT 24
Peak memory 213272 kb
Host smart-71555bed-9f34-41e9-b9ed-116a78fff971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867440228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2867440228
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3585377692
Short name T1049
Test name
Test status
Simulation time 530018854 ps
CPU time 3.23 seconds
Started Jun 06 02:55:23 PM PDT 24
Finished Jun 06 02:55:32 PM PDT 24
Peak memory 205096 kb
Host smart-87627cd0-570f-46a3-8cd2-c825b20e3321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585377692 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3585377692
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.1683012669
Short name T570
Test name
Test status
Simulation time 10349246771 ps
CPU time 12.58 seconds
Started Jun 06 02:55:21 PM PDT 24
Finished Jun 06 02:55:39 PM PDT 24
Peak memory 254952 kb
Host smart-d266f4de-723e-42e3-aea9-fc8c03b3e7b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683012669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.1683012669
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2741890859
Short name T991
Test name
Test status
Simulation time 10728807130 ps
CPU time 11.53 seconds
Started Jun 06 02:55:21 PM PDT 24
Finished Jun 06 02:55:38 PM PDT 24
Peak memory 314920 kb
Host smart-e6ac6d31-e048-41d5-ac8b-a01b347980d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741890859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2741890859
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.3025717230
Short name T314
Test name
Test status
Simulation time 1407124396 ps
CPU time 2.23 seconds
Started Jun 06 02:55:21 PM PDT 24
Finished Jun 06 02:55:29 PM PDT 24
Peak memory 205100 kb
Host smart-7fcf2f55-f01c-4d22-b273-38cd0ad48f53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025717230 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.3025717230
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.1479334867
Short name T749
Test name
Test status
Simulation time 1063934867 ps
CPU time 5.74 seconds
Started Jun 06 02:55:23 PM PDT 24
Finished Jun 06 02:55:34 PM PDT 24
Peak memory 205056 kb
Host smart-eab9f4bf-260a-4c84-9a42-418710f8f144
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479334867 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.1479334867
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2447507507
Short name T598
Test name
Test status
Simulation time 1836292944 ps
CPU time 3.21 seconds
Started Jun 06 02:55:22 PM PDT 24
Finished Jun 06 02:55:31 PM PDT 24
Peak memory 205096 kb
Host smart-ae5e7cdd-0d56-4833-be81-b8f2b7c6ade9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447507507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2447507507
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3314014897
Short name T1034
Test name
Test status
Simulation time 673522178 ps
CPU time 4.49 seconds
Started Jun 06 02:55:09 PM PDT 24
Finished Jun 06 02:55:20 PM PDT 24
Peak memory 205064 kb
Host smart-039098dd-3f6f-4dba-aabb-83da5521c95d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314014897 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3314014897
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3064498312
Short name T1291
Test name
Test status
Simulation time 16063622741 ps
CPU time 217.71 seconds
Started Jun 06 02:55:07 PM PDT 24
Finished Jun 06 02:58:52 PM PDT 24
Peak memory 2443548 kb
Host smart-1c16dbce-cfd2-43dd-8016-4c69adc25967
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064498312 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3064498312
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3100887981
Short name T509
Test name
Test status
Simulation time 10084955806 ps
CPU time 37.08 seconds
Started Jun 06 02:55:10 PM PDT 24
Finished Jun 06 02:55:54 PM PDT 24
Peak memory 205128 kb
Host smart-4670e63d-bdb7-41af-ac6c-8da2580d69c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100887981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3100887981
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1391410211
Short name T1432
Test name
Test status
Simulation time 5247942137 ps
CPU time 57.42 seconds
Started Jun 06 02:55:09 PM PDT 24
Finished Jun 06 02:56:13 PM PDT 24
Peak memory 205756 kb
Host smart-ee3f57a4-2e2c-4e1c-b584-83dcd042bc74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391410211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1391410211
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2210564993
Short name T1386
Test name
Test status
Simulation time 44349228043 ps
CPU time 74.92 seconds
Started Jun 06 02:55:09 PM PDT 24
Finished Jun 06 02:56:31 PM PDT 24
Peak memory 1178864 kb
Host smart-c53cd82e-ec18-40f3-9cf2-0ffc26521f50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210564993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2210564993
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.126769787
Short name T592
Test name
Test status
Simulation time 5723730231 ps
CPU time 27.96 seconds
Started Jun 06 02:55:08 PM PDT 24
Finished Jun 06 02:55:42 PM PDT 24
Peak memory 482540 kb
Host smart-2c985862-ac4a-403f-b9dc-57f0a340c367
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126769787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.126769787
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.34625841
Short name T1403
Test name
Test status
Simulation time 4757283187 ps
CPU time 7.15 seconds
Started Jun 06 02:55:09 PM PDT 24
Finished Jun 06 02:55:23 PM PDT 24
Peak memory 221436 kb
Host smart-3cbf08de-112a-4052-be99-98d7cd6e4253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34625841 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_timeout.34625841
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2266142979
Short name T1175
Test name
Test status
Simulation time 50061157 ps
CPU time 0.64 seconds
Started Jun 06 02:55:36 PM PDT 24
Finished Jun 06 02:55:41 PM PDT 24
Peak memory 204948 kb
Host smart-6cd2bf5e-7942-4d49-91f4-bbf83394b8ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266142979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2266142979
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1236643817
Short name T887
Test name
Test status
Simulation time 270673279 ps
CPU time 10.66 seconds
Started Jun 06 02:55:25 PM PDT 24
Finished Jun 06 02:55:41 PM PDT 24
Peak memory 240052 kb
Host smart-ebffa718-9478-46af-8336-2bb51c131d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236643817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1236643817
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.564729075
Short name T801
Test name
Test status
Simulation time 498172654 ps
CPU time 25.42 seconds
Started Jun 06 02:55:21 PM PDT 24
Finished Jun 06 02:55:51 PM PDT 24
Peak memory 301016 kb
Host smart-ac329663-0153-4882-bdea-70bce064c9d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564729075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empt
y.564729075
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.470882187
Short name T1400
Test name
Test status
Simulation time 2502334331 ps
CPU time 152.02 seconds
Started Jun 06 02:55:21 PM PDT 24
Finished Jun 06 02:57:59 PM PDT 24
Peak memory 577264 kb
Host smart-d1abf8c3-14ed-4f01-9561-02fd6c6e0e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470882187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.470882187
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.2967678987
Short name T1365
Test name
Test status
Simulation time 1812111266 ps
CPU time 55.02 seconds
Started Jun 06 02:55:22 PM PDT 24
Finished Jun 06 02:56:22 PM PDT 24
Peak memory 562176 kb
Host smart-d43692c5-e3c4-42a1-8da0-03a50d8fb934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967678987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.2967678987
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.48852578
Short name T216
Test name
Test status
Simulation time 1640578692 ps
CPU time 0.99 seconds
Started Jun 06 02:55:22 PM PDT 24
Finished Jun 06 02:55:29 PM PDT 24
Peak memory 204784 kb
Host smart-d1337bb2-5ad6-441c-8b46-9afca1997c90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48852578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_fmt
.48852578
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3925973573
Short name T784
Test name
Test status
Simulation time 795037764 ps
CPU time 11.63 seconds
Started Jun 06 02:55:21 PM PDT 24
Finished Jun 06 02:55:38 PM PDT 24
Peak memory 240928 kb
Host smart-eda0e773-3fb5-436b-b0f3-09ef1fd9ec38
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925973573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3925973573
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2779559823
Short name T1055
Test name
Test status
Simulation time 12672564146 ps
CPU time 193.12 seconds
Started Jun 06 02:55:23 PM PDT 24
Finished Jun 06 02:58:41 PM PDT 24
Peak memory 1559508 kb
Host smart-41a26b64-5515-4dad-8201-f8c42e4f4d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779559823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2779559823
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1063993720
Short name T798
Test name
Test status
Simulation time 372568116 ps
CPU time 15.25 seconds
Started Jun 06 02:55:35 PM PDT 24
Finished Jun 06 02:55:55 PM PDT 24
Peak memory 205056 kb
Host smart-d74fa03a-8d5b-48e8-8e4d-778855b2f857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063993720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1063993720
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.1843935870
Short name T29
Test name
Test status
Simulation time 1672638476 ps
CPU time 25.12 seconds
Started Jun 06 02:55:34 PM PDT 24
Finished Jun 06 02:56:03 PM PDT 24
Peak memory 329504 kb
Host smart-6e03e71a-839e-46b6-9894-515b1ce0d488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843935870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.1843935870
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.3914905225
Short name T1155
Test name
Test status
Simulation time 29782079 ps
CPU time 0.68 seconds
Started Jun 06 02:55:20 PM PDT 24
Finished Jun 06 02:55:26 PM PDT 24
Peak memory 204680 kb
Host smart-ce392b56-9fcc-4ae4-aee4-b20f344848bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914905225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3914905225
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.1827453382
Short name T32
Test name
Test status
Simulation time 26957785300 ps
CPU time 1394.51 seconds
Started Jun 06 02:55:23 PM PDT 24
Finished Jun 06 03:18:43 PM PDT 24
Peak memory 2048300 kb
Host smart-37d64670-8216-4a4d-8119-6817a5615708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827453382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1827453382
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2492027973
Short name T141
Test name
Test status
Simulation time 8345131795 ps
CPU time 35.81 seconds
Started Jun 06 02:55:22 PM PDT 24
Finished Jun 06 02:56:04 PM PDT 24
Peak memory 402120 kb
Host smart-0088cefc-fac6-4042-bb7f-49f1f92b53eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492027973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2492027973
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3107595550
Short name T334
Test name
Test status
Simulation time 691791890 ps
CPU time 11.51 seconds
Started Jun 06 02:55:24 PM PDT 24
Finished Jun 06 02:55:41 PM PDT 24
Peak memory 220676 kb
Host smart-cbebf7e7-a059-4e3e-b8da-de1a911f0c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107595550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3107595550
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.3116727043
Short name T1350
Test name
Test status
Simulation time 490139704 ps
CPU time 2.42 seconds
Started Jun 06 02:55:34 PM PDT 24
Finished Jun 06 02:55:41 PM PDT 24
Peak memory 205144 kb
Host smart-f71fdbb7-b484-4578-a322-e62803779ac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116727043 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.3116727043
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2635380398
Short name T1127
Test name
Test status
Simulation time 10906998152 ps
CPU time 3.74 seconds
Started Jun 06 02:55:34 PM PDT 24
Finished Jun 06 02:55:42 PM PDT 24
Peak memory 218768 kb
Host smart-850ef241-fe8e-4ae0-b59e-5f53cf122134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635380398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2635380398
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2964695095
Short name T755
Test name
Test status
Simulation time 10154264310 ps
CPU time 32.17 seconds
Started Jun 06 02:55:33 PM PDT 24
Finished Jun 06 02:56:10 PM PDT 24
Peak memory 371368 kb
Host smart-74d71482-2422-47bf-94dc-cb9f12c6a26c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964695095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2964695095
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.3860811294
Short name T316
Test name
Test status
Simulation time 1501883268 ps
CPU time 3.56 seconds
Started Jun 06 02:55:33 PM PDT 24
Finished Jun 06 02:55:41 PM PDT 24
Peak memory 205008 kb
Host smart-835ffab3-086f-4898-ae0e-8d8c513c68e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860811294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.3860811294
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.1137497130
Short name T1096
Test name
Test status
Simulation time 1056228028 ps
CPU time 6.33 seconds
Started Jun 06 02:55:35 PM PDT 24
Finished Jun 06 02:55:45 PM PDT 24
Peak memory 205020 kb
Host smart-075b53fc-62aa-4bdc-8f3c-6d22b9b18dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137497130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.1137497130
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.1376365521
Short name T483
Test name
Test status
Simulation time 984839940 ps
CPU time 3.21 seconds
Started Jun 06 02:55:32 PM PDT 24
Finished Jun 06 02:55:40 PM PDT 24
Peak memory 205120 kb
Host smart-fc4e73c9-1903-4bcd-b6db-5209eabb6a90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376365521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.1376365521
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.2166079680
Short name T323
Test name
Test status
Simulation time 9217418549 ps
CPU time 5.05 seconds
Started Jun 06 02:55:22 PM PDT 24
Finished Jun 06 02:55:33 PM PDT 24
Peak memory 205204 kb
Host smart-6be37852-ae2e-4674-b5a3-5ed683c3b728
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166079680 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.2166079680
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.2099431917
Short name T1309
Test name
Test status
Simulation time 21532057499 ps
CPU time 60.32 seconds
Started Jun 06 02:55:25 PM PDT 24
Finished Jun 06 02:56:30 PM PDT 24
Peak memory 859696 kb
Host smart-4f36d526-de2b-46a5-8dbc-dc8f251cbb6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099431917 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2099431917
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.544959369
Short name T703
Test name
Test status
Simulation time 5015897374 ps
CPU time 39.89 seconds
Started Jun 06 02:55:23 PM PDT 24
Finished Jun 06 02:56:08 PM PDT 24
Peak memory 205020 kb
Host smart-23c87d60-6dd4-469c-9df1-8f7e58e4107f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544959369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.544959369
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.101210259
Short name T411
Test name
Test status
Simulation time 628926485 ps
CPU time 12.23 seconds
Started Jun 06 02:55:23 PM PDT 24
Finished Jun 06 02:55:41 PM PDT 24
Peak memory 208204 kb
Host smart-cb1e7dab-aa1c-436d-8715-f73af08b2687
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101210259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.101210259
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1168944257
Short name T1130
Test name
Test status
Simulation time 50607318900 ps
CPU time 163.35 seconds
Started Jun 06 02:55:24 PM PDT 24
Finished Jun 06 02:58:12 PM PDT 24
Peak memory 1920324 kb
Host smart-31ef98c2-2b23-4849-bdcb-0ceaf673d917
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168944257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1168944257
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3107751189
Short name T420
Test name
Test status
Simulation time 22878711017 ps
CPU time 202.6 seconds
Started Jun 06 02:55:23 PM PDT 24
Finished Jun 06 02:58:51 PM PDT 24
Peak memory 1797036 kb
Host smart-59c69d67-9e10-4968-8c1d-6d7a2f366f91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107751189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3107751189
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1694906507
Short name T1226
Test name
Test status
Simulation time 2416983433 ps
CPU time 6.88 seconds
Started Jun 06 02:55:24 PM PDT 24
Finished Jun 06 02:55:36 PM PDT 24
Peak memory 218640 kb
Host smart-25e9f95a-85aa-4348-995c-16089d5db5a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694906507 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1694906507
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.456429196
Short name T19
Test name
Test status
Simulation time 1079064541 ps
CPU time 20.1 seconds
Started Jun 06 02:55:38 PM PDT 24
Finished Jun 06 02:56:04 PM PDT 24
Peak memory 205076 kb
Host smart-6433d135-9296-4e5c-8aca-f2cab9b2e173
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456429196 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.456429196
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2966364699
Short name T285
Test name
Test status
Simulation time 56387122 ps
CPU time 0.61 seconds
Started Jun 06 02:55:47 PM PDT 24
Finished Jun 06 02:55:51 PM PDT 24
Peak memory 204716 kb
Host smart-9c24229d-4ca0-40ea-ab37-ef35844fda14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966364699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2966364699
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.3223373430
Short name T1092
Test name
Test status
Simulation time 139742169 ps
CPU time 1.41 seconds
Started Jun 06 02:55:36 PM PDT 24
Finished Jun 06 02:55:43 PM PDT 24
Peak memory 213236 kb
Host smart-61607fe1-b8bd-4835-b5eb-2979df4cce90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223373430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.3223373430
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.2682546825
Short name T1385
Test name
Test status
Simulation time 829795227 ps
CPU time 5.04 seconds
Started Jun 06 02:55:35 PM PDT 24
Finished Jun 06 02:55:44 PM PDT 24
Peak memory 256652 kb
Host smart-207e3e44-7713-47ee-8bff-fc74c4b0f71d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682546825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.2682546825
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.821365612
Short name T871
Test name
Test status
Simulation time 15820034440 ps
CPU time 115.06 seconds
Started Jun 06 02:55:35 PM PDT 24
Finished Jun 06 02:57:34 PM PDT 24
Peak memory 560384 kb
Host smart-3de0c35c-7cbb-4332-9ddd-41804ab387e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821365612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.821365612
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.4213503618
Short name T1453
Test name
Test status
Simulation time 7037105631 ps
CPU time 124.2 seconds
Started Jun 06 02:55:34 PM PDT 24
Finished Jun 06 02:57:43 PM PDT 24
Peak memory 582000 kb
Host smart-ca0de5ec-6628-4e1e-89bd-479a4e3d52e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213503618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.4213503618
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.835929513
Short name T477
Test name
Test status
Simulation time 83359742 ps
CPU time 0.99 seconds
Started Jun 06 02:55:36 PM PDT 24
Finished Jun 06 02:55:41 PM PDT 24
Peak memory 204760 kb
Host smart-9cfe84ff-d922-4766-be9d-10f4c69c1e12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835929513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.835929513
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.3638910519
Short name T510
Test name
Test status
Simulation time 842017793 ps
CPU time 9.87 seconds
Started Jun 06 02:55:35 PM PDT 24
Finished Jun 06 02:55:49 PM PDT 24
Peak memory 204992 kb
Host smart-7b0bdd8e-3e9e-49c6-ac3f-2c3edea2387e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638910519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.3638910519
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.4207802082
Short name T1085
Test name
Test status
Simulation time 5549873132 ps
CPU time 389.18 seconds
Started Jun 06 02:55:39 PM PDT 24
Finished Jun 06 03:02:13 PM PDT 24
Peak memory 1350928 kb
Host smart-f9c3245c-d47b-4704-a842-05d4339362e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207802082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.4207802082
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.4214629517
Short name T1143
Test name
Test status
Simulation time 1105882342 ps
CPU time 23.15 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:25 PM PDT 24
Peak memory 205024 kb
Host smart-36f90f0a-e78b-41b0-8fc0-01e2d583ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214629517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.4214629517
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2945354711
Short name T297
Test name
Test status
Simulation time 2716720342 ps
CPU time 17.81 seconds
Started Jun 06 02:55:48 PM PDT 24
Finished Jun 06 02:56:09 PM PDT 24
Peak memory 262004 kb
Host smart-f51cb350-df7b-4875-a07e-caef0ed7b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945354711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2945354711
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3341074273
Short name T227
Test name
Test status
Simulation time 70130343 ps
CPU time 0.7 seconds
Started Jun 06 02:55:38 PM PDT 24
Finished Jun 06 02:55:44 PM PDT 24
Peak memory 204780 kb
Host smart-ddd0bbaa-59a4-418e-bc61-bebdda4cdf48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341074273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3341074273
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.2036604645
Short name T409
Test name
Test status
Simulation time 17430252698 ps
CPU time 77.74 seconds
Started Jun 06 02:55:35 PM PDT 24
Finished Jun 06 02:56:57 PM PDT 24
Peak memory 559740 kb
Host smart-32e8adfd-f8e0-4a5a-8e4b-75174acf6999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036604645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.2036604645
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3771027017
Short name T636
Test name
Test status
Simulation time 1699521076 ps
CPU time 31.56 seconds
Started Jun 06 02:55:36 PM PDT 24
Finished Jun 06 02:56:13 PM PDT 24
Peak memory 317392 kb
Host smart-ea57ba2c-957c-4b66-956f-81b8d1725074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771027017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3771027017
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.397046217
Short name T9
Test name
Test status
Simulation time 1472752038 ps
CPU time 6.35 seconds
Started Jun 06 02:55:40 PM PDT 24
Finished Jun 06 02:55:51 PM PDT 24
Peak memory 220904 kb
Host smart-372fe330-84be-4500-a4fc-873fc3626b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397046217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.397046217
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.2758974592
Short name T1083
Test name
Test status
Simulation time 1000700354 ps
CPU time 2.87 seconds
Started Jun 06 02:55:40 PM PDT 24
Finished Jun 06 02:55:48 PM PDT 24
Peak memory 205116 kb
Host smart-88eb9b36-7c7e-44a0-a51d-3d7c51b58e7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758974592 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.2758974592
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.3040543913
Short name T1461
Test name
Test status
Simulation time 10765952197 ps
CPU time 8.23 seconds
Started Jun 06 02:55:39 PM PDT 24
Finished Jun 06 02:55:53 PM PDT 24
Peak memory 242388 kb
Host smart-a7dc3442-5a4e-448f-8482-be029130f12b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040543913 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.3040543913
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2426968908
Short name T73
Test name
Test status
Simulation time 10161988289 ps
CPU time 34.6 seconds
Started Jun 06 02:56:12 PM PDT 24
Finished Jun 06 02:56:50 PM PDT 24
Peak memory 456036 kb
Host smart-c1eea13c-622f-4ecc-9324-03b057782cfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426968908 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2426968908
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.842558968
Short name T573
Test name
Test status
Simulation time 1289822379 ps
CPU time 6.6 seconds
Started Jun 06 02:55:45 PM PDT 24
Finished Jun 06 02:55:55 PM PDT 24
Peak memory 205100 kb
Host smart-9bdafc32-220f-4e59-bda3-8fe15f6cda07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842558968 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.842558968
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.871943433
Short name T763
Test name
Test status
Simulation time 1112187556 ps
CPU time 6.17 seconds
Started Jun 06 02:55:45 PM PDT 24
Finished Jun 06 02:55:55 PM PDT 24
Peak memory 205068 kb
Host smart-364dc29f-6138-4aa5-b5e9-218fc0bcad96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871943433 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.871943433
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.2099824025
Short name T731
Test name
Test status
Simulation time 2452835792 ps
CPU time 2.24 seconds
Started Jun 06 02:55:37 PM PDT 24
Finished Jun 06 02:55:44 PM PDT 24
Peak memory 205100 kb
Host smart-35c03f3a-9c2e-415c-9759-48071053aa03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099824025 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.2099824025
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.1740536668
Short name T1311
Test name
Test status
Simulation time 3126964180 ps
CPU time 5.14 seconds
Started Jun 06 02:55:36 PM PDT 24
Finished Jun 06 02:55:45 PM PDT 24
Peak memory 213264 kb
Host smart-22df2d94-4431-491c-8291-8578820e1176
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740536668 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.1740536668
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.521218402
Short name T1181
Test name
Test status
Simulation time 32352234209 ps
CPU time 105.45 seconds
Started Jun 06 02:55:40 PM PDT 24
Finished Jun 06 02:57:30 PM PDT 24
Peak memory 1772708 kb
Host smart-607ce9c9-071b-429d-9575-17e3a24ce128
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521218402 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.521218402
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.160656555
Short name T555
Test name
Test status
Simulation time 813660730 ps
CPU time 11.38 seconds
Started Jun 06 02:55:37 PM PDT 24
Finished Jun 06 02:55:54 PM PDT 24
Peak memory 205056 kb
Host smart-2a6285aa-fd1f-491a-8455-e63fbea2efb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160656555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_tar
get_smoke.160656555
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1476908788
Short name T368
Test name
Test status
Simulation time 7699269903 ps
CPU time 73.65 seconds
Started Jun 06 02:55:39 PM PDT 24
Finished Jun 06 02:56:58 PM PDT 24
Peak memory 209276 kb
Host smart-730a86fa-169a-40ee-ad7a-006ecf45cffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476908788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1476908788
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1319639442
Short name T381
Test name
Test status
Simulation time 24979964739 ps
CPU time 85.86 seconds
Started Jun 06 02:55:39 PM PDT 24
Finished Jun 06 02:57:10 PM PDT 24
Peak memory 1250852 kb
Host smart-d3a2b070-0b33-417f-923c-eee07aa8ccaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319639442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1319639442
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3259760586
Short name T723
Test name
Test status
Simulation time 32395036811 ps
CPU time 1483.86 seconds
Started Jun 06 02:55:35 PM PDT 24
Finished Jun 06 03:20:24 PM PDT 24
Peak memory 3098796 kb
Host smart-88f5a3c3-338b-47c1-9bc7-fac933b52a4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259760586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3259760586
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1404477377
Short name T973
Test name
Test status
Simulation time 6143963278 ps
CPU time 7.43 seconds
Started Jun 06 02:55:36 PM PDT 24
Finished Jun 06 02:55:48 PM PDT 24
Peak memory 221424 kb
Host smart-852df306-05b9-4ce4-85c2-922758b29dd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404477377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1404477377
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.1867532582
Short name T623
Test name
Test status
Simulation time 1042678117 ps
CPU time 17.71 seconds
Started Jun 06 02:55:48 PM PDT 24
Finished Jun 06 02:56:09 PM PDT 24
Peak memory 205048 kb
Host smart-043fd698-228b-48dc-aaaa-56aff7e44e5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867532582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.1867532582
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1407875705
Short name T278
Test name
Test status
Simulation time 18026283 ps
CPU time 0.6 seconds
Started Jun 06 02:55:48 PM PDT 24
Finished Jun 06 02:55:51 PM PDT 24
Peak memory 204700 kb
Host smart-0668f35b-da0d-47c4-8eb8-7455828a7e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407875705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1407875705
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.629003071
Short name T757
Test name
Test status
Simulation time 114485886 ps
CPU time 1.86 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:03 PM PDT 24
Peak memory 213264 kb
Host smart-f51853a2-8494-41c8-99f6-8864d49f3517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629003071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.629003071
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.2789889600
Short name T712
Test name
Test status
Simulation time 854732664 ps
CPU time 11.53 seconds
Started Jun 06 02:55:44 PM PDT 24
Finished Jun 06 02:56:00 PM PDT 24
Peak memory 247472 kb
Host smart-c35219cf-a4a3-4d19-a2f8-ff009fcaa6f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789889600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.2789889600
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.646955360
Short name T1216
Test name
Test status
Simulation time 9296720048 ps
CPU time 90.27 seconds
Started Jun 06 02:55:42 PM PDT 24
Finished Jun 06 02:57:17 PM PDT 24
Peak memory 786308 kb
Host smart-94c9a3f5-028f-4a12-b63e-de7410f31045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646955360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.646955360
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.908247099
Short name T276
Test name
Test status
Simulation time 2696119662 ps
CPU time 47.55 seconds
Started Jun 06 02:55:45 PM PDT 24
Finished Jun 06 02:56:37 PM PDT 24
Peak memory 540712 kb
Host smart-2fd6befa-535d-437a-99f5-3543d6b4f9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908247099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.908247099
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2694558199
Short name T215
Test name
Test status
Simulation time 242267087 ps
CPU time 1.01 seconds
Started Jun 06 02:55:47 PM PDT 24
Finished Jun 06 02:55:52 PM PDT 24
Peak memory 204736 kb
Host smart-2dadccce-01a3-4f91-99b7-dd053b591f0f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694558199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2694558199
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1410711795
Short name T448
Test name
Test status
Simulation time 1365347020 ps
CPU time 4.39 seconds
Started Jun 06 02:55:45 PM PDT 24
Finished Jun 06 02:55:53 PM PDT 24
Peak memory 229360 kb
Host smart-08e17bbf-6a10-4e03-ae9d-df569a36d12b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410711795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1410711795
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.901675164
Short name T987
Test name
Test status
Simulation time 7201308017 ps
CPU time 81.81 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:57:23 PM PDT 24
Peak memory 1013584 kb
Host smart-85d0d1f2-763c-4803-939f-db10cd5eb92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901675164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.901675164
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.1843249747
Short name T1483
Test name
Test status
Simulation time 621272344 ps
CPU time 16.13 seconds
Started Jun 06 02:55:45 PM PDT 24
Finished Jun 06 02:56:05 PM PDT 24
Peak memory 204980 kb
Host smart-1608df2f-e4eb-44f9-a598-46537fd5abbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843249747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.1843249747
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1873445121
Short name T803
Test name
Test status
Simulation time 1591163293 ps
CPU time 28.95 seconds
Started Jun 06 02:55:44 PM PDT 24
Finished Jun 06 02:56:17 PM PDT 24
Peak memory 301768 kb
Host smart-82e9d4bc-26de-4dbd-8988-c068151eeeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873445121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1873445121
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.3131093036
Short name T1382
Test name
Test status
Simulation time 59682376 ps
CPU time 0.66 seconds
Started Jun 06 02:55:43 PM PDT 24
Finished Jun 06 02:55:48 PM PDT 24
Peak memory 204692 kb
Host smart-8b14da0d-73ca-4746-a43e-8e96e6679576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131093036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.3131093036
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2903458614
Short name T1156
Test name
Test status
Simulation time 6879372138 ps
CPU time 218.94 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:59:40 PM PDT 24
Peak memory 1380920 kb
Host smart-cbbd2a7b-15cd-4af8-abff-af06d6c7a724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903458614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2903458614
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3289885037
Short name T1380
Test name
Test status
Simulation time 1880285742 ps
CPU time 42.1 seconds
Started Jun 06 02:55:43 PM PDT 24
Finished Jun 06 02:56:29 PM PDT 24
Peak memory 426796 kb
Host smart-a1ddf11c-93e0-46c6-a9b2-f9326aca24ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289885037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3289885037
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.2289821321
Short name T1188
Test name
Test status
Simulation time 2907137186 ps
CPU time 11.38 seconds
Started Jun 06 02:55:44 PM PDT 24
Finished Jun 06 02:56:00 PM PDT 24
Peak memory 221196 kb
Host smart-6d66e132-a3e7-431b-9353-c39def75d7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289821321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2289821321
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3500397442
Short name T318
Test name
Test status
Simulation time 1230293335 ps
CPU time 3.58 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:05 PM PDT 24
Peak memory 213272 kb
Host smart-7aaeaa44-df9a-4a3d-8851-d96604da1f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500397442 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3500397442
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.1658809317
Short name T457
Test name
Test status
Simulation time 10206799723 ps
CPU time 26.69 seconds
Started Jun 06 02:55:45 PM PDT 24
Finished Jun 06 02:56:16 PM PDT 24
Peak memory 295492 kb
Host smart-9a527771-49b5-499c-b89c-dc16e4e74ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658809317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.1658809317
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.144880541
Short name T795
Test name
Test status
Simulation time 10099543405 ps
CPU time 67.54 seconds
Started Jun 06 02:55:43 PM PDT 24
Finished Jun 06 02:56:55 PM PDT 24
Peak memory 481028 kb
Host smart-71275ebd-81e8-4172-af0c-d031633db929
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144880541 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.i2c_target_fifo_reset_tx.144880541
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.1169347387
Short name T1459
Test name
Test status
Simulation time 1067386494 ps
CPU time 4.82 seconds
Started Jun 06 02:55:46 PM PDT 24
Finished Jun 06 02:55:55 PM PDT 24
Peak memory 205060 kb
Host smart-a343ca69-a0b4-4b1e-8356-b0814606f7eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169347387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.1169347387
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.2955268775
Short name T405
Test name
Test status
Simulation time 1045321258 ps
CPU time 5.57 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:07 PM PDT 24
Peak memory 205024 kb
Host smart-3e49830b-2ed6-4752-b9e3-afb9a99836f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955268775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.2955268775
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.2444067822
Short name T14
Test name
Test status
Simulation time 322936113 ps
CPU time 2.24 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:03 PM PDT 24
Peak memory 205036 kb
Host smart-8032f81b-9709-4802-a987-f4c5f3b3fa91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444067822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.2444067822
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3583384060
Short name T331
Test name
Test status
Simulation time 5685558446 ps
CPU time 3.86 seconds
Started Jun 06 02:55:48 PM PDT 24
Finished Jun 06 02:55:55 PM PDT 24
Peak memory 205132 kb
Host smart-8ac0408c-381d-4723-a760-1a501407598c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583384060 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3583384060
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.354378335
Short name T1278
Test name
Test status
Simulation time 2874185795 ps
CPU time 9.76 seconds
Started Jun 06 02:55:45 PM PDT 24
Finished Jun 06 02:55:59 PM PDT 24
Peak memory 496456 kb
Host smart-18292b04-9221-48ed-a003-c3950316d78c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354378335 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.354378335
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1210738871
Short name T581
Test name
Test status
Simulation time 731206129 ps
CPU time 10.94 seconds
Started Jun 06 02:55:42 PM PDT 24
Finished Jun 06 02:55:57 PM PDT 24
Peak memory 205032 kb
Host smart-111f2561-3a68-4a37-ada2-aef8f3b58d4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210738871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1210738871
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2959037213
Short name T529
Test name
Test status
Simulation time 626643404 ps
CPU time 5.44 seconds
Started Jun 06 02:55:46 PM PDT 24
Finished Jun 06 02:55:55 PM PDT 24
Peak memory 205040 kb
Host smart-78366b71-c5d6-41b1-9cc8-d1b548a7780f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959037213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2959037213
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2705666648
Short name T789
Test name
Test status
Simulation time 12816290236 ps
CPU time 8.04 seconds
Started Jun 06 02:55:48 PM PDT 24
Finished Jun 06 02:56:00 PM PDT 24
Peak memory 205092 kb
Host smart-9e69f35d-2102-4dc4-bd05-2d9f2bdad6ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705666648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2705666648
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.670575686
Short name T111
Test name
Test status
Simulation time 36884382050 ps
CPU time 88.21 seconds
Started Jun 06 02:55:48 PM PDT 24
Finished Jun 06 02:57:20 PM PDT 24
Peak memory 808640 kb
Host smart-dd299ce2-c934-476a-8046-a384e528b738
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670575686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.670575686
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2987386098
Short name T1221
Test name
Test status
Simulation time 1293732811 ps
CPU time 6.99 seconds
Started Jun 06 02:55:48 PM PDT 24
Finished Jun 06 02:55:58 PM PDT 24
Peak memory 216436 kb
Host smart-0b517283-2eb1-4f3b-9df0-967ca90f519e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987386098 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2987386098
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.338465094
Short name T1033
Test name
Test status
Simulation time 1341915683 ps
CPU time 17.91 seconds
Started Jun 06 02:55:48 PM PDT 24
Finished Jun 06 02:56:09 PM PDT 24
Peak memory 205028 kb
Host smart-6fe513d7-2003-4ba3-8438-bfcf284bda49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338465094 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.338465094
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3786192555
Short name T559
Test name
Test status
Simulation time 77717216 ps
CPU time 0.65 seconds
Started Jun 06 02:55:58 PM PDT 24
Finished Jun 06 02:56:03 PM PDT 24
Peak memory 204796 kb
Host smart-8f904d95-ddbe-477c-ab9e-7dec06e61d70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786192555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3786192555
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.2532491087
Short name T1437
Test name
Test status
Simulation time 83690131 ps
CPU time 1.34 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:56:01 PM PDT 24
Peak memory 213328 kb
Host smart-23509938-be3e-457d-bf58-407afcf6e16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532491087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.2532491087
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.1572485731
Short name T1484
Test name
Test status
Simulation time 837799752 ps
CPU time 4.78 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:56:04 PM PDT 24
Peak memory 244420 kb
Host smart-454b9d05-047b-4883-a844-82eaf3ec19c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572485731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.1572485731
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.304881049
Short name T960
Test name
Test status
Simulation time 3239773005 ps
CPU time 282.62 seconds
Started Jun 06 02:55:55 PM PDT 24
Finished Jun 06 03:00:42 PM PDT 24
Peak memory 980180 kb
Host smart-3950a449-6dc4-47a4-ac9c-e1d062a97d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304881049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.304881049
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2860763060
Short name T1374
Test name
Test status
Simulation time 1563512124 ps
CPU time 52.12 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:53 PM PDT 24
Peak memory 575116 kb
Host smart-83e07086-ac12-4825-91a9-674b38d09a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860763060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2860763060
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.4053227791
Short name T1244
Test name
Test status
Simulation time 155062630 ps
CPU time 1.09 seconds
Started Jun 06 02:55:55 PM PDT 24
Finished Jun 06 02:55:59 PM PDT 24
Peak memory 204936 kb
Host smart-278e5df6-e1db-42b6-acf2-129322f37cf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053227791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.4053227791
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3318565325
Short name T85
Test name
Test status
Simulation time 213739916 ps
CPU time 6.61 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:08 PM PDT 24
Peak memory 221888 kb
Host smart-0830693c-700b-43c9-8075-c5071b2b2fb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318565325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3318565325
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1408825636
Short name T1126
Test name
Test status
Simulation time 20050869996 ps
CPU time 95.22 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:57:36 PM PDT 24
Peak memory 1104860 kb
Host smart-685ddc32-369d-41e7-8bf5-78df1718e535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408825636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1408825636
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.975974607
Short name T1158
Test name
Test status
Simulation time 311234326 ps
CPU time 4.81 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:07 PM PDT 24
Peak memory 204992 kb
Host smart-4661b5c6-3d92-4d74-9846-d90054d553bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975974607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.975974607
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.4203804652
Short name T1449
Test name
Test status
Simulation time 4568384926 ps
CPU time 43.97 seconds
Started Jun 06 02:56:01 PM PDT 24
Finished Jun 06 02:56:49 PM PDT 24
Peak memory 401200 kb
Host smart-dd1f393f-9027-4966-aff6-57ffeea2600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203804652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.4203804652
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2237317763
Short name T130
Test name
Test status
Simulation time 56247223 ps
CPU time 0.65 seconds
Started Jun 06 02:55:44 PM PDT 24
Finished Jun 06 02:55:49 PM PDT 24
Peak memory 204728 kb
Host smart-7ca7af94-220e-44f9-ac30-dbd7781a6b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237317763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2237317763
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3780135360
Short name T208
Test name
Test status
Simulation time 30010073968 ps
CPU time 1113.26 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 03:14:35 PM PDT 24
Peak memory 213404 kb
Host smart-595a83c8-5227-41c6-a742-a77b377e25e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780135360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3780135360
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.714456861
Short name T1494
Test name
Test status
Simulation time 6711977654 ps
CPU time 80.86 seconds
Started Jun 06 02:55:46 PM PDT 24
Finished Jun 06 02:57:10 PM PDT 24
Peak memory 384108 kb
Host smart-9bf5db84-1a78-415b-b37b-7d07a9952b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714456861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.714456861
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.3493103170
Short name T251
Test name
Test status
Simulation time 13820763450 ps
CPU time 1507.35 seconds
Started Jun 06 02:55:54 PM PDT 24
Finished Jun 06 03:21:05 PM PDT 24
Peak memory 1770668 kb
Host smart-0f41a295-e209-40f9-8eb3-9c531c8499e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493103170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.3493103170
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.1456489844
Short name T1418
Test name
Test status
Simulation time 1441411044 ps
CPU time 11.55 seconds
Started Jun 06 02:56:00 PM PDT 24
Finished Jun 06 02:56:16 PM PDT 24
Peak memory 221420 kb
Host smart-8faf17ef-6332-4269-a506-ddd23602690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456489844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.1456489844
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1429098345
Short name T122
Test name
Test status
Simulation time 1434445063 ps
CPU time 3.89 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:56:04 PM PDT 24
Peak memory 205092 kb
Host smart-e27afcd7-b0b5-4d57-828f-5ca92cfa605e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429098345 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1429098345
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1018817912
Short name T572
Test name
Test status
Simulation time 10527166306 ps
CPU time 13.34 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:56:13 PM PDT 24
Peak memory 271252 kb
Host smart-1b29c825-ac6f-43b2-8d76-7d51eef155ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018817912 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1018817912
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.738056878
Short name T1422
Test name
Test status
Simulation time 10180119731 ps
CPU time 40.03 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:56:39 PM PDT 24
Peak memory 404668 kb
Host smart-cdf48994-6182-4b02-9785-1fe8d95d8721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738056878 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.738056878
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.1023199726
Short name T239
Test name
Test status
Simulation time 1228411220 ps
CPU time 6.45 seconds
Started Jun 06 02:55:55 PM PDT 24
Finished Jun 06 02:56:05 PM PDT 24
Peak memory 205136 kb
Host smart-97a2a62a-7421-4b34-b9a8-c4638a05cf21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023199726 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.1023199726
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.3980930706
Short name T1433
Test name
Test status
Simulation time 1169348739 ps
CPU time 2.16 seconds
Started Jun 06 02:55:59 PM PDT 24
Finished Jun 06 02:56:05 PM PDT 24
Peak memory 205236 kb
Host smart-7263b427-9f37-48ad-ac26-0bd8228fd1e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980930706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.3980930706
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.1757439053
Short name T982
Test name
Test status
Simulation time 404279209 ps
CPU time 2.73 seconds
Started Jun 06 02:56:03 PM PDT 24
Finished Jun 06 02:56:09 PM PDT 24
Peak memory 204996 kb
Host smart-d7640cd1-97bd-47c6-b40d-1a2979ea0689
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757439053 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.1757439053
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3381905822
Short name T852
Test name
Test status
Simulation time 1152320699 ps
CPU time 6.24 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:56:05 PM PDT 24
Peak memory 207424 kb
Host smart-a83f403b-9c51-4966-99f0-08d6c32757c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381905822 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3381905822
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.4121148479
Short name T484
Test name
Test status
Simulation time 3989266763 ps
CPU time 9.82 seconds
Started Jun 06 02:56:03 PM PDT 24
Finished Jun 06 02:56:16 PM PDT 24
Peak memory 205064 kb
Host smart-b972d1b9-5de3-4ac5-b6a3-006a300a38f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121148479 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.4121148479
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.1555652557
Short name T151
Test name
Test status
Simulation time 3964203714 ps
CPU time 38.74 seconds
Started Jun 06 02:55:59 PM PDT 24
Finished Jun 06 02:56:42 PM PDT 24
Peak memory 205120 kb
Host smart-a56361e4-5d9b-48b4-a362-069db7c9e431
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555652557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.1555652557
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.3210956896
Short name T367
Test name
Test status
Simulation time 4825942601 ps
CPU time 51.32 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:56:51 PM PDT 24
Peak memory 205924 kb
Host smart-15d53f20-9551-41de-8abb-61c9de778b3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210956896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.3210956896
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.711868577
Short name T359
Test name
Test status
Simulation time 32746098741 ps
CPU time 366.22 seconds
Started Jun 06 02:55:58 PM PDT 24
Finished Jun 06 03:02:09 PM PDT 24
Peak memory 3221956 kb
Host smart-7f6d0e04-8ad8-4012-8186-b644f3189ced
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711868577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_wr.711868577
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.4263399406
Short name T1479
Test name
Test status
Simulation time 13484588516 ps
CPU time 216.23 seconds
Started Jun 06 02:55:58 PM PDT 24
Finished Jun 06 02:59:39 PM PDT 24
Peak memory 879344 kb
Host smart-fb0fce7a-e851-463b-b85c-367ea5adcd56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263399406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.4263399406
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.1456663538
Short name T754
Test name
Test status
Simulation time 4873440817 ps
CPU time 7.42 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:56:09 PM PDT 24
Peak memory 221428 kb
Host smart-3b3b76ba-a09d-4372-8cbf-577384322389
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456663538 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.1456663538
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.2016332751
Short name T1387
Test name
Test status
Simulation time 1059776525 ps
CPU time 18.37 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:56:18 PM PDT 24
Peak memory 205112 kb
Host smart-ce08ae14-0012-4842-97e3-fc692b356492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016332751 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.2016332751
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.390899706
Short name T517
Test name
Test status
Simulation time 80079260 ps
CPU time 0.59 seconds
Started Jun 06 02:50:13 PM PDT 24
Finished Jun 06 02:50:15 PM PDT 24
Peak memory 204780 kb
Host smart-931a9df7-f969-44da-9a0a-fa8f0b9b2a59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390899706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.390899706
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.238990797
Short name T1349
Test name
Test status
Simulation time 225038925 ps
CPU time 2.62 seconds
Started Jun 06 02:49:58 PM PDT 24
Finished Jun 06 02:50:01 PM PDT 24
Peak memory 213376 kb
Host smart-2baa7bc5-5153-4fd9-80d1-d99f736788a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238990797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.238990797
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2024978667
Short name T1251
Test name
Test status
Simulation time 513178880 ps
CPU time 26.72 seconds
Started Jun 06 02:49:58 PM PDT 24
Finished Jun 06 02:50:26 PM PDT 24
Peak memory 314740 kb
Host smart-fad0d36e-4fd3-47ec-8089-0d4d0f47e6dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024978667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2024978667
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3830532256
Short name T384
Test name
Test status
Simulation time 4349348027 ps
CPU time 39.51 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:40 PM PDT 24
Peak memory 471708 kb
Host smart-65da3d05-ecca-45aa-a4e5-ccc0a5832a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830532256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3830532256
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.740583453
Short name T853
Test name
Test status
Simulation time 1492160083 ps
CPU time 110.93 seconds
Started Jun 06 02:49:58 PM PDT 24
Finished Jun 06 02:51:50 PM PDT 24
Peak memory 560116 kb
Host smart-a2797e82-9ba3-4ff4-ab2d-d8a351ee4e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740583453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.740583453
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1864856376
Short name T378
Test name
Test status
Simulation time 441773731 ps
CPU time 1.05 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:02 PM PDT 24
Peak memory 204928 kb
Host smart-8d27c6c9-585c-486c-baff-3d6fa02e883a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864856376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1864856376
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2770715622
Short name T322
Test name
Test status
Simulation time 228492287 ps
CPU time 11.39 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:12 PM PDT 24
Peak memory 204952 kb
Host smart-8a8762f4-363b-4064-90fe-0e63111d1b3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770715622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2770715622
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.4257452918
Short name T1131
Test name
Test status
Simulation time 11467884392 ps
CPU time 196.14 seconds
Started Jun 06 02:50:01 PM PDT 24
Finished Jun 06 02:53:18 PM PDT 24
Peak memory 888104 kb
Host smart-eb14f56a-c6bb-4c75-8d09-ab25b80c2635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257452918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.4257452918
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.8382015
Short name T469
Test name
Test status
Simulation time 134296653 ps
CPU time 2.48 seconds
Started Jun 06 02:50:07 PM PDT 24
Finished Jun 06 02:50:11 PM PDT 24
Peak memory 205004 kb
Host smart-6c9dd6ba-8e8a-4f92-9026-0320556312a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8382015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.8382015
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.4258073659
Short name T249
Test name
Test status
Simulation time 6569246318 ps
CPU time 32.21 seconds
Started Jun 06 02:50:08 PM PDT 24
Finished Jun 06 02:50:41 PM PDT 24
Peak memory 378004 kb
Host smart-4c47fd4c-b247-4125-bc6d-01049c42bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258073659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.4258073659
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2009758585
Short name T1282
Test name
Test status
Simulation time 18548086 ps
CPU time 0.65 seconds
Started Jun 06 02:50:01 PM PDT 24
Finished Jun 06 02:50:03 PM PDT 24
Peak memory 204660 kb
Host smart-d38cecd4-6c9f-43a5-8b26-365e9dd33017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009758585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2009758585
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3095039531
Short name T545
Test name
Test status
Simulation time 3640014896 ps
CPU time 23.78 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:24 PM PDT 24
Peak memory 417988 kb
Host smart-363147a3-6c79-4671-adf6-dd56eacd3002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095039531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3095039531
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.1032684558
Short name T993
Test name
Test status
Simulation time 23116539394 ps
CPU time 84.76 seconds
Started Jun 06 02:49:58 PM PDT 24
Finished Jun 06 02:51:24 PM PDT 24
Peak memory 374256 kb
Host smart-b847c636-8270-4ee6-8515-3311ed4520bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032684558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.1032684558
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3626010093
Short name T1057
Test name
Test status
Simulation time 26691617452 ps
CPU time 153.59 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:52:34 PM PDT 24
Peak memory 951668 kb
Host smart-98464abb-2c7c-4c05-9b43-d1cfac5c3feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626010093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3626010093
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.38224370
Short name T417
Test name
Test status
Simulation time 911082731 ps
CPU time 40.84 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:42 PM PDT 24
Peak memory 213268 kb
Host smart-96416923-4f1e-48c4-930c-309bfa782282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38224370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.38224370
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1164527720
Short name T158
Test name
Test status
Simulation time 319699064 ps
CPU time 0.97 seconds
Started Jun 06 02:50:06 PM PDT 24
Finished Jun 06 02:50:08 PM PDT 24
Peak memory 222764 kb
Host smart-9ff095c2-203b-4864-ba3f-33d953e5bf69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164527720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1164527720
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.2678749756
Short name T470
Test name
Test status
Simulation time 724326366 ps
CPU time 3.97 seconds
Started Jun 06 02:50:06 PM PDT 24
Finished Jun 06 02:50:11 PM PDT 24
Peak memory 204520 kb
Host smart-07f39b67-426b-4cc1-a77c-5c0605c9f041
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678749756 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.2678749756
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.4216276485
Short name T882
Test name
Test status
Simulation time 10174236189 ps
CPU time 25.79 seconds
Started Jun 06 02:50:04 PM PDT 24
Finished Jun 06 02:50:31 PM PDT 24
Peak memory 272764 kb
Host smart-1d58a0da-ef29-4594-9679-52484c3ff6df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216276485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.4216276485
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2370152846
Short name T889
Test name
Test status
Simulation time 10090751663 ps
CPU time 65.6 seconds
Started Jun 06 02:50:05 PM PDT 24
Finished Jun 06 02:51:12 PM PDT 24
Peak memory 513920 kb
Host smart-601774f5-8964-4d95-bc0e-2027cb4e491e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370152846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2370152846
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.4117327305
Short name T864
Test name
Test status
Simulation time 5684220643 ps
CPU time 2.21 seconds
Started Jun 06 02:50:07 PM PDT 24
Finished Jun 06 02:50:11 PM PDT 24
Peak memory 205128 kb
Host smart-805b51b5-7ed7-4729-8e09-72685054cdff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117327305 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.4117327305
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.320443376
Short name T1168
Test name
Test status
Simulation time 1101411043 ps
CPU time 2 seconds
Started Jun 06 02:50:07 PM PDT 24
Finished Jun 06 02:50:10 PM PDT 24
Peak memory 205008 kb
Host smart-bf5efb90-4413-413e-83ef-da1257949101
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320443376 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.320443376
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.785270406
Short name T878
Test name
Test status
Simulation time 407610387 ps
CPU time 2.75 seconds
Started Jun 06 02:50:05 PM PDT 24
Finished Jun 06 02:50:09 PM PDT 24
Peak memory 205136 kb
Host smart-38be94a1-c2e2-4de7-bc53-e4e4de8613a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785270406 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.785270406
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3728567302
Short name T682
Test name
Test status
Simulation time 853263945 ps
CPU time 4.73 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:06 PM PDT 24
Peak memory 213252 kb
Host smart-dafb851f-5251-4b79-b7f8-e2e16859d046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728567302 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3728567302
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.715363006
Short name T452
Test name
Test status
Simulation time 13822109519 ps
CPU time 20.57 seconds
Started Jun 06 02:50:04 PM PDT 24
Finished Jun 06 02:50:26 PM PDT 24
Peak memory 475120 kb
Host smart-49f267ab-630e-477d-a318-f67c5956376e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715363006 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.715363006
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3841302381
Short name T1366
Test name
Test status
Simulation time 3493042671 ps
CPU time 38.23 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:39 PM PDT 24
Peak memory 205084 kb
Host smart-3b522b4f-8acf-4b90-899e-9f6ab47c4096
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841302381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3841302381
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1485898677
Short name T1377
Test name
Test status
Simulation time 1539103840 ps
CPU time 12.74 seconds
Started Jun 06 02:49:59 PM PDT 24
Finished Jun 06 02:50:13 PM PDT 24
Peak memory 207228 kb
Host smart-df949c40-ad43-4e25-a78b-7ca65359b3d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485898677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1485898677
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.3482289093
Short name T1481
Test name
Test status
Simulation time 58485822741 ps
CPU time 1687.6 seconds
Started Jun 06 02:49:58 PM PDT 24
Finished Jun 06 03:18:08 PM PDT 24
Peak memory 9340004 kb
Host smart-6db5f433-4929-4668-a68c-2bde4877ce0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482289093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.3482289093
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.777494474
Short name T154
Test name
Test status
Simulation time 25192900119 ps
CPU time 1641.14 seconds
Started Jun 06 02:50:02 PM PDT 24
Finished Jun 06 03:17:25 PM PDT 24
Peak memory 6136272 kb
Host smart-d53ec099-134a-4185-8569-1bbf2e6a91b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777494474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.777494474
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.1798813438
Short name T1325
Test name
Test status
Simulation time 2630604285 ps
CPU time 7.68 seconds
Started Jun 06 02:50:06 PM PDT 24
Finished Jun 06 02:50:15 PM PDT 24
Peak memory 221460 kb
Host smart-50799f16-5e1f-4c62-95ed-246cb136a306
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798813438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.1798813438
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.1965915089
Short name T704
Test name
Test status
Simulation time 1165372440 ps
CPU time 15.9 seconds
Started Jun 06 02:50:06 PM PDT 24
Finished Jun 06 02:50:23 PM PDT 24
Peak memory 205000 kb
Host smart-cc6b72d0-52bb-48e3-85a8-f095cf537ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965915089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.1965915089
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3232411455
Short name T342
Test name
Test status
Simulation time 24882206 ps
CPU time 0.61 seconds
Started Jun 06 02:56:10 PM PDT 24
Finished Jun 06 02:56:14 PM PDT 24
Peak memory 204764 kb
Host smart-3bb876e8-a409-435e-ae1d-c492f653ed6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232411455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3232411455
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.2904129239
Short name T523
Test name
Test status
Simulation time 466642549 ps
CPU time 2.15 seconds
Started Jun 06 02:55:58 PM PDT 24
Finished Jun 06 02:56:05 PM PDT 24
Peak memory 213316 kb
Host smart-45c5a46d-ea45-4bd0-92ba-86a472e3aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904129239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.2904129239
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3703134869
Short name T937
Test name
Test status
Simulation time 798552595 ps
CPU time 9.05 seconds
Started Jun 06 02:55:59 PM PDT 24
Finished Jun 06 02:56:12 PM PDT 24
Peak memory 288560 kb
Host smart-c6f0937f-92e7-4bbe-829a-cc3044269260
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703134869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3703134869
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.37202158
Short name T347
Test name
Test status
Simulation time 1486289947 ps
CPU time 97.24 seconds
Started Jun 06 02:55:58 PM PDT 24
Finished Jun 06 02:57:40 PM PDT 24
Peak memory 524376 kb
Host smart-f3979f9e-5aa1-44f9-ac3c-a942b9188e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37202158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.37202158
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2980015312
Short name T404
Test name
Test status
Simulation time 21185328422 ps
CPU time 125.63 seconds
Started Jun 06 02:55:56 PM PDT 24
Finished Jun 06 02:58:05 PM PDT 24
Peak memory 625140 kb
Host smart-9f3738c3-1ef2-46be-832a-04c78681306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980015312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2980015312
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.482446799
Short name T219
Test name
Test status
Simulation time 222538973 ps
CPU time 1.05 seconds
Started Jun 06 02:56:01 PM PDT 24
Finished Jun 06 02:56:06 PM PDT 24
Peak memory 204892 kb
Host smart-4782c5bc-b531-496c-a267-978897a7034a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482446799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.482446799
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.3501016749
Short name T1305
Test name
Test status
Simulation time 537522405 ps
CPU time 4.03 seconds
Started Jun 06 02:55:59 PM PDT 24
Finished Jun 06 02:56:07 PM PDT 24
Peak memory 226276 kb
Host smart-200bd832-dd2b-4e64-93f0-7e0cdad62fd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501016749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.3501016749
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3760857640
Short name T968
Test name
Test status
Simulation time 15542738267 ps
CPU time 216.28 seconds
Started Jun 06 02:56:02 PM PDT 24
Finished Jun 06 02:59:42 PM PDT 24
Peak memory 903080 kb
Host smart-c65ae0fe-ba45-4cd0-8543-463354103343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760857640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3760857640
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.1046756842
Short name T1277
Test name
Test status
Simulation time 1401919282 ps
CPU time 14.24 seconds
Started Jun 06 02:56:10 PM PDT 24
Finished Jun 06 02:56:28 PM PDT 24
Peak memory 205036 kb
Host smart-e81b05de-146c-47a8-b68f-8d3e54b9736a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046756842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.1046756842
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3878094311
Short name T818
Test name
Test status
Simulation time 7356903000 ps
CPU time 39.56 seconds
Started Jun 06 02:56:06 PM PDT 24
Finished Jun 06 02:56:50 PM PDT 24
Peak memory 332964 kb
Host smart-9785869a-4610-41d2-9b85-1e5b4ebd5f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878094311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3878094311
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.1784453500
Short name T83
Test name
Test status
Simulation time 86521727 ps
CPU time 0.64 seconds
Started Jun 06 02:55:58 PM PDT 24
Finished Jun 06 02:56:03 PM PDT 24
Peak memory 204684 kb
Host smart-2ac24658-0645-4091-96f1-94b832d403db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784453500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.1784453500
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1101281067
Short name T916
Test name
Test status
Simulation time 7194843423 ps
CPU time 28.05 seconds
Started Jun 06 02:55:59 PM PDT 24
Finished Jun 06 02:56:31 PM PDT 24
Peak memory 215792 kb
Host smart-f962a3fa-af23-4c15-82b3-310dc2b41287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101281067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1101281067
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.455189258
Short name T926
Test name
Test status
Simulation time 7182499849 ps
CPU time 83.59 seconds
Started Jun 06 02:55:57 PM PDT 24
Finished Jun 06 02:57:25 PM PDT 24
Peak memory 313036 kb
Host smart-7a289885-3140-49e6-bd24-ebeaaf30082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455189258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.455189258
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.4089407090
Short name T775
Test name
Test status
Simulation time 622159085 ps
CPU time 11.23 seconds
Started Jun 06 02:56:00 PM PDT 24
Finished Jun 06 02:56:15 PM PDT 24
Peak memory 221520 kb
Host smart-7ac6fe10-78a2-404e-a943-6277bba09210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089407090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.4089407090
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.1635219701
Short name T5
Test name
Test status
Simulation time 2252490552 ps
CPU time 2.98 seconds
Started Jun 06 02:56:05 PM PDT 24
Finished Jun 06 02:56:12 PM PDT 24
Peak memory 205224 kb
Host smart-97d590f6-3811-4b39-b89d-8445aaf47ad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635219701 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.1635219701
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.504369298
Short name T75
Test name
Test status
Simulation time 10089841418 ps
CPU time 46.63 seconds
Started Jun 06 02:56:05 PM PDT 24
Finished Jun 06 02:56:56 PM PDT 24
Peak memory 348808 kb
Host smart-f5135b63-4342-4038-a234-b6ee3fd7932e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504369298 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.504369298
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.370099607
Short name T414
Test name
Test status
Simulation time 10849117863 ps
CPU time 7.22 seconds
Started Jun 06 02:56:08 PM PDT 24
Finished Jun 06 02:56:20 PM PDT 24
Peak memory 246160 kb
Host smart-ee974d1f-3298-4c12-bda9-37845f2c2891
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370099607 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.370099607
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.859692477
Short name T1075
Test name
Test status
Simulation time 1459154468 ps
CPU time 6.21 seconds
Started Jun 06 02:56:06 PM PDT 24
Finished Jun 06 02:56:17 PM PDT 24
Peak memory 205032 kb
Host smart-af0f4f8a-0d3e-42d0-b7dc-119fc6939d6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859692477 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.859692477
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.2637975629
Short name T505
Test name
Test status
Simulation time 1144869627 ps
CPU time 5.55 seconds
Started Jun 06 02:56:09 PM PDT 24
Finished Jun 06 02:56:19 PM PDT 24
Peak memory 205140 kb
Host smart-1f158b25-10e2-47f9-bfeb-a0a14cd20ec7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637975629 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.2637975629
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.427856462
Short name T226
Test name
Test status
Simulation time 466009023 ps
CPU time 2.75 seconds
Started Jun 06 02:56:05 PM PDT 24
Finished Jun 06 02:56:12 PM PDT 24
Peak memory 205032 kb
Host smart-f09c159d-8d20-47ec-92c0-1e3f0f05bb8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427856462 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 40.i2c_target_hrst.427856462
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.4049331475
Short name T1339
Test name
Test status
Simulation time 4201242165 ps
CPU time 5.94 seconds
Started Jun 06 02:56:06 PM PDT 24
Finished Jun 06 02:56:16 PM PDT 24
Peak memory 213340 kb
Host smart-80fd4823-7780-4171-832c-f50e3caaf823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049331475 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.4049331475
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.720977478
Short name T1093
Test name
Test status
Simulation time 5108260594 ps
CPU time 52.53 seconds
Started Jun 06 02:56:12 PM PDT 24
Finished Jun 06 02:57:08 PM PDT 24
Peak memory 1354892 kb
Host smart-2e2848ae-e9f7-4539-8836-ab7edb9e279d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720977478 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.720977478
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.1230208757
Short name T149
Test name
Test status
Simulation time 4568897379 ps
CPU time 19.87 seconds
Started Jun 06 02:56:06 PM PDT 24
Finished Jun 06 02:56:31 PM PDT 24
Peak memory 205220 kb
Host smart-83f11cc5-6c18-4e6e-9173-23544149420b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230208757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.1230208757
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2547759284
Short name T872
Test name
Test status
Simulation time 2535326117 ps
CPU time 10.98 seconds
Started Jun 06 02:56:05 PM PDT 24
Finished Jun 06 02:56:21 PM PDT 24
Peak memory 207776 kb
Host smart-14a2d354-70bb-4297-b841-7b5c934b9f9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547759284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2547759284
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.441318814
Short name T1234
Test name
Test status
Simulation time 48635218143 ps
CPU time 136.12 seconds
Started Jun 06 02:56:07 PM PDT 24
Finished Jun 06 02:58:28 PM PDT 24
Peak memory 1756844 kb
Host smart-f0817a22-8f6a-4ff8-83f9-c9160ea4d027
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441318814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.441318814
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.272058507
Short name T603
Test name
Test status
Simulation time 7976597692 ps
CPU time 27.65 seconds
Started Jun 06 02:56:11 PM PDT 24
Finished Jun 06 02:56:42 PM PDT 24
Peak memory 535036 kb
Host smart-610f4d8b-2c9c-4ca1-b8ed-2838c59ffa8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272058507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_t
arget_stretch.272058507
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.856705480
Short name T833
Test name
Test status
Simulation time 2595707041 ps
CPU time 7.32 seconds
Started Jun 06 02:56:06 PM PDT 24
Finished Jun 06 02:56:18 PM PDT 24
Peak memory 213376 kb
Host smart-c1e20f88-227a-48c7-8a92-8eaa5a483935
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856705480 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.856705480
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.806391753
Short name T531
Test name
Test status
Simulation time 1145375999 ps
CPU time 14.88 seconds
Started Jun 06 02:56:09 PM PDT 24
Finished Jun 06 02:56:28 PM PDT 24
Peak memory 205076 kb
Host smart-601ee7bd-6abc-481c-9b0f-be3d9c7ed070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806391753 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.806391753
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.1219074971
Short name T1401
Test name
Test status
Simulation time 20102330 ps
CPU time 0.64 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:56:23 PM PDT 24
Peak memory 204760 kb
Host smart-141f7369-51c6-4cd7-9490-bc7f8de080b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219074971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.1219074971
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.300628258
Short name T408
Test name
Test status
Simulation time 85560740 ps
CPU time 1.3 seconds
Started Jun 06 02:56:11 PM PDT 24
Finished Jun 06 02:56:15 PM PDT 24
Peak memory 213356 kb
Host smart-f8f909a0-4898-4547-9599-2d188e87d23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300628258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.300628258
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.1039710030
Short name T413
Test name
Test status
Simulation time 786098281 ps
CPU time 9.72 seconds
Started Jun 06 02:56:07 PM PDT 24
Finished Jun 06 02:56:21 PM PDT 24
Peak memory 227236 kb
Host smart-feaabd00-b56b-4fbd-af5e-a923277bdad9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039710030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.1039710030
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.1298376807
Short name T1370
Test name
Test status
Simulation time 2065592860 ps
CPU time 142.22 seconds
Started Jun 06 02:56:12 PM PDT 24
Finished Jun 06 02:58:37 PM PDT 24
Peak memory 700392 kb
Host smart-016b20e9-d390-4596-a324-968ffccfb316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298376807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.1298376807
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.874594327
Short name T433
Test name
Test status
Simulation time 1758429864 ps
CPU time 52.33 seconds
Started Jun 06 02:56:10 PM PDT 24
Finished Jun 06 02:57:06 PM PDT 24
Peak memory 608404 kb
Host smart-e5ea91a0-ca52-477b-abe8-b907e9be875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874594327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.874594327
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1842372543
Short name T856
Test name
Test status
Simulation time 691098790 ps
CPU time 1.15 seconds
Started Jun 06 02:56:07 PM PDT 24
Finished Jun 06 02:56:12 PM PDT 24
Peak memory 205000 kb
Host smart-f1b0649f-17b1-4fbe-812c-bb1e7744a800
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842372543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1842372543
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.790866021
Short name T631
Test name
Test status
Simulation time 167762493 ps
CPU time 7.7 seconds
Started Jun 06 02:56:08 PM PDT 24
Finished Jun 06 02:56:20 PM PDT 24
Peak memory 205004 kb
Host smart-2072d335-679b-443f-90b6-8889a3c1011d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790866021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
790866021
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.934321575
Short name T1383
Test name
Test status
Simulation time 10442920561 ps
CPU time 143.77 seconds
Started Jun 06 02:56:06 PM PDT 24
Finished Jun 06 02:58:35 PM PDT 24
Peak memory 1507916 kb
Host smart-807cb94a-6c19-4993-8a42-40a8358a1f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934321575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.934321575
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.418033059
Short name T1074
Test name
Test status
Simulation time 437262975 ps
CPU time 5.37 seconds
Started Jun 06 02:56:20 PM PDT 24
Finished Jun 06 02:56:29 PM PDT 24
Peak memory 205016 kb
Host smart-d724e2ad-8a0e-4611-99a0-7ee3b56a3bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418033059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.418033059
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.2393268286
Short name T1329
Test name
Test status
Simulation time 10842983938 ps
CPU time 15.95 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:56:38 PM PDT 24
Peak memory 256304 kb
Host smart-b1f6c585-6a9a-4c7f-97b0-f45304fd7784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393268286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.2393268286
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.2924531661
Short name T1381
Test name
Test status
Simulation time 50495345 ps
CPU time 0.68 seconds
Started Jun 06 02:56:07 PM PDT 24
Finished Jun 06 02:56:13 PM PDT 24
Peak memory 204684 kb
Host smart-364bba52-8e38-4284-adea-c90014a0bd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924531661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2924531661
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3174107491
Short name T790
Test name
Test status
Simulation time 7178896647 ps
CPU time 545.74 seconds
Started Jun 06 02:56:08 PM PDT 24
Finished Jun 06 03:05:18 PM PDT 24
Peak memory 1334976 kb
Host smart-e905d195-25e1-4e76-a07d-03d2b67b25b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174107491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3174107491
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.1605804491
Short name T727
Test name
Test status
Simulation time 6431255749 ps
CPU time 64.26 seconds
Started Jun 06 02:56:12 PM PDT 24
Finished Jun 06 02:57:19 PM PDT 24
Peak memory 286000 kb
Host smart-cfcc4abc-8501-497f-b750-e6e8bb58454b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605804491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1605804491
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.2158676968
Short name T247
Test name
Test status
Simulation time 33127468546 ps
CPU time 380.82 seconds
Started Jun 06 02:56:11 PM PDT 24
Finished Jun 06 03:02:35 PM PDT 24
Peak memory 1484724 kb
Host smart-12fcd1bc-6cdf-4b76-b780-55586cff1f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158676968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.2158676968
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1235785590
Short name T1298
Test name
Test status
Simulation time 1255091129 ps
CPU time 10.15 seconds
Started Jun 06 02:56:08 PM PDT 24
Finished Jun 06 02:56:23 PM PDT 24
Peak memory 213324 kb
Host smart-adeb5d90-eb61-4978-b5a3-3aa8d1f768cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235785590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1235785590
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.655425968
Short name T1007
Test name
Test status
Simulation time 813834736 ps
CPU time 2.68 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:56:25 PM PDT 24
Peak memory 205108 kb
Host smart-f5846565-8f1d-497e-91a0-27a9d1f40b19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655425968 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.655425968
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.3814186013
Short name T832
Test name
Test status
Simulation time 10246670183 ps
CPU time 8.73 seconds
Started Jun 06 02:56:17 PM PDT 24
Finished Jun 06 02:56:30 PM PDT 24
Peak memory 260680 kb
Host smart-a12e6066-4707-4b2f-bef5-558059b1acdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814186013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.3814186013
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.1411054841
Short name T830
Test name
Test status
Simulation time 2910332682 ps
CPU time 3.1 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:56:25 PM PDT 24
Peak memory 205148 kb
Host smart-c1f85cfd-0b62-495d-9b55-0af38ced1eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411054841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.1411054841
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.2375781466
Short name T1488
Test name
Test status
Simulation time 1028769196 ps
CPU time 5.39 seconds
Started Jun 06 02:56:19 PM PDT 24
Finished Jun 06 02:56:28 PM PDT 24
Peak memory 205124 kb
Host smart-e3cc6c44-64aa-482d-a359-692e59ada7f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375781466 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.2375781466
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.4292019959
Short name T797
Test name
Test status
Simulation time 4995140737 ps
CPU time 2.69 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:56:25 PM PDT 24
Peak memory 205044 kb
Host smart-40d74a6e-9545-4021-88cb-169576057d0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292019959 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.4292019959
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.4188491205
Short name T120
Test name
Test status
Simulation time 3411268273 ps
CPU time 3.41 seconds
Started Jun 06 02:56:07 PM PDT 24
Finished Jun 06 02:56:15 PM PDT 24
Peak memory 205124 kb
Host smart-b0e7dc84-4d55-4fd4-bca3-cbeced70a270
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188491205 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.4188491205
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.4102160839
Short name T612
Test name
Test status
Simulation time 5223642195 ps
CPU time 5.62 seconds
Started Jun 06 02:56:07 PM PDT 24
Finished Jun 06 02:56:17 PM PDT 24
Peak memory 205076 kb
Host smart-09e61f43-76c5-4001-a5b1-55f2b336c36e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102160839 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.4102160839
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.79081200
Short name T116
Test name
Test status
Simulation time 778408181 ps
CPU time 28.7 seconds
Started Jun 06 02:56:09 PM PDT 24
Finished Jun 06 02:56:42 PM PDT 24
Peak memory 205144 kb
Host smart-2a283c2d-ad1a-4b82-8475-a8c91067c6b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79081200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_targ
et_smoke.79081200
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2486313281
Short name T539
Test name
Test status
Simulation time 8964268815 ps
CPU time 20.3 seconds
Started Jun 06 02:56:08 PM PDT 24
Finished Jun 06 02:56:33 PM PDT 24
Peak memory 224500 kb
Host smart-f406cd7b-4266-4d6d-9409-6f84b7886e98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486313281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2486313281
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.4134515578
Short name T694
Test name
Test status
Simulation time 57825337610 ps
CPU time 207.2 seconds
Started Jun 06 02:56:10 PM PDT 24
Finished Jun 06 02:59:41 PM PDT 24
Peak memory 2339708 kb
Host smart-de8eccc6-babe-4929-8522-eef3950a1f10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134515578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.4134515578
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.337300893
Short name T589
Test name
Test status
Simulation time 13549015666 ps
CPU time 182.51 seconds
Started Jun 06 02:56:11 PM PDT 24
Finished Jun 06 02:59:17 PM PDT 24
Peak memory 785556 kb
Host smart-395c746b-9b3c-41ec-9c67-f9cb65ed1727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337300893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.337300893
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.2768484889
Short name T454
Test name
Test status
Simulation time 1181888742 ps
CPU time 6.78 seconds
Started Jun 06 02:56:11 PM PDT 24
Finished Jun 06 02:56:21 PM PDT 24
Peak memory 213364 kb
Host smart-2ea87ff3-b71b-4b07-b1c5-74994eeeb649
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768484889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.2768484889
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.429357446
Short name T809
Test name
Test status
Simulation time 1403644174 ps
CPU time 18.3 seconds
Started Jun 06 02:56:19 PM PDT 24
Finished Jun 06 02:56:41 PM PDT 24
Peak memory 205060 kb
Host smart-b904b95b-2832-4d2e-a968-d96b0e59d896
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429357446 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.429357446
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.928098543
Short name T571
Test name
Test status
Simulation time 17300903 ps
CPU time 0.64 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:36 PM PDT 24
Peak memory 204740 kb
Host smart-bbc9a857-0783-4aee-a980-5b3780d3f743
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928098543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.928098543
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.459749691
Short name T1177
Test name
Test status
Simulation time 350627810 ps
CPU time 2.15 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:56:25 PM PDT 24
Peak memory 213336 kb
Host smart-77d99634-620b-4f73-a67a-0dcb83454361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459749691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.459749691
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3579038403
Short name T841
Test name
Test status
Simulation time 307232385 ps
CPU time 15.22 seconds
Started Jun 06 02:56:17 PM PDT 24
Finished Jun 06 02:56:37 PM PDT 24
Peak memory 246804 kb
Host smart-913346cc-584f-47ff-8f0a-fe7e21e918ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579038403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3579038403
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.3129361555
Short name T1331
Test name
Test status
Simulation time 2577787817 ps
CPU time 81.34 seconds
Started Jun 06 02:56:20 PM PDT 24
Finished Jun 06 02:57:45 PM PDT 24
Peak memory 763680 kb
Host smart-d17199a1-b6ab-404f-b19d-99575c1905e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129361555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.3129361555
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1924901113
Short name T107
Test name
Test status
Simulation time 8890065783 ps
CPU time 80.65 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:57:43 PM PDT 24
Peak memory 710352 kb
Host smart-a852083b-0c9e-41fe-8ff9-4209634e948b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924901113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1924901113
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2622150028
Short name T419
Test name
Test status
Simulation time 485748251 ps
CPU time 0.87 seconds
Started Jun 06 02:56:19 PM PDT 24
Finished Jun 06 02:56:24 PM PDT 24
Peak memory 204796 kb
Host smart-ac84c510-55fe-43f3-8b78-b52bc6466b0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622150028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2622150028
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1266981874
Short name T1384
Test name
Test status
Simulation time 682835617 ps
CPU time 4.14 seconds
Started Jun 06 02:56:16 PM PDT 24
Finished Jun 06 02:56:24 PM PDT 24
Peak memory 205048 kb
Host smart-236d688b-4553-4363-b171-51a29cfbcf7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266981874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1266981874
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2101514826
Short name T1228
Test name
Test status
Simulation time 15899378073 ps
CPU time 299.75 seconds
Started Jun 06 02:56:17 PM PDT 24
Finished Jun 06 03:01:21 PM PDT 24
Peak memory 1132756 kb
Host smart-5b680906-2120-4c72-899a-b8d4d173dddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101514826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2101514826
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.3170773294
Short name T997
Test name
Test status
Simulation time 1660092904 ps
CPU time 16.88 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:53 PM PDT 24
Peak memory 205060 kb
Host smart-169bf2c9-bfaf-4609-ad01-37782392794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170773294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.3170773294
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.2380134204
Short name T651
Test name
Test status
Simulation time 7991305873 ps
CPU time 33.36 seconds
Started Jun 06 02:56:34 PM PDT 24
Finished Jun 06 02:57:10 PM PDT 24
Peak memory 291928 kb
Host smart-856e242d-418e-4e47-90ae-036bdd30cec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380134204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.2380134204
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.2414574070
Short name T65
Test name
Test status
Simulation time 84065738 ps
CPU time 0.67 seconds
Started Jun 06 02:56:19 PM PDT 24
Finished Jun 06 02:56:24 PM PDT 24
Peak memory 204664 kb
Host smart-14ebb0c6-202c-4afe-a21d-06c802227376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414574070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.2414574070
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.1311681969
Short name T941
Test name
Test status
Simulation time 6797264047 ps
CPU time 71.71 seconds
Started Jun 06 02:56:16 PM PDT 24
Finished Jun 06 02:57:33 PM PDT 24
Peak memory 415364 kb
Host smart-ee83f306-888f-42b2-8a8f-9fddbfb7fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311681969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.1311681969
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.2258287264
Short name T254
Test name
Test status
Simulation time 32690113520 ps
CPU time 1198.48 seconds
Started Jun 06 02:56:17 PM PDT 24
Finished Jun 06 03:16:21 PM PDT 24
Peak memory 3221044 kb
Host smart-0c67b21c-97e6-4aa8-abf1-42efd4010e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258287264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2258287264
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1468152166
Short name T626
Test name
Test status
Simulation time 754967278 ps
CPU time 14.48 seconds
Started Jun 06 02:56:19 PM PDT 24
Finished Jun 06 02:56:38 PM PDT 24
Peak memory 215172 kb
Host smart-ed7519e1-6400-4fca-a526-e192aafd1bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468152166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1468152166
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2006236806
Short name T1063
Test name
Test status
Simulation time 817955668 ps
CPU time 2.53 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:36 PM PDT 24
Peak memory 205308 kb
Host smart-5e773735-a2d7-48dd-862f-2ecd92d405b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006236806 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2006236806
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.2094420741
Short name T210
Test name
Test status
Simulation time 10129818994 ps
CPU time 45 seconds
Started Jun 06 02:56:17 PM PDT 24
Finished Jun 06 02:57:06 PM PDT 24
Peak memory 348732 kb
Host smart-7a749269-b238-40b6-bdfc-c535d79e3a2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094420741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.2094420741
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.959578688
Short name T1342
Test name
Test status
Simulation time 10103069253 ps
CPU time 65.75 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:57:40 PM PDT 24
Peak memory 485016 kb
Host smart-e4571e49-e1a8-468d-aea8-9a0b7e98037b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959578688 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.959578688
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.1566600859
Short name T1393
Test name
Test status
Simulation time 1553612344 ps
CPU time 2.36 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:35 PM PDT 24
Peak memory 205084 kb
Host smart-9bf9d04e-c5fa-434e-b507-8316b5dfda5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566600859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1566600859
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.2515791440
Short name T1087
Test name
Test status
Simulation time 1048109746 ps
CPU time 1.9 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:37 PM PDT 24
Peak memory 205092 kb
Host smart-5a730ed9-453e-4aa8-a4d1-12cea91d8f2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515791440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.2515791440
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.4189804474
Short name T827
Test name
Test status
Simulation time 306818987 ps
CPU time 1.95 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:35 PM PDT 24
Peak memory 205052 kb
Host smart-7b31e7b8-47f5-41b9-9fa1-7eb907bca0a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189804474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.4189804474
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.1549234739
Short name T1084
Test name
Test status
Simulation time 5625727685 ps
CPU time 6.63 seconds
Started Jun 06 02:56:17 PM PDT 24
Finished Jun 06 02:56:28 PM PDT 24
Peak memory 219264 kb
Host smart-61dd390e-4a70-437a-af9b-988554177f1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549234739 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.1549234739
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.2319078969
Short name T645
Test name
Test status
Simulation time 20510930713 ps
CPU time 153.41 seconds
Started Jun 06 02:56:19 PM PDT 24
Finished Jun 06 02:58:56 PM PDT 24
Peak memory 2358524 kb
Host smart-2a6ee958-f539-44ea-b346-67c111237965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319078969 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.2319078969
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1578706558
Short name T153
Test name
Test status
Simulation time 861318038 ps
CPU time 13.87 seconds
Started Jun 06 02:56:19 PM PDT 24
Finished Jun 06 02:56:37 PM PDT 24
Peak memory 205104 kb
Host smart-851eadc3-7e9f-43c4-b867-7fb12cd24e4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578706558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1578706558
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.3876067613
Short name T277
Test name
Test status
Simulation time 3697614676 ps
CPU time 30.71 seconds
Started Jun 06 02:56:17 PM PDT 24
Finished Jun 06 02:56:52 PM PDT 24
Peak memory 236316 kb
Host smart-b4df335e-ebff-4fc2-a6b6-e9e42216e5e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876067613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.3876067613
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.3220753766
Short name T268
Test name
Test status
Simulation time 13185433536 ps
CPU time 8 seconds
Started Jun 06 02:56:20 PM PDT 24
Finished Jun 06 02:56:32 PM PDT 24
Peak memory 205280 kb
Host smart-e3d3e38b-81e8-4d28-a5da-f6afbd15b92a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220753766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.3220753766
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.4249059462
Short name T766
Test name
Test status
Simulation time 5077645954 ps
CPU time 124.3 seconds
Started Jun 06 02:56:19 PM PDT 24
Finished Jun 06 02:58:28 PM PDT 24
Peak memory 1300748 kb
Host smart-e0bcff20-69fe-415d-bc66-4a7fe8fb46fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249059462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.4249059462
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.489813625
Short name T1022
Test name
Test status
Simulation time 13339220162 ps
CPU time 7.33 seconds
Started Jun 06 02:56:18 PM PDT 24
Finished Jun 06 02:56:29 PM PDT 24
Peak memory 220488 kb
Host smart-4463abcf-5bd9-471d-8435-8a9981eae9c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489813625 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_timeout.489813625
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.2788791863
Short name T994
Test name
Test status
Simulation time 1244401810 ps
CPU time 16.58 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:49 PM PDT 24
Peak memory 205060 kb
Host smart-8b9439f1-8913-44bc-8a3b-526b2ad36539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788791863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.2788791863
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3473951741
Short name T769
Test name
Test status
Simulation time 17827785 ps
CPU time 0.61 seconds
Started Jun 06 02:56:41 PM PDT 24
Finished Jun 06 02:56:44 PM PDT 24
Peak memory 204708 kb
Host smart-ce1b4706-2eb4-4355-a40a-f8d5adb93914
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473951741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3473951741
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1010716642
Short name T1208
Test name
Test status
Simulation time 552773158 ps
CPU time 1.64 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:37 PM PDT 24
Peak memory 213304 kb
Host smart-429a8551-2c66-48f8-a6d4-018f49a1e9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010716642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1010716642
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.3407458681
Short name T336
Test name
Test status
Simulation time 2678064785 ps
CPU time 7.36 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:41 PM PDT 24
Peak memory 277280 kb
Host smart-ff0acbc1-0259-44a6-bbbb-2145ec9a8071
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407458681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.3407458681
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1765287834
Short name T344
Test name
Test status
Simulation time 3484507046 ps
CPU time 126.36 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:58:42 PM PDT 24
Peak memory 630660 kb
Host smart-abc3449f-6302-423d-acd7-3f09164c3896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765287834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1765287834
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2974775747
Short name T134
Test name
Test status
Simulation time 1425914546 ps
CPU time 107.52 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:58:23 PM PDT 24
Peak memory 555896 kb
Host smart-705663a6-d5df-4241-b07a-215fcd4ebb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974775747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2974775747
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2232682527
Short name T930
Test name
Test status
Simulation time 253761766 ps
CPU time 1.05 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:37 PM PDT 24
Peak memory 204960 kb
Host smart-48df9d8a-fbb5-4994-9ec8-12b361cfddbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232682527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2232682527
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1786091871
Short name T1345
Test name
Test status
Simulation time 327449994 ps
CPU time 3.72 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:39 PM PDT 24
Peak memory 205076 kb
Host smart-b11f49a4-576f-40a8-92ce-bb12a268722c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786091871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1786091871
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.966906523
Short name T1160
Test name
Test status
Simulation time 3585698981 ps
CPU time 91.71 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:58:06 PM PDT 24
Peak memory 1053900 kb
Host smart-5a490487-b669-4fda-9ef6-9b2d40a1830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966906523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.966906523
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3853981755
Short name T618
Test name
Test status
Simulation time 1603660939 ps
CPU time 6.75 seconds
Started Jun 06 02:56:30 PM PDT 24
Finished Jun 06 02:56:38 PM PDT 24
Peak memory 205224 kb
Host smart-636a6e77-94f0-4dfc-b6fb-d56c181cd8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853981755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3853981755
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3489580498
Short name T1132
Test name
Test status
Simulation time 5266828233 ps
CPU time 55.49 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:57:30 PM PDT 24
Peak memory 470480 kb
Host smart-d2a37fe1-fdde-40d9-8f6b-66901e501e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489580498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3489580498
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.949166462
Short name T1442
Test name
Test status
Simulation time 100779189 ps
CPU time 0.63 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:36 PM PDT 24
Peak memory 204712 kb
Host smart-8c422132-a1f3-4eca-a8e3-b23049b25632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949166462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.949166462
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.278221541
Short name T1368
Test name
Test status
Simulation time 936197993 ps
CPU time 7.74 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:41 PM PDT 24
Peak memory 214656 kb
Host smart-5f7b4a50-0841-4f35-ad3a-8dfdaf0dbbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278221541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.278221541
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.2594288010
Short name T459
Test name
Test status
Simulation time 12669583306 ps
CPU time 32.31 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:57:07 PM PDT 24
Peak memory 329040 kb
Host smart-3b4bfc0b-8d6f-466f-9561-c7943fc642d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594288010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.2594288010
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.1709216674
Short name T813
Test name
Test status
Simulation time 88402927126 ps
CPU time 1453.69 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 03:20:50 PM PDT 24
Peak memory 2434160 kb
Host smart-4f1f0b0f-b576-4bcf-ae00-3854394ce61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709216674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.1709216674
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.3919517360
Short name T992
Test name
Test status
Simulation time 786123427 ps
CPU time 14.48 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:56:49 PM PDT 24
Peak memory 218568 kb
Host smart-0a883c01-ae7c-4df2-a563-b3b4de202f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919517360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.3919517360
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.622459896
Short name T25
Test name
Test status
Simulation time 1807059061 ps
CPU time 4.62 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:41 PM PDT 24
Peak memory 205320 kb
Host smart-14071ab9-2ebd-47ed-986e-acd05d9d7511
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622459896 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.622459896
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.1358557575
Short name T1416
Test name
Test status
Simulation time 10242109182 ps
CPU time 25.21 seconds
Started Jun 06 02:56:30 PM PDT 24
Finished Jun 06 02:56:56 PM PDT 24
Peak memory 289080 kb
Host smart-8505cdc5-0872-4f09-b685-d31992b22621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358557575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.1358557575
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.316428307
Short name T428
Test name
Test status
Simulation time 10117510395 ps
CPU time 64.67 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:57:38 PM PDT 24
Peak memory 478060 kb
Host smart-0e2769ca-3994-4dcd-aab5-bae81bdcd789
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316428307 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.i2c_target_fifo_reset_tx.316428307
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.2286956922
Short name T548
Test name
Test status
Simulation time 1250514200 ps
CPU time 6.66 seconds
Started Jun 06 02:56:43 PM PDT 24
Finished Jun 06 02:56:52 PM PDT 24
Peak memory 205088 kb
Host smart-79875c2f-930f-4c7d-a0d8-baf8474c958d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286956922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.2286956922
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.3910278317
Short name T848
Test name
Test status
Simulation time 1056978159 ps
CPU time 5.49 seconds
Started Jun 06 02:56:42 PM PDT 24
Finished Jun 06 02:56:49 PM PDT 24
Peak memory 205008 kb
Host smart-fbc246c9-9074-437f-9a6c-dedb529d8b31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910278317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.3910278317
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.1118312899
Short name T366
Test name
Test status
Simulation time 413266155 ps
CPU time 2.73 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:56:38 PM PDT 24
Peak memory 205108 kb
Host smart-8ab94ef2-8c64-4af0-bff0-16dbb92aa084
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118312899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.1118312899
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.312682738
Short name T662
Test name
Test status
Simulation time 3128492133 ps
CPU time 8.79 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:56:43 PM PDT 24
Peak memory 220136 kb
Host smart-394f8f26-1f48-4af3-82ce-854b30a7b020
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312682738 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.312682738
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2612623855
Short name T237
Test name
Test status
Simulation time 7289389065 ps
CPU time 9.96 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:42 PM PDT 24
Peak memory 205172 kb
Host smart-cb17fa59-0534-42f6-a703-1233405323fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612623855 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2612623855
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1329729369
Short name T464
Test name
Test status
Simulation time 473734163 ps
CPU time 6.08 seconds
Started Jun 06 02:56:33 PM PDT 24
Finished Jun 06 02:56:41 PM PDT 24
Peak memory 205068 kb
Host smart-c72aefbc-0f98-4342-a20a-01ca12714259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329729369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1329729369
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3443366849
Short name T1267
Test name
Test status
Simulation time 4550474870 ps
CPU time 19.35 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:56:54 PM PDT 24
Peak memory 217000 kb
Host smart-e45fbb6a-16a1-45a6-b049-c612e592bfab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443366849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3443366849
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2656439341
Short name T1026
Test name
Test status
Simulation time 7836910314 ps
CPU time 7.87 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:42 PM PDT 24
Peak memory 205156 kb
Host smart-ec858aef-d23e-4d78-9676-105a6d5cf3a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656439341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2656439341
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.422748472
Short name T632
Test name
Test status
Simulation time 13866593775 ps
CPU time 120.69 seconds
Started Jun 06 02:56:32 PM PDT 24
Finished Jun 06 02:58:34 PM PDT 24
Peak memory 1158456 kb
Host smart-e8e3971d-c3f4-4ea1-8423-d2adf030a210
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422748472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_t
arget_stretch.422748472
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.4218161209
Short name T825
Test name
Test status
Simulation time 5687701306 ps
CPU time 8.19 seconds
Started Jun 06 02:56:31 PM PDT 24
Finished Jun 06 02:56:42 PM PDT 24
Peak memory 221452 kb
Host smart-a1af0c46-a1a7-4f87-b497-b909235b22d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218161209 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.4218161209
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.4163113433
Short name T385
Test name
Test status
Simulation time 1040129106 ps
CPU time 19.38 seconds
Started Jun 06 02:56:43 PM PDT 24
Finished Jun 06 02:57:05 PM PDT 24
Peak memory 205072 kb
Host smart-e6532546-4ea5-4ff9-84fc-95c8804a1f21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163113433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.4163113433
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1048283584
Short name T1069
Test name
Test status
Simulation time 17063648 ps
CPU time 0.63 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:57:28 PM PDT 24
Peak memory 204712 kb
Host smart-d02e8532-ee8d-49cf-8b99-c35ab5e011e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048283584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1048283584
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.4271508731
Short name T599
Test name
Test status
Simulation time 871899501 ps
CPU time 1.85 seconds
Started Jun 06 02:56:54 PM PDT 24
Finished Jun 06 02:56:58 PM PDT 24
Peak memory 213352 kb
Host smart-a36fc68d-0747-4ded-b20b-ab6772671769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271508731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.4271508731
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.501781007
Short name T699
Test name
Test status
Simulation time 3835214907 ps
CPU time 19.93 seconds
Started Jun 06 02:56:53 PM PDT 24
Finished Jun 06 02:57:15 PM PDT 24
Peak memory 281568 kb
Host smart-57eebaeb-762b-4e12-acd3-aec4f700c1e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501781007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.501781007
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3460126146
Short name T748
Test name
Test status
Simulation time 8162293825 ps
CPU time 42.36 seconds
Started Jun 06 02:56:53 PM PDT 24
Finished Jun 06 02:57:37 PM PDT 24
Peak memory 379764 kb
Host smart-3bfa3bdb-7b26-4e2d-8e0f-aab122936ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460126146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3460126146
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.3693088179
Short name T1257
Test name
Test status
Simulation time 23357126291 ps
CPU time 69.92 seconds
Started Jun 06 02:56:53 PM PDT 24
Finished Jun 06 02:58:05 PM PDT 24
Peak memory 730560 kb
Host smart-aad78946-1e69-4824-b2bd-d66454c1f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693088179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.3693088179
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2406972459
Short name T1373
Test name
Test status
Simulation time 111597090 ps
CPU time 0.95 seconds
Started Jun 06 02:56:52 PM PDT 24
Finished Jun 06 02:56:54 PM PDT 24
Peak memory 204772 kb
Host smart-b42a27ec-fbd6-4684-89b4-b3544082164f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406972459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2406972459
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.2313858845
Short name T146
Test name
Test status
Simulation time 221076496 ps
CPU time 12.23 seconds
Started Jun 06 02:56:53 PM PDT 24
Finished Jun 06 02:57:06 PM PDT 24
Peak memory 245080 kb
Host smart-0a8b874b-9bb7-4593-9a37-b03febdb68ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313858845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.2313858845
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2050089705
Short name T520
Test name
Test status
Simulation time 12745217715 ps
CPU time 232.21 seconds
Started Jun 06 02:56:53 PM PDT 24
Finished Jun 06 03:00:47 PM PDT 24
Peak memory 993988 kb
Host smart-8a4196d9-26d5-446e-8bd2-b1a7c14d2905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050089705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2050089705
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3423732193
Short name T776
Test name
Test status
Simulation time 308003756 ps
CPU time 3.95 seconds
Started Jun 06 02:57:11 PM PDT 24
Finished Jun 06 02:57:19 PM PDT 24
Peak memory 204972 kb
Host smart-406a0fe6-9f38-4348-a56e-d125a31e7022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423732193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3423732193
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3339072565
Short name T1337
Test name
Test status
Simulation time 1524002863 ps
CPU time 22.41 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:57:35 PM PDT 24
Peak memory 314624 kb
Host smart-2853bfb5-484c-44a5-98f8-8d07e4d7ed1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339072565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3339072565
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2318370699
Short name T984
Test name
Test status
Simulation time 191302328 ps
CPU time 0.67 seconds
Started Jun 06 02:56:42 PM PDT 24
Finished Jun 06 02:56:45 PM PDT 24
Peak memory 204792 kb
Host smart-89ba2b8c-2307-43fd-8cb9-de5570574840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318370699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2318370699
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.954333193
Short name T338
Test name
Test status
Simulation time 1603366629 ps
CPU time 31.52 seconds
Started Jun 06 02:56:43 PM PDT 24
Finished Jun 06 02:57:16 PM PDT 24
Peak memory 334340 kb
Host smart-f26711b3-1f86-4340-bc43-8956871e1987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954333193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.954333193
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.22575384
Short name T112
Test name
Test status
Simulation time 14285569009 ps
CPU time 685.51 seconds
Started Jun 06 02:56:54 PM PDT 24
Finished Jun 06 03:08:21 PM PDT 24
Peak memory 2153748 kb
Host smart-ff7d40e5-847f-4a28-9e05-5d49e64de7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22575384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.22575384
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.2029473933
Short name T406
Test name
Test status
Simulation time 1338819970 ps
CPU time 30.48 seconds
Started Jun 06 02:56:52 PM PDT 24
Finished Jun 06 02:57:24 PM PDT 24
Peak memory 213300 kb
Host smart-ffb41b10-8f67-4e4b-809a-6e6f9c8cb57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029473933 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.2029473933
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.2166349985
Short name T1079
Test name
Test status
Simulation time 864385230 ps
CPU time 4.17 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:57:18 PM PDT 24
Peak memory 213364 kb
Host smart-d294ab3c-5687-49ce-b7b1-2a4d64b91e8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166349985 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.2166349985
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.3660825734
Short name T616
Test name
Test status
Simulation time 11180955933 ps
CPU time 4.08 seconds
Started Jun 06 02:57:11 PM PDT 24
Finished Jun 06 02:57:19 PM PDT 24
Peak memory 213820 kb
Host smart-daac2302-5bb9-406f-8384-45f1ab35e10f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660825734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.3660825734
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1828285476
Short name T1031
Test name
Test status
Simulation time 10940187875 ps
CPU time 8.67 seconds
Started Jun 06 02:57:08 PM PDT 24
Finished Jun 06 02:57:19 PM PDT 24
Peak memory 276528 kb
Host smart-919c9468-2862-4d1f-a3dd-13c6f6001eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828285476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1828285476
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.646481021
Short name T421
Test name
Test status
Simulation time 1836755247 ps
CPU time 3.19 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:57:17 PM PDT 24
Peak memory 205096 kb
Host smart-a6a0259d-a07d-43bc-bc19-1d5fc0a0534c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646481021 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.646481021
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.2033012488
Short name T441
Test name
Test status
Simulation time 1062971462 ps
CPU time 5.31 seconds
Started Jun 06 02:57:08 PM PDT 24
Finished Jun 06 02:57:16 PM PDT 24
Peak memory 205144 kb
Host smart-979aa18f-626b-447a-a970-bad791e51267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033012488 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.2033012488
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.3908494404
Short name T1205
Test name
Test status
Simulation time 1729453453 ps
CPU time 3.1 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:57:17 PM PDT 24
Peak memory 205088 kb
Host smart-3c26945d-e30c-4a9c-9b09-2bb54f4e8158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908494404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.3908494404
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3563596678
Short name T105
Test name
Test status
Simulation time 3801685382 ps
CPU time 3.89 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:57:17 PM PDT 24
Peak memory 206612 kb
Host smart-0a710e11-e486-4d96-9970-406c7ed842c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563596678 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3563596678
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3814634243
Short name T21
Test name
Test status
Simulation time 16793994211 ps
CPU time 61.07 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:58:15 PM PDT 24
Peak memory 999924 kb
Host smart-e836859d-226d-4bd4-9296-2620a978bd3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814634243 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3814634243
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2100551061
Short name T1151
Test name
Test status
Simulation time 8334498156 ps
CPU time 29.58 seconds
Started Jun 06 02:56:56 PM PDT 24
Finished Jun 06 02:57:28 PM PDT 24
Peak memory 205112 kb
Host smart-01a5fa69-f80d-40ee-ab0e-21d4d6ee9e20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100551061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2100551061
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.3022210086
Short name T410
Test name
Test status
Simulation time 14101885112 ps
CPU time 27.77 seconds
Started Jun 06 02:56:55 PM PDT 24
Finished Jun 06 02:57:25 PM PDT 24
Peak memory 223732 kb
Host smart-f94c6b70-3be8-478e-a7b6-17e072f822bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022210086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.3022210086
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2634232178
Short name T733
Test name
Test status
Simulation time 62239349799 ps
CPU time 87.29 seconds
Started Jun 06 02:56:55 PM PDT 24
Finished Jun 06 02:58:24 PM PDT 24
Peak memory 1212324 kb
Host smart-48082ad6-0092-411e-bdac-4a5b16c50aeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634232178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2634232178
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1692534946
Short name T661
Test name
Test status
Simulation time 6368566900 ps
CPU time 4.5 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:57:19 PM PDT 24
Peak memory 222612 kb
Host smart-33d5c478-27f6-4a37-8af0-1b6a531c1bb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692534946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1692534946
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1919178915
Short name T498
Test name
Test status
Simulation time 2692656989 ps
CPU time 7.88 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:57:21 PM PDT 24
Peak memory 216988 kb
Host smart-9e7fe8d3-4616-4cf5-833d-ef85acbcc2dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919178915 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1919178915
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3423146657
Short name T422
Test name
Test status
Simulation time 1058482775 ps
CPU time 19.75 seconds
Started Jun 06 02:57:09 PM PDT 24
Finished Jun 06 02:57:32 PM PDT 24
Peak memory 205064 kb
Host smart-f85ef9a0-5852-4c64-9faf-e7c7a635d485
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423146657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3423146657
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.914235515
Short name T320
Test name
Test status
Simulation time 17435429 ps
CPU time 0.63 seconds
Started Jun 06 02:57:22 PM PDT 24
Finished Jun 06 02:57:27 PM PDT 24
Peak memory 204704 kb
Host smart-d75688ff-75f1-4335-bbc4-23134dde914c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914235515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.914235515
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3396593689
Short name T693
Test name
Test status
Simulation time 996424191 ps
CPU time 3.9 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:57:32 PM PDT 24
Peak memory 232632 kb
Host smart-18d36b5b-2b85-4115-b801-8591b1dcee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396593689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3396593689
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3225127297
Short name T291
Test name
Test status
Simulation time 463035579 ps
CPU time 9.11 seconds
Started Jun 06 02:57:22 PM PDT 24
Finished Jun 06 02:57:34 PM PDT 24
Peak memory 270236 kb
Host smart-5fae7eb2-2a68-4884-bfd0-7d391d749efe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225127297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3225127297
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.3404816621
Short name T1123
Test name
Test status
Simulation time 2766062067 ps
CPU time 111.22 seconds
Started Jun 06 02:57:22 PM PDT 24
Finished Jun 06 02:59:17 PM PDT 24
Peak memory 887592 kb
Host smart-917a7678-f3c0-4197-9a98-00e912da9c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404816621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.3404816621
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.1581840292
Short name T877
Test name
Test status
Simulation time 1972116610 ps
CPU time 125.12 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:59:34 PM PDT 24
Peak memory 611300 kb
Host smart-acc1a19e-3338-4ee6-8d66-bcd8fc59c87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581840292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.1581840292
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.102580384
Short name T806
Test name
Test status
Simulation time 137551907 ps
CPU time 1.03 seconds
Started Jun 06 02:57:22 PM PDT 24
Finished Jun 06 02:57:26 PM PDT 24
Peak memory 204776 kb
Host smart-39645a09-16eb-4383-9d39-dd9f85f8c943
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102580384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_fm
t.102580384
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.1971988702
Short name T144
Test name
Test status
Simulation time 656004001 ps
CPU time 4 seconds
Started Jun 06 02:57:21 PM PDT 24
Finished Jun 06 02:57:27 PM PDT 24
Peak memory 205096 kb
Host smart-1ce26fd8-5abe-4430-9ef1-061920f7999b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971988702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.1971988702
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.414550521
Short name T807
Test name
Test status
Simulation time 11887775300 ps
CPU time 223.01 seconds
Started Jun 06 02:57:21 PM PDT 24
Finished Jun 06 03:01:07 PM PDT 24
Peak memory 943012 kb
Host smart-29e462ac-f056-4d20-b8b8-3b1cd45dc486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414550521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.414550521
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2505299020
Short name T1427
Test name
Test status
Simulation time 2309618861 ps
CPU time 5.84 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:36 PM PDT 24
Peak memory 205124 kb
Host smart-5910e0ab-9a59-4e1d-b259-e67f276235e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505299020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2505299020
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.816508776
Short name T1038
Test name
Test status
Simulation time 1869899685 ps
CPU time 37.18 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:58:06 PM PDT 24
Peak memory 378084 kb
Host smart-25541652-3851-4b92-9cd0-f534bd3abe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816508776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.816508776
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1380145046
Short name T132
Test name
Test status
Simulation time 32594495 ps
CPU time 0.67 seconds
Started Jun 06 02:57:25 PM PDT 24
Finished Jun 06 02:57:31 PM PDT 24
Peak memory 204776 kb
Host smart-b6a41f02-af61-4a7e-89aa-55cc2efde97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380145046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1380145046
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2204067152
Short name T1068
Test name
Test status
Simulation time 18547131249 ps
CPU time 256.34 seconds
Started Jun 06 02:57:22 PM PDT 24
Finished Jun 06 03:01:42 PM PDT 24
Peak memory 205140 kb
Host smart-40e98dcc-9c18-4d67-85bb-f7dda1298210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204067152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2204067152
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1417351924
Short name T664
Test name
Test status
Simulation time 6551092984 ps
CPU time 80.22 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:58:50 PM PDT 24
Peak memory 361668 kb
Host smart-39ca268a-994a-4e1e-885a-55e5b4e3c12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417351924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1417351924
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.2186983748
Short name T113
Test name
Test status
Simulation time 16140389711 ps
CPU time 1112.45 seconds
Started Jun 06 02:57:26 PM PDT 24
Finished Jun 06 03:16:04 PM PDT 24
Peak memory 3357084 kb
Host smart-5746f58f-d97c-4dac-bf55-1908e1ba09a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186983748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.2186983748
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.1026262213
Short name T1137
Test name
Test status
Simulation time 10587439896 ps
CPU time 9.06 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:57:36 PM PDT 24
Peak memory 216300 kb
Host smart-4f1f097e-1237-4884-a8e2-152a420fd43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026262213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1026262213
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.3006140653
Short name T940
Test name
Test status
Simulation time 1051714154 ps
CPU time 5.4 seconds
Started Jun 06 02:57:21 PM PDT 24
Finished Jun 06 02:57:29 PM PDT 24
Peak memory 213300 kb
Host smart-67c6b559-2afb-4e8a-ab88-6709648700df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006140653 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.3006140653
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3029762133
Short name T78
Test name
Test status
Simulation time 10727863382 ps
CPU time 9.32 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:38 PM PDT 24
Peak memory 245628 kb
Host smart-cf5bd063-f9d2-4658-adde-1f16c9928607
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029762133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3029762133
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.3542576733
Short name T262
Test name
Test status
Simulation time 10184663005 ps
CPU time 85.02 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:58:55 PM PDT 24
Peak memory 514320 kb
Host smart-8192e38d-f501-4766-87d0-2a1b659d40b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542576733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.3542576733
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.1633283931
Short name T897
Test name
Test status
Simulation time 1944838471 ps
CPU time 2.93 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:33 PM PDT 24
Peak memory 205140 kb
Host smart-37659f88-76f1-459c-941f-b01ae4613a57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633283931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.1633283931
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.1370349585
Short name T1091
Test name
Test status
Simulation time 1019826976 ps
CPU time 6.16 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:35 PM PDT 24
Peak memory 205060 kb
Host smart-0f2710d4-ef2b-41ed-a88b-93dfe6dc01c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370349585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.1370349585
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.155144304
Short name T379
Test name
Test status
Simulation time 1811212957 ps
CPU time 2.53 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:57:31 PM PDT 24
Peak memory 205076 kb
Host smart-27d2ae93-60c4-4d23-ac5b-477460725f1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155144304 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.i2c_target_hrst.155144304
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2791367850
Short name T282
Test name
Test status
Simulation time 1317326988 ps
CPU time 6.91 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:57:35 PM PDT 24
Peak memory 213328 kb
Host smart-59ddd944-e5c9-4e62-865e-2a4b9de21f6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791367850 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2791367850
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.1651437595
Short name T601
Test name
Test status
Simulation time 18378295824 ps
CPU time 110.56 seconds
Started Jun 06 02:57:25 PM PDT 24
Finished Jun 06 02:59:21 PM PDT 24
Peak memory 1503128 kb
Host smart-e76cd97d-2e55-431f-a478-ecb69d811505
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651437595 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.1651437595
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.2327516327
Short name T1200
Test name
Test status
Simulation time 1672517954 ps
CPU time 13.79 seconds
Started Jun 06 02:57:25 PM PDT 24
Finished Jun 06 02:57:45 PM PDT 24
Peak memory 205000 kb
Host smart-dfcf8cfa-9ec4-4d23-8419-44b366fd758b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327516327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.2327516327
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.837230375
Short name T535
Test name
Test status
Simulation time 5932475437 ps
CPU time 55.41 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:58:23 PM PDT 24
Peak memory 207236 kb
Host smart-1f89ca12-2f12-489c-9257-18712ae00d88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837230375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.837230375
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.4068776985
Short name T305
Test name
Test status
Simulation time 37056058652 ps
CPU time 18.66 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:48 PM PDT 24
Peak memory 484484 kb
Host smart-cc30ae93-9f90-4b8a-9dad-e278ab486160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068776985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.4068776985
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.3454778543
Short name T697
Test name
Test status
Simulation time 16940759341 ps
CPU time 772.83 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 03:10:22 PM PDT 24
Peak memory 3507924 kb
Host smart-755ab556-a586-4be6-a3a3-328d3534088b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454778543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.3454778543
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.3306837268
Short name T62
Test name
Test status
Simulation time 4562572112 ps
CPU time 6.89 seconds
Started Jun 06 02:57:26 PM PDT 24
Finished Jun 06 02:57:38 PM PDT 24
Peak memory 218164 kb
Host smart-028b814b-8453-420d-bca1-2e9e89b431f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306837268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.3306837268
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.2135800479
Short name T720
Test name
Test status
Simulation time 1051796794 ps
CPU time 16.29 seconds
Started Jun 06 02:57:21 PM PDT 24
Finished Jun 06 02:57:40 PM PDT 24
Peak memory 205072 kb
Host smart-b26a38a2-a24b-4d42-9ae3-9e34a4f3bbe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135800479 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.2135800479
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.86451890
Short name T502
Test name
Test status
Simulation time 16029011 ps
CPU time 0.62 seconds
Started Jun 06 02:57:32 PM PDT 24
Finished Jun 06 02:57:36 PM PDT 24
Peak memory 204752 kb
Host smart-c247d4b9-bf6e-418f-b9f2-bcfffdcd2a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86451890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.86451890
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.3325069814
Short name T1446
Test name
Test status
Simulation time 558889120 ps
CPU time 2.2 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:31 PM PDT 24
Peak memory 205148 kb
Host smart-19d734a5-7183-499f-a1f1-7e9417b71e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325069814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.3325069814
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.40969188
Short name T962
Test name
Test status
Simulation time 322008683 ps
CPU time 5.28 seconds
Started Jun 06 02:57:26 PM PDT 24
Finished Jun 06 02:57:36 PM PDT 24
Peak memory 232380 kb
Host smart-135efc91-be1e-4319-9ca0-b2de7a0aa34b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40969188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empty
.40969188
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1036184848
Short name T869
Test name
Test status
Simulation time 2596863890 ps
CPU time 192.11 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 03:00:41 PM PDT 24
Peak memory 771044 kb
Host smart-528caa28-1cec-487e-a250-c83e79c22333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036184848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1036184848
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.3429723595
Short name T1417
Test name
Test status
Simulation time 5095750751 ps
CPU time 183.14 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 03:00:30 PM PDT 24
Peak memory 756248 kb
Host smart-df752b02-49de-46b4-85c9-b062c93b4d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429723595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3429723595
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.3237378068
Short name T500
Test name
Test status
Simulation time 369628157 ps
CPU time 1.06 seconds
Started Jun 06 02:57:22 PM PDT 24
Finished Jun 06 02:57:26 PM PDT 24
Peak memory 204996 kb
Host smart-f3670be7-7dfd-4ca6-96dd-b8d5d969e80c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237378068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.3237378068
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.429723606
Short name T915
Test name
Test status
Simulation time 454319425 ps
CPU time 5.6 seconds
Started Jun 06 02:57:21 PM PDT 24
Finished Jun 06 02:57:29 PM PDT 24
Peak memory 248096 kb
Host smart-a6060262-24d1-4862-a92d-27cf0220b3d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429723606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx.
429723606
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1741802011
Short name T460
Test name
Test status
Simulation time 4151865229 ps
CPU time 130.2 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:59:38 PM PDT 24
Peak memory 1185668 kb
Host smart-a5fea3e6-25a5-46c2-9275-0d61532a31b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741802011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1741802011
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.2601793004
Short name T888
Test name
Test status
Simulation time 5442434435 ps
CPU time 21.74 seconds
Started Jun 06 02:57:26 PM PDT 24
Finished Jun 06 02:57:53 PM PDT 24
Peak memory 328668 kb
Host smart-924d4bb6-2866-4b3d-9d72-241f2cd2c77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601793004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.2601793004
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_perf.1278977592
Short name T944
Test name
Test status
Simulation time 9495305426 ps
CPU time 231.67 seconds
Started Jun 06 02:57:22 PM PDT 24
Finished Jun 06 03:01:17 PM PDT 24
Peak memory 1280264 kb
Host smart-3ff39c97-c8c5-421a-8ce5-442626a0d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278977592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.1278977592
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1935620634
Short name T1089
Test name
Test status
Simulation time 8426509031 ps
CPU time 40.77 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:58:09 PM PDT 24
Peak memory 351012 kb
Host smart-d82e6d29-83d4-49e3-87c5-7f4450da3881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935620634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1935620634
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.583825444
Short name T582
Test name
Test status
Simulation time 852759043 ps
CPU time 11.38 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:40 PM PDT 24
Peak memory 217036 kb
Host smart-e4888400-3fa3-49d6-8d53-f16c1f12ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583825444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.583825444
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.506946103
Short name T439
Test name
Test status
Simulation time 1044923822 ps
CPU time 3.59 seconds
Started Jun 06 02:57:25 PM PDT 24
Finished Jun 06 02:57:33 PM PDT 24
Peak memory 205080 kb
Host smart-ca9201d1-18c9-447f-9e44-2ace6adfd379
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506946103 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.506946103
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2546379188
Short name T1059
Test name
Test status
Simulation time 10095031274 ps
CPU time 46.81 seconds
Started Jun 06 02:57:25 PM PDT 24
Finished Jun 06 02:58:17 PM PDT 24
Peak memory 358408 kb
Host smart-437047e6-4c9f-4516-81cd-b5f9f92b8b5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546379188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2546379188
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.477625538
Short name T152
Test name
Test status
Simulation time 10114987364 ps
CPU time 77.37 seconds
Started Jun 06 02:57:25 PM PDT 24
Finished Jun 06 02:58:47 PM PDT 24
Peak memory 519768 kb
Host smart-16ff2695-a110-4502-8b11-00b81b676b6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477625538 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.477625538
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.911248280
Short name T560
Test name
Test status
Simulation time 1444090745 ps
CPU time 3.81 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:33 PM PDT 24
Peak memory 205124 kb
Host smart-4b32fef9-c38d-4061-8a99-2acefa3261f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911248280 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.911248280
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.3263081022
Short name T261
Test name
Test status
Simulation time 1143437867 ps
CPU time 1.94 seconds
Started Jun 06 02:57:26 PM PDT 24
Finished Jun 06 02:57:33 PM PDT 24
Peak memory 205112 kb
Host smart-eff4c2fd-6466-47bc-b226-c6f4d179ae3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263081022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.3263081022
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2449291133
Short name T717
Test name
Test status
Simulation time 461773372 ps
CPU time 2.71 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:31 PM PDT 24
Peak memory 205056 kb
Host smart-880f46ee-4dc4-4358-8513-7f71790c3c77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449291133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2449291133
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1882575611
Short name T303
Test name
Test status
Simulation time 2266218445 ps
CPU time 5.76 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:35 PM PDT 24
Peak memory 213340 kb
Host smart-147921d4-d668-43ff-a662-46c27e26a5e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882575611 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1882575611
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.717675954
Short name T823
Test name
Test status
Simulation time 16598749425 ps
CPU time 204.15 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 03:00:54 PM PDT 24
Peak memory 2385444 kb
Host smart-232d01ec-c17a-4e06-8534-59c4845a762f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717675954 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.717675954
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.3898220440
Short name T530
Test name
Test status
Simulation time 1808889708 ps
CPU time 12.6 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:57:40 PM PDT 24
Peak memory 205112 kb
Host smart-7a7d9a36-f152-4156-8fe9-25b96009104b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898220440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.3898220440
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.143507740
Short name T399
Test name
Test status
Simulation time 2443522380 ps
CPU time 25.94 seconds
Started Jun 06 02:57:25 PM PDT 24
Finished Jun 06 02:57:56 PM PDT 24
Peak memory 205172 kb
Host smart-4a7b5279-b4ad-4e1f-ae97-6413e36cb918
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143507740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c
_target_stress_rd.143507740
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.1757257935
Short name T1235
Test name
Test status
Simulation time 13157326488 ps
CPU time 6.23 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:35 PM PDT 24
Peak memory 205160 kb
Host smart-60382407-1b5e-47d6-ae4d-7ce7a5b5b495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757257935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.1757257935
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.1757404098
Short name T270
Test name
Test status
Simulation time 13025015498 ps
CPU time 73.9 seconds
Started Jun 06 02:57:23 PM PDT 24
Finished Jun 06 02:58:42 PM PDT 24
Peak memory 842404 kb
Host smart-7d0bbfa4-c8c8-456d-822c-aeea23569c7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757404098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.1757404098
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.2626608783
Short name T630
Test name
Test status
Simulation time 9268925555 ps
CPU time 6.91 seconds
Started Jun 06 02:57:25 PM PDT 24
Finished Jun 06 02:57:37 PM PDT 24
Peak memory 219084 kb
Host smart-44816031-aade-4c6f-b07d-70015213f921
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626608783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.2626608783
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.684798647
Short name T1444
Test name
Test status
Simulation time 1181451756 ps
CPU time 18.87 seconds
Started Jun 06 02:57:27 PM PDT 24
Finished Jun 06 02:57:51 PM PDT 24
Peak memory 205092 kb
Host smart-ecca2ae7-9f44-48da-adab-f4f93a9f90f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684798647 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.684798647
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.3400453831
Short name T610
Test name
Test status
Simulation time 27857696 ps
CPU time 0.6 seconds
Started Jun 06 02:57:41 PM PDT 24
Finished Jun 06 02:57:47 PM PDT 24
Peak memory 204732 kb
Host smart-396477e6-acde-459f-a009-cffd922b5f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400453831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3400453831
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.1483911797
Short name T515
Test name
Test status
Simulation time 145996015 ps
CPU time 6.36 seconds
Started Jun 06 02:57:33 PM PDT 24
Finished Jun 06 02:57:44 PM PDT 24
Peak memory 221256 kb
Host smart-ddba4d40-ac74-4a2c-9dac-5733f0e8cb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483911797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.1483911797
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.348436947
Short name T558
Test name
Test status
Simulation time 263124450 ps
CPU time 5.09 seconds
Started Jun 06 02:57:31 PM PDT 24
Finished Jun 06 02:57:41 PM PDT 24
Peak memory 258532 kb
Host smart-cd48a4ad-3443-4ac1-a1fd-b8df05772075
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348436947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.348436947
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1727809307
Short name T1161
Test name
Test status
Simulation time 2079156010 ps
CPU time 157.6 seconds
Started Jun 06 02:57:31 PM PDT 24
Finished Jun 06 03:00:13 PM PDT 24
Peak memory 711440 kb
Host smart-ea361e78-c230-44c3-b513-38593614b2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727809307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1727809307
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.1752255553
Short name T963
Test name
Test status
Simulation time 3725897719 ps
CPU time 225.42 seconds
Started Jun 06 02:57:26 PM PDT 24
Finished Jun 06 03:01:17 PM PDT 24
Peak memory 861480 kb
Host smart-17a2af30-bbb2-4ab7-9cc8-e631c013d214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752255553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.1752255553
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2743621958
Short name T758
Test name
Test status
Simulation time 99461452 ps
CPU time 0.99 seconds
Started Jun 06 02:57:34 PM PDT 24
Finished Jun 06 02:57:39 PM PDT 24
Peak memory 204772 kb
Host smart-84e2fd7a-f748-4fe5-9703-96ca5d2e2a43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743621958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2743621958
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3659169958
Short name T1347
Test name
Test status
Simulation time 403627879 ps
CPU time 11.27 seconds
Started Jun 06 02:57:24 PM PDT 24
Finished Jun 06 02:57:41 PM PDT 24
Peak memory 242000 kb
Host smart-9f37be2c-ab6d-450c-9b11-172bf44da408
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659169958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3659169958
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.4150283403
Short name T1402
Test name
Test status
Simulation time 16992419830 ps
CPU time 134.82 seconds
Started Jun 06 02:57:32 PM PDT 24
Finished Jun 06 02:59:51 PM PDT 24
Peak memory 1218356 kb
Host smart-ee6269ba-5551-4b27-83ef-8e5c475e6002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150283403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.4150283403
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.80684212
Short name T40
Test name
Test status
Simulation time 1759910839 ps
CPU time 5.87 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:53 PM PDT 24
Peak memory 205088 kb
Host smart-918c804a-683c-4da5-aa11-365fa34a18d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80684212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.80684212
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.972338079
Short name T36
Test name
Test status
Simulation time 8847186169 ps
CPU time 30.76 seconds
Started Jun 06 02:57:45 PM PDT 24
Finished Jun 06 02:58:21 PM PDT 24
Peak memory 381592 kb
Host smart-59024bca-e16e-4f8b-a5c0-6758035aae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972338079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.972338079
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.723874905
Short name T836
Test name
Test status
Simulation time 83663920 ps
CPU time 0.72 seconds
Started Jun 06 02:57:33 PM PDT 24
Finished Jun 06 02:57:38 PM PDT 24
Peak memory 204668 kb
Host smart-ced64ff0-7c63-48b2-818b-991062e8bf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723874905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.723874905
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.145475206
Short name T1362
Test name
Test status
Simulation time 388103638 ps
CPU time 3.91 seconds
Started Jun 06 02:57:30 PM PDT 24
Finished Jun 06 02:57:39 PM PDT 24
Peak memory 229688 kb
Host smart-aa0f0699-e6d5-41c5-8553-6dba77df5161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145475206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.145475206
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1706344954
Short name T506
Test name
Test status
Simulation time 9819347532 ps
CPU time 45.8 seconds
Started Jun 06 02:57:26 PM PDT 24
Finished Jun 06 02:58:17 PM PDT 24
Peak memory 359872 kb
Host smart-de8f6049-c0eb-4cb0-acd9-d3f5445b89b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706344954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1706344954
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.3244993371
Short name T1105
Test name
Test status
Simulation time 22287583487 ps
CPU time 1244.03 seconds
Started Jun 06 02:57:31 PM PDT 24
Finished Jun 06 03:18:19 PM PDT 24
Peak memory 1773040 kb
Host smart-a6037d02-75ab-4b08-85e9-8d497ff1b351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244993371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.3244993371
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.2258472264
Short name T1028
Test name
Test status
Simulation time 3096239331 ps
CPU time 16.42 seconds
Started Jun 06 02:57:32 PM PDT 24
Finished Jun 06 02:57:52 PM PDT 24
Peak memory 221552 kb
Host smart-e87e9995-a120-47bf-9d13-84a4002664a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258472264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.2258472264
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3476937884
Short name T280
Test name
Test status
Simulation time 499481608 ps
CPU time 2.46 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:57:51 PM PDT 24
Peak memory 205092 kb
Host smart-20b1a219-5579-461d-953c-dfc4a67e9e4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476937884 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3476937884
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.925014391
Short name T438
Test name
Test status
Simulation time 10093366867 ps
CPU time 44.4 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:58:33 PM PDT 24
Peak memory 361544 kb
Host smart-c3c52baa-ce79-46a8-944c-e5138a90c08d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925014391 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.925014391
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.1110711947
Short name T327
Test name
Test status
Simulation time 10451789969 ps
CPU time 9.02 seconds
Started Jun 06 02:57:35 PM PDT 24
Finished Jun 06 02:57:49 PM PDT 24
Peak memory 276724 kb
Host smart-762d1e74-b08a-4a4f-af8f-9099278c1bdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110711947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.1110711947
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.2638003565
Short name T928
Test name
Test status
Simulation time 1057473160 ps
CPU time 4.86 seconds
Started Jun 06 02:57:34 PM PDT 24
Finished Jun 06 02:57:43 PM PDT 24
Peak memory 205100 kb
Host smart-ae5af58b-27ef-4a09-9c41-af749a0131d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638003565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.2638003565
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.101956626
Short name T526
Test name
Test status
Simulation time 1085912035 ps
CPU time 5.36 seconds
Started Jun 06 02:57:41 PM PDT 24
Finished Jun 06 02:57:52 PM PDT 24
Peak memory 205140 kb
Host smart-de81637a-8733-42ba-a39f-04e546ab876f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101956626 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.101956626
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.1546772949
Short name T13
Test name
Test status
Simulation time 317535613 ps
CPU time 2.48 seconds
Started Jun 06 02:57:40 PM PDT 24
Finished Jun 06 02:57:47 PM PDT 24
Peak memory 205056 kb
Host smart-566cb267-16af-4c53-ada2-10f09f43227e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546772949 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.1546772949
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2905558967
Short name T583
Test name
Test status
Simulation time 3441180233 ps
CPU time 4.11 seconds
Started Jun 06 02:57:34 PM PDT 24
Finished Jun 06 02:57:43 PM PDT 24
Peak memory 205200 kb
Host smart-ec50e02f-26d2-4fec-a4bd-a0c15442f604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905558967 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2905558967
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.227076578
Short name T1485
Test name
Test status
Simulation time 8404808071 ps
CPU time 119.86 seconds
Started Jun 06 02:57:36 PM PDT 24
Finished Jun 06 02:59:40 PM PDT 24
Peak memory 2145440 kb
Host smart-5f73deaa-4415-4167-9ac5-98fc6e9a1a64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227076578 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.227076578
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.4147219011
Short name T1073
Test name
Test status
Simulation time 1041693630 ps
CPU time 15.91 seconds
Started Jun 06 02:57:33 PM PDT 24
Finished Jun 06 02:57:53 PM PDT 24
Peak memory 205016 kb
Host smart-160c8bd7-fb6d-4586-8350-faa4e7c3636e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147219011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.4147219011
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.213521271
Short name T315
Test name
Test status
Simulation time 860632320 ps
CPU time 14.83 seconds
Started Jun 06 02:57:35 PM PDT 24
Finished Jun 06 02:57:54 PM PDT 24
Peak memory 216212 kb
Host smart-9d51e7da-7018-4fa4-a6dc-a34fee65d737
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213521271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.213521271
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.880089301
Short name T678
Test name
Test status
Simulation time 53349788511 ps
CPU time 192.92 seconds
Started Jun 06 02:57:36 PM PDT 24
Finished Jun 06 03:00:53 PM PDT 24
Peak memory 2041284 kb
Host smart-d4bcb21e-728e-4615-8336-41b0cff0f447
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880089301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_wr.880089301
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.2034429385
Short name T1409
Test name
Test status
Simulation time 38803647840 ps
CPU time 944.75 seconds
Started Jun 06 02:57:31 PM PDT 24
Finished Jun 06 03:13:20 PM PDT 24
Peak memory 4509156 kb
Host smart-78510263-8990-4647-ae0a-06a6ece2c88b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034429385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.2034429385
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1099555301
Short name T577
Test name
Test status
Simulation time 1068014793 ps
CPU time 6.32 seconds
Started Jun 06 02:57:36 PM PDT 24
Finished Jun 06 02:57:47 PM PDT 24
Peak memory 212408 kb
Host smart-2c64c47f-21bb-4a40-9706-692701b86bb5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099555301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1099555301
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.2026894150
Short name T1163
Test name
Test status
Simulation time 1269590091 ps
CPU time 16.84 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:58:04 PM PDT 24
Peak memory 205108 kb
Host smart-daefae46-d499-4452-b7c4-75732e606696
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026894150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.2026894150
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.906068492
Short name T1146
Test name
Test status
Simulation time 18204996 ps
CPU time 0.63 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:48 PM PDT 24
Peak memory 204740 kb
Host smart-e36ee3bf-17f0-407f-8dcd-2912c6211313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906068492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.906068492
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3201454092
Short name T1044
Test name
Test status
Simulation time 764958240 ps
CPU time 8.17 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:57:56 PM PDT 24
Peak memory 280796 kb
Host smart-be82bd63-024f-4a48-b9ad-bdc0dec57833
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201454092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3201454092
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.837080679
Short name T1201
Test name
Test status
Simulation time 1875914225 ps
CPU time 57.57 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:58:45 PM PDT 24
Peak memory 649792 kb
Host smart-740e20c6-5eb5-4940-a498-18bb2ebcd6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837080679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.837080679
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.4262470625
Short name T1322
Test name
Test status
Simulation time 8714062041 ps
CPU time 63.45 seconds
Started Jun 06 02:57:41 PM PDT 24
Finished Jun 06 02:58:49 PM PDT 24
Peak memory 609608 kb
Host smart-3b3ea125-fa95-4ef2-8d4f-0c526954aee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262470625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.4262470625
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2577025085
Short name T746
Test name
Test status
Simulation time 604389558 ps
CPU time 0.93 seconds
Started Jun 06 02:57:40 PM PDT 24
Finished Jun 06 02:57:45 PM PDT 24
Peak memory 204780 kb
Host smart-00db46a8-b016-432f-b725-ed6565c85566
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577025085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2577025085
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3241672942
Short name T550
Test name
Test status
Simulation time 254921583 ps
CPU time 3.37 seconds
Started Jun 06 02:57:35 PM PDT 24
Finished Jun 06 02:57:43 PM PDT 24
Peak memory 205020 kb
Host smart-03e41760-3c38-4d25-b9ff-715af2dbe8b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241672942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3241672942
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.4202500888
Short name T1395
Test name
Test status
Simulation time 3714021546 ps
CPU time 111.46 seconds
Started Jun 06 02:57:34 PM PDT 24
Finished Jun 06 02:59:29 PM PDT 24
Peak memory 1089448 kb
Host smart-4301dc68-9345-4dd0-97ad-b58e70372da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202500888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4202500888
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.1144692806
Short name T783
Test name
Test status
Simulation time 745952009 ps
CPU time 15.9 seconds
Started Jun 06 02:57:40 PM PDT 24
Finished Jun 06 02:58:01 PM PDT 24
Peak memory 205056 kb
Host smart-ab5bb345-d74d-4aa5-bd9e-c81c8e6e23c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144692806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1144692806
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3662827091
Short name T317
Test name
Test status
Simulation time 1709170180 ps
CPU time 27.26 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:58:16 PM PDT 24
Peak memory 353076 kb
Host smart-1e3aa67d-2954-480b-a6c4-6513c0a8b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662827091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3662827091
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.965362586
Short name T126
Test name
Test status
Simulation time 113551779 ps
CPU time 0.68 seconds
Started Jun 06 02:57:35 PM PDT 24
Finished Jun 06 02:57:40 PM PDT 24
Peak memory 204740 kb
Host smart-dde6ae6e-2c75-47cc-acab-5b124fe37c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965362586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.965362586
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.1835846225
Short name T810
Test name
Test status
Simulation time 8837974420 ps
CPU time 305.01 seconds
Started Jun 06 02:57:40 PM PDT 24
Finished Jun 06 03:02:50 PM PDT 24
Peak memory 1404796 kb
Host smart-a8af0f9d-b22e-4eb4-b2bb-df6e2bd4ce8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835846225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.1835846225
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.418927603
Short name T998
Test name
Test status
Simulation time 5447369714 ps
CPU time 31.12 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:58:20 PM PDT 24
Peak memory 326272 kb
Host smart-2394b1fd-5c9e-4dc1-add3-e57a5b451886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418927603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.418927603
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.711233727
Short name T1173
Test name
Test status
Simulation time 1838067476 ps
CPU time 10.7 seconds
Started Jun 06 02:57:39 PM PDT 24
Finished Jun 06 02:57:54 PM PDT 24
Peak memory 221420 kb
Host smart-3a42b569-2702-4c1a-8b6a-18c5b8d76628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711233727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.711233727
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1891900533
Short name T675
Test name
Test status
Simulation time 1019657872 ps
CPU time 3.32 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:57:52 PM PDT 24
Peak memory 205116 kb
Host smart-ae621a8e-20cf-49c3-963f-734d2c23bdf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891900533 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1891900533
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.1498475504
Short name T1128
Test name
Test status
Simulation time 10298877429 ps
CPU time 11.38 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:59 PM PDT 24
Peak memory 240660 kb
Host smart-983322a2-a7d2-4181-b485-125563e48604
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498475504 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.1498475504
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1600508469
Short name T849
Test name
Test status
Simulation time 10407865143 ps
CPU time 14.81 seconds
Started Jun 06 02:57:39 PM PDT 24
Finished Jun 06 02:57:59 PM PDT 24
Peak memory 344864 kb
Host smart-87aca128-07b3-4326-83e3-a86305a9404c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600508469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1600508469
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.601469816
Short name T525
Test name
Test status
Simulation time 1877626975 ps
CPU time 2.55 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:57:51 PM PDT 24
Peak memory 205128 kb
Host smart-f8a574bb-e7c4-4ffe-b716-7a5b9eb0c1e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601469816 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.601469816
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.587511893
Short name T418
Test name
Test status
Simulation time 1044685680 ps
CPU time 5.46 seconds
Started Jun 06 02:57:41 PM PDT 24
Finished Jun 06 02:57:52 PM PDT 24
Peak memory 205088 kb
Host smart-16a51938-5656-4f88-b304-fbf8bbcf3dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587511893 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.587511893
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.791133385
Short name T1124
Test name
Test status
Simulation time 354854511 ps
CPU time 2.42 seconds
Started Jun 06 02:57:37 PM PDT 24
Finished Jun 06 02:57:43 PM PDT 24
Peak memory 205084 kb
Host smart-1f31e94a-d5b6-488f-86dc-b2cc5b44b9b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791133385 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.791133385
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3814257474
Short name T482
Test name
Test status
Simulation time 1006614606 ps
CPU time 5.12 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:53 PM PDT 24
Peak memory 205496 kb
Host smart-dc208d6b-5424-45e1-b334-b624ced251ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814257474 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3814257474
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.2120818392
Short name T1106
Test name
Test status
Simulation time 19642593561 ps
CPU time 144.15 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 03:00:12 PM PDT 24
Peak memory 1678532 kb
Host smart-e5639a26-386d-4f2d-af6e-1019242813f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120818392 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.2120818392
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2495751042
Short name T552
Test name
Test status
Simulation time 1348585532 ps
CPU time 53.35 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:58:42 PM PDT 24
Peak memory 205084 kb
Host smart-6f4b92ec-b61e-48f5-a708-b1047780e242
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495751042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2495751042
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1798484028
Short name T1458
Test name
Test status
Simulation time 5105331974 ps
CPU time 20.77 seconds
Started Jun 06 02:57:38 PM PDT 24
Finished Jun 06 02:58:03 PM PDT 24
Peak memory 215716 kb
Host smart-d9ce327c-5210-4984-b8ab-fe0d639abcb9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798484028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1798484028
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.1323282341
Short name T1419
Test name
Test status
Simulation time 58414806041 ps
CPU time 291.41 seconds
Started Jun 06 02:57:38 PM PDT 24
Finished Jun 06 03:02:34 PM PDT 24
Peak memory 2872768 kb
Host smart-ea076027-deae-4170-902f-4c782526786a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323282341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.1323282341
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1244650135
Short name T966
Test name
Test status
Simulation time 13042405068 ps
CPU time 29.88 seconds
Started Jun 06 02:57:40 PM PDT 24
Finished Jun 06 02:58:15 PM PDT 24
Peak memory 482660 kb
Host smart-3b856405-fe83-4583-b541-d6ef47c3cc72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244650135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1244650135
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1910098195
Short name T896
Test name
Test status
Simulation time 6634476882 ps
CPU time 6.74 seconds
Started Jun 06 02:57:39 PM PDT 24
Finished Jun 06 02:57:50 PM PDT 24
Peak memory 213332 kb
Host smart-ae897db1-5122-473c-b844-9cf66c8c0c74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910098195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1910098195
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.3734765319
Short name T398
Test name
Test status
Simulation time 1089327069 ps
CPU time 20.08 seconds
Started Jun 06 02:57:41 PM PDT 24
Finished Jun 06 02:58:07 PM PDT 24
Peak memory 205088 kb
Host smart-a0a16177-1ab2-430b-8ef6-a0b7867b7657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734765319 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.3734765319
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.1705736474
Short name T1469
Test name
Test status
Simulation time 26920351 ps
CPU time 0.64 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:49 PM PDT 24
Peak memory 204880 kb
Host smart-53ec0ec0-f17e-4746-9b10-5dd9411647b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705736474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1705736474
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.568602687
Short name T35
Test name
Test status
Simulation time 165708255 ps
CPU time 1.69 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:49 PM PDT 24
Peak memory 213304 kb
Host smart-98167dcb-c3e1-4387-8a7e-496f07d86ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568602687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.568602687
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1077172483
Short name T961
Test name
Test status
Simulation time 688828169 ps
CPU time 6 seconds
Started Jun 06 02:57:39 PM PDT 24
Finished Jun 06 02:57:50 PM PDT 24
Peak memory 262140 kb
Host smart-2e53dfac-9781-4575-9f0a-ba7968c13e2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077172483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1077172483
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.4261217453
Short name T695
Test name
Test status
Simulation time 6016674458 ps
CPU time 49.79 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:58:38 PM PDT 24
Peak memory 563220 kb
Host smart-5b448e24-710a-4656-86bf-519be52e429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261217453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.4261217453
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.746511680
Short name T311
Test name
Test status
Simulation time 3460614509 ps
CPU time 49.61 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:58:37 PM PDT 24
Peak memory 619324 kb
Host smart-2115df0f-599e-452e-9dd7-eb7249229e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746511680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.746511680
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.142968682
Short name T1043
Test name
Test status
Simulation time 236731067 ps
CPU time 0.89 seconds
Started Jun 06 02:57:44 PM PDT 24
Finished Jun 06 02:57:50 PM PDT 24
Peak memory 204740 kb
Host smart-b2e1b8bc-fe24-4f18-9639-ddb83d27c0b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142968682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fm
t.142968682
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.961786196
Short name T1404
Test name
Test status
Simulation time 192085412 ps
CPU time 9.71 seconds
Started Jun 06 02:57:41 PM PDT 24
Finished Jun 06 02:57:56 PM PDT 24
Peak memory 204972 kb
Host smart-cbc59fd1-11a3-49b7-b775-051bc0642032
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961786196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx.
961786196
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3384275740
Short name T101
Test name
Test status
Simulation time 5267931913 ps
CPU time 59.01 seconds
Started Jun 06 02:57:41 PM PDT 24
Finished Jun 06 02:58:45 PM PDT 24
Peak memory 847052 kb
Host smart-65aa964c-42a8-4c0b-a64a-d9a1bd024d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384275740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3384275740
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.150258918
Short name T1150
Test name
Test status
Simulation time 751351124 ps
CPU time 3.59 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:57:52 PM PDT 24
Peak memory 205200 kb
Host smart-954fa419-abcb-44e0-b59c-6d72dbfc56c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150258918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.150258918
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3017287297
Short name T451
Test name
Test status
Simulation time 3691598277 ps
CPU time 29.34 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:58:18 PM PDT 24
Peak memory 353808 kb
Host smart-e60418cd-0752-4e87-86c1-c67998de76ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017287297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3017287297
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1344368010
Short name T929
Test name
Test status
Simulation time 28171497 ps
CPU time 0.64 seconds
Started Jun 06 02:57:44 PM PDT 24
Finished Jun 06 02:57:50 PM PDT 24
Peak memory 204668 kb
Host smart-2a95b06f-3de2-4149-9677-5748a6fdab7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344368010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1344368010
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.42795686
Short name T489
Test name
Test status
Simulation time 27335149287 ps
CPU time 140.23 seconds
Started Jun 06 02:57:44 PM PDT 24
Finished Jun 06 03:00:10 PM PDT 24
Peak memory 205148 kb
Host smart-0dabccc7-08ef-4671-9595-3eccf2f1fddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42795686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.42795686
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.2843143279
Short name T713
Test name
Test status
Simulation time 1052634125 ps
CPU time 15.24 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:58:04 PM PDT 24
Peak memory 284044 kb
Host smart-0aa40f2b-5ec5-4d0c-8510-ec7becb5705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843143279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.2843143279
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.2588406023
Short name T42
Test name
Test status
Simulation time 35322566131 ps
CPU time 390.79 seconds
Started Jun 06 02:57:45 PM PDT 24
Finished Jun 06 03:04:21 PM PDT 24
Peak memory 1845280 kb
Host smart-85fae7ef-9b6b-42ce-b48d-c0ac946d0dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588406023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.2588406023
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.4150548028
Short name T1112
Test name
Test status
Simulation time 3793456603 ps
CPU time 33.94 seconds
Started Jun 06 02:57:41 PM PDT 24
Finished Jun 06 02:58:20 PM PDT 24
Peak memory 213396 kb
Host smart-5c1ac555-2d6c-4092-a6dc-b1bae40fd868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150548028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.4150548028
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.332390356
Short name T565
Test name
Test status
Simulation time 415801833 ps
CPU time 2.43 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:50 PM PDT 24
Peak memory 205084 kb
Host smart-4741a2b2-428a-40c9-9e1b-ac15e6e0c3df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332390356 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.332390356
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.3883904889
Short name T902
Test name
Test status
Simulation time 10292587474 ps
CPU time 12.86 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:58:02 PM PDT 24
Peak memory 251752 kb
Host smart-46ef985f-e407-48e1-91af-bb9b3af4b998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883904889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.3883904889
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.2524385298
Short name T1256
Test name
Test status
Simulation time 10199916899 ps
CPU time 78.9 seconds
Started Jun 06 02:57:40 PM PDT 24
Finished Jun 06 02:59:04 PM PDT 24
Peak memory 653052 kb
Host smart-98eaf719-63eb-4e62-a30d-3b52b6c132a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524385298 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.2524385298
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.33435960
Short name T957
Test name
Test status
Simulation time 1205161080 ps
CPU time 2.56 seconds
Started Jun 06 02:57:39 PM PDT 24
Finished Jun 06 02:57:46 PM PDT 24
Peak memory 205136 kb
Host smart-64645244-e1ca-4b2f-8730-ffe3e0354ac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33435960 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.33435960
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.2275070206
Short name T561
Test name
Test status
Simulation time 1243896895 ps
CPU time 3.21 seconds
Started Jun 06 02:57:44 PM PDT 24
Finished Jun 06 02:57:53 PM PDT 24
Peak memory 205068 kb
Host smart-2ac27337-ffff-48f7-95a2-e251c0988f92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275070206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.2275070206
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.357879314
Short name T485
Test name
Test status
Simulation time 2074651156 ps
CPU time 3.3 seconds
Started Jun 06 02:57:40 PM PDT 24
Finished Jun 06 02:57:48 PM PDT 24
Peak memory 205036 kb
Host smart-27350c48-1b1b-4015-98b1-4ce0e35c948b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357879314 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.357879314
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.2551652140
Short name T1250
Test name
Test status
Simulation time 854004289 ps
CPU time 4.83 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 02:57:53 PM PDT 24
Peak memory 214404 kb
Host smart-11be6780-78cb-4151-adda-4a9125e0de49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551652140 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.2551652140
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.4134924075
Short name T1269
Test name
Test status
Simulation time 20184436549 ps
CPU time 56.83 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:58:45 PM PDT 24
Peak memory 1200472 kb
Host smart-6029d253-4739-4d25-a5fe-040097eab56c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134924075 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.4134924075
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.951753159
Short name T954
Test name
Test status
Simulation time 2675290552 ps
CPU time 10.13 seconds
Started Jun 06 02:57:40 PM PDT 24
Finished Jun 06 02:57:55 PM PDT 24
Peak memory 205144 kb
Host smart-07b3fdec-513d-437a-8218-5e53d9646606
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951753159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.951753159
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.1137067581
Short name T934
Test name
Test status
Simulation time 558401826 ps
CPU time 5.14 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:53 PM PDT 24
Peak memory 205160 kb
Host smart-d79449e8-b28e-417a-bfed-005a22291a1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137067581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.1137067581
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.676601547
Short name T1148
Test name
Test status
Simulation time 66376293473 ps
CPU time 331.51 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 03:03:20 PM PDT 24
Peak memory 2958432 kb
Host smart-d324d078-2b4a-4774-883f-3efe5b2ec9e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676601547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.676601547
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1146244202
Short name T1335
Test name
Test status
Simulation time 35577994799 ps
CPU time 249.27 seconds
Started Jun 06 02:57:43 PM PDT 24
Finished Jun 06 03:01:58 PM PDT 24
Peak memory 1827804 kb
Host smart-d7cb5256-f185-47a1-8f03-297f29c2178c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146244202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1146244202
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2218125250
Short name T343
Test name
Test status
Simulation time 5359029592 ps
CPU time 7.25 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:57:54 PM PDT 24
Peak memory 220244 kb
Host smart-cc6119c0-4264-4abb-823c-62705983d87c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218125250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2218125250
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.739561592
Short name T544
Test name
Test status
Simulation time 1121545350 ps
CPU time 21.22 seconds
Started Jun 06 02:57:42 PM PDT 24
Finished Jun 06 02:58:09 PM PDT 24
Peak memory 205276 kb
Host smart-c6974160-af01-44c6-bbef-dce03ba83c9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739561592 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.739561592
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.4244011015
Short name T1023
Test name
Test status
Simulation time 19136900 ps
CPU time 0.66 seconds
Started Jun 06 02:50:16 PM PDT 24
Finished Jun 06 02:50:18 PM PDT 24
Peak memory 204732 kb
Host smart-ed7619d4-66d0-40e2-8f79-733948901db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244011015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.4244011015
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.338693436
Short name T1186
Test name
Test status
Simulation time 578170972 ps
CPU time 2.28 seconds
Started Jun 06 02:50:10 PM PDT 24
Finished Jun 06 02:50:13 PM PDT 24
Peak memory 213280 kb
Host smart-f6ec4267-e1ba-4a39-bec8-264f2c499870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338693436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.338693436
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.3873692961
Short name T620
Test name
Test status
Simulation time 2042219137 ps
CPU time 26.72 seconds
Started Jun 06 02:50:12 PM PDT 24
Finished Jun 06 02:50:40 PM PDT 24
Peak memory 313848 kb
Host smart-a34e8be5-3964-4f76-ad6e-168185c05957
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873692961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.3873692961
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2598707059
Short name T958
Test name
Test status
Simulation time 9178044529 ps
CPU time 89.3 seconds
Started Jun 06 02:50:16 PM PDT 24
Finished Jun 06 02:51:47 PM PDT 24
Peak memory 778104 kb
Host smart-a577585d-86a9-428c-86ee-2162d2a4c6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598707059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2598707059
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.1209980097
Short name T607
Test name
Test status
Simulation time 4736210371 ps
CPU time 68.87 seconds
Started Jun 06 02:50:09 PM PDT 24
Finished Jun 06 02:51:19 PM PDT 24
Peak memory 607960 kb
Host smart-6a84bf11-7693-40dd-ae3b-933ab73c2796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209980097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.1209980097
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2066014002
Short name T330
Test name
Test status
Simulation time 496919555 ps
CPU time 0.94 seconds
Started Jun 06 02:50:11 PM PDT 24
Finished Jun 06 02:50:13 PM PDT 24
Peak memory 204700 kb
Host smart-cdf63190-9ed8-471b-a015-c04e381afd23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066014002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2066014002
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2702905419
Short name T1447
Test name
Test status
Simulation time 121802808 ps
CPU time 6.59 seconds
Started Jun 06 02:50:09 PM PDT 24
Finished Jun 06 02:50:17 PM PDT 24
Peak memory 205028 kb
Host smart-d7523f2d-eac6-47da-ab2a-93051f388570
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702905419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2702905419
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.209853462
Short name T591
Test name
Test status
Simulation time 8291582691 ps
CPU time 112.42 seconds
Started Jun 06 02:50:09 PM PDT 24
Finished Jun 06 02:52:02 PM PDT 24
Peak memory 1065952 kb
Host smart-47bcea2c-dabc-48e2-a4a9-d1fc978e6b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209853462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.209853462
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.3084533444
Short name T842
Test name
Test status
Simulation time 386154386 ps
CPU time 6.13 seconds
Started Jun 06 02:50:13 PM PDT 24
Finished Jun 06 02:50:21 PM PDT 24
Peak memory 205048 kb
Host smart-43f1c016-2e1a-4e79-9177-d211fad394c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084533444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.3084533444
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.755037088
Short name T945
Test name
Test status
Simulation time 7652166309 ps
CPU time 36.45 seconds
Started Jun 06 02:50:15 PM PDT 24
Finished Jun 06 02:50:53 PM PDT 24
Peak memory 386296 kb
Host smart-c3b8eba3-1940-4afb-ba4f-8b30a6e7f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755037088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.755037088
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3417099169
Short name T1098
Test name
Test status
Simulation time 50281240 ps
CPU time 0.68 seconds
Started Jun 06 02:50:11 PM PDT 24
Finished Jun 06 02:50:13 PM PDT 24
Peak memory 204744 kb
Host smart-2be4bd3b-4115-4fab-8c9a-326cef92d708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417099169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3417099169
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3665765853
Short name T1170
Test name
Test status
Simulation time 27268493857 ps
CPU time 597.51 seconds
Started Jun 06 02:50:10 PM PDT 24
Finished Jun 06 03:00:10 PM PDT 24
Peak memory 1527580 kb
Host smart-50cbd83c-edc0-48b6-9518-a436ed997620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665765853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3665765853
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3181784406
Short name T319
Test name
Test status
Simulation time 1674954361 ps
CPU time 28.28 seconds
Started Jun 06 02:50:09 PM PDT 24
Finished Jun 06 02:50:38 PM PDT 24
Peak memory 352400 kb
Host smart-5a30472d-a7a6-4f74-8bb3-babc84b0aded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181784406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3181784406
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2293865775
Short name T252
Test name
Test status
Simulation time 60332119365 ps
CPU time 349.1 seconds
Started Jun 06 02:50:16 PM PDT 24
Finished Jun 06 02:56:07 PM PDT 24
Peak memory 1021568 kb
Host smart-1c44b7ef-e40c-40c2-833d-9eb29b47d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293865775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2293865775
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.3485812749
Short name T1440
Test name
Test status
Simulation time 2512888875 ps
CPU time 21.82 seconds
Started Jun 06 02:50:10 PM PDT 24
Finished Jun 06 02:50:34 PM PDT 24
Peak memory 229420 kb
Host smart-6aedf11d-b2b9-4b9b-83ba-946135981143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485812749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.3485812749
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.3188012802
Short name T1343
Test name
Test status
Simulation time 692363637 ps
CPU time 3.84 seconds
Started Jun 06 02:50:16 PM PDT 24
Finished Jun 06 02:50:21 PM PDT 24
Peak memory 205120 kb
Host smart-c8b4a0ac-03d0-44c1-8a29-5bf43277323d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188012802 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.3188012802
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.3178641932
Short name T1413
Test name
Test status
Simulation time 10287406231 ps
CPU time 23.55 seconds
Started Jun 06 02:50:10 PM PDT 24
Finished Jun 06 02:50:35 PM PDT 24
Peak memory 290444 kb
Host smart-738d3252-e0f8-46fe-84b2-7c37305b6974
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178641932 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.3178641932
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2760411266
Short name T1025
Test name
Test status
Simulation time 10235448036 ps
CPU time 39.91 seconds
Started Jun 06 02:50:10 PM PDT 24
Finished Jun 06 02:50:51 PM PDT 24
Peak memory 472772 kb
Host smart-ec774cfd-9cb9-4456-ab97-57bcf4923787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760411266 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2760411266
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.2990334587
Short name T397
Test name
Test status
Simulation time 1607010582 ps
CPU time 4.02 seconds
Started Jun 06 02:50:13 PM PDT 24
Finished Jun 06 02:50:19 PM PDT 24
Peak memory 205060 kb
Host smart-bf30acbc-1f56-440c-a192-703abb5e3971
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990334587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.2990334587
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.1805885502
Short name T791
Test name
Test status
Simulation time 1051577971 ps
CPU time 3.4 seconds
Started Jun 06 02:50:15 PM PDT 24
Finished Jun 06 02:50:21 PM PDT 24
Peak memory 205128 kb
Host smart-508741fc-0ffe-4568-81d6-d7cb3b319596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805885502 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.1805885502
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.287445110
Short name T23
Test name
Test status
Simulation time 344181580 ps
CPU time 2.38 seconds
Started Jun 06 02:50:10 PM PDT 24
Finished Jun 06 02:50:15 PM PDT 24
Peak memory 205080 kb
Host smart-3a14dc76-d8bb-44c2-be52-0f24c38f8cb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287445110 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.287445110
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.912006226
Short name T942
Test name
Test status
Simulation time 1651191042 ps
CPU time 8.21 seconds
Started Jun 06 02:50:11 PM PDT 24
Finished Jun 06 02:50:21 PM PDT 24
Peak memory 213288 kb
Host smart-148e588a-f54d-4d9d-98cf-bd4ad37b9f2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912006226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.912006226
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3072877412
Short name T1248
Test name
Test status
Simulation time 8765171818 ps
CPU time 6.49 seconds
Started Jun 06 02:50:10 PM PDT 24
Finished Jun 06 02:50:18 PM PDT 24
Peak memory 205140 kb
Host smart-dce15a66-08b1-42f2-92bf-39dfe6218901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072877412 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3072877412
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.338931575
Short name T427
Test name
Test status
Simulation time 11733136836 ps
CPU time 44.3 seconds
Started Jun 06 02:50:09 PM PDT 24
Finished Jun 06 02:50:54 PM PDT 24
Peak memory 205192 kb
Host smart-dc3b7e09-5e3a-466d-bd19-b0982505ea9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338931575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.338931575
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.978724613
Short name T1142
Test name
Test status
Simulation time 6000137613 ps
CPU time 20.02 seconds
Started Jun 06 02:50:10 PM PDT 24
Finished Jun 06 02:50:31 PM PDT 24
Peak memory 228836 kb
Host smart-c862960c-225f-411a-92a1-ceebe4d97263
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978724613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.978724613
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2972799662
Short name T909
Test name
Test status
Simulation time 11384836138 ps
CPU time 20.51 seconds
Started Jun 06 02:50:09 PM PDT 24
Finished Jun 06 02:50:30 PM PDT 24
Peak memory 205092 kb
Host smart-eb9f306a-7665-4f10-8031-4463b5d1b600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972799662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2972799662
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3264953734
Short name T745
Test name
Test status
Simulation time 33020984257 ps
CPU time 226.86 seconds
Started Jun 06 02:50:12 PM PDT 24
Finished Jun 06 02:54:01 PM PDT 24
Peak memory 1814248 kb
Host smart-0f62a7c1-0918-4cb8-a65b-d578b11a1dcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264953734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3264953734
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.4156300032
Short name T654
Test name
Test status
Simulation time 12980707938 ps
CPU time 7.47 seconds
Started Jun 06 02:50:11 PM PDT 24
Finished Jun 06 02:50:20 PM PDT 24
Peak memory 213396 kb
Host smart-35e4cd28-967c-4009-900a-f0a8d87a0f1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156300032 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.4156300032
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.1643932275
Short name T1472
Test name
Test status
Simulation time 1047435861 ps
CPU time 15.68 seconds
Started Jun 06 02:50:11 PM PDT 24
Finished Jun 06 02:50:29 PM PDT 24
Peak memory 205068 kb
Host smart-28659ed1-2f97-45c8-a520-fcb63afda4dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643932275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.1643932275
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2464687807
Short name T881
Test name
Test status
Simulation time 42089382 ps
CPU time 0.63 seconds
Started Jun 06 02:50:23 PM PDT 24
Finished Jun 06 02:50:25 PM PDT 24
Peak memory 204676 kb
Host smart-a02696c2-36e9-4ffe-a267-96f4771a3087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464687807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2464687807
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.3557364192
Short name T1064
Test name
Test status
Simulation time 67192259 ps
CPU time 1.32 seconds
Started Jun 06 02:50:17 PM PDT 24
Finished Jun 06 02:50:20 PM PDT 24
Peak memory 216340 kb
Host smart-034c31eb-3ed0-4c3a-ad04-a6559a0ff7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557364192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.3557364192
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.1000783056
Short name T972
Test name
Test status
Simulation time 1020704583 ps
CPU time 4.61 seconds
Started Jun 06 02:50:12 PM PDT 24
Finished Jun 06 02:50:19 PM PDT 24
Peak memory 251976 kb
Host smart-4432758c-bcea-4c0b-b0f6-57321291c367
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000783056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.1000783056
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.849033740
Short name T1178
Test name
Test status
Simulation time 21181662728 ps
CPU time 64.43 seconds
Started Jun 06 02:50:14 PM PDT 24
Finished Jun 06 02:51:21 PM PDT 24
Peak memory 689436 kb
Host smart-75766209-0a60-4d98-bdcf-ea0efcb5ca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849033740 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.849033740
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3502596975
Short name T883
Test name
Test status
Simulation time 2374084394 ps
CPU time 187 seconds
Started Jun 06 02:50:13 PM PDT 24
Finished Jun 06 02:53:22 PM PDT 24
Peak memory 732360 kb
Host smart-3b2beabe-6ac1-425e-bd74-fa832ed7d5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502596975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3502596975
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.2642003607
Short name T218
Test name
Test status
Simulation time 113857961 ps
CPU time 0.91 seconds
Started Jun 06 02:50:14 PM PDT 24
Finished Jun 06 02:50:17 PM PDT 24
Peak memory 204700 kb
Host smart-91ce8dd6-e8b0-436c-860a-534928a77359
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642003607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.2642003607
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3860859297
Short name T1097
Test name
Test status
Simulation time 252558005 ps
CPU time 6.38 seconds
Started Jun 06 02:50:15 PM PDT 24
Finished Jun 06 02:50:23 PM PDT 24
Peak memory 252216 kb
Host smart-05646ef3-afec-4d6d-9e9b-c4bc3bcd48e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860859297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3860859297
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.3141971666
Short name T51
Test name
Test status
Simulation time 2979169761 ps
CPU time 63.66 seconds
Started Jun 06 02:50:14 PM PDT 24
Finished Jun 06 02:51:19 PM PDT 24
Peak memory 898060 kb
Host smart-22ee782f-21b0-4b4a-87c0-604c6df4a7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141971666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.3141971666
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.258683939
Short name T556
Test name
Test status
Simulation time 1434294208 ps
CPU time 14.85 seconds
Started Jun 06 02:50:23 PM PDT 24
Finished Jun 06 02:50:40 PM PDT 24
Peak memory 205032 kb
Host smart-e2320442-7fb8-4e64-907a-db461757ce43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258683939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.258683939
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.896165861
Short name T986
Test name
Test status
Simulation time 4650236496 ps
CPU time 22.53 seconds
Started Jun 06 02:50:20 PM PDT 24
Finished Jun 06 02:50:44 PM PDT 24
Peak memory 343448 kb
Host smart-87d3abde-df9a-4c3b-aaff-fa80d94ed129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896165861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.896165861
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.971910232
Short name T128
Test name
Test status
Simulation time 53980309 ps
CPU time 0.63 seconds
Started Jun 06 02:50:15 PM PDT 24
Finished Jun 06 02:50:18 PM PDT 24
Peak memory 204728 kb
Host smart-5000f432-e2a3-4c9f-9fe5-c7ad3ecc5797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971910232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.971910232
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.556282318
Short name T1009
Test name
Test status
Simulation time 749235784 ps
CPU time 8.91 seconds
Started Jun 06 02:50:14 PM PDT 24
Finished Jun 06 02:50:25 PM PDT 24
Peak memory 205084 kb
Host smart-451ca329-b0cf-4015-9cec-447248d697f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556282318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.556282318
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1167745905
Short name T721
Test name
Test status
Simulation time 28455461938 ps
CPU time 114.87 seconds
Started Jun 06 02:50:51 PM PDT 24
Finished Jun 06 02:52:47 PM PDT 24
Peak memory 470616 kb
Host smart-aec3cdbb-1e63-41af-9545-4987fc25dd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167745905 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1167745905
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.3147521830
Short name T1431
Test name
Test status
Simulation time 69980445211 ps
CPU time 723.78 seconds
Started Jun 06 02:50:11 PM PDT 24
Finished Jun 06 03:02:17 PM PDT 24
Peak memory 1571212 kb
Host smart-fa9a0e6c-5ba3-4bc0-a530-ee967e167534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147521830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3147521830
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1533480515
Short name T326
Test name
Test status
Simulation time 3706227250 ps
CPU time 12.79 seconds
Started Jun 06 02:50:17 PM PDT 24
Finished Jun 06 02:50:32 PM PDT 24
Peak memory 229680 kb
Host smart-30649daa-bf31-4cac-8bdd-df422fa05d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533480515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1533480515
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.916904645
Short name T914
Test name
Test status
Simulation time 3156924043 ps
CPU time 3.69 seconds
Started Jun 06 02:50:24 PM PDT 24
Finished Jun 06 02:50:29 PM PDT 24
Peak memory 205076 kb
Host smart-5a4c2081-e3d0-47ca-8657-f6d08125c57d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916904645 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.916904645
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.404045981
Short name T1179
Test name
Test status
Simulation time 10706295083 ps
CPU time 6.69 seconds
Started Jun 06 02:50:20 PM PDT 24
Finished Jun 06 02:50:28 PM PDT 24
Peak memory 222260 kb
Host smart-933840c5-04c7-466e-b1e9-ac686841cc75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404045981 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_acq.404045981
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.591367495
Short name T1101
Test name
Test status
Simulation time 10230616419 ps
CPU time 39.64 seconds
Started Jun 06 02:50:25 PM PDT 24
Finished Jun 06 02:51:06 PM PDT 24
Peak memory 438368 kb
Host smart-e90c453c-3505-416f-a278-74b4d77490e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591367495 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.i2c_target_fifo_reset_tx.591367495
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.2360551358
Short name T1223
Test name
Test status
Simulation time 1659266947 ps
CPU time 2.23 seconds
Started Jun 06 02:50:21 PM PDT 24
Finished Jun 06 02:50:24 PM PDT 24
Peak memory 205048 kb
Host smart-7ef4c1f2-aa5c-4dd5-81dd-e3be612661d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360551358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.2360551358
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.353161527
Short name T150
Test name
Test status
Simulation time 1163686870 ps
CPU time 1.84 seconds
Started Jun 06 02:50:25 PM PDT 24
Finished Jun 06 02:50:28 PM PDT 24
Peak memory 205088 kb
Host smart-4fdfd456-678e-4221-bc22-66176cacb64b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353161527 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.353161527
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.209402155
Short name T290
Test name
Test status
Simulation time 364860275 ps
CPU time 2.44 seconds
Started Jun 06 02:50:26 PM PDT 24
Finished Jun 06 02:50:30 PM PDT 24
Peak memory 205160 kb
Host smart-36402c0a-7990-4223-b640-6f5c150499f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209402155 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_hrst.209402155
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.3374210486
Short name T1352
Test name
Test status
Simulation time 996287187 ps
CPU time 5.29 seconds
Started Jun 06 02:50:21 PM PDT 24
Finished Jun 06 02:50:28 PM PDT 24
Peak memory 217332 kb
Host smart-7397002a-0ddc-4647-a2fa-b3118bbfbeee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374210486 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.3374210486
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.3907367027
Short name T1149
Test name
Test status
Simulation time 19714885607 ps
CPU time 6.24 seconds
Started Jun 06 02:50:23 PM PDT 24
Finished Jun 06 02:50:31 PM PDT 24
Peak memory 205140 kb
Host smart-1a738e2b-78dc-4bff-a252-93c06d7b0d7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907367027 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.3907367027
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.3201834385
Short name T1099
Test name
Test status
Simulation time 535032017 ps
CPU time 20.09 seconds
Started Jun 06 02:50:15 PM PDT 24
Finished Jun 06 02:50:37 PM PDT 24
Peak memory 205044 kb
Host smart-e71bd5d6-79bc-4b92-98e6-0cf43dacdd21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201834385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.3201834385
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.4066952587
Short name T1204
Test name
Test status
Simulation time 1234203515 ps
CPU time 12.96 seconds
Started Jun 06 02:50:13 PM PDT 24
Finished Jun 06 02:50:27 PM PDT 24
Peak memory 205084 kb
Host smart-f74aabc2-efda-47eb-89ee-64622ddd2d89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066952587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.4066952587
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1516759388
Short name T622
Test name
Test status
Simulation time 17523212075 ps
CPU time 31.2 seconds
Started Jun 06 02:50:14 PM PDT 24
Finished Jun 06 02:50:47 PM PDT 24
Peak memory 205168 kb
Host smart-4e0339e7-8527-42f2-818e-5b231cd5a047
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516759388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1516759388
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.4256322575
Short name T298
Test name
Test status
Simulation time 7489862216 ps
CPU time 249.71 seconds
Started Jun 06 02:50:23 PM PDT 24
Finished Jun 06 02:54:34 PM PDT 24
Peak memory 1067336 kb
Host smart-71f463e1-c66c-4334-a67d-0bbf56c04abe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256322575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.4256322575
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3979314204
Short name T63
Test name
Test status
Simulation time 5085671109 ps
CPU time 6.9 seconds
Started Jun 06 02:50:25 PM PDT 24
Finished Jun 06 02:50:34 PM PDT 24
Peak memory 213424 kb
Host smart-59ce36be-8919-40fa-bb10-b82e2a933541
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979314204 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3979314204
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.2583662573
Short name T1274
Test name
Test status
Simulation time 1204302989 ps
CPU time 18.73 seconds
Started Jun 06 02:50:23 PM PDT 24
Finished Jun 06 02:50:44 PM PDT 24
Peak memory 205040 kb
Host smart-978ef19b-fefa-45dc-8cb8-db21e6a6f22f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583662573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.2583662573
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.2193285177
Short name T373
Test name
Test status
Simulation time 34220258 ps
CPU time 0.6 seconds
Started Jun 06 02:50:29 PM PDT 24
Finished Jun 06 02:50:32 PM PDT 24
Peak memory 204756 kb
Host smart-4610eb31-9950-4f05-a8ab-8e834769ba80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193285177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.2193285177
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.4166270296
Short name T1047
Test name
Test status
Simulation time 111442968 ps
CPU time 1.77 seconds
Started Jun 06 02:50:26 PM PDT 24
Finished Jun 06 02:50:30 PM PDT 24
Peak memory 213336 kb
Host smart-219e8327-9b62-4299-b2d0-d2ecd579b294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166270296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.4166270296
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2333120210
Short name T60
Test name
Test status
Simulation time 1365978617 ps
CPU time 5.64 seconds
Started Jun 06 02:50:26 PM PDT 24
Finished Jun 06 02:50:34 PM PDT 24
Peak memory 248868 kb
Host smart-e9147241-ded2-4ada-a6a6-3bd67e7ee71b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333120210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2333120210
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.3100417360
Short name T729
Test name
Test status
Simulation time 11243645755 ps
CPU time 189.76 seconds
Started Jun 06 02:50:30 PM PDT 24
Finished Jun 06 02:53:42 PM PDT 24
Peak memory 787276 kb
Host smart-713abf82-c350-4182-9a6f-8d39a4113b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100417360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.3100417360
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2952627527
Short name T904
Test name
Test status
Simulation time 2066971460 ps
CPU time 164.75 seconds
Started Jun 06 02:50:35 PM PDT 24
Finished Jun 06 02:53:21 PM PDT 24
Peak memory 718096 kb
Host smart-b6d3c98f-e438-430d-87ee-5cac58e30142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952627527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2952627527
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.1493407062
Short name T518
Test name
Test status
Simulation time 87209902 ps
CPU time 0.85 seconds
Started Jun 06 02:50:25 PM PDT 24
Finished Jun 06 02:50:28 PM PDT 24
Peak memory 204736 kb
Host smart-a47f27d5-1fa0-440b-8d2b-c37de0adf685
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493407062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.1493407062
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3779200299
Short name T1454
Test name
Test status
Simulation time 218062499 ps
CPU time 12.83 seconds
Started Jun 06 02:50:32 PM PDT 24
Finished Jun 06 02:50:46 PM PDT 24
Peak memory 248012 kb
Host smart-47900ded-e0b6-4ec5-8e48-53b117892ed4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779200299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3779200299
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.2658090515
Short name T1276
Test name
Test status
Simulation time 21282286244 ps
CPU time 441.19 seconds
Started Jun 06 02:50:24 PM PDT 24
Finished Jun 06 02:57:46 PM PDT 24
Peak memory 1506608 kb
Host smart-16b71672-5016-4c0c-9aac-f75eab964290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658090515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.2658090515
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.1502525598
Short name T393
Test name
Test status
Simulation time 1053432452 ps
CPU time 10.95 seconds
Started Jun 06 02:50:35 PM PDT 24
Finished Jun 06 02:50:46 PM PDT 24
Peak memory 205216 kb
Host smart-6744adc0-b495-4f3b-bc8d-09be6771921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502525598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.1502525598
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.527776034
Short name T57
Test name
Test status
Simulation time 5482506524 ps
CPU time 27.12 seconds
Started Jun 06 02:50:37 PM PDT 24
Finished Jun 06 02:51:05 PM PDT 24
Peak memory 274500 kb
Host smart-bc9700b4-0368-4bd0-9931-06d9dc968980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527776034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.527776034
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.282793770
Short name T862
Test name
Test status
Simulation time 17239191 ps
CPU time 0.65 seconds
Started Jun 06 02:50:25 PM PDT 24
Finished Jun 06 02:50:28 PM PDT 24
Peak memory 204688 kb
Host smart-05309030-cde2-4327-a673-451e109f8cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282793770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.282793770
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2905204036
Short name T1314
Test name
Test status
Simulation time 2590516945 ps
CPU time 73.11 seconds
Started Jun 06 02:50:27 PM PDT 24
Finished Jun 06 02:51:42 PM PDT 24
Peak memory 492252 kb
Host smart-6a03a3d0-6086-4aeb-9bd9-20889c95f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905204036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2905204036
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.3319284491
Short name T492
Test name
Test status
Simulation time 8621277267 ps
CPU time 28.02 seconds
Started Jun 06 02:50:25 PM PDT 24
Finished Jun 06 02:50:54 PM PDT 24
Peak memory 341084 kb
Host smart-3101ff8e-f20b-49ed-ab3b-3ed225335318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319284491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3319284491
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2106992373
Short name T376
Test name
Test status
Simulation time 3103254958 ps
CPU time 35.9 seconds
Started Jun 06 02:50:29 PM PDT 24
Finished Jun 06 02:51:07 PM PDT 24
Peak memory 213432 kb
Host smart-62dcf91b-993d-4c8e-9e08-9d6386ee9e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106992373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2106992373
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.274104314
Short name T480
Test name
Test status
Simulation time 1012043358 ps
CPU time 3.29 seconds
Started Jun 06 02:50:29 PM PDT 24
Finished Jun 06 02:50:33 PM PDT 24
Peak memory 213256 kb
Host smart-adbc9d03-1653-4d83-a2e2-bc8b45154d0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274104314 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.274104314
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2545665410
Short name T542
Test name
Test status
Simulation time 10355287234 ps
CPU time 12.86 seconds
Started Jun 06 02:50:36 PM PDT 24
Finished Jun 06 02:50:51 PM PDT 24
Peak memory 261336 kb
Host smart-0d1196d8-09c1-49c1-aa2a-642d03d8550f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545665410 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2545665410
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.1162367320
Short name T1215
Test name
Test status
Simulation time 10093621166 ps
CPU time 70.87 seconds
Started Jun 06 02:50:37 PM PDT 24
Finished Jun 06 02:51:50 PM PDT 24
Peak memory 641572 kb
Host smart-08536fdc-6d87-414e-9268-bca813f68e6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162367320 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.1162367320
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.2627400229
Short name T995
Test name
Test status
Simulation time 1879105482 ps
CPU time 2.55 seconds
Started Jun 06 02:50:37 PM PDT 24
Finished Jun 06 02:50:41 PM PDT 24
Peak memory 205184 kb
Host smart-41d2de02-9421-49ec-8aab-b3f35cb16a57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627400229 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.2627400229
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.1161378797
Short name T1375
Test name
Test status
Simulation time 1441858949 ps
CPU time 2.49 seconds
Started Jun 06 02:50:31 PM PDT 24
Finished Jun 06 02:50:35 PM PDT 24
Peak memory 205136 kb
Host smart-b1fc86a6-f466-41b9-a831-e25b990336c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161378797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.1161378797
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.3677403545
Short name T228
Test name
Test status
Simulation time 1906499105 ps
CPU time 2.89 seconds
Started Jun 06 02:50:28 PM PDT 24
Finished Jun 06 02:50:32 PM PDT 24
Peak memory 205060 kb
Host smart-e16efbe9-f86a-48d9-acea-41af740727e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677403545 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.3677403545
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2192120711
Short name T1260
Test name
Test status
Simulation time 787880608 ps
CPU time 4.51 seconds
Started Jun 06 02:50:36 PM PDT 24
Finished Jun 06 02:50:42 PM PDT 24
Peak memory 205068 kb
Host smart-6003c508-1f1e-4b0e-a510-e469bcc37b6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192120711 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2192120711
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.1406082859
Short name T1159
Test name
Test status
Simulation time 6207195732 ps
CPU time 67.25 seconds
Started Jun 06 02:50:37 PM PDT 24
Finished Jun 06 02:51:46 PM PDT 24
Peak memory 1625084 kb
Host smart-1e34c906-1f6b-4ea2-a01c-5355d37a2851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406082859 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.1406082859
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.4267223273
Short name T1471
Test name
Test status
Simulation time 1095615878 ps
CPU time 15.04 seconds
Started Jun 06 02:50:36 PM PDT 24
Finished Jun 06 02:50:52 PM PDT 24
Peak memory 205068 kb
Host smart-3c8fde55-acf3-4821-a3c5-2737f3ec8627
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267223273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.4267223273
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.4020237904
Short name T1207
Test name
Test status
Simulation time 3728233297 ps
CPU time 14.22 seconds
Started Jun 06 02:50:24 PM PDT 24
Finished Jun 06 02:50:39 PM PDT 24
Peak memory 217604 kb
Host smart-08e4177c-6da6-47a1-ae72-5bacd63cfb2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020237904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.4020237904
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.3859252954
Short name T949
Test name
Test status
Simulation time 11267376255 ps
CPU time 11.74 seconds
Started Jun 06 02:50:36 PM PDT 24
Finished Jun 06 02:50:50 PM PDT 24
Peak memory 205044 kb
Host smart-5e1d463c-d111-4a57-bfef-d01b108a968c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859252954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.3859252954
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2872573155
Short name T933
Test name
Test status
Simulation time 18255382980 ps
CPU time 299.67 seconds
Started Jun 06 02:50:24 PM PDT 24
Finished Jun 06 02:55:25 PM PDT 24
Peak memory 1056424 kb
Host smart-e205e28c-5e84-45b1-a4ce-ce87838b8d50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872573155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2872573155
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1937144941
Short name T1036
Test name
Test status
Simulation time 6169837106 ps
CPU time 7.11 seconds
Started Jun 06 02:50:30 PM PDT 24
Finished Jun 06 02:50:39 PM PDT 24
Peak memory 221332 kb
Host smart-8d461dd4-883a-4c76-a0ff-b04fe8711554
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937144941 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1937144941
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.80595171
Short name T943
Test name
Test status
Simulation time 1338764085 ps
CPU time 18.21 seconds
Started Jun 06 02:50:29 PM PDT 24
Finished Jun 06 02:50:49 PM PDT 24
Peak memory 205080 kb
Host smart-ab520a58-390e-48a2-96c0-3d34ce00638c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80595171 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.80595171
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.858460461
Short name T1180
Test name
Test status
Simulation time 40065368 ps
CPU time 0.63 seconds
Started Jun 06 02:50:48 PM PDT 24
Finished Jun 06 02:50:51 PM PDT 24
Peak memory 204732 kb
Host smart-df69a458-2ab4-4f45-81b2-403705340367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858460461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.858460461
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.2080155302
Short name T611
Test name
Test status
Simulation time 184474145 ps
CPU time 2.55 seconds
Started Jun 06 02:50:39 PM PDT 24
Finished Jun 06 02:50:44 PM PDT 24
Peak memory 213280 kb
Host smart-6c9a753d-7900-41f3-993a-c830567a4cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080155302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.2080155302
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.3898916540
Short name T4
Test name
Test status
Simulation time 832603209 ps
CPU time 6.49 seconds
Started Jun 06 02:50:37 PM PDT 24
Finished Jun 06 02:50:45 PM PDT 24
Peak memory 259532 kb
Host smart-ddc7985d-27bb-44e1-8a7f-1d9ce1b0968f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898916540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.3898916540
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.2986998172
Short name T495
Test name
Test status
Simulation time 2852553705 ps
CPU time 85.76 seconds
Started Jun 06 02:50:39 PM PDT 24
Finished Jun 06 02:52:07 PM PDT 24
Peak memory 763804 kb
Host smart-b2349264-c7b4-453d-b551-c253f68462ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986998172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.2986998172
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.1339217643
Short name T294
Test name
Test status
Simulation time 3854689455 ps
CPU time 99.98 seconds
Started Jun 06 02:50:30 PM PDT 24
Finished Jun 06 02:52:12 PM PDT 24
Peak memory 525224 kb
Host smart-928c27b1-b4be-45cc-9993-a078d23f1e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339217643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.1339217643
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.732125624
Short name T1281
Test name
Test status
Simulation time 237222749 ps
CPU time 0.88 seconds
Started Jun 06 02:50:30 PM PDT 24
Finished Jun 06 02:50:32 PM PDT 24
Peak memory 204752 kb
Host smart-8854b63c-87d5-4741-85a4-3b30d6932d80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732125624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt
.732125624
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.3178628465
Short name T956
Test name
Test status
Simulation time 571535517 ps
CPU time 4.3 seconds
Started Jun 06 02:50:40 PM PDT 24
Finished Jun 06 02:50:46 PM PDT 24
Peak memory 227148 kb
Host smart-ca7e8e6b-0b66-4a5a-8482-7b91aa567cb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178628465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
3178628465
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.1381375068
Short name T815
Test name
Test status
Simulation time 2618644219 ps
CPU time 177.41 seconds
Started Jun 06 02:50:29 PM PDT 24
Finished Jun 06 02:53:28 PM PDT 24
Peak memory 855728 kb
Host smart-19575ced-16d2-4e43-94de-028c3314e383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381375068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.1381375068
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.2214417349
Short name T779
Test name
Test status
Simulation time 1089431599 ps
CPU time 4.3 seconds
Started Jun 06 02:51:06 PM PDT 24
Finished Jun 06 02:51:14 PM PDT 24
Peak memory 205092 kb
Host smart-81b37556-d931-4562-9c85-c1a600d33234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214417349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.2214417349
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.3388041827
Short name T588
Test name
Test status
Simulation time 7308061658 ps
CPU time 36.84 seconds
Started Jun 06 02:50:54 PM PDT 24
Finished Jun 06 02:51:32 PM PDT 24
Peak memory 346508 kb
Host smart-1f00aefe-2126-4b69-b9e1-f4e273a8cb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388041827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.3388041827
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2855771356
Short name T1076
Test name
Test status
Simulation time 29050550 ps
CPU time 0.7 seconds
Started Jun 06 02:50:30 PM PDT 24
Finished Jun 06 02:50:33 PM PDT 24
Peak memory 204764 kb
Host smart-ac06cdf8-40fb-4445-bb48-5a9a96e547fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855771356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2855771356
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2880083502
Short name T497
Test name
Test status
Simulation time 49851824381 ps
CPU time 545.58 seconds
Started Jun 06 02:50:39 PM PDT 24
Finished Jun 06 02:59:46 PM PDT 24
Peak memory 2416888 kb
Host smart-3e54a3c2-4bfc-4f10-9e1f-2c1aa021b15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880083502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2880083502
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2773606123
Short name T429
Test name
Test status
Simulation time 1923273218 ps
CPU time 37.43 seconds
Started Jun 06 02:50:37 PM PDT 24
Finished Jun 06 02:51:16 PM PDT 24
Peak memory 421864 kb
Host smart-2a564b8c-529f-44a9-8764-ffa7c54ffb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773606123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2773606123
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.3982132459
Short name T1071
Test name
Test status
Simulation time 1512733816 ps
CPU time 20.05 seconds
Started Jun 06 02:50:40 PM PDT 24
Finished Jun 06 02:51:01 PM PDT 24
Peak memory 213304 kb
Host smart-d6abc245-7c3c-452f-b5d7-eab76443be9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982132459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.3982132459
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.337049655
Short name T892
Test name
Test status
Simulation time 19412533259 ps
CPU time 5.32 seconds
Started Jun 06 02:50:47 PM PDT 24
Finished Jun 06 02:50:54 PM PDT 24
Peak memory 205144 kb
Host smart-641d945a-f7a5-43b3-935f-ee5ce62d2df3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337049655 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.337049655
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3450998470
Short name T1266
Test name
Test status
Simulation time 10288998454 ps
CPU time 8.65 seconds
Started Jun 06 02:50:40 PM PDT 24
Finished Jun 06 02:50:50 PM PDT 24
Peak memory 229800 kb
Host smart-157d2b0a-f215-436b-b5ce-e8e859f8b0c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450998470 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3450998470
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.1432004329
Short name T348
Test name
Test status
Simulation time 10118660595 ps
CPU time 36.91 seconds
Started Jun 06 02:50:40 PM PDT 24
Finished Jun 06 02:51:19 PM PDT 24
Peak memory 454484 kb
Host smart-24f5951c-7571-4818-ab7f-976ddb0a91e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432004329 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.1432004329
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.2163591191
Short name T308
Test name
Test status
Simulation time 1353141240 ps
CPU time 6.08 seconds
Started Jun 06 02:50:55 PM PDT 24
Finished Jun 06 02:51:02 PM PDT 24
Peak memory 205244 kb
Host smart-652d29a2-24e7-4653-83a7-1fedfabf9bf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163591191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.2163591191
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.4264074215
Short name T689
Test name
Test status
Simulation time 1361299922 ps
CPU time 1.83 seconds
Started Jun 06 02:50:49 PM PDT 24
Finished Jun 06 02:50:53 PM PDT 24
Peak memory 205096 kb
Host smart-c2539dd3-f44e-4f1f-b034-2a3c79a1cf37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264074215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.4264074215
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1156946156
Short name T1053
Test name
Test status
Simulation time 2331412880 ps
CPU time 3.25 seconds
Started Jun 06 02:50:50 PM PDT 24
Finished Jun 06 02:50:55 PM PDT 24
Peak memory 205136 kb
Host smart-aa9faad9-9e63-416b-bc2d-d2f799f40e96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156946156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1156946156
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3036495189
Short name T1412
Test name
Test status
Simulation time 1571689666 ps
CPU time 8.36 seconds
Started Jun 06 02:50:40 PM PDT 24
Finished Jun 06 02:50:50 PM PDT 24
Peak memory 221308 kb
Host smart-935f9b78-ed5d-40c8-b5c3-9e9401fb7e21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036495189 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3036495189
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.720342597
Short name T1111
Test name
Test status
Simulation time 4989492087 ps
CPU time 3.94 seconds
Started Jun 06 02:50:41 PM PDT 24
Finished Jun 06 02:50:47 PM PDT 24
Peak memory 205180 kb
Host smart-0a1a4baa-2601-4683-b1e3-e70362e559f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720342597 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.720342597
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.815404709
Short name T668
Test name
Test status
Simulation time 4101581487 ps
CPU time 14.46 seconds
Started Jun 06 02:50:41 PM PDT 24
Finished Jun 06 02:50:57 PM PDT 24
Peak memory 205072 kb
Host smart-5035d523-1a09-47f3-a155-abdbbc3c3e51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815404709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.815404709
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.3422606106
Short name T1145
Test name
Test status
Simulation time 3207609291 ps
CPU time 25.8 seconds
Started Jun 06 02:50:40 PM PDT 24
Finished Jun 06 02:51:08 PM PDT 24
Peak memory 232996 kb
Host smart-7518f924-5898-44df-8961-6ed4ebbf532a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422606106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.3422606106
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2587435299
Short name T238
Test name
Test status
Simulation time 37475505669 ps
CPU time 729.28 seconds
Started Jun 06 02:50:41 PM PDT 24
Finished Jun 06 03:02:52 PM PDT 24
Peak memory 1948856 kb
Host smart-d81a17fd-d781-4d30-aee2-2b1edc2ec7de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587435299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2587435299
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.2834141189
Short name T1428
Test name
Test status
Simulation time 4844701610 ps
CPU time 7.84 seconds
Started Jun 06 02:50:40 PM PDT 24
Finished Jun 06 02:50:50 PM PDT 24
Peak memory 216192 kb
Host smart-fad6e8c2-d196-4c52-bae5-aa867200f293
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834141189 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.2834141189
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.217454364
Short name T637
Test name
Test status
Simulation time 1122400688 ps
CPU time 15.8 seconds
Started Jun 06 02:50:48 PM PDT 24
Finished Jun 06 02:51:05 PM PDT 24
Peak memory 205084 kb
Host smart-f449d992-d65c-4977-8d7a-5be9e31b0a8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217454364 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.217454364
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1278723001
Short name T793
Test name
Test status
Simulation time 24153790 ps
CPU time 0.62 seconds
Started Jun 06 02:51:01 PM PDT 24
Finished Jun 06 02:51:03 PM PDT 24
Peak memory 204696 kb
Host smart-40adeee1-580d-4274-91ab-4eab80ae2992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278723001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1278723001
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1867435318
Short name T353
Test name
Test status
Simulation time 891150123 ps
CPU time 7.04 seconds
Started Jun 06 02:50:49 PM PDT 24
Finished Jun 06 02:50:57 PM PDT 24
Peak memory 213292 kb
Host smart-9129e29f-63c0-44b6-988d-a0ba748f7048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867435318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1867435318
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.1412687299
Short name T978
Test name
Test status
Simulation time 431876981 ps
CPU time 8.63 seconds
Started Jun 06 02:50:48 PM PDT 24
Finished Jun 06 02:50:58 PM PDT 24
Peak memory 285284 kb
Host smart-f91ee42c-bf33-47c9-ac96-7d2eb7926c66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412687299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.1412687299
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.3022234836
Short name T147
Test name
Test status
Simulation time 2346722458 ps
CPU time 138.21 seconds
Started Jun 06 02:50:48 PM PDT 24
Finished Jun 06 02:53:08 PM PDT 24
Peak memory 461520 kb
Host smart-756d7cc4-3ef4-4985-aca3-536c9be93e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022234836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.3022234836
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.563292250
Short name T145
Test name
Test status
Simulation time 1927310470 ps
CPU time 149.74 seconds
Started Jun 06 02:50:50 PM PDT 24
Finished Jun 06 02:53:22 PM PDT 24
Peak memory 683844 kb
Host smart-f214110b-3c11-429e-b32d-c1ca5c7d76e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563292250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.563292250
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1304299101
Short name T647
Test name
Test status
Simulation time 430305299 ps
CPU time 0.94 seconds
Started Jun 06 02:50:49 PM PDT 24
Finished Jun 06 02:50:52 PM PDT 24
Peak memory 204716 kb
Host smart-969a9fe6-8f90-46d8-a145-87f35ecfd12d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304299101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1304299101
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1614899416
Short name T578
Test name
Test status
Simulation time 451947969 ps
CPU time 4.72 seconds
Started Jun 06 02:50:51 PM PDT 24
Finished Jun 06 02:50:57 PM PDT 24
Peak memory 236456 kb
Host smart-6ec7603d-57c6-4711-aa11-3d4c124bd48c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614899416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1614899416
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3085750678
Short name T1029
Test name
Test status
Simulation time 3491856423 ps
CPU time 60.79 seconds
Started Jun 06 02:50:49 PM PDT 24
Finished Jun 06 02:51:51 PM PDT 24
Peak memory 844236 kb
Host smart-f7c971b3-6f97-4958-82c3-1376318954ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085750678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3085750678
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.4079436784
Short name T444
Test name
Test status
Simulation time 609519148 ps
CPU time 7.82 seconds
Started Jun 06 02:51:00 PM PDT 24
Finished Jun 06 02:51:10 PM PDT 24
Peak memory 205048 kb
Host smart-5ea4b785-ba45-460b-9a28-3dc767b37ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079436784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.4079436784
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2586961286
Short name T1323
Test name
Test status
Simulation time 2512956216 ps
CPU time 121.45 seconds
Started Jun 06 02:50:57 PM PDT 24
Finished Jun 06 02:53:01 PM PDT 24
Peak memory 525684 kb
Host smart-06205402-d29f-4691-a07f-0c0008670b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586961286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2586961286
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.529051664
Short name T133
Test name
Test status
Simulation time 28942473 ps
CPU time 0.68 seconds
Started Jun 06 02:50:48 PM PDT 24
Finished Jun 06 02:50:51 PM PDT 24
Peak memory 204696 kb
Host smart-5d5f9be5-0ed2-4640-8b80-59d082f325fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529051664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.529051664
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.622630611
Short name T855
Test name
Test status
Simulation time 3333926887 ps
CPU time 29.61 seconds
Started Jun 06 02:50:47 PM PDT 24
Finished Jun 06 02:51:18 PM PDT 24
Peak memory 491660 kb
Host smart-818a4b57-f825-4133-ab92-2ba7b6c38d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622630611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.622630611
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.413884975
Short name T1147
Test name
Test status
Simulation time 1270595582 ps
CPU time 25.01 seconds
Started Jun 06 02:50:50 PM PDT 24
Finished Jun 06 02:51:17 PM PDT 24
Peak memory 326704 kb
Host smart-c1e1bb01-775a-4023-a88b-6c8fc6cfcee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413884975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.413884975
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2272840678
Short name T207
Test name
Test status
Simulation time 31252758656 ps
CPU time 1597.47 seconds
Started Jun 06 02:50:48 PM PDT 24
Finished Jun 06 03:17:27 PM PDT 24
Peak memory 2621728 kb
Host smart-ed09abc8-6d53-4e53-92ce-a0ffc6c83962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272840678 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2272840678
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2864804040
Short name T124
Test name
Test status
Simulation time 900517202 ps
CPU time 14.95 seconds
Started Jun 06 02:50:50 PM PDT 24
Finished Jun 06 02:51:06 PM PDT 24
Peak memory 221536 kb
Host smart-08052fa5-e132-4a49-84c6-b67385f0c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864804040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2864804040
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.3832623465
Short name T1094
Test name
Test status
Simulation time 3151194044 ps
CPU time 3.36 seconds
Started Jun 06 02:50:59 PM PDT 24
Finished Jun 06 02:51:04 PM PDT 24
Peak memory 205140 kb
Host smart-866e47f1-b56d-4191-a3f7-ff4cb23a4d06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832623465 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.3832623465
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1542298023
Short name T1426
Test name
Test status
Simulation time 10154698674 ps
CPU time 41.99 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:51:41 PM PDT 24
Peak memory 324568 kb
Host smart-1764640d-9a4c-4b6c-8b80-c19846571f32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542298023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1542298023
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.502971871
Short name T1104
Test name
Test status
Simulation time 10607415968 ps
CPU time 12.4 seconds
Started Jun 06 02:50:58 PM PDT 24
Finished Jun 06 02:51:12 PM PDT 24
Peak memory 302672 kb
Host smart-f773fb8d-05ab-4e29-a1fa-bfa32f1431db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502971871 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.502971871
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.4259943930
Short name T1315
Test name
Test status
Simulation time 1527418630 ps
CPU time 2.26 seconds
Started Jun 06 02:50:59 PM PDT 24
Finished Jun 06 02:51:03 PM PDT 24
Peak memory 205044 kb
Host smart-b2429ce6-1007-4bcb-ac34-04d9b6f4ced0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259943930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.4259943930
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.2875856930
Short name T921
Test name
Test status
Simulation time 1069868439 ps
CPU time 5.7 seconds
Started Jun 06 02:50:57 PM PDT 24
Finished Jun 06 02:51:03 PM PDT 24
Peak memory 205028 kb
Host smart-eec7a49a-d1c5-4bb0-a09c-606ad7f91899
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875856930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.2875856930
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1167807623
Short name T1441
Test name
Test status
Simulation time 1987605326 ps
CPU time 2.98 seconds
Started Jun 06 02:50:57 PM PDT 24
Finished Jun 06 02:51:02 PM PDT 24
Peak memory 205112 kb
Host smart-eb80d4e7-72be-4132-98a8-f8700d8931b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167807623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1167807623
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.864905158
Short name T734
Test name
Test status
Simulation time 1024469637 ps
CPU time 5.36 seconds
Started Jun 06 02:50:55 PM PDT 24
Finished Jun 06 02:51:01 PM PDT 24
Peak memory 205260 kb
Host smart-f2a8089d-6718-4f04-8ca6-aa9005cc7fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864905158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.864905158
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2813855086
Short name T1152
Test name
Test status
Simulation time 11108030922 ps
CPU time 23.18 seconds
Started Jun 06 02:50:50 PM PDT 24
Finished Jun 06 02:51:15 PM PDT 24
Peak memory 555736 kb
Host smart-dc0aad71-a8c0-46ae-bf39-241d54968215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813855086 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2813855086
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1891349442
Short name T1358
Test name
Test status
Simulation time 3930179060 ps
CPU time 44.88 seconds
Started Jun 06 02:50:49 PM PDT 24
Finished Jun 06 02:51:35 PM PDT 24
Peak memory 205092 kb
Host smart-be29bea5-d4ad-45a8-9b3b-3cc677a05cbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891349442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1891349442
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1927004010
Short name T476
Test name
Test status
Simulation time 4981776927 ps
CPU time 16.1 seconds
Started Jun 06 02:50:48 PM PDT 24
Finished Jun 06 02:51:05 PM PDT 24
Peak memory 213148 kb
Host smart-a5847d18-02da-4ed3-ba8d-a894749e0ca7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927004010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1927004010
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.2829639242
Short name T1198
Test name
Test status
Simulation time 13751594469 ps
CPU time 7.71 seconds
Started Jun 06 02:50:50 PM PDT 24
Finished Jun 06 02:50:59 PM PDT 24
Peak memory 205100 kb
Host smart-519d8f29-070e-414f-bb6d-a957feeb5f4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829639242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.2829639242
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2755800722
Short name T642
Test name
Test status
Simulation time 25901671929 ps
CPU time 507.98 seconds
Started Jun 06 02:50:48 PM PDT 24
Finished Jun 06 02:59:18 PM PDT 24
Peak memory 1517248 kb
Host smart-b734f27e-49ce-4bd8-a663-75fdf7d82b33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755800722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2755800722
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1043029630
Short name T701
Test name
Test status
Simulation time 1443368683 ps
CPU time 7.63 seconds
Started Jun 06 02:50:57 PM PDT 24
Finished Jun 06 02:51:06 PM PDT 24
Peak memory 205116 kb
Host smart-c7d59523-9374-497c-9309-e68779f5ddfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043029630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1043029630
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.3534904973
Short name T655
Test name
Test status
Simulation time 1108846559 ps
CPU time 15.32 seconds
Started Jun 06 02:50:59 PM PDT 24
Finished Jun 06 02:51:16 PM PDT 24
Peak memory 205096 kb
Host smart-c29d867c-89af-4895-ba08-4b1dbdec3d84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534904973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.3534904973
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%