Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	997698	1			T1	8		T2	2		T3	4
all_values[1]	997698	1			T1	8		T2	2		T3	4
all_values[2]	997698	1			T1	8		T2	2		T3	4
all_values[3]	997698	1			T1	8		T2	2		T3	4
all_values[4]	997698	1			T1	8		T2	2		T3	4
all_values[5]	997698	1			T1	8		T2	2		T3	4
all_values[6]	997698	1			T1	8		T2	2		T3	4
all_values[7]	997698	1			T1	8		T2	2		T3	4
all_values[8]	997698	1			T1	8		T2	2		T3	4
all_values[9]	997698	1			T1	8		T2	2		T3	4
all_values[10]	997698	1			T1	8		T2	2		T3	4
all_values[11]	997698	1			T1	8		T2	2		T3	4
all_values[12]	997698	1			T1	8		T2	2		T3	4
all_values[13]	997698	1			T1	8		T2	2		T3	4
all_values[14]	997698	1			T1	8		T2	2		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12188217

1

T1

101

T2

26

T3

49

auto[1]

2777253

1

T1

19

T2

4

T3

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12980496

1

T1

120

T2

30

T3

60

auto[1]

1984974

1

T40

396814

T41

58841

T42

28166

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	81944	1			T4	579		T8	2248		T9	2026
all_values[0]	auto[0]	auto[1]	11699	1			T40	5802		T41	34		T42	24
all_values[0]	auto[1]	auto[0]	789237	1			T1	8		T2	2		T3	4
all_values[0]	auto[1]	auto[1]	114818	1			T40	20653		T41	4493		T42	1989
all_values[1]	auto[0]	auto[0]	859065	1			T1	8		T2	2		T3	4
all_values[1]	auto[0]	auto[1]	137924	1			T40	26445		T41	4524		T42	2010
all_values[1]	auto[1]	auto[0]	443	1			T10	2		T42	1		T49	23
all_values[1]	auto[1]	auto[1]	266	1			T40	9		T41	1		T42	2
all_values[2]	auto[0]	auto[0]	859364	1			T1	8		T2	2		T3	3
all_values[2]	auto[0]	auto[1]	138015	1			T40	26452		T41	4525		T42	2011
all_values[2]	auto[1]	auto[0]	109	1			T3	1		T18	3		T19	3
all_values[2]	auto[1]	auto[1]	210	1			T40	1		T41	1		T42	2
all_values[3]	auto[0]	auto[0]	864501	1			T1	8		T2	2		T3	4
all_values[3]	auto[0]	auto[1]	132984	1			T40	26452		T41	4525		T42	2011
all_values[3]	auto[1]	auto[1]	213	1			T40	3		T42	1		T49	3
all_values[4]	auto[0]	auto[0]	859459	1			T1	8		T2	2		T3	4
all_values[4]	auto[0]	auto[1]	138012	1			T40	26453		T41	4526		T42	2011
all_values[4]	auto[1]	auto[0]	18	1			T45	1		T135	1		T218	1
all_values[4]	auto[1]	auto[1]	209	1			T40	2		T41	1		T42	1
all_values[5]	auto[0]	auto[0]	887696	1			T1	8		T2	2		T3	4
all_values[5]	auto[0]	auto[1]	109758	1			T40	26451		T42	2009		T49	4841
all_values[5]	auto[1]	auto[1]	244	1			T40	3		T42	2		T49	6
all_values[6]	auto[0]	auto[0]	859509	1			T1	8		T2	2		T3	4
all_values[6]	auto[0]	auto[1]	137955	1			T40	26451		T41	4523		T42	2009
all_values[6]	auto[1]	auto[1]	234	1			T40	4		T41	3		T42	3
all_values[7]	auto[0]	auto[0]	839016	1			T1	8		T2	2		T3	4
all_values[7]	auto[0]	auto[1]	127252	1			T40	26104		T41	4259		T42	1907
all_values[7]	auto[1]	auto[0]	27266	1			T4	138		T8	8		T9	318
all_values[7]	auto[1]	auto[1]	4164	1			T40	351		T41	268		T42	105
all_values[8]	auto[0]	auto[0]	859455	1			T1	8		T2	2		T3	4
all_values[8]	auto[0]	auto[1]	137996	1			T40	26453		T41	4525		T42	2011
all_values[8]	auto[1]	auto[1]	247	1			T41	1		T49	4		T57	4
all_values[9]	auto[0]	auto[0]	138108	1			T1	5		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	15331	1			T40	759		T41	457		T42	369
all_values[9]	auto[1]	auto[0]	721378	1			T1	3		T3	1		T4	3
all_values[9]	auto[1]	auto[1]	122881	1			T40	25695		T41	4069		T42	1643
all_values[10]	auto[0]	auto[0]	888599	1			T1	8		T2	2		T3	4
all_values[10]	auto[0]	auto[1]	108902	1			T40	26452		T41	4524		T42	2011
all_values[10]	auto[1]	auto[1]	197	1			T40	2		T41	3		T42	1
all_values[11]	auto[0]	auto[0]	2671	1			T4	2		T8	2		T9	26
all_values[11]	auto[0]	auto[1]	632	1			T40	12		T49	12		T57	3
all_values[11]	auto[1]	auto[0]	863634	1			T1	8		T2	2		T3	4
all_values[11]	auto[1]	auto[1]	130761	1			T40	26441		T49	4832		T57	2950
all_values[12]	auto[0]	auto[0]	859430	1			T1	8		T2	2		T3	3
all_values[12]	auto[0]	auto[1]	138028	1			T40	26453		T41	4526		T42	2011
all_values[12]	auto[1]	auto[0]	24	1			T3	1		T138	2		T219	1
all_values[12]	auto[1]	auto[1]	216	1			T40	2		T41	1		T42	1
all_values[13]	auto[0]	auto[0]	860076	1			T1	8		T2	2		T3	4
all_values[13]	auto[0]	auto[1]	137379	1			T40	26453		T41	4525		T42	2011
all_values[13]	auto[1]	auto[1]	243	1			T40	2		T49	3		T57	4
all_values[14]	auto[0]	auto[0]	859494	1			T1	8		T2	2		T3	4
all_values[14]	auto[0]	auto[1]	137963	1			T40	26454		T41	4523		T42	2009
all_values[14]	auto[1]	auto[1]	241	1			T41	4		T42	2		T73	5