Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	997698	1			T1	8		T2	2		T3	4
all_pins[1]	997698	1			T1	8		T2	2		T3	4
all_pins[2]	997698	1			T1	8		T2	2		T3	4
all_pins[3]	997698	1			T1	8		T2	2		T3	4
all_pins[4]	997698	1			T1	8		T2	2		T3	4
all_pins[5]	997698	1			T1	8		T2	2		T3	4
all_pins[6]	997698	1			T1	8		T2	2		T3	4
all_pins[7]	997698	1			T1	8		T2	2		T3	4
all_pins[8]	997698	1			T1	8		T2	2		T3	4
all_pins[9]	997698	1			T1	8		T2	2		T3	4
all_pins[10]	997698	1			T1	8		T2	2		T3	4
all_pins[11]	997698	1			T1	8		T2	2		T3	4
all_pins[12]	997698	1			T1	8		T2	2		T3	4
all_pins[13]	997698	1			T1	8		T2	2		T3	4
all_pins[14]	997698	1			T1	8		T2	2		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	12193993	1			T1	101		T2	26		T3	49
values[0x1]	2771477	1			T1	19		T2	4		T3	11
transitions[0x0=>0x1]	2770484	1			T1	19		T2	4		T3	10
transitions[0x1=>0x0]	2769316	1			T1	18		T2	3		T3	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97567	1			T4	579		T8	2248		T9	2031
all_pins[0]	values[0x1]	900131	1			T1	8		T2	2		T3	4
all_pins[0]	transitions[0x0=>0x1]	899572	1			T1	8		T2	2		T3	4
all_pins[0]	transitions[0x1=>0x0]	136	1			T42	1		T49	2		T57	1
all_pins[1]	values[0x0]	997003	1			T1	8		T2	2		T3	4
all_pins[1]	values[0x1]	695	1			T10	2		T40	9		T42	2
all_pins[1]	transitions[0x0=>0x1]	663	1			T10	2		T40	9		T42	2
all_pins[1]	transitions[0x1=>0x0]	194	1			T3	1		T18	3		T19	3
all_pins[2]	values[0x0]	997472	1			T1	8		T2	2		T3	3
all_pins[2]	values[0x1]	226	1			T3	1		T18	3		T19	3
all_pins[2]	transitions[0x0=>0x1]	205	1			T3	1		T18	3		T19	3
all_pins[2]	transitions[0x1=>0x0]	80	1			T40	1		T42	1		T49	1
all_pins[3]	values[0x0]	997597	1			T1	8		T2	2		T3	4
all_pins[3]	values[0x1]	101	1			T40	2		T42	1		T49	2
all_pins[3]	transitions[0x0=>0x1]	81	1			T40	2		T49	2		T57	3
all_pins[3]	transitions[0x1=>0x0]	98	1			T45	1		T135	1		T49	1
all_pins[4]	values[0x0]	997580	1			T1	8		T2	2		T3	4
all_pins[4]	values[0x1]	118	1			T45	1		T42	1		T135	1
all_pins[4]	transitions[0x0=>0x1]	94	1			T45	1		T42	1		T135	1
all_pins[4]	transitions[0x1=>0x0]	95	1			T40	3		T49	3		T57	2
all_pins[5]	values[0x0]	997579	1			T1	8		T2	2		T3	4
all_pins[5]	values[0x1]	119	1			T40	3		T49	4		T57	2
all_pins[5]	transitions[0x0=>0x1]	78	1			T49	2		T57	1		T120	2
all_pins[5]	transitions[0x1=>0x0]	87	1			T40	1		T42	2		T73	3
all_pins[6]	values[0x0]	997570	1			T1	8		T2	2		T3	4
all_pins[6]	values[0x1]	128	1			T40	4		T42	2		T49	2
all_pins[6]	transitions[0x0=>0x1]	95	1			T40	4		T42	2		T49	1
all_pins[6]	transitions[0x1=>0x0]	34947	1			T4	138		T8	8		T9	392
all_pins[7]	values[0x0]	962718	1			T1	8		T2	2		T3	4
all_pins[7]	values[0x1]	34980	1			T4	138		T8	8		T9	392
all_pins[7]	transitions[0x0=>0x1]	34955	1			T4	138		T8	8		T9	392
all_pins[7]	transitions[0x1=>0x0]	105	1			T41	1		T57	1		T73	1
all_pins[8]	values[0x0]	997568	1			T1	8		T2	2		T3	4
all_pins[8]	values[0x1]	130	1			T41	1		T57	1		T73	1
all_pins[8]	transitions[0x0=>0x1]	92	1			T41	1		T57	1		T48	1
all_pins[8]	transitions[0x1=>0x0]	844180	1			T1	3		T3	1		T4	3
all_pins[9]	values[0x0]	153480	1			T1	5		T2	2		T3	3
all_pins[9]	values[0x1]	844218	1			T1	3		T3	1		T4	3
all_pins[9]	transitions[0x0=>0x1]	844197	1			T1	3		T3	1		T4	3
all_pins[9]	transitions[0x1=>0x0]	70	1			T41	1		T49	1		T57	1
all_pins[10]	values[0x0]	997607	1			T1	8		T2	2		T3	4
all_pins[10]	values[0x1]	91	1			T41	2		T49	2		T57	2
all_pins[10]	transitions[0x0=>0x1]	67	1			T41	1		T49	1		T57	2
all_pins[10]	transitions[0x1=>0x0]	990137	1			T1	8		T2	2		T3	4
all_pins[11]	values[0x0]	7537	1			T4	2		T8	2		T9	26
all_pins[11]	values[0x1]	990161	1			T1	8		T2	2		T3	4
all_pins[11]	transitions[0x0=>0x1]	990098	1			T1	8		T2	2		T3	3
all_pins[11]	transitions[0x1=>0x0]	80	1			T40	1		T49	1		T73	2
all_pins[12]	values[0x0]	997555	1			T1	8		T2	2		T3	3
all_pins[12]	values[0x1]	143	1			T3	1		T18	1		T19	1
all_pins[12]	transitions[0x0=>0x1]	116	1			T3	1		T18	1		T19	1
all_pins[12]	transitions[0x1=>0x0]	92	1			T40	1		T73	1		T48	2
all_pins[13]	values[0x0]	997579	1			T1	8		T2	2		T3	4
all_pins[13]	values[0x1]	119	1			T40	1		T73	3		T48	3
all_pins[13]	transitions[0x0=>0x1]	96	1			T40	1		T73	2		T112	3
all_pins[13]	transitions[0x1=>0x0]	94	1			T41	2		T42	2		T73	2
all_pins[14]	values[0x0]	997581	1			T1	8		T2	2		T3	4
all_pins[14]	values[0x1]	117	1			T41	2		T42	2		T73	3
all_pins[14]	transitions[0x0=>0x1]	75	1			T42	2		T73	2		T48	5
all_pins[14]	transitions[0x1=>0x0]	898921	1			T1	7		T2	1		T3	3