Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	528	1			T40	4		T41	4		T42	4
all_values[1]	528	1			T40	4		T41	4		T42	4
all_values[2]	528	1			T40	4		T41	4		T42	4
all_values[3]	528	1			T40	4		T41	4		T42	4
all_values[4]	528	1			T40	4		T41	4		T42	4
all_values[5]	528	1			T40	4		T41	4		T42	4
all_values[6]	528	1			T40	4		T41	4		T42	4
all_values[7]	528	1			T40	4		T41	4		T42	4
all_values[8]	528	1			T40	4		T41	4		T42	4
all_values[9]	528	1			T40	4		T41	4		T42	4
all_values[10]	528	1			T40	4		T41	4		T42	4
all_values[11]	528	1			T40	4		T41	4		T42	4
all_values[12]	528	1			T40	4		T41	4		T42	4
all_values[13]	528	1			T40	4		T41	4		T42	4
all_values[14]	528	1			T40	4		T41	4		T42	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4230

1

T40

35

T41

30

T42

44

auto[1]

3690

1

T40

25

T41

30

T42

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T40

11

T41

18

T42

20

auto[1]

6742

1

T40

49

T41

42

T42

40

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4746

1

T40

35

T41

40

T42

41

auto[1]

3174

1

T40

25

T41

20

T42

19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	31	1			T57	2		T48	1		T249	2
all_values[0]	auto[0]	auto[0]	auto[1]	126	1			T40	1		T41	2		T42	1
all_values[0]	auto[0]	auto[1]	auto[0]	19	1			T57	1		T73	1		T112	1
all_values[0]	auto[0]	auto[1]	auto[1]	123	1			T40	2		T49	2		T57	2
all_values[0]	auto[1]	auto[0]	auto[1]	126	1			T41	1		T42	3		T49	2
all_values[0]	auto[1]	auto[1]	auto[1]	103	1			T40	1		T41	1		T49	1
all_values[1]	auto[0]	auto[0]	auto[0]	52	1			T40	1		T41	1		T42	1
all_values[1]	auto[0]	auto[0]	auto[1]	112	1			T40	1		T41	1		T57	2
all_values[1]	auto[0]	auto[1]	auto[0]	30	1			T41	1		T49	1		T57	1
all_values[1]	auto[0]	auto[1]	auto[1]	105	1			T40	1		T42	1		T49	2
all_values[1]	auto[1]	auto[0]	auto[1]	118	1			T40	1		T41	1		T42	2
all_values[1]	auto[1]	auto[1]	auto[1]	111	1			T49	3		T57	2		T73	2
all_values[2]	auto[0]	auto[0]	auto[0]	52	1			T40	2		T48	1		T120	1
all_values[2]	auto[0]	auto[0]	auto[1]	115	1			T41	2		T42	2		T57	2
all_values[2]	auto[0]	auto[1]	auto[0]	27	1			T41	1		T49	3		T76	1
all_values[2]	auto[0]	auto[1]	auto[1]	124	1			T40	1		T49	1		T57	2
all_values[2]	auto[1]	auto[0]	auto[1]	95	1			T41	1		T42	2		T49	1
all_values[2]	auto[1]	auto[1]	auto[1]	115	1			T40	1		T49	2		T57	3
all_values[3]	auto[0]	auto[0]	auto[0]	58	1			T42	1		T120	6		T249	2
all_values[3]	auto[0]	auto[0]	auto[1]	113	1			T40	1		T42	1		T49	1
all_values[3]	auto[0]	auto[1]	auto[0]	43	1			T41	2		T112	1		T249	2
all_values[3]	auto[0]	auto[1]	auto[1]	109	1			T40	1		T41	1		T42	1
all_values[3]	auto[1]	auto[0]	auto[1]	118	1			T40	2		T49	3		T73	2
all_values[3]	auto[1]	auto[1]	auto[1]	87	1			T41	1		T42	1		T49	1
all_values[4]	auto[0]	auto[0]	auto[0]	45	1			T42	1		T73	1		T120	1
all_values[4]	auto[0]	auto[0]	auto[1]	125	1			T40	2		T57	3		T73	4
all_values[4]	auto[0]	auto[1]	auto[0]	29	1			T248	1		T250	1		T251	1
all_values[4]	auto[0]	auto[1]	auto[1]	120	1			T41	3		T42	2		T49	4
all_values[4]	auto[1]	auto[0]	auto[1]	123	1			T40	1		T49	2		T57	1
all_values[4]	auto[1]	auto[1]	auto[1]	86	1			T40	1		T41	1		T42	1
all_values[5]	auto[0]	auto[0]	auto[0]	51	1			T40	1		T41	1		T42	1
all_values[5]	auto[0]	auto[0]	auto[1]	122	1			T42	1		T57	1		T48	5
all_values[5]	auto[0]	auto[1]	auto[0]	33	1			T41	3		T42	1		T73	4
all_values[5]	auto[0]	auto[1]	auto[1]	110	1			T40	2		T49	1		T57	3
all_values[5]	auto[1]	auto[0]	auto[1]	107	1			T40	1		T49	3		T57	1
all_values[5]	auto[1]	auto[1]	auto[1]	105	1			T42	1		T49	3		T57	2
all_values[6]	auto[0]	auto[0]	auto[0]	40	1			T42	1		T48	1		T120	3
all_values[6]	auto[0]	auto[0]	auto[1]	119	1			T41	1		T42	1		T57	2
all_values[6]	auto[0]	auto[1]	auto[0]	46	1			T41	1		T49	1		T48	1
all_values[6]	auto[0]	auto[1]	auto[1]	110	1			T40	1		T42	1		T49	3
all_values[6]	auto[1]	auto[0]	auto[1]	116	1			T41	2		T42	1		T49	1
all_values[6]	auto[1]	auto[1]	auto[1]	97	1			T40	3		T49	2		T57	2
all_values[7]	auto[0]	auto[0]	auto[0]	54	1			T42	1		T49	2		T112	4
all_values[7]	auto[0]	auto[0]	auto[1]	128	1			T40	1		T41	2		T49	2
all_values[7]	auto[0]	auto[1]	auto[0]	28	1			T73	1		T250	4		T121	1
all_values[7]	auto[0]	auto[1]	auto[1]	108	1			T40	1		T42	1		T57	1
all_values[7]	auto[1]	auto[0]	auto[1]	114	1			T40	2		T41	1		T42	2
all_values[7]	auto[1]	auto[1]	auto[1]	96	1			T41	1		T49	3		T57	2
all_values[8]	auto[0]	auto[0]	auto[0]	34	1			T40	2		T42	1		T252	1
all_values[8]	auto[0]	auto[0]	auto[1]	125	1			T41	1		T42	1		T49	2
all_values[8]	auto[0]	auto[1]	auto[0]	26	1			T41	1		T42	1		T73	1
all_values[8]	auto[0]	auto[1]	auto[1]	124	1			T40	1		T41	1		T57	2
all_values[8]	auto[1]	auto[0]	auto[1]	117	1			T40	1		T49	5		T57	2
all_values[8]	auto[1]	auto[1]	auto[1]	102	1			T41	1		T42	1		T57	2
all_values[9]	auto[0]	auto[0]	auto[0]	48	1			T40	1		T42	1		T73	1
all_values[9]	auto[0]	auto[0]	auto[1]	112	1			T40	1		T41	1		T42	1
all_values[9]	auto[0]	auto[1]	auto[0]	35	1			T41	1		T48	1		T250	1
all_values[9]	auto[0]	auto[1]	auto[1]	128	1			T40	1		T41	1		T42	1
all_values[9]	auto[1]	auto[0]	auto[1]	107	1			T40	1		T41	1		T42	1
all_values[9]	auto[1]	auto[1]	auto[1]	98	1			T49	2		T57	2		T73	2
all_values[10]	auto[0]	auto[0]	auto[0]	64	1			T40	1		T42	1		T49	1
all_values[10]	auto[0]	auto[0]	auto[1]	106	1			T40	1		T42	2		T57	1
all_values[10]	auto[0]	auto[1]	auto[0]	45	1			T57	1		T73	1		T48	1
all_values[10]	auto[0]	auto[1]	auto[1]	116	1			T41	1		T49	3		T57	2
all_values[10]	auto[1]	auto[0]	auto[1]	109	1			T40	2		T41	2		T42	1
all_values[10]	auto[1]	auto[1]	auto[1]	88	1			T41	1		T49	2		T57	2
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T40	2		T41	3		T42	3
all_values[11]	auto[0]	auto[0]	auto[1]	123	1			T40	1		T49	1		T57	1
all_values[11]	auto[0]	auto[1]	auto[0]	26	1			T41	1		T42	1		T49	3
all_values[11]	auto[0]	auto[1]	auto[1]	134	1			T49	1		T57	2		T73	3
all_values[11]	auto[1]	auto[0]	auto[1]	115	1			T49	1		T57	2		T73	1
all_values[11]	auto[1]	auto[1]	auto[1]	89	1			T40	1		T49	1		T57	2
all_values[12]	auto[0]	auto[0]	auto[0]	32	1			T42	1		T121	2		T253	1
all_values[12]	auto[0]	auto[0]	auto[1]	130	1			T40	1		T41	2		T42	1
all_values[12]	auto[0]	auto[1]	auto[0]	27	1			T48	1		T251	1		T122	1
all_values[12]	auto[0]	auto[1]	auto[1]	123	1			T40	1		T41	1		T42	1
all_values[12]	auto[1]	auto[0]	auto[1]	117	1			T42	1		T57	2		T73	1
all_values[12]	auto[1]	auto[1]	auto[1]	99	1			T40	2		T41	1		T49	1
all_values[13]	auto[0]	auto[0]	auto[0]	48	1			T41	1		T42	2		T120	2
all_values[13]	auto[0]	auto[0]	auto[1]	145	1			T41	1		T42	1		T49	5
all_values[13]	auto[0]	auto[1]	auto[0]	18	1			T41	1		T48	1		T250	2
all_values[13]	auto[0]	auto[1]	auto[1]	107	1			T40	1		T73	3		T48	1
all_values[13]	auto[1]	auto[0]	auto[1]	116	1			T40	2		T41	1		T42	1
all_values[13]	auto[1]	auto[1]	auto[1]	94	1			T40	1		T57	1		T73	2
all_values[14]	auto[0]	auto[0]	auto[0]	60	1			T40	1		T42	2		T49	1
all_values[14]	auto[0]	auto[0]	auto[1]	113	1			T41	1		T49	3		T57	4
all_values[14]	auto[0]	auto[1]	auto[0]	36	1			T112	1		T120	2		T76	2
all_values[14]	auto[0]	auto[1]	auto[1]	113	1			T40	1		T42	1		T49	1
all_values[14]	auto[1]	auto[0]	auto[1]	108	1			T40	1		T42	1		T49	2
all_values[14]	auto[1]	auto[1]	auto[1]	98	1			T40	1		T41	3		T57	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal