Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1022353	1			T1	223		T2	2		T3	2
all_values[1]	1022353	1			T1	223		T2	2		T3	2
all_values[2]	1022353	1			T1	223		T2	2		T3	2
all_values[3]	1022353	1			T1	223		T2	2		T3	2
all_values[4]	1022353	1			T1	223		T2	2		T3	2
all_values[5]	1022353	1			T1	223		T2	2		T3	2
all_values[6]	1022353	1			T1	223		T2	2		T3	2
all_values[7]	1022353	1			T1	223		T2	2		T3	2
all_values[8]	1022353	1			T1	223		T2	2		T3	2
all_values[9]	1022353	1			T1	223		T2	2		T3	2
all_values[10]	1022353	1			T1	223		T2	2		T3	2
all_values[11]	1022353	1			T1	223		T2	2		T3	2
all_values[12]	1022353	1			T1	223		T2	2		T3	2
all_values[13]	1022353	1			T1	223		T2	2		T3	2
all_values[14]	1022353	1			T1	223		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12545237

1

T1

2907

T2

26

T3

27

auto[1]

2790058

1

T1

438

T2

4

T3

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13383001

1

T1

3345

T2

30

T3

30

auto[1]

1952294

1

T53

57

T49

36150

T84

57

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	95686	1			T1	34		T6	1		T7	125
all_values[0]	auto[0]	auto[1]	16512	1			T49	1994		T61	949		T231	3277
all_values[0]	auto[1]	auto[0]	810935	1			T1	189		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	99220	1			T53	6		T49	588		T61	5838
all_values[1]	auto[0]	auto[0]	882472	1			T1	223		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	139268	1			T53	4		T49	2580		T84	5
all_values[1]	auto[1]	auto[0]	379	1			T50	30		T143	1		T242	1
all_values[1]	auto[1]	auto[1]	234	1			T53	2		T49	3		T84	1
all_values[2]	auto[0]	auto[0]	882755	1			T1	223		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	139285	1			T49	2579		T84	3		T61	6784
all_values[2]	auto[1]	auto[0]	91	1			T149	3		T243	3		T120	1
all_values[2]	auto[1]	auto[1]	222	1			T49	4		T84	3		T61	4
all_values[3]	auto[0]	auto[0]	888289	1			T1	223		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	133793	1			T49	2579		T84	5		T61	6783
all_values[3]	auto[1]	auto[1]	271	1			T49	4		T84	1		T61	5
all_values[4]	auto[0]	auto[0]	908181	1			T1	223		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	113957	1			T53	4		T49	2578		T61	6785
all_values[4]	auto[1]	auto[0]	17	1			T45	1		T239	1		T236	1
all_values[4]	auto[1]	auto[1]	198	1			T53	2		T49	3		T61	2
all_values[5]	auto[0]	auto[0]	882882	1			T1	223		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	139253	1			T53	3		T49	2581		T84	5
all_values[5]	auto[1]	auto[1]	218	1			T53	3		T49	1		T84	1
all_values[6]	auto[0]	auto[0]	903929	1			T1	223		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	118194	1			T53	5		T49	2577		T84	3
all_values[6]	auto[1]	auto[1]	230	1			T53	1		T49	3		T84	2
all_values[7]	auto[0]	auto[0]	858226	1			T1	208		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	135177	1			T49	2029		T84	3		T61	6361
all_values[7]	auto[1]	auto[0]	24679	1			T1	15		T6	1		T7	4
all_values[7]	auto[1]	auto[1]	4271	1			T49	553		T84	2		T61	426
all_values[8]	auto[0]	auto[0]	898216	1			T1	223		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	123901	1			T53	6		T84	5		T61	6785
all_values[8]	auto[1]	auto[1]	236	1			T84	1		T61	2		T226	4
all_values[9]	auto[0]	auto[0]	163311	1			T1	208		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	30168	1			T49	2574		T61	1919		T226	4843
all_values[9]	auto[1]	auto[0]	719608	1			T1	15		T6	1		T7	2
all_values[9]	auto[1]	auto[1]	109266	1			T49	6		T61	4867		T226	4742
all_values[10]	auto[0]	auto[0]	882890	1			T1	223		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	139264	1			T53	3		T49	2579		T84	4
all_values[10]	auto[1]	auto[1]	199	1			T53	2		T49	3		T84	1
all_values[11]	auto[0]	auto[0]	2689	1			T1	4		T3	1		T5	1
all_values[11]	auto[0]	auto[1]	542	1			T49	18		T61	11		T226	25
all_values[11]	auto[1]	auto[0]	880172	1			T1	219		T2	2		T3	1
all_values[11]	auto[1]	auto[1]	138950	1			T53	6		T49	2565		T61	6775
all_values[12]	auto[0]	auto[0]	901170	1			T1	223		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	120973	1			T49	2581		T84	5		T61	6784
all_values[12]	auto[1]	auto[0]	27	1			T243	1		T244	1		T245	1
all_values[12]	auto[1]	auto[1]	183	1			T49	2		T84	1		T61	3
all_values[13]	auto[0]	auto[0]	882894	1			T1	223		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	139233	1			T53	2		T49	2580		T84	5
all_values[13]	auto[1]	auto[1]	226	1			T53	2		T49	3		T84	1
all_values[14]	auto[0]	auto[0]	913503	1			T1	223		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	108624	1			T53	3		T49	2578		T61	6786
all_values[14]	auto[1]	auto[1]	226	1			T53	3		T49	5		T61	2