Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1022353	1			T1	223		T2	2		T3	2
all_pins[1]	1022353	1			T1	223		T2	2		T3	2
all_pins[2]	1022353	1			T1	223		T2	2		T3	2
all_pins[3]	1022353	1			T1	223		T2	2		T3	2
all_pins[4]	1022353	1			T1	223		T2	2		T3	2
all_pins[5]	1022353	1			T1	223		T2	2		T3	2
all_pins[6]	1022353	1			T1	223		T2	2		T3	2
all_pins[7]	1022353	1			T1	223		T2	2		T3	2
all_pins[8]	1022353	1			T1	223		T2	2		T3	2
all_pins[9]	1022353	1			T1	223		T2	2		T3	2
all_pins[10]	1022353	1			T1	223		T2	2		T3	2
all_pins[11]	1022353	1			T1	223		T2	2		T3	2
all_pins[12]	1022353	1			T1	223		T2	2		T3	2
all_pins[13]	1022353	1			T1	223		T2	2		T3	2
all_pins[14]	1022353	1			T1	223		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	12550544	1			T1	2906		T2	26		T3	27
values[0x1]	2784751	1			T1	439		T2	4		T3	3
transitions[0x0=>0x1]	2783792	1			T1	439		T2	4		T3	3
transitions[0x1=>0x0]	2782621	1			T1	438		T2	3		T3	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	115606	1			T1	34		T6	1		T7	125
all_pins[0]	values[0x1]	906747	1			T1	189		T2	2		T3	2
all_pins[0]	transitions[0x0=>0x1]	906232	1			T1	189		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	74	1			T49	2		T61	2		T226	1
all_pins[1]	values[0x0]	1021764	1			T1	223		T2	2		T3	2
all_pins[1]	values[0x1]	589	1			T50	34		T143	1		T242	1
all_pins[1]	transitions[0x0=>0x1]	563	1			T50	34		T143	1		T242	1
all_pins[1]	transitions[0x1=>0x0]	178	1			T149	3		T243	3		T120	1
all_pins[2]	values[0x0]	1022149	1			T1	223		T2	2		T3	2
all_pins[2]	values[0x1]	204	1			T149	3		T243	3		T120	1
all_pins[2]	transitions[0x0=>0x1]	168	1			T149	3		T243	3		T120	1
all_pins[2]	transitions[0x1=>0x0]	97	1			T49	3		T61	1		T226	1
all_pins[3]	values[0x0]	1022220	1			T1	223		T2	2		T3	2
all_pins[3]	values[0x1]	133	1			T49	3		T61	2		T226	3
all_pins[3]	transitions[0x0=>0x1]	95	1			T49	1		T61	2		T226	2
all_pins[3]	transitions[0x1=>0x0]	96	1			T53	2		T45	1		T239	1
all_pins[4]	values[0x0]	1022219	1			T1	223		T2	2		T3	2
all_pins[4]	values[0x1]	134	1			T53	2		T45	1		T49	2
all_pins[4]	transitions[0x0=>0x1]	109	1			T53	1		T45	1		T49	2
all_pins[4]	transitions[0x1=>0x0]	89	1			T53	1		T84	1		T61	1
all_pins[5]	values[0x0]	1022239	1			T1	223		T2	2		T3	2
all_pins[5]	values[0x1]	114	1			T53	2		T84	1		T61	1
all_pins[5]	transitions[0x0=>0x1]	91	1			T53	2		T84	1		T61	1
all_pins[5]	transitions[0x1=>0x0]	92	1			T49	2		T226	3		T62	2
all_pins[6]	values[0x0]	1022238	1			T1	223		T2	2		T3	2
all_pins[6]	values[0x1]	115	1			T49	2		T226	4		T62	2
all_pins[6]	transitions[0x0=>0x1]	83	1			T49	2		T226	1		T62	2
all_pins[6]	transitions[0x1=>0x0]	31875	1			T1	16		T6	1		T7	4
all_pins[7]	values[0x0]	990446	1			T1	207		T2	2		T3	2
all_pins[7]	values[0x1]	31907	1			T1	16		T6	1		T7	4
all_pins[7]	transitions[0x0=>0x1]	31864	1			T1	16		T6	1		T7	4
all_pins[7]	transitions[0x1=>0x0]	80	1			T84	1		T62	2		T260	1
all_pins[8]	values[0x0]	1022230	1			T1	223		T2	2		T3	2
all_pins[8]	values[0x1]	123	1			T84	1		T226	3		T231	1
all_pins[8]	transitions[0x0=>0x1]	89	1			T84	1		T226	3		T231	1
all_pins[8]	transitions[0x1=>0x0]	828774	1			T1	15		T6	1		T7	2
all_pins[9]	values[0x0]	193545	1			T1	208		T2	2		T3	2
all_pins[9]	values[0x1]	828808	1			T1	15		T6	1		T7	2
all_pins[9]	transitions[0x0=>0x1]	828788	1			T1	15		T6	1		T7	2
all_pins[9]	transitions[0x1=>0x0]	82	1			T53	1		T49	3		T226	1
all_pins[10]	values[0x0]	1022251	1			T1	223		T2	2		T3	2
all_pins[10]	values[0x1]	102	1			T53	1		T49	3		T226	1
all_pins[10]	transitions[0x0=>0x1]	70	1			T49	2		T231	1		T62	2
all_pins[10]	transitions[0x1=>0x0]	1015401	1			T1	219		T2	2		T3	1
all_pins[11]	values[0x0]	6920	1			T1	4		T3	1		T5	1
all_pins[11]	values[0x1]	1015433	1			T1	219		T2	2		T3	1
all_pins[11]	transitions[0x0=>0x1]	1015377	1			T1	219		T2	2		T3	1
all_pins[11]	transitions[0x1=>0x0]	53	1			T49	2		T61	1		T62	2
all_pins[12]	values[0x0]	1022244	1			T1	223		T2	2		T3	2
all_pins[12]	values[0x1]	109	1			T243	1		T49	2		T61	1
all_pins[12]	transitions[0x0=>0x1]	94	1			T243	1		T49	1		T61	1
all_pins[12]	transitions[0x1=>0x0]	118	1			T53	2		T49	1		T84	1
all_pins[13]	values[0x0]	1022220	1			T1	223		T2	2		T3	2
all_pins[13]	values[0x1]	133	1			T53	2		T49	2		T84	1
all_pins[13]	transitions[0x0=>0x1]	110	1			T53	2		T49	2		T84	1
all_pins[13]	transitions[0x1=>0x0]	77	1			T49	3		T61	1		T231	3
all_pins[14]	values[0x0]	1022253	1			T1	223		T2	2		T3	2
all_pins[14]	values[0x1]	100	1			T49	3		T61	1		T231	3
all_pins[14]	transitions[0x0=>0x1]	59	1			T49	1		T61	1		T231	2
all_pins[14]	transitions[0x1=>0x0]	905535	1			T1	188		T2	1		T3	1