Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	490	1			T53	4		T49	7		T84	4
all_values[1]	490	1			T53	4		T49	7		T84	4
all_values[2]	490	1			T53	4		T49	7		T84	4
all_values[3]	490	1			T53	4		T49	7		T84	4
all_values[4]	490	1			T53	4		T49	7		T84	4
all_values[5]	490	1			T53	4		T49	7		T84	4
all_values[6]	490	1			T53	4		T49	7		T84	4
all_values[7]	490	1			T53	4		T49	7		T84	4
all_values[8]	490	1			T53	4		T49	7		T84	4
all_values[9]	490	1			T53	4		T49	7		T84	4
all_values[10]	490	1			T53	4		T49	7		T84	4
all_values[11]	490	1			T53	4		T49	7		T84	4
all_values[12]	490	1			T53	4		T49	7		T84	4
all_values[13]	490	1			T53	4		T49	7		T84	4
all_values[14]	490	1			T53	4		T49	7		T84	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3941

1

T53

26

T49

53

T84

23

auto[1]

3409

1

T53

34

T49

52

T84

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1209

1

T53

23

T49

19

T84

23

auto[1]

6141

1

T53

37

T49

86

T84

37

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4386

1

T53

42

T49

62

T84

44

auto[1]

2964

1

T53

18

T49

43

T84

16

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	62	1			T49	1		T84	1		T61	1
all_values[0]	auto[0]	auto[0]	auto[1]	118	1			T53	3		T49	2		T61	3
all_values[0]	auto[0]	auto[1]	auto[0]	57	1			T84	3		T226	3		T231	1
all_values[0]	auto[0]	auto[1]	auto[1]	80	1			T49	1		T62	3		T260	1
all_values[0]	auto[1]	auto[0]	auto[1]	90	1			T61	1		T231	1		T62	3
all_values[0]	auto[1]	auto[1]	auto[1]	83	1			T53	1		T49	3		T61	3
all_values[1]	auto[0]	auto[0]	auto[0]	40	1			T261	1		T262	1		T263	1
all_values[1]	auto[0]	auto[0]	auto[1]	104	1			T53	2		T49	2		T61	4
all_values[1]	auto[0]	auto[1]	auto[0]	20	1			T264	1		T249	1		T123	1
all_values[1]	auto[0]	auto[1]	auto[1]	120	1			T49	2		T84	3		T61	2
all_values[1]	auto[1]	auto[0]	auto[1]	112	1			T53	1		T49	1		T61	2
all_values[1]	auto[1]	auto[1]	auto[1]	94	1			T53	1		T49	2		T84	1
all_values[2]	auto[0]	auto[0]	auto[0]	24	1			T226	1		T62	1		T265	1
all_values[2]	auto[0]	auto[0]	auto[1]	120	1			T49	3		T61	4		T249	2
all_values[2]	auto[0]	auto[1]	auto[0]	30	1			T53	4		T231	2		T62	1
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T84	1		T226	1		T231	1
all_values[2]	auto[1]	auto[0]	auto[1]	123	1			T49	2		T84	1		T61	3
all_values[2]	auto[1]	auto[1]	auto[1]	99	1			T49	2		T84	2		T61	1
all_values[3]	auto[0]	auto[0]	auto[0]	47	1			T53	3		T249	1		T121	1
all_values[3]	auto[0]	auto[0]	auto[1]	109	1			T49	2		T84	2		T61	4
all_values[3]	auto[0]	auto[1]	auto[0]	21	1			T53	1		T231	1		T266	1
all_values[3]	auto[0]	auto[1]	auto[1]	97	1			T49	2		T226	2		T231	2
all_values[3]	auto[1]	auto[0]	auto[1]	126	1			T49	2		T84	1		T61	3
all_values[3]	auto[1]	auto[1]	auto[1]	90	1			T49	1		T84	1		T61	1
all_values[4]	auto[0]	auto[0]	auto[0]	56	1			T49	2		T61	1		T231	1
all_values[4]	auto[0]	auto[0]	auto[1]	85	1			T61	3		T62	3		T260	1
all_values[4]	auto[0]	auto[1]	auto[0]	34	1			T84	4		T231	3		T266	2
all_values[4]	auto[0]	auto[1]	auto[1]	117	1			T53	2		T49	2		T61	2
all_values[4]	auto[1]	auto[0]	auto[1]	115	1			T49	1		T61	1		T226	2
all_values[4]	auto[1]	auto[1]	auto[1]	83	1			T53	2		T49	2		T61	1
all_values[5]	auto[0]	auto[0]	auto[0]	49	1			T226	1		T62	1		T249	1
all_values[5]	auto[0]	auto[0]	auto[1]	109	1			T49	2		T61	2		T226	1
all_values[5]	auto[0]	auto[1]	auto[0]	35	1			T49	1		T231	1		T264	2
all_values[5]	auto[0]	auto[1]	auto[1]	126	1			T53	2		T49	3		T84	3
all_values[5]	auto[1]	auto[0]	auto[1]	86	1			T53	1		T49	1		T61	2
all_values[5]	auto[1]	auto[1]	auto[1]	85	1			T53	1		T84	1		T61	3
all_values[6]	auto[0]	auto[0]	auto[0]	33	1			T49	1		T61	2		T267	1
all_values[6]	auto[0]	auto[0]	auto[1]	116	1			T53	2		T49	1		T84	1
all_values[6]	auto[0]	auto[1]	auto[0]	35	1			T49	2		T84	1		T231	1
all_values[6]	auto[0]	auto[1]	auto[1]	103	1			T49	1		T61	2		T226	1
all_values[6]	auto[1]	auto[0]	auto[1]	107	1			T53	1		T49	1		T84	1
all_values[6]	auto[1]	auto[1]	auto[1]	96	1			T53	1		T49	1		T84	1
all_values[7]	auto[0]	auto[0]	auto[0]	50	1			T53	2		T49	1		T61	1
all_values[7]	auto[0]	auto[0]	auto[1]	110	1			T49	1		T84	1		T61	2
all_values[7]	auto[0]	auto[1]	auto[0]	30	1			T53	2		T84	1		T231	1
all_values[7]	auto[0]	auto[1]	auto[1]	99	1			T49	1		T61	1		T226	1
all_values[7]	auto[1]	auto[0]	auto[1]	124	1			T49	2		T84	1		T61	3
all_values[7]	auto[1]	auto[1]	auto[1]	77	1			T49	2		T84	1		T61	1
all_values[8]	auto[0]	auto[0]	auto[0]	41	1			T49	5		T61	1		T62	2
all_values[8]	auto[0]	auto[0]	auto[1]	110	1			T53	2		T84	3		T61	2
all_values[8]	auto[0]	auto[1]	auto[0]	29	1			T49	2		T231	1		T264	4
all_values[8]	auto[0]	auto[1]	auto[1]	107	1			T53	1		T61	3		T226	1
all_values[8]	auto[1]	auto[0]	auto[1]	107	1			T61	2		T226	1		T231	1
all_values[8]	auto[1]	auto[1]	auto[1]	96	1			T53	1		T84	1		T226	2
all_values[9]	auto[0]	auto[0]	auto[0]	53	1			T53	2		T49	2		T84	2
all_values[9]	auto[0]	auto[0]	auto[1]	114	1			T61	3		T226	1		T231	1
all_values[9]	auto[0]	auto[1]	auto[0]	52	1			T53	2		T49	1		T84	2
all_values[9]	auto[0]	auto[1]	auto[1]	83	1			T49	2		T61	2		T62	1
all_values[9]	auto[1]	auto[0]	auto[1]	90	1			T49	1		T226	3		T231	2
all_values[9]	auto[1]	auto[1]	auto[1]	98	1			T49	1		T61	1		T231	1
all_values[10]	auto[0]	auto[0]	auto[0]	53	1			T49	1		T61	5		T62	1
all_values[10]	auto[0]	auto[0]	auto[1]	117	1			T53	1		T49	2		T84	2
all_values[10]	auto[0]	auto[1]	auto[0]	24	1			T53	1		T84	1		T61	1
all_values[10]	auto[0]	auto[1]	auto[1]	97	1			T49	1		T226	2		T231	2
all_values[10]	auto[1]	auto[0]	auto[1]	103	1			T53	1		T84	1		T61	1
all_values[10]	auto[1]	auto[1]	auto[1]	96	1			T53	1		T49	3		T226	1
all_values[11]	auto[0]	auto[0]	auto[0]	45	1			T84	1		T61	2		T62	1
all_values[11]	auto[0]	auto[0]	auto[1]	110	1			T49	2		T61	3		T226	2
all_values[11]	auto[0]	auto[1]	auto[0]	23	1			T84	3		T267	1		T121	1
all_values[11]	auto[0]	auto[1]	auto[1]	103	1			T53	1		T61	1		T226	1
all_values[11]	auto[1]	auto[0]	auto[1]	107	1			T49	3		T61	2		T62	2
all_values[11]	auto[1]	auto[1]	auto[1]	102	1			T53	3		T49	2		T226	1
all_values[12]	auto[0]	auto[0]	auto[0]	56	1			T53	1		T61	1		T121	1
all_values[12]	auto[0]	auto[0]	auto[1]	113	1			T49	1		T84	1		T61	2
all_values[12]	auto[0]	auto[1]	auto[0]	44	1			T53	3		T231	4		T249	2
all_values[12]	auto[0]	auto[1]	auto[1]	94	1			T49	4		T84	2		T61	2
all_values[12]	auto[1]	auto[0]	auto[1]	94	1			T61	2		T62	2		T260	2
all_values[12]	auto[1]	auto[1]	auto[1]	89	1			T49	2		T84	1		T61	1
all_values[13]	auto[0]	auto[0]	auto[0]	53	1			T53	1		T61	1		T231	1
all_values[13]	auto[0]	auto[0]	auto[1]	93	1			T49	3		T84	2		T61	1
all_values[13]	auto[0]	auto[1]	auto[0]	44	1			T53	1		T231	1		T62	1
all_values[13]	auto[0]	auto[1]	auto[1]	106	1			T53	1		T61	2		T226	1
all_values[13]	auto[1]	auto[0]	auto[1]	91	1			T49	2		T61	3		T226	2
all_values[13]	auto[1]	auto[1]	auto[1]	103	1			T53	1		T49	2		T84	2
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T84	2		T249	1		T268	1
all_values[14]	auto[0]	auto[0]	auto[1]	113	1			T53	2		T49	1		T61	5
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T84	2		T226	4		T264	1
all_values[14]	auto[0]	auto[1]	auto[1]	110	1			T49	2		T61	1		T231	1
all_values[14]	auto[1]	auto[0]	auto[1]	121	1			T53	1		T49	2		T61	1
all_values[14]	auto[1]	auto[1]	auto[1]	77	1			T53	1		T49	2		T61	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal