Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	916488	1			T1	220		T2	3		T3	356
all_values[1]	916488	1			T1	220		T2	3		T3	356
all_values[2]	916488	1			T1	220		T2	3		T3	356
all_values[3]	916488	1			T1	220		T2	3		T3	356
all_values[4]	916488	1			T1	220		T2	3		T3	356
all_values[5]	916488	1			T1	220		T2	3		T3	356
all_values[6]	916488	1			T1	220		T2	3		T3	356
all_values[7]	916488	1			T1	220		T2	3		T3	356
all_values[8]	916488	1			T1	220		T2	3		T3	356
all_values[9]	916488	1			T1	220		T2	3		T3	356
all_values[10]	916488	1			T1	220		T2	3		T3	356
all_values[11]	916488	1			T1	220		T2	3		T3	356
all_values[12]	916488	1			T1	220		T2	3		T3	356
all_values[13]	916488	1			T1	220		T2	3		T3	356
all_values[14]	916488	1			T1	220		T2	3		T3	356

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11234098

1

T1

2868

T2

39

T3

4491

auto[1]

2513222

1

T1

432

T2

6

T3

849

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12331838

1

T1

3300

T2

45

T3

5340

auto[1]

1415482

1

T80

153

T81

145456

T31

71

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	75989	1			T1	5		T2	1		T3	14
all_values[0]	auto[0]	auto[1]	7924	1			T80	8		T81	478		T33	18
all_values[0]	auto[1]	auto[0]	750129	1			T1	215		T2	2		T3	342
all_values[0]	auto[1]	auto[1]	82446	1			T80	4		T81	9219		T31	4
all_values[1]	auto[0]	auto[0]	848235	1			T1	220		T2	3		T3	356
all_values[1]	auto[0]	auto[1]	67601	1			T80	9		T81	9693		T31	4
all_values[1]	auto[1]	auto[0]	415	1			T80	6		T74	21		T244	1
all_values[1]	auto[1]	auto[1]	237	1			T80	2		T81	4		T31	1
all_values[2]	auto[0]	auto[0]	815178	1			T1	220		T2	3		T3	356
all_values[2]	auto[0]	auto[1]	101059	1			T80	9		T81	9694		T31	4
all_values[2]	auto[1]	auto[0]	53	1			T245	1		T246	1		T247	1
all_values[2]	auto[1]	auto[1]	198	1			T80	3		T81	2		T31	2
all_values[3]	auto[0]	auto[0]	819296	1			T1	220		T2	3		T3	356
all_values[3]	auto[0]	auto[1]	96968	1			T80	8		T81	9696		T31	2
all_values[3]	auto[1]	auto[1]	224	1			T80	2		T81	1		T31	3
all_values[4]	auto[0]	auto[0]	833752	1			T1	220		T2	3		T3	356
all_values[4]	auto[0]	auto[1]	82541	1			T80	9		T81	9692		T31	5
all_values[4]	auto[1]	auto[0]	10	1			T34	1		T248	1		T249	1
all_values[4]	auto[1]	auto[1]	185	1			T80	3		T81	2		T31	1
all_values[5]	auto[0]	auto[0]	834736	1			T1	220		T2	3		T3	356
all_values[5]	auto[0]	auto[1]	81527	1			T80	5		T81	9695		T31	5
all_values[5]	auto[1]	auto[1]	225	1			T80	6		T81	3		T31	1
all_values[6]	auto[0]	auto[0]	830275	1			T1	220		T2	3		T3	356
all_values[6]	auto[0]	auto[1]	86017	1			T80	7		T81	9692		T31	4
all_values[6]	auto[1]	auto[1]	196	1			T80	1		T81	6		T31	1
all_values[7]	auto[0]	auto[0]	786943	1			T1	218		T2	2		T3	220
all_values[7]	auto[0]	auto[1]	97265	1			T81	9340		T31	3		T33	439
all_values[7]	auto[1]	auto[0]	28746	1			T1	2		T2	1		T3	136
all_values[7]	auto[1]	auto[1]	3534	1			T81	358		T31	3		T33	2
all_values[8]	auto[0]	auto[0]	815197	1			T1	220		T2	3		T3	356
all_values[8]	auto[0]	auto[1]	101073	1			T80	9		T81	9692		T33	440
all_values[8]	auto[1]	auto[1]	218	1			T80	3		T81	6		T33	2
all_values[9]	auto[0]	auto[0]	173540	1			T1	220		T2	2		T3	338
all_values[9]	auto[0]	auto[1]	10630	1			T80	4		T81	455		T31	3
all_values[9]	auto[1]	auto[0]	641681	1			T2	1		T3	18		T4	1
all_values[9]	auto[1]	auto[1]	90637	1			T80	4		T81	9242		T31	3
all_values[10]	auto[0]	auto[0]	815190	1			T1	220		T2	3		T3	356
all_values[10]	auto[0]	auto[1]	101088	1			T80	9		T81	9695		T31	3
all_values[10]	auto[1]	auto[1]	210	1			T80	3		T81	1		T31	2
all_values[11]	auto[0]	auto[0]	2848	1			T1	5		T2	1		T3	3
all_values[11]	auto[0]	auto[1]	423	1			T80	3		T81	5		T33	16
all_values[11]	auto[1]	auto[0]	813253	1			T1	215		T2	2		T3	353
all_values[11]	auto[1]	auto[1]	99964	1			T80	6		T81	9693		T31	5
all_values[12]	auto[0]	auto[0]	815435	1			T1	220		T2	3		T3	356
all_values[12]	auto[0]	auto[1]	100846	1			T80	8		T81	9697		T33	441
all_values[12]	auto[1]	auto[0]	17	1			T246	1		T250	1		T251	1
all_values[12]	auto[1]	auto[1]	190	1			T80	4		T81	1		T33	1
all_values[13]	auto[0]	auto[0]	815700	1			T1	220		T2	3		T3	356
all_values[13]	auto[0]	auto[1]	100547	1			T80	5		T81	9693		T31	2
all_values[13]	auto[1]	auto[1]	241	1			T80	7		T81	4		T31	4
all_values[14]	auto[0]	auto[0]	815220	1			T1	220		T2	3		T3	356
all_values[14]	auto[0]	auto[1]	101055	1			T80	5		T81	9692		T31	3
all_values[14]	auto[1]	auto[1]	213	1			T80	7		T81	5		T31	3