Unified Coverage Report :: Group :: i2c_env_pkg::i2c_fifo_reset_cg

Group : i2c_env_pkg::i2c_fifo_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.82	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_fifo_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	24	6	18	75.00

Variables for Group i2c_env_pkg::i2c_fifo_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_overflow	2	1	1	50.00	100	1	1	2
cp_acq_threshold	2	0	2	100.00	100	1	1	2
cp_acqrst	2	0	2	100.00	100	1	1	2
cp_fmt_threshold	2	0	2	100.00	100	1	1	2
cp_fmtrst	2	0	2	100.00	100	1	1	2
cp_rx_overflow	2	1	1	50.00	100	1	1	2
cp_rx_threshold	2	0	2	100.00	100	1	1	2
cp_rxrst	2	0	2	100.00	100	1	1	2
cp_tx_threshold	2	0	2	100.00	100	1	1	2
cp_txrst	2	0	2	100.00	100	1	1	2

Crosses for Group i2c_env_pkg::i2c_fifo_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_fmt_threshold_cross	4	0	4	100.00	100	1	1	0
cp_rx_threshold_cross	4	1	3	75.00	100	1	1	0
cp_acq_threshold_cross	4	1	3	75.00	100	1	1	0
cp_rx_overflow_cross	4	2	2	50.00	100	1	1	0
cp_acq_overflow_cross	4	2	2	50.00	100	1	1	0
cp_tx_threshold_cross	4	0	4	100.00	100	1	1	0

Summary for Variable cp_acq_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_acq_overflow

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3387

1

T1

1

T2

1

T3

2

---

Summary for Variable cp_acq_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acq_threshold

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3386	1			T1	1		T2	1		T3	2
auto[1]	1	1			T222	1		-	-		-	-

---

Summary for Variable cp_acqrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_acqrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

884

1

T48

10

T223

1

T224

1

auto[1]

2503

1

T1

1

T2

1

T3

2

---

Summary for Variable cp_fmt_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmt_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3023

1

T1

1

T2

1

T3

2

auto[1]

364

1

T5

2

T67

2

T225

2

---

Summary for Variable cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_fmtrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T5

2

T48

5

T67

2

auto[1]

2737

1

T1

1

T2

1

T3

2

---

Summary for Variable cp_rx_overflow

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_rx_overflow

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3387

1

T1

1

T2

1

T3

2

---

Summary for Variable cp_rx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3354

1

T1

1

T2

1

T3

2

auto[1]

33

1

T226

1

T151

1

T227

1

---

Summary for Variable cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1001

1

T5

2

T48

10

T67

2

auto[1]

2386

1

T1

1

T2

1

T3

2

---

Summary for Variable cp_tx_threshold

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_tx_threshold

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3069

1

T1

1

T2

1

T3

2

auto[1]

318

1

T5

2

T223

1

T224

2

---

Summary for Variable cp_txrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_txrst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

884

1

T5

1

T48

10

T67

1

auto[1]

2503

1

T1

1

T2

1

T3

2

---

Summary for Cross cp_fmt_threshold_cross

Samples crossed: cp_fmt_threshold cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_fmt_threshold_cross

Bins

cp_fmt_threshold

cp_fmtrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

386

1

T48

5

T49

9

T50

6

auto[0]

auto[1]

2637

1

T1

1

T2

1

T3

2

auto[1]

auto[0]

264

1

T5

2

T67

2

T225

2

auto[1]

auto[1]

100

1

T80

4

T81

3

T31

1

---

Summary for Cross cp_rx_threshold_cross

Samples crossed: cp_rx_threshold cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cp_rx_threshold_cross

Uncovered bins

cp_rx_threshold	cp_rxrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_rx_threshold

cp_rxrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

1001

1

T5

2

T48

10

T67

2

auto[0]

auto[1]

2353

1

T1

1

T2

1

T3

2

auto[1]

auto[1]

33

1

T226

1

T151

1

T227

1

---

Summary for Cross cp_acq_threshold_cross

Samples crossed: cp_acq_threshold cp_fmtrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	1	3	75.00	1

Automatically Generated Cross Bins for cp_acq_threshold_cross

Uncovered bins

cp_acq_threshold	cp_fmtrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_acq_threshold	cp_fmtrst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	649	1			T5	2		T48	5		T67	2
auto[0]	auto[1]	2737	1			T1	1		T2	1		T3	2
auto[1]	auto[0]	1	1			T222	1		-	-		-	-

---

Summary for Cross cp_rx_overflow_cross

Samples crossed: cp_rx_overflow cp_rxrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cp_rx_overflow_cross

Element holes

cp_rx_overflow	cp_rxrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Covered bins

cp_rx_overflow

cp_rxrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

1001

1

T5

2

T48

10

T67

2

auto[0]

auto[1]

2386

1

T1

1

T2

1

T3

2

---

Summary for Cross cp_acq_overflow_cross

Samples crossed: cp_acq_overflow cp_acqrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for cp_acq_overflow_cross

Element holes

cp_acq_overflow	cp_acqrst	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	2

Covered bins

cp_acq_overflow

cp_acqrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

884

1

T48

10

T223

1

T224

1

auto[0]

auto[1]

2503

1

T1

1

T2

1

T3

2

---

Summary for Cross cp_tx_threshold_cross

Samples crossed: cp_tx_threshold cp_txrst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for cp_tx_threshold_cross

Bins

cp_tx_threshold

cp_txrst

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

780

1

T48

10

T67

1

T225

1

auto[0]

auto[1]

2289

1

T1

1

T2

1

T3

2

auto[1]

auto[0]

104

1

T5

1

T226

2

T151

2

auto[1]

auto[1]

214

1

T5

1

T223

1

T224

2