Unified Coverage Report :: Group :: i2c_env_pkg::i2c_scl_stretch_cg

Group : i2c_env_pkg::i2c_scl_stretch_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv

---

Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group i2c_env_pkg::i2c_scl_stretch_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acq_fifo_size	2	0	2	100.00	100	1	1	0
cp_host_mode_stretch	1	0	1	100.00	100	1	1	0
cp_target_scl_stretch_addr_write	1	0	1	100.00	100	1	1	0
cp_tx_fifo_size	2	0	2	100.00	100	1	1	0

Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_target_scl_stretch_read	4	0	4	100.00	100	1	1	0

Summary for Variable cp_acq_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_acq_fifo_size

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_empty

106917089

1

T5

6

T6

768

T8

332

empty

98202956

1

T1

1094

T2

195014

T3

87365

---

Summary for Variable cp_host_mode_stretch

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins

NAME	COUNT	STATUS
unused	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

stretch

62951524

1

T1

1094

T2

72712

T3

85812

---

Summary for Variable cp_target_scl_stretch_addr_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_target_scl_stretch_addr_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

addr_write_byte_stretch

395690

1

T14

20864

T15

3333

T16

3387

---

Summary for Variable cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_tx_fifo_size

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

not_empty

43446558

1

T6

123

T8

169

T17

3899

empty

161673503

1

T1

1094

T2

195014

T3

87365

---

Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for cp_target_scl_stretch_read

Bins

cp_acq_fifo_size

cp_tx_fifo_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

empty

not_empty

49

1

T280

49

-

-

-

-

empty

empty

395779

1

T6

248

T8

6

T9

6931

User Defined Cross Bins for cp_target_scl_stretch_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read_byte_stretch

190014

1

T6

645

T8

84

T17

407

scl_stretch_read_request

43635114

1

T6

768

T8

253

T17

4306