Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	916488	1			T1	220		T2	3		T3	356
all_pins[1]	916488	1			T1	220		T2	3		T3	356
all_pins[2]	916488	1			T1	220		T2	3		T3	356
all_pins[3]	916488	1			T1	220		T2	3		T3	356
all_pins[4]	916488	1			T1	220		T2	3		T3	356
all_pins[5]	916488	1			T1	220		T2	3		T3	356
all_pins[6]	916488	1			T1	220		T2	3		T3	356
all_pins[7]	916488	1			T1	220		T2	3		T3	356
all_pins[8]	916488	1			T1	220		T2	3		T3	356
all_pins[9]	916488	1			T1	220		T2	3		T3	356
all_pins[10]	916488	1			T1	220		T2	3		T3	356
all_pins[11]	916488	1			T1	220		T2	3		T3	356
all_pins[12]	916488	1			T1	220		T2	3		T3	356
all_pins[13]	916488	1			T1	220		T2	3		T3	356
all_pins[14]	916488	1			T1	220		T2	3		T3	356

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11238861	1			T1	2868		T2	39		T3	4472
values[0x1]	2508459	1			T1	432		T2	6		T3	868
transitions[0x0=>0x1]	2507538	1			T1	432		T2	6		T3	868
transitions[0x1=>0x0]	2506395	1			T1	431		T2	5		T3	867

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	87143	1			T1	5		T2	1		T3	14
all_pins[0]	values[0x1]	829345	1			T1	215		T2	2		T3	342
all_pins[0]	transitions[0x0=>0x1]	828808	1			T1	215		T2	2		T3	342
all_pins[0]	transitions[0x1=>0x0]	116	1			T81	3		T221	1		T54	1
all_pins[1]	values[0x0]	915835	1			T1	220		T2	3		T3	356
all_pins[1]	values[0x1]	653	1			T80	6		T268	1		T81	4
all_pins[1]	transitions[0x0=>0x1]	629	1			T80	6		T268	1		T81	4
all_pins[1]	transitions[0x1=>0x0]	122	1			T80	1		T31	1		T33	1
all_pins[2]	values[0x0]	916342	1			T1	220		T2	3		T3	356
all_pins[2]	values[0x1]	146	1			T80	1		T31	1		T33	1
all_pins[2]	transitions[0x0=>0x1]	123	1			T80	1		T31	1		T33	1
all_pins[2]	transitions[0x1=>0x0]	92	1			T80	2		T31	1		T33	2
all_pins[3]	values[0x0]	916373	1			T1	220		T2	3		T3	356
all_pins[3]	values[0x1]	115	1			T80	2		T31	1		T33	2
all_pins[3]	transitions[0x0=>0x1]	98	1			T80	2		T31	1		T33	2
all_pins[3]	transitions[0x1=>0x0]	80	1			T34	1		T81	1		T33	1
all_pins[4]	values[0x0]	916391	1			T1	220		T2	3		T3	356
all_pins[4]	values[0x1]	97	1			T34	1		T81	1		T33	1
all_pins[4]	transitions[0x0=>0x1]	77	1			T34	1		T81	1		T33	1
all_pins[4]	transitions[0x1=>0x0]	97	1			T80	1		T81	3		T31	1
all_pins[5]	values[0x0]	916371	1			T1	220		T2	3		T3	356
all_pins[5]	values[0x1]	117	1			T80	1		T81	3		T31	1
all_pins[5]	transitions[0x0=>0x1]	81	1			T80	1		T81	2		T31	1
all_pins[5]	transitions[0x1=>0x0]	66	1			T81	2		T221	1		T269	1
all_pins[6]	values[0x0]	916386	1			T1	220		T2	3		T3	356
all_pins[6]	values[0x1]	102	1			T81	3		T33	1		T221	2
all_pins[6]	transitions[0x0=>0x1]	84	1			T81	3		T221	1		T54	2
all_pins[6]	transitions[0x1=>0x0]	35319	1			T1	2		T2	1		T3	155
all_pins[7]	values[0x0]	881151	1			T1	218		T2	2		T3	201
all_pins[7]	values[0x1]	35337	1			T1	2		T2	1		T3	155
all_pins[7]	transitions[0x0=>0x1]	35313	1			T1	2		T2	1		T3	155
all_pins[7]	transitions[0x1=>0x0]	86	1			T80	2		T81	4		T33	2
all_pins[8]	values[0x0]	916378	1			T1	220		T2	3		T3	356
all_pins[8]	values[0x1]	110	1			T80	2		T81	5		T33	2
all_pins[8]	transitions[0x0=>0x1]	91	1			T80	2		T81	5		T33	2
all_pins[8]	transitions[0x1=>0x0]	732194	1			T2	1		T3	18		T4	1
all_pins[9]	values[0x0]	184275	1			T1	220		T2	2		T3	338
all_pins[9]	values[0x1]	732213	1			T2	1		T3	18		T4	1
all_pins[9]	transitions[0x0=>0x1]	732195	1			T2	1		T3	18		T4	1
all_pins[9]	transitions[0x1=>0x0]	89	1			T80	2		T31	1		T33	3
all_pins[10]	values[0x0]	916381	1			T1	220		T2	3		T3	356
all_pins[10]	values[0x1]	107	1			T80	3		T31	1		T33	3
all_pins[10]	transitions[0x0=>0x1]	70	1			T80	1		T31	1		T33	2
all_pins[10]	transitions[0x1=>0x0]	909725	1			T1	215		T2	2		T3	353
all_pins[11]	values[0x0]	6726	1			T1	5		T2	1		T3	3
all_pins[11]	values[0x1]	909762	1			T1	215		T2	2		T3	353
all_pins[11]	transitions[0x0=>0x1]	909721	1			T1	215		T2	2		T3	353
all_pins[11]	transitions[0x1=>0x0]	71	1			T80	2		T81	1		T221	1
all_pins[12]	values[0x0]	916376	1			T1	220		T2	3		T3	356
all_pins[12]	values[0x1]	112	1			T80	2		T81	1		T221	1
all_pins[12]	transitions[0x0=>0x1]	88	1			T81	1		T221	1		T246	1
all_pins[12]	transitions[0x1=>0x0]	96	1			T80	2		T81	3		T31	2
all_pins[13]	values[0x0]	916368	1			T1	220		T2	3		T3	356
all_pins[13]	values[0x1]	120	1			T80	4		T81	3		T31	2
all_pins[13]	transitions[0x0=>0x1]	83	1			T80	4		T81	1		T54	1
all_pins[13]	transitions[0x1=>0x0]	86	1			T80	3		T81	1		T33	1
all_pins[14]	values[0x0]	916365	1			T1	220		T2	3		T3	356
all_pins[14]	values[0x1]	123	1			T80	3		T81	3		T31	2
all_pins[14]	transitions[0x0=>0x1]	77	1			T80	3		T81	2		T31	1
all_pins[14]	transitions[0x1=>0x0]	828156	1			T1	214		T2	1		T3	341