Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	465	1			T80	7		T81	7		T31	4
all_values[1]	465	1			T80	7		T81	7		T31	4
all_values[2]	465	1			T80	7		T81	7		T31	4
all_values[3]	465	1			T80	7		T81	7		T31	4
all_values[4]	465	1			T80	7		T81	7		T31	4
all_values[5]	465	1			T80	7		T81	7		T31	4
all_values[6]	465	1			T80	7		T81	7		T31	4
all_values[7]	465	1			T80	7		T81	7		T31	4
all_values[8]	465	1			T80	7		T81	7		T31	4
all_values[9]	465	1			T80	7		T81	7		T31	4
all_values[10]	465	1			T80	7		T81	7		T31	4
all_values[11]	465	1			T80	7		T81	7		T31	4
all_values[12]	465	1			T80	7		T81	7		T31	4
all_values[13]	465	1			T80	7		T81	7		T31	4
all_values[14]	465	1			T80	7		T81	7		T31	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3648

1

T80

45

T81

41

T31

28

auto[1]

3327

1

T80

60

T81

64

T31

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T80

22

T81

14

T31

15

auto[1]

5869

1

T80

83

T81

91

T31

45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4091

1

T80

65

T81

59

T31

38

auto[1]

2884

1

T80

40

T81

46

T31

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	52	1			T31	2		T33	1		T54	5
all_values[0]	auto[0]	auto[0]	auto[1]	105	1			T80	2		T81	1		T31	1
all_values[0]	auto[0]	auto[1]	auto[0]	24	1			T81	1		T54	2		T270	1
all_values[0]	auto[0]	auto[1]	auto[1]	97	1			T80	4		T81	2		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	114	1			T81	3		T31	1		T33	2
all_values[0]	auto[1]	auto[1]	auto[1]	73	1			T80	1		T33	2		T221	4
all_values[1]	auto[0]	auto[0]	auto[0]	50	1			T33	4		T111	1		T271	2
all_values[1]	auto[0]	auto[0]	auto[1]	90	1			T80	1		T33	1		T221	1
all_values[1]	auto[0]	auto[1]	auto[0]	38	1			T80	1		T81	1		T31	1
all_values[1]	auto[0]	auto[1]	auto[1]	117	1			T80	3		T81	3		T31	2
all_values[1]	auto[1]	auto[0]	auto[1]	100	1			T80	2		T81	1		T221	4
all_values[1]	auto[1]	auto[1]	auto[1]	70	1			T81	2		T31	1		T33	1
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T54	1		T272	1		T111	1
all_values[2]	auto[0]	auto[0]	auto[1]	98	1			T80	1		T81	2		T31	1
all_values[2]	auto[0]	auto[1]	auto[0]	30	1			T81	2		T54	3		T269	1
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T80	3		T81	1		T31	1
all_values[2]	auto[1]	auto[0]	auto[1]	99	1			T81	1		T31	1		T33	4
all_values[2]	auto[1]	auto[1]	auto[1]	99	1			T80	3		T81	1		T31	1
all_values[3]	auto[0]	auto[0]	auto[0]	37	1			T80	1		T31	1		T33	1
all_values[3]	auto[0]	auto[0]	auto[1]	104	1			T80	1		T81	2		T31	2
all_values[3]	auto[0]	auto[1]	auto[0]	32	1			T80	1		T81	1		T221	1
all_values[3]	auto[0]	auto[1]	auto[1]	107	1			T80	1		T81	1		T33	2
all_values[3]	auto[1]	auto[0]	auto[1]	96	1			T80	1		T81	2		T31	1
all_values[3]	auto[1]	auto[1]	auto[1]	89	1			T80	2		T81	1		T221	2
all_values[4]	auto[0]	auto[0]	auto[0]	29	1			T81	1		T260	1		T112	2
all_values[4]	auto[0]	auto[0]	auto[1]	108	1			T80	4		T81	1		T31	1
all_values[4]	auto[0]	auto[1]	auto[0]	34	1			T81	3		T272	2		T112	1
all_values[4]	auto[0]	auto[1]	auto[1]	109	1			T31	2		T33	3		T221	5
all_values[4]	auto[1]	auto[0]	auto[1]	105	1			T80	3		T81	1		T31	1
all_values[4]	auto[1]	auto[1]	auto[1]	80	1			T81	1		T33	1		T221	5
all_values[5]	auto[0]	auto[0]	auto[0]	37	1			T260	1		T270	1		T112	2
all_values[5]	auto[0]	auto[0]	auto[1]	96	1			T80	3		T33	1		T221	4
all_values[5]	auto[0]	auto[1]	auto[0]	35	1			T80	1		T33	1		T221	1
all_values[5]	auto[0]	auto[1]	auto[1]	103	1			T81	2		T31	2		T33	1
all_values[5]	auto[1]	auto[0]	auto[1]	96	1			T80	2		T221	1		T54	2
all_values[5]	auto[1]	auto[1]	auto[1]	98	1			T80	1		T81	5		T31	2
all_values[6]	auto[0]	auto[0]	auto[0]	55	1			T33	1		T221	1		T271	1
all_values[6]	auto[0]	auto[0]	auto[1]	86	1			T80	1		T81	2		T33	1
all_values[6]	auto[0]	auto[1]	auto[0]	53	1			T80	4		T31	1		T221	4
all_values[6]	auto[0]	auto[1]	auto[1]	98	1			T80	1		T81	1		T31	2
all_values[6]	auto[1]	auto[0]	auto[1]	96	1			T80	1		T81	1		T33	4
all_values[6]	auto[1]	auto[1]	auto[1]	77	1			T81	3		T31	1		T221	2
all_values[7]	auto[0]	auto[0]	auto[0]	55	1			T80	6		T33	2		T54	1
all_values[7]	auto[0]	auto[0]	auto[1]	98	1			T81	1		T33	2		T54	1
all_values[7]	auto[0]	auto[1]	auto[0]	31	1			T80	1		T269	1		T272	3
all_values[7]	auto[0]	auto[1]	auto[1]	93	1			T81	3		T31	2		T221	4
all_values[7]	auto[1]	auto[0]	auto[1]	104	1			T81	2		T33	1		T221	2
all_values[7]	auto[1]	auto[1]	auto[1]	84	1			T81	1		T31	2		T33	2
all_values[8]	auto[0]	auto[0]	auto[0]	39	1			T31	2		T33	1		T221	1
all_values[8]	auto[0]	auto[0]	auto[1]	105	1			T80	1		T33	2		T221	3
all_values[8]	auto[0]	auto[1]	auto[0]	20	1			T31	2		T221	1		T54	1
all_values[8]	auto[0]	auto[1]	auto[1]	101	1			T80	3		T81	2		T33	2
all_values[8]	auto[1]	auto[0]	auto[1]	113	1			T80	2		T81	1		T33	1
all_values[8]	auto[1]	auto[1]	auto[1]	87	1			T80	1		T81	4		T33	1
all_values[9]	auto[0]	auto[0]	auto[0]	36	1			T80	1		T54	1		T272	1
all_values[9]	auto[0]	auto[0]	auto[1]	96	1			T80	1		T81	2		T31	2
all_values[9]	auto[0]	auto[1]	auto[0]	29	1			T80	3		T81	1		T33	1
all_values[9]	auto[0]	auto[1]	auto[1]	110	1			T81	2		T33	2		T221	4
all_values[9]	auto[1]	auto[0]	auto[1]	117	1			T81	1		T31	2		T221	2
all_values[9]	auto[1]	auto[1]	auto[1]	77	1			T80	2		T81	1		T33	3
all_values[10]	auto[0]	auto[0]	auto[0]	31	1			T54	1		T269	1		T260	1
all_values[10]	auto[0]	auto[0]	auto[1]	107	1			T81	2		T31	1		T33	1
all_values[10]	auto[0]	auto[1]	auto[0]	23	1			T81	2		T31	1		T269	1
all_values[10]	auto[0]	auto[1]	auto[1]	94	1			T80	4		T81	2		T33	2
all_values[10]	auto[1]	auto[0]	auto[1]	109	1			T81	1		T31	1		T33	1
all_values[10]	auto[1]	auto[1]	auto[1]	101	1			T80	3		T31	1		T33	3
all_values[11]	auto[0]	auto[0]	auto[0]	43	1			T80	1		T31	1		T54	1
all_values[11]	auto[0]	auto[0]	auto[1]	93	1			T81	1		T33	1		T221	3
all_values[11]	auto[0]	auto[1]	auto[0]	29	1			T80	2		T221	1		T271	1
all_values[11]	auto[0]	auto[1]	auto[1]	100	1			T80	1		T81	1		T31	1
all_values[11]	auto[1]	auto[0]	auto[1]	110	1			T81	3		T31	1		T33	2
all_values[11]	auto[1]	auto[1]	auto[1]	90	1			T80	3		T81	2		T31	1
all_values[12]	auto[0]	auto[0]	auto[0]	39	1			T31	2		T221	1		T270	2
all_values[12]	auto[0]	auto[0]	auto[1]	102	1			T80	1		T81	3		T33	1
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T31	2		T33	1		T221	1
all_values[12]	auto[0]	auto[1]	auto[1]	105	1			T80	2		T81	3		T33	4
all_values[12]	auto[1]	auto[0]	auto[1]	100	1			T80	2		T221	2		T54	1
all_values[12]	auto[1]	auto[1]	auto[1]	90	1			T80	2		T81	1		T33	1
all_values[13]	auto[0]	auto[0]	auto[0]	43	1			T111	1		T115	1		T77	1
all_values[13]	auto[0]	auto[0]	auto[1]	88	1			T80	1		T81	1		T31	1
all_values[13]	auto[0]	auto[1]	auto[0]	27	1			T81	1		T221	4		T272	1
all_values[13]	auto[0]	auto[1]	auto[1]	93	1			T80	2		T81	2		T31	1
all_values[13]	auto[1]	auto[0]	auto[1]	107	1			T81	2		T31	1		T33	2
all_values[13]	auto[1]	auto[1]	auto[1]	107	1			T80	4		T81	1		T31	1
all_values[14]	auto[0]	auto[0]	auto[0]	46	1			T54	3		T269	2		T260	3
all_values[14]	auto[0]	auto[0]	auto[1]	71	1			T80	1		T33	1		T221	1
all_values[14]	auto[0]	auto[1]	auto[0]	35	1			T81	1		T269	3		T270	2
all_values[14]	auto[0]	auto[1]	auto[1]	117	1			T80	1		T81	2		T31	1
all_values[14]	auto[1]	auto[0]	auto[1]	98	1			T80	5		T81	3		T31	2
all_values[14]	auto[1]	auto[1]	auto[1]	98	1			T81	1		T31	1		T33	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal