Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	889329	1			T1	238		T2	1		T3	3
all_values[1]	889329	1			T1	238		T2	1		T3	3
all_values[2]	889329	1			T1	238		T2	1		T3	3
all_values[3]	889329	1			T1	238		T2	1		T3	3
all_values[4]	889329	1			T1	238		T2	1		T3	3
all_values[5]	889329	1			T1	238		T2	1		T3	3
all_values[6]	889329	1			T1	238		T2	1		T3	3
all_values[7]	889329	1			T1	238		T2	1		T3	3
all_values[8]	889329	1			T1	238		T2	1		T3	3
all_values[9]	889329	1			T1	238		T2	1		T3	3
all_values[10]	889329	1			T1	238		T2	1		T3	3
all_values[11]	889329	1			T1	238		T2	1		T3	3
all_values[12]	889329	1			T1	238		T2	1		T3	3
all_values[13]	889329	1			T1	238		T2	1		T3	3
all_values[14]	889329	1			T1	238		T2	1		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10944066

1

T1

3090

T2

15

T3

39

auto[1]

2395869

1

T1

480

T3

6

T4

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12467813

1

T1

3570

T2

15

T3

45

auto[1]

872122

1

T34

120

T143

238

T77

144877

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	95213	1			T1	20		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	5303	1			T34	3		T143	12		T77	55
all_values[0]	auto[1]	auto[0]	741652	1			T1	218		T3	2		T4	2
all_values[0]	auto[1]	auto[1]	47161	1			T34	5		T143	5		T77	9604
all_values[1]	auto[0]	auto[0]	828848	1			T1	238		T2	1		T3	3
all_values[1]	auto[0]	auto[1]	59717	1			T34	6		T143	10		T77	9654
all_values[1]	auto[1]	auto[0]	556	1			T215	24		T35	18		T103	37
all_values[1]	auto[1]	auto[1]	208	1			T34	2		T143	5		T77	3
all_values[2]	auto[0]	auto[0]	829364	1			T1	238		T2	1		T3	3
all_values[2]	auto[0]	auto[1]	59717	1			T34	7		T143	10		T77	9656
all_values[2]	auto[1]	auto[0]	50	1			T226	1		T230	1		T231	1
all_values[2]	auto[1]	auto[1]	198	1			T34	2		T143	3		T77	2
all_values[3]	auto[0]	auto[0]	829401	1			T1	238		T2	1		T3	3
all_values[3]	auto[0]	auto[1]	59690	1			T34	5		T143	17		T77	9656
all_values[3]	auto[1]	auto[1]	238	1			T34	4		T77	2		T59	8
all_values[4]	auto[0]	auto[0]	836596	1			T1	238		T2	1		T3	3
all_values[4]	auto[0]	auto[1]	52515	1			T34	7		T143	12		T77	9654
all_values[4]	auto[1]	auto[0]	27	1			T41	1		T42	4		T232	2
all_values[4]	auto[1]	auto[1]	191	1			T34	2		T143	5		T77	4
all_values[5]	auto[0]	auto[0]	830292	1			T1	238		T2	1		T3	3
all_values[5]	auto[0]	auto[1]	58802	1			T34	7		T143	14		T77	9653
all_values[5]	auto[1]	auto[1]	235	1			T34	2		T143	3		T77	4
all_values[6]	auto[0]	auto[0]	829405	1			T1	238		T2	1		T3	3
all_values[6]	auto[0]	auto[1]	59670	1			T34	7		T143	11		T77	9652
all_values[6]	auto[1]	auto[1]	254	1			T34	2		T143	5		T77	7
all_values[7]	auto[0]	auto[0]	806213	1			T1	221		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	50307	1			T34	4		T143	8		T77	9519
all_values[7]	auto[1]	auto[0]	30427	1			T1	17		T3	1		T4	1
all_values[7]	auto[1]	auto[1]	2382	1			T34	3		T143	8		T77	140
all_values[8]	auto[0]	auto[0]	829387	1			T1	238		T2	1		T3	3
all_values[8]	auto[0]	auto[1]	59692	1			T34	7		T143	13		T77	9654
all_values[8]	auto[1]	auto[1]	250	1			T34	2		T143	4		T77	5
all_values[9]	auto[0]	auto[0]	184394	1			T1	228		T2	1		T3	2
all_values[9]	auto[0]	auto[1]	19824	1			T34	6		T143	7		T77	428
all_values[9]	auto[1]	auto[0]	645000	1			T1	10		T3	1		T4	1
all_values[9]	auto[1]	auto[1]	40111	1			T34	3		T143	8		T77	9231
all_values[10]	auto[0]	auto[0]	829663	1			T1	238		T2	1		T3	3
all_values[10]	auto[0]	auto[1]	59450	1			T34	6		T143	10		T77	9655
all_values[10]	auto[1]	auto[1]	216	1			T34	3		T143	5		T77	4
all_values[11]	auto[0]	auto[0]	2886	1			T1	3		T2	1		T3	1
all_values[11]	auto[0]	auto[1]	446	1			T34	5		T143	6		T77	14
all_values[11]	auto[1]	auto[0]	826538	1			T1	235		T3	2		T4	2
all_values[11]	auto[1]	auto[1]	59459	1			T34	4		T143	6		T77	9645
all_values[12]	auto[0]	auto[0]	829395	1			T1	238		T2	1		T3	3
all_values[12]	auto[0]	auto[1]	59706	1			T34	6		T143	13		T77	9655
all_values[12]	auto[1]	auto[0]	8	1			T226	1		T233	1		T234	1
all_values[12]	auto[1]	auto[1]	220	1			T34	1		T143	4		T77	3
all_values[13]	auto[0]	auto[0]	833094	1			T1	238		T2	1		T3	3
all_values[13]	auto[0]	auto[1]	55997	1			T34	5		T143	11		T77	9656
all_values[13]	auto[1]	auto[1]	238	1			T34	4		T143	6		T77	3
all_values[14]	auto[0]	auto[0]	829404	1			T1	238		T2	1		T3	3
all_values[14]	auto[0]	auto[1]	59675	1			T143	11		T77	9654		T59	1778
all_values[14]	auto[1]	auto[1]	250	1			T143	6		T77	5		T59	1