Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	889329	1			T1	238		T2	1		T3	3
all_pins[1]	889329	1			T1	238		T2	1		T3	3
all_pins[2]	889329	1			T1	238		T2	1		T3	3
all_pins[3]	889329	1			T1	238		T2	1		T3	3
all_pins[4]	889329	1			T1	238		T2	1		T3	3
all_pins[5]	889329	1			T1	238		T2	1		T3	3
all_pins[6]	889329	1			T1	238		T2	1		T3	3
all_pins[7]	889329	1			T1	238		T2	1		T3	3
all_pins[8]	889329	1			T1	238		T2	1		T3	3
all_pins[9]	889329	1			T1	238		T2	1		T3	3
all_pins[10]	889329	1			T1	238		T2	1		T3	3
all_pins[11]	889329	1			T1	238		T2	1		T3	3
all_pins[12]	889329	1			T1	238		T2	1		T3	3
all_pins[13]	889329	1			T1	238		T2	1		T3	3
all_pins[14]	889329	1			T1	238		T2	1		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10949235	1			T1	3088		T2	15		T3	39
values[0x1]	2390700	1			T1	482		T3	6		T4	6
transitions[0x0=>0x1]	2389627	1			T1	482		T3	6		T4	6
transitions[0x1=>0x0]	2388479	1			T1	481		T3	5		T4	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	103698	1			T1	19		T2	1		T3	1
all_pins[0]	values[0x1]	785631	1			T1	219		T3	2		T4	2
all_pins[0]	transitions[0x0=>0x1]	784918	1			T1	219		T3	2		T4	2
all_pins[0]	transitions[0x1=>0x0]	80	1			T34	1		T143	1		T59	2
all_pins[1]	values[0x0]	888536	1			T1	238		T2	1		T3	3
all_pins[1]	values[0x1]	793	1			T34	1		T143	1		T215	31
all_pins[1]	transitions[0x0=>0x1]	775	1			T34	1		T143	1		T215	31
all_pins[1]	transitions[0x1=>0x0]	132	1			T34	1		T226	1		T230	1
all_pins[2]	values[0x0]	889179	1			T1	238		T2	1		T3	3
all_pins[2]	values[0x1]	150	1			T34	1		T226	1		T230	1
all_pins[2]	transitions[0x0=>0x1]	121	1			T226	1		T230	1		T77	1
all_pins[2]	transitions[0x1=>0x0]	96	1			T34	3		T59	3		T50	1
all_pins[3]	values[0x0]	889204	1			T1	238		T2	1		T3	3
all_pins[3]	values[0x1]	125	1			T34	4		T77	1		T59	4
all_pins[3]	transitions[0x0=>0x1]	100	1			T34	2		T59	2		T50	1
all_pins[3]	transitions[0x1=>0x0]	101	1			T41	1		T42	5		T232	3
all_pins[4]	values[0x0]	889203	1			T1	238		T2	1		T3	3
all_pins[4]	values[0x1]	126	1			T41	1		T42	5		T232	3
all_pins[4]	transitions[0x0=>0x1]	105	1			T41	1		T42	5		T232	3
all_pins[4]	transitions[0x1=>0x0]	84	1			T77	1		T50	2		T104	1
all_pins[5]	values[0x0]	889224	1			T1	238		T2	1		T3	3
all_pins[5]	values[0x1]	105	1			T34	2		T143	1		T77	1
all_pins[5]	transitions[0x0=>0x1]	80	1			T143	1		T59	1		T50	2
all_pins[5]	transitions[0x1=>0x0]	93	1			T143	2		T77	1		T59	3
all_pins[6]	values[0x0]	889211	1			T1	238		T2	1		T3	3
all_pins[6]	values[0x1]	118	1			T34	2		T143	2		T77	2
all_pins[6]	transitions[0x0=>0x1]	94	1			T34	2		T143	1		T59	3
all_pins[6]	transitions[0x1=>0x0]	35631	1			T1	18		T3	1		T4	1
all_pins[7]	values[0x0]	853674	1			T1	220		T2	1		T3	2
all_pins[7]	values[0x1]	35655	1			T1	18		T3	1		T4	1
all_pins[7]	transitions[0x0=>0x1]	35638	1			T1	18		T3	1		T4	1
all_pins[7]	transitions[0x1=>0x0]	87	1			T34	1		T77	2		T59	1
all_pins[8]	values[0x0]	889225	1			T1	238		T2	1		T3	3
all_pins[8]	values[0x1]	104	1			T34	1		T143	2		T77	4
all_pins[8]	transitions[0x0=>0x1]	76	1			T143	1		T50	1		T104	1
all_pins[8]	transitions[0x1=>0x0]	684986	1			T1	10		T3	1		T4	1
all_pins[9]	values[0x0]	204315	1			T1	228		T2	1		T3	2
all_pins[9]	values[0x1]	685014	1			T1	10		T3	1		T4	1
all_pins[9]	transitions[0x0=>0x1]	684990	1			T1	10		T3	1		T4	1
all_pins[9]	transitions[0x1=>0x0]	78	1			T34	2		T143	1		T59	2
all_pins[10]	values[0x0]	889227	1			T1	238		T2	1		T3	3
all_pins[10]	values[0x1]	102	1			T34	3		T143	1		T77	1
all_pins[10]	transitions[0x0=>0x1]	75	1			T34	3		T77	1		T59	2
all_pins[10]	transitions[0x1=>0x0]	882385	1			T1	235		T3	2		T4	2
all_pins[11]	values[0x0]	6917	1			T1	3		T2	1		T3	1
all_pins[11]	values[0x1]	882412	1			T1	235		T3	2		T4	2
all_pins[11]	transitions[0x0=>0x1]	882383	1			T1	235		T3	2		T4	2
all_pins[11]	transitions[0x1=>0x0]	87	1			T77	3		T59	4		T50	2
all_pins[12]	values[0x0]	889213	1			T1	238		T2	1		T3	3
all_pins[12]	values[0x1]	116	1			T226	1		T77	3		T231	1
all_pins[12]	transitions[0x0=>0x1]	90	1			T226	1		T77	3		T231	1
all_pins[12]	transitions[0x1=>0x0]	93	1			T34	2		T143	1		T77	2
all_pins[13]	values[0x0]	889210	1			T1	238		T2	1		T3	3
all_pins[13]	values[0x1]	119	1			T34	2		T143	1		T77	2
all_pins[13]	transitions[0x0=>0x1]	92	1			T34	2		T143	1		T77	2
all_pins[13]	transitions[0x1=>0x0]	103	1			T143	3		T77	3		T50	1
all_pins[14]	values[0x0]	889199	1			T1	238		T2	1		T3	3
all_pins[14]	values[0x1]	130	1			T143	3		T77	3		T59	1
all_pins[14]	transitions[0x0=>0x1]	90	1			T143	3		T77	3		T59	1
all_pins[14]	transitions[0x1=>0x0]	784443	1			T1	218		T3	1		T4	1