Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	492	1			T34	4		T143	11		T77	7
all_values[1]	492	1			T34	4		T143	11		T77	7
all_values[2]	492	1			T34	4		T143	11		T77	7
all_values[3]	492	1			T34	4		T143	11		T77	7
all_values[4]	492	1			T34	4		T143	11		T77	7
all_values[5]	492	1			T34	4		T143	11		T77	7
all_values[6]	492	1			T34	4		T143	11		T77	7
all_values[7]	492	1			T34	4		T143	11		T77	7
all_values[8]	492	1			T34	4		T143	11		T77	7
all_values[9]	492	1			T34	4		T143	11		T77	7
all_values[10]	492	1			T34	4		T143	11		T77	7
all_values[11]	492	1			T34	4		T143	11		T77	7
all_values[12]	492	1			T34	4		T143	11		T77	7
all_values[13]	492	1			T34	4		T143	11		T77	7
all_values[14]	492	1			T34	4		T143	11		T77	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3997

1

T34

37

T143

91

T77

58

auto[1]

3383

1

T34

23

T143

74

T77

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073

1

T34

10

T143

17

T77

8

auto[1]

6307

1

T34

50

T143

148

T77

97

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4324

1

T34

33

T143

99

T77

51

auto[1]

3056

1

T34

27

T143

66

T77

54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	50	1			T34	1		T50	1		T257	1
all_values[0]	auto[0]	auto[0]	auto[1]	97	1			T34	1		T143	5		T77	2
all_values[0]	auto[0]	auto[1]	auto[0]	28	1			T257	2		T51	1		T54	2
all_values[0]	auto[0]	auto[1]	auto[1]	128	1			T143	4		T77	1		T59	5
all_values[0]	auto[1]	auto[0]	auto[1]	102	1			T34	2		T143	1		T77	3
all_values[0]	auto[1]	auto[1]	auto[1]	87	1			T143	1		T77	1		T59	3
all_values[1]	auto[0]	auto[0]	auto[0]	45	1			T34	1		T143	1		T77	2
all_values[1]	auto[0]	auto[0]	auto[1]	105	1			T34	1		T143	3		T77	2
all_values[1]	auto[0]	auto[1]	auto[0]	29	1			T143	1		T50	1		T54	1
all_values[1]	auto[0]	auto[1]	auto[1]	108	1			T143	1		T59	7		T104	2
all_values[1]	auto[1]	auto[0]	auto[1]	124	1			T34	2		T143	4		T77	3
all_values[1]	auto[1]	auto[1]	auto[1]	81	1			T143	1		T59	3		T50	2
all_values[2]	auto[0]	auto[0]	auto[0]	50	1			T143	1		T77	1		T59	1
all_values[2]	auto[0]	auto[0]	auto[1]	113	1			T34	1		T143	4		T77	1
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T143	3		T59	2		T50	1
all_values[2]	auto[0]	auto[1]	auto[1]	100	1			T34	1		T77	3		T59	5
all_values[2]	auto[1]	auto[0]	auto[1]	106	1			T34	2		T143	3		T59	2
all_values[2]	auto[1]	auto[1]	auto[1]	92	1			T77	2		T59	1		T50	1
all_values[3]	auto[0]	auto[0]	auto[0]	40	1			T77	1		T104	1		T257	1
all_values[3]	auto[0]	auto[0]	auto[1]	109	1			T143	5		T77	2		T59	6
all_values[3]	auto[0]	auto[1]	auto[0]	17	1			T54	1		T258	1		T259	2
all_values[3]	auto[0]	auto[1]	auto[1]	102	1			T34	2		T143	3		T59	1
all_values[3]	auto[1]	auto[0]	auto[1]	123	1			T34	1		T77	2		T59	3
all_values[3]	auto[1]	auto[1]	auto[1]	101	1			T34	1		T143	3		T77	2
all_values[4]	auto[0]	auto[0]	auto[0]	38	1			T77	1		T260	1		T53	1
all_values[4]	auto[0]	auto[0]	auto[1]	128	1			T143	1		T77	2		T59	5
all_values[4]	auto[0]	auto[1]	auto[0]	21	1			T50	1		T107	4		T261	2
all_values[4]	auto[0]	auto[1]	auto[1]	114	1			T34	2		T143	5		T59	3
all_values[4]	auto[1]	auto[0]	auto[1]	109	1			T34	1		T143	2		T77	3
all_values[4]	auto[1]	auto[1]	auto[1]	82	1			T34	1		T143	3		T77	1
all_values[5]	auto[0]	auto[0]	auto[0]	46	1			T77	2		T50	1		T260	1
all_values[5]	auto[0]	auto[0]	auto[1]	115	1			T143	5		T77	2		T59	5
all_values[5]	auto[0]	auto[1]	auto[0]	29	1			T257	1		T51	1		T107	1
all_values[5]	auto[0]	auto[1]	auto[1]	99	1			T34	2		T143	3		T59	4
all_values[5]	auto[1]	auto[0]	auto[1]	113	1			T34	1		T143	2		T77	1
all_values[5]	auto[1]	auto[1]	auto[1]	90	1			T34	1		T143	1		T77	2
all_values[6]	auto[0]	auto[0]	auto[0]	52	1			T59	1		T260	2		T257	1
all_values[6]	auto[0]	auto[0]	auto[1]	107	1			T143	3		T77	2		T59	4
all_values[6]	auto[0]	auto[1]	auto[0]	24	1			T143	1		T50	1		T104	1
all_values[6]	auto[0]	auto[1]	auto[1]	111	1			T34	2		T143	2		T77	2
all_values[6]	auto[1]	auto[0]	auto[1]	118	1			T34	1		T143	3		T77	2
all_values[6]	auto[1]	auto[1]	auto[1]	80	1			T34	1		T143	2		T77	1
all_values[7]	auto[0]	auto[0]	auto[0]	40	1			T34	1		T59	3		T50	1
all_values[7]	auto[0]	auto[0]	auto[1]	119	1			T34	1		T143	2		T77	2
all_values[7]	auto[0]	auto[1]	auto[0]	36	1			T34	1		T143	1		T59	2
all_values[7]	auto[0]	auto[1]	auto[1]	104	1			T143	3		T77	1		T59	3
all_values[7]	auto[1]	auto[0]	auto[1]	105	1			T34	1		T143	3		T77	1
all_values[7]	auto[1]	auto[1]	auto[1]	88	1			T143	2		T77	3		T50	1
all_values[8]	auto[0]	auto[0]	auto[0]	36	1			T59	3		T50	1		T51	1
all_values[8]	auto[0]	auto[0]	auto[1]	138	1			T34	2		T143	6		T59	5
all_values[8]	auto[0]	auto[1]	auto[0]	18	1			T54	1		T107	1		T259	2
all_values[8]	auto[0]	auto[1]	auto[1]	95	1			T143	1		T77	2		T59	1
all_values[8]	auto[1]	auto[0]	auto[1]	123	1			T34	1		T143	2		T77	2
all_values[8]	auto[1]	auto[1]	auto[1]	82	1			T34	1		T143	2		T77	3
all_values[9]	auto[0]	auto[0]	auto[0]	44	1			T59	4		T50	1		T260	2
all_values[9]	auto[0]	auto[0]	auto[1]	128	1			T34	2		T143	2		T59	5
all_values[9]	auto[0]	auto[1]	auto[0]	17	1			T143	2		T59	1		T260	1
all_values[9]	auto[0]	auto[1]	auto[1]	98	1			T77	3		T59	2		T50	2
all_values[9]	auto[1]	auto[0]	auto[1]	117	1			T34	1		T143	5		T77	1
all_values[9]	auto[1]	auto[1]	auto[1]	88	1			T34	1		T143	2		T77	3
all_values[10]	auto[0]	auto[0]	auto[0]	55	1			T143	1		T50	1		T260	2
all_values[10]	auto[0]	auto[0]	auto[1]	105	1			T143	3		T77	2		T59	4
all_values[10]	auto[0]	auto[1]	auto[0]	28	1			T143	1		T54	1		T114	1
all_values[10]	auto[0]	auto[1]	auto[1]	88	1			T34	1		T143	1		T77	1
all_values[10]	auto[1]	auto[0]	auto[1]	117	1			T34	1		T143	4		T77	3
all_values[10]	auto[1]	auto[1]	auto[1]	99	1			T34	2		T143	1		T77	1
all_values[11]	auto[0]	auto[0]	auto[0]	45	1			T143	2		T50	2		T260	4
all_values[11]	auto[0]	auto[0]	auto[1]	109	1			T34	1		T77	3		T59	7
all_values[11]	auto[0]	auto[1]	auto[0]	46	1			T143	3		T260	5		T54	1
all_values[11]	auto[0]	auto[1]	auto[1]	99	1			T34	2		T143	3		T59	3
all_values[11]	auto[1]	auto[0]	auto[1]	100	1			T34	1		T143	1		T77	4
all_values[11]	auto[1]	auto[1]	auto[1]	93	1			T143	2		T50	2		T104	2
all_values[12]	auto[0]	auto[0]	auto[0]	40	1			T34	2		T77	1		T53	1
all_values[12]	auto[0]	auto[0]	auto[1]	96	1			T34	1		T143	5		T77	2
all_values[12]	auto[0]	auto[1]	auto[0]	26	1			T257	1		T262	1		T263	2
all_values[12]	auto[0]	auto[1]	auto[1]	110	1			T143	2		T77	1		T59	3
all_values[12]	auto[1]	auto[0]	auto[1]	117	1			T34	1		T143	2		T59	4
all_values[12]	auto[1]	auto[1]	auto[1]	103	1			T143	2		T77	3		T59	5
all_values[13]	auto[0]	auto[0]	auto[0]	41	1			T50	1		T260	1		T53	2
all_values[13]	auto[0]	auto[0]	auto[1]	89	1			T34	1		T143	3		T59	3
all_values[13]	auto[0]	auto[1]	auto[0]	35	1			T104	1		T54	1		T261	1
all_values[13]	auto[0]	auto[1]	auto[1]	115	1			T143	2		T77	2		T59	5
all_values[13]	auto[1]	auto[0]	auto[1]	109	1			T34	2		T143	4		T77	1
all_values[13]	auto[1]	auto[1]	auto[1]	103	1			T34	1		T143	2		T77	4
all_values[14]	auto[0]	auto[0]	auto[0]	43	1			T34	3		T59	2		T50	2
all_values[14]	auto[0]	auto[0]	auto[1]	91	1			T143	1		T59	5		T50	3
all_values[14]	auto[0]	auto[1]	auto[0]	23	1			T34	1		T59	2		T54	1
all_values[14]	auto[0]	auto[1]	auto[1]	131	1			T143	4		T77	5		T59	1
all_values[14]	auto[1]	auto[0]	auto[1]	100	1			T143	2		T77	2		T50	1
all_values[14]	auto[1]	auto[1]	auto[1]	104	1			T143	4		T59	5		T50	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal