Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	739986	1			T1	3		T2	3		T3	2
all_values[1]	739986	1			T1	3		T2	3		T3	2
all_values[2]	739986	1			T1	3		T2	3		T3	2
all_values[3]	739986	1			T1	3		T2	3		T3	2
all_values[4]	739986	1			T1	3		T2	3		T3	2
all_values[5]	739986	1			T1	3		T2	3		T3	2
all_values[6]	739986	1			T1	3		T2	3		T3	2
all_values[7]	739986	1			T1	3		T2	3		T3	2
all_values[8]	739986	1			T1	3		T2	3		T3	2
all_values[9]	739986	1			T1	3		T2	3		T3	2
all_values[10]	739986	1			T1	3		T2	3		T3	2
all_values[11]	739986	1			T1	3		T2	3		T3	2
all_values[12]	739986	1			T1	3		T2	3		T3	2
all_values[13]	739986	1			T1	3		T2	3		T3	2
all_values[14]	739986	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9124304

1

T1

39

T2

39

T3

30

auto[1]

1975486

1

T1

6

T2

6

T4

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10103665

1

T1

45

T2

45

T3

30

auto[1]

996125

1

T139

153748

T46

7413

T44

337

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	89602	1			T1	1		T2	1		T3	2
all_values[0]	auto[0]	auto[1]	4312	1			T139	336		T46	23		T44	12
all_values[0]	auto[1]	auto[0]	594986	1			T1	2		T2	2		T4	2
all_values[0]	auto[1]	auto[1]	51086	1			T139	9915		T46	472		T44	11
all_values[1]	auto[0]	auto[0]	670416	1			T1	3		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	69059	1			T139	10245		T46	492		T44	17
all_values[1]	auto[1]	auto[0]	262	1			T44	50		T109	2		T50	1
all_values[1]	auto[1]	auto[1]	249	1			T139	3		T46	3		T44	4
all_values[2]	auto[0]	auto[0]	670342	1			T1	3		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	69403	1			T139	10245		T46	489		T44	19
all_values[2]	auto[1]	auto[0]	50	1			T11	1		T140	1		T18	1
all_values[2]	auto[1]	auto[1]	191	1			T139	4		T46	3		T44	4
all_values[3]	auto[0]	auto[0]	666378	1			T1	3		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	73359	1			T139	10246		T46	490		T44	13
all_values[3]	auto[1]	auto[1]	249	1			T139	2		T46	5		T44	9
all_values[4]	auto[0]	auto[0]	681461	1			T1	3		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	58298	1			T139	10246		T46	492		T44	18
all_values[4]	auto[1]	auto[0]	24	1			T241	1		T51	2		T242	1
all_values[4]	auto[1]	auto[1]	203	1			T139	3		T46	2		T44	3
all_values[5]	auto[0]	auto[0]	665813	1			T1	3		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	73927	1			T139	10248		T46	493		T44	18
all_values[5]	auto[1]	auto[1]	246	1			T139	3		T46	2		T44	5
all_values[6]	auto[0]	auto[0]	671242	1			T1	3		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	68506	1			T139	10247		T46	489		T44	16
all_values[6]	auto[1]	auto[1]	238	1			T139	4		T46	4		T44	7
all_values[7]	auto[0]	auto[0]	644917	1			T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	70573	1			T139	10104		T46	424		T44	16
all_values[7]	auto[1]	auto[0]	20923	1			T1	1		T2	1		T4	1
all_values[7]	auto[1]	auto[1]	3573	1			T139	145		T46	71		T44	7
all_values[8]	auto[0]	auto[0]	683501	1			T1	3		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	56231	1			T139	10246		T46	490		T44	18
all_values[8]	auto[1]	auto[1]	254	1			T139	4		T46	5		T44	5
all_values[9]	auto[0]	auto[0]	162064	1			T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	12596	1			T139	341		T46	463		T44	12
all_values[9]	auto[1]	auto[0]	508655	1			T1	1		T2	1		T4	1
all_values[9]	auto[1]	auto[1]	56671	1			T139	9910		T46	29		T44	10
all_values[10]	auto[0]	auto[0]	685097	1			T1	3		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	54667	1			T139	10248		T46	490		T44	19
all_values[10]	auto[1]	auto[1]	222	1			T139	3		T46	5		T44	4
all_values[11]	auto[0]	auto[0]	2672	1			T1	1		T2	1		T3	2
all_values[11]	auto[0]	auto[1]	579	1			T139	17		T46	10		T44	11
all_values[11]	auto[1]	auto[0]	674564	1			T1	2		T2	2		T4	2
all_values[11]	auto[1]	auto[1]	62171	1			T139	10234		T46	484		T44	11
all_values[12]	auto[0]	auto[0]	666064	1			T1	3		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	73703	1			T139	10245		T46	491		T44	18
all_values[12]	auto[1]	auto[0]	10	1			T19	1		T243	1		T244	1
all_values[12]	auto[1]	auto[1]	209	1			T139	3		T46	3		T44	4
all_values[13]	auto[0]	auto[0]	670689	1			T1	3		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	69072	1			T139	10246		T46	493		T44	18
all_values[13]	auto[1]	auto[1]	225	1			T139	5		T46	1		T44	5
all_values[14]	auto[0]	auto[0]	673933	1			T1	3		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	65828	1			T139	10248		T46	495		T44	14
all_values[14]	auto[1]	auto[1]	225	1			T139	2		T44	9		T45	2