Group : i2c_env_pkg::i2c_scl_stretch_cg
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Group : i2c_env_pkg::i2c_scl_stretch_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
90.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_i2c_env_0.1/i2c_env_cov.sv



Summary for Group i2c_env_pkg::i2c_scl_stretch_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 4 1 3 75.00


Variables for Group i2c_env_pkg::i2c_scl_stretch_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_acq_fifo_size 2 0 2 100.00 100 1 1 0
cp_host_mode_stretch 1 0 1 100.00 100 1 1 0
cp_target_scl_stretch_addr_write 1 0 1 100.00 100 1 1 0
cp_tx_fifo_size 2 0 2 100.00 100 1 1 0


Crosses for Group i2c_env_pkg::i2c_scl_stretch_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_target_scl_stretch_read 4 1 3 75.00 100 1 1 0


Summary for Variable cp_acq_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_acq_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 117690580 1 T8 3745 T12 2154 T17 367
empty 86146931 1 T1 199188 T2 180433 T4 149539



Summary for Variable cp_host_mode_stretch

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_host_mode_stretch

Excluded/Illegal bins
NAMECOUNTSTATUS
unused 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stretch 53087747 1 T1 76752 T2 126261 T4 83289



Summary for Variable cp_target_scl_stretch_addr_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_target_scl_stretch_addr_write

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
addr_write_byte_stretch 466324 1 T20 6428 T22 2038 T23 4063



Summary for Variable cp_tx_fifo_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_tx_fifo_size

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_empty 40523507 1 T8 2764 T12 1347 T21 2690
empty 163314044 1 T1 199188 T2 180433 T4 149539



Summary for Cross cp_target_scl_stretch_read

Samples crossed: cp_acq_fifo_size cp_tx_fifo_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 1 3 75.00 1
Automatically Generated Cross Bins 2 1 1 50.00 1
User Defined Cross Bins 2 0 2 100.00


Automatically Generated Cross Bins for cp_target_scl_stretch_read

Uncovered bins
cp_acq_fifo_sizecp_tx_fifo_sizeCOUNTAT LEASTNUMBERSTATUS
[empty] [not_empty] 0 1 1


Covered bins
cp_acq_fifo_sizecp_tx_fifo_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
empty empty 383923 1 T8 154 T17 847 T14 816


User Defined Cross Bins for cp_target_scl_stretch_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
read_byte_stretch 196411 1 T8 446 T12 296 T17 367
scl_stretch_read_request 40719354 1 T8 3210 T12 1643 T17 367

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