Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	739986	1			T1	3		T2	3		T3	2
all_pins[1]	739986	1			T1	3		T2	3		T3	2
all_pins[2]	739986	1			T1	3		T2	3		T3	2
all_pins[3]	739986	1			T1	3		T2	3		T3	2
all_pins[4]	739986	1			T1	3		T2	3		T3	2
all_pins[5]	739986	1			T1	3		T2	3		T3	2
all_pins[6]	739986	1			T1	3		T2	3		T3	2
all_pins[7]	739986	1			T1	3		T2	3		T3	2
all_pins[8]	739986	1			T1	3		T2	3		T3	2
all_pins[9]	739986	1			T1	3		T2	3		T3	2
all_pins[10]	739986	1			T1	3		T2	3		T3	2
all_pins[11]	739986	1			T1	3		T2	3		T3	2
all_pins[12]	739986	1			T1	3		T2	3		T3	2
all_pins[13]	739986	1			T1	3		T2	3		T3	2
all_pins[14]	739986	1			T1	3		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9130079	1			T1	39		T2	39		T3	30
values[0x1]	1969711	1			T1	6		T2	6		T4	6
transitions[0x0=>0x1]	1968881	1			T1	6		T2	6		T4	6
transitions[0x1=>0x0]	1967735	1			T1	5		T2	5		T4	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	97145	1			T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	642841	1			T1	2		T2	2		T4	2
all_pins[0]	transitions[0x0=>0x1]	642445	1			T1	2		T2	2		T4	2
all_pins[0]	transitions[0x1=>0x0]	80	1			T139	1		T46	2		T44	1
all_pins[1]	values[0x0]	739510	1			T1	3		T2	3		T3	2
all_pins[1]	values[0x1]	476	1			T139	1		T46	2		T44	63
all_pins[1]	transitions[0x0=>0x1]	453	1			T139	1		T46	2		T44	62
all_pins[1]	transitions[0x1=>0x0]	117	1			T11	1		T140	1		T139	2
all_pins[2]	values[0x0]	739846	1			T1	3		T2	3		T3	2
all_pins[2]	values[0x1]	140	1			T11	1		T140	1		T139	2
all_pins[2]	transitions[0x0=>0x1]	116	1			T11	1		T140	1		T139	2
all_pins[2]	transitions[0x1=>0x0]	104	1			T46	2		T44	4		T271	2
all_pins[3]	values[0x0]	739858	1			T1	3		T2	3		T3	2
all_pins[3]	values[0x1]	128	1			T46	2		T44	6		T271	4
all_pins[3]	transitions[0x0=>0x1]	96	1			T46	2		T44	4		T271	4
all_pins[3]	transitions[0x1=>0x0]	115	1			T139	1		T46	1		T45	4
all_pins[4]	values[0x0]	739839	1			T1	3		T2	3		T3	2
all_pins[4]	values[0x1]	147	1			T139	1		T46	1		T44	2
all_pins[4]	transitions[0x0=>0x1]	115	1			T139	1		T46	1		T44	1
all_pins[4]	transitions[0x1=>0x0]	64	1			T46	2		T204	1		T240	1
all_pins[5]	values[0x0]	739890	1			T1	3		T2	3		T3	2
all_pins[5]	values[0x1]	96	1			T46	2		T44	1		T204	2
all_pins[5]	transitions[0x0=>0x1]	65	1			T46	1		T204	1		T240	1
all_pins[5]	transitions[0x1=>0x0]	81	1			T139	1		T46	2		T44	2
all_pins[6]	values[0x0]	739874	1			T1	3		T2	3		T3	2
all_pins[6]	values[0x1]	112	1			T139	1		T46	3		T44	3
all_pins[6]	transitions[0x0=>0x1]	84	1			T139	1		T46	3		T44	3
all_pins[6]	transitions[0x1=>0x0]	26729	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x0]	713229	1			T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	26757	1			T1	1		T2	1		T4	1
all_pins[7]	transitions[0x0=>0x1]	26713	1			T1	1		T2	1		T4	1
all_pins[7]	transitions[0x1=>0x0]	96	1			T139	1		T46	2		T44	1
all_pins[8]	values[0x0]	739846	1			T1	3		T2	3		T3	2
all_pins[8]	values[0x1]	140	1			T139	2		T46	3		T44	2
all_pins[8]	transitions[0x0=>0x1]	103	1			T139	2		T46	3		T44	2
all_pins[8]	transitions[0x1=>0x0]	565200	1			T1	1		T2	1		T4	1
all_pins[9]	values[0x0]	174749	1			T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	565237	1			T1	1		T2	1		T4	1
all_pins[9]	transitions[0x0=>0x1]	565210	1			T1	1		T2	1		T4	1
all_pins[9]	transitions[0x1=>0x0]	84	1			T139	1		T44	2		T45	1
all_pins[10]	values[0x0]	739875	1			T1	3		T2	3		T3	2
all_pins[10]	values[0x1]	111	1			T139	2		T46	2		T44	3
all_pins[10]	transitions[0x0=>0x1]	79	1			T139	2		T46	1		T44	2
all_pins[10]	transitions[0x1=>0x0]	733171	1			T1	2		T2	2		T4	2
all_pins[11]	values[0x0]	6783	1			T1	1		T2	1		T3	2
all_pins[11]	values[0x1]	733203	1			T1	2		T2	2		T4	2
all_pins[11]	transitions[0x0=>0x1]	733161	1			T1	2		T2	2		T4	2
all_pins[11]	transitions[0x1=>0x0]	73	1			T46	1		T44	2		T45	2
all_pins[12]	values[0x0]	739871	1			T1	3		T2	3		T3	2
all_pins[12]	values[0x1]	115	1			T139	1		T46	2		T44	2
all_pins[12]	transitions[0x0=>0x1]	88	1			T139	1		T46	2		T44	2
all_pins[12]	transitions[0x1=>0x0]	79	1			T139	3		T46	1		T44	3
all_pins[13]	values[0x0]	739880	1			T1	3		T2	3		T3	2
all_pins[13]	values[0x1]	106	1			T139	3		T46	1		T44	3
all_pins[13]	transitions[0x0=>0x1]	82	1			T139	2		T46	1		T44	2
all_pins[13]	transitions[0x1=>0x0]	78	1			T139	1		T44	3		T271	2
all_pins[14]	values[0x0]	739884	1			T1	3		T2	3		T3	2
all_pins[14]	values[0x1]	102	1			T139	2		T44	4		T271	3
all_pins[14]	transitions[0x0=>0x1]	71	1			T139	1		T44	3		T271	3
all_pins[14]	transitions[0x1=>0x0]	641664	1			T1	1		T2	1		T4	1