Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	517	1			T139	7		T46	7		T44	11
all_values[1]	517	1			T139	7		T46	7		T44	11
all_values[2]	517	1			T139	7		T46	7		T44	11
all_values[3]	517	1			T139	7		T46	7		T44	11
all_values[4]	517	1			T139	7		T46	7		T44	11
all_values[5]	517	1			T139	7		T46	7		T44	11
all_values[6]	517	1			T139	7		T46	7		T44	11
all_values[7]	517	1			T139	7		T46	7		T44	11
all_values[8]	517	1			T139	7		T46	7		T44	11
all_values[9]	517	1			T139	7		T46	7		T44	11
all_values[10]	517	1			T139	7		T46	7		T44	11
all_values[11]	517	1			T139	7		T46	7		T44	11
all_values[12]	517	1			T139	7		T46	7		T44	11
all_values[13]	517	1			T139	7		T46	7		T44	11
all_values[14]	517	1			T139	7		T46	7		T44	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4030

1

T139

51

T46

41

T44

101

auto[1]

3725

1

T139

54

T46

64

T44

64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1206

1

T139

17

T46

12

T44

8

auto[1]

6549

1

T139

88

T46

93

T44

157

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4647

1

T139

57

T46

57

T44

100

auto[1]

3108

1

T139

48

T46

48

T44

65

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	55	1			T271	1		T204	1		T268	1
all_values[0]	auto[0]	auto[0]	auto[1]	118	1			T139	2		T46	2		T44	6
all_values[0]	auto[0]	auto[1]	auto[0]	45	1			T45	1		T204	2		T240	2
all_values[0]	auto[0]	auto[1]	auto[1]	104	1			T139	2		T46	1		T44	1
all_values[0]	auto[1]	auto[0]	auto[1]	100	1			T139	1		T46	2		T44	3
all_values[0]	auto[1]	auto[1]	auto[1]	95	1			T139	2		T46	2		T44	1
all_values[1]	auto[0]	auto[0]	auto[0]	37	1			T139	1		T44	2		T268	1
all_values[1]	auto[0]	auto[0]	auto[1]	116	1			T139	1		T46	2		T44	2
all_values[1]	auto[0]	auto[1]	auto[0]	28	1			T139	2		T204	1		T70	2
all_values[1]	auto[0]	auto[1]	auto[1]	128	1			T46	2		T44	3		T45	4
all_values[1]	auto[1]	auto[0]	auto[1]	106	1			T139	2		T46	1		T44	2
all_values[1]	auto[1]	auto[1]	auto[1]	102	1			T139	1		T46	2		T44	2
all_values[2]	auto[0]	auto[0]	auto[0]	45	1			T139	2		T46	1		T271	1
all_values[2]	auto[0]	auto[0]	auto[1]	124	1			T46	1		T44	4		T45	2
all_values[2]	auto[0]	auto[1]	auto[0]	31	1			T46	2		T54	2		T69	1
all_values[2]	auto[0]	auto[1]	auto[1]	126	1			T139	1		T44	3		T45	2
all_values[2]	auto[1]	auto[0]	auto[1]	106	1			T139	2		T46	1		T44	2
all_values[2]	auto[1]	auto[1]	auto[1]	85	1			T139	2		T46	2		T44	2
all_values[3]	auto[0]	auto[0]	auto[0]	52	1			T139	3		T44	1		T50	1
all_values[3]	auto[0]	auto[0]	auto[1]	104	1			T139	1		T46	2		T44	2
all_values[3]	auto[0]	auto[1]	auto[0]	26	1			T45	2		T50	1		T70	1
all_values[3]	auto[0]	auto[1]	auto[1]	125	1			T139	1		T46	1		T44	3
all_values[3]	auto[1]	auto[0]	auto[1]	100	1			T139	1		T46	2		T44	2
all_values[3]	auto[1]	auto[1]	auto[1]	110	1			T139	1		T46	2		T44	3
all_values[4]	auto[0]	auto[0]	auto[0]	52	1			T139	2		T44	2		T271	4
all_values[4]	auto[0]	auto[0]	auto[1]	108	1			T139	2		T46	2		T44	4
all_values[4]	auto[0]	auto[1]	auto[0]	39	1			T46	1		T45	1		T271	7
all_values[4]	auto[0]	auto[1]	auto[1]	115	1			T46	2		T44	2		T45	2
all_values[4]	auto[1]	auto[0]	auto[1]	96	1			T139	1		T46	1		T44	1
all_values[4]	auto[1]	auto[1]	auto[1]	107	1			T139	2		T46	1		T44	2
all_values[5]	auto[0]	auto[0]	auto[0]	27	1			T271	2		T240	1		T272	3
all_values[5]	auto[0]	auto[0]	auto[1]	144	1			T139	1		T46	1		T44	2
all_values[5]	auto[0]	auto[1]	auto[0]	20	1			T45	1		T271	2		T50	1
all_values[5]	auto[0]	auto[1]	auto[1]	99	1			T139	2		T46	2		T44	3
all_values[5]	auto[1]	auto[0]	auto[1]	128	1			T139	4		T46	1		T44	5
all_values[5]	auto[1]	auto[1]	auto[1]	99	1			T46	3		T44	1		T45	1
all_values[6]	auto[0]	auto[0]	auto[0]	47	1			T204	2		T272	4		T273	4
all_values[6]	auto[0]	auto[0]	auto[1]	126	1			T139	3		T44	4		T45	3
all_values[6]	auto[0]	auto[1]	auto[0]	39	1			T46	2		T50	1		T240	1
all_values[6]	auto[0]	auto[1]	auto[1]	102	1			T139	1		T46	2		T44	1
all_values[6]	auto[1]	auto[0]	auto[1]	103	1			T139	2		T46	1		T44	3
all_values[6]	auto[1]	auto[1]	auto[1]	100	1			T139	1		T46	2		T44	3
all_values[7]	auto[0]	auto[0]	auto[0]	40	1			T204	2		T240	2		T54	1
all_values[7]	auto[0]	auto[0]	auto[1]	106	1			T139	1		T46	1		T44	4
all_values[7]	auto[0]	auto[1]	auto[0]	40	1			T139	2		T50	1		T204	1
all_values[7]	auto[0]	auto[1]	auto[1]	127	1			T139	1		T46	2		T44	5
all_values[7]	auto[1]	auto[0]	auto[1]	98	1			T46	1		T44	2		T45	4
all_values[7]	auto[1]	auto[1]	auto[1]	106	1			T139	3		T46	3		T45	1
all_values[8]	auto[0]	auto[0]	auto[0]	43	1			T240	3		T268	1		T274	3
all_values[8]	auto[0]	auto[0]	auto[1]	116	1			T139	1		T46	1		T44	3
all_values[8]	auto[0]	auto[1]	auto[0]	26	1			T139	1		T275	1		T274	1
all_values[8]	auto[0]	auto[1]	auto[1]	124	1			T139	2		T46	2		T44	4
all_values[8]	auto[1]	auto[0]	auto[1]	104	1			T46	2		T44	3		T50	1
all_values[8]	auto[1]	auto[1]	auto[1]	104	1			T139	3		T46	2		T44	1
all_values[9]	auto[0]	auto[0]	auto[0]	49	1			T44	1		T271	8		T204	1
all_values[9]	auto[0]	auto[0]	auto[1]	120	1			T139	2		T46	1		T44	4
all_values[9]	auto[0]	auto[1]	auto[0]	30	1			T46	3		T271	1		T50	1
all_values[9]	auto[0]	auto[1]	auto[1]	111	1			T139	2		T46	1		T44	1
all_values[9]	auto[1]	auto[0]	auto[1]	100	1			T139	1		T44	2		T204	3
all_values[9]	auto[1]	auto[1]	auto[1]	107	1			T139	2		T46	2		T44	3
all_values[10]	auto[0]	auto[0]	auto[0]	64	1			T69	6		T268	2		T112	1
all_values[10]	auto[0]	auto[0]	auto[1]	102	1			T139	1		T46	2		T44	4
all_values[10]	auto[0]	auto[1]	auto[0]	27	1			T240	2		T69	1		T268	2
all_values[10]	auto[0]	auto[1]	auto[1]	102	1			T139	3		T44	3		T45	1
all_values[10]	auto[1]	auto[0]	auto[1]	114	1			T139	1		T46	1		T44	3
all_values[10]	auto[1]	auto[1]	auto[1]	108	1			T139	2		T46	4		T44	1
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T44	1		T240	2		T272	1
all_values[11]	auto[0]	auto[0]	auto[1]	127	1			T139	2		T46	2		T44	3
all_values[11]	auto[0]	auto[1]	auto[0]	37	1			T46	1		T240	5		T54	1
all_values[11]	auto[0]	auto[1]	auto[1]	107	1			T139	1		T46	2		T44	3
all_values[11]	auto[1]	auto[0]	auto[1]	110	1			T139	3		T44	1		T45	3
all_values[11]	auto[1]	auto[1]	auto[1]	95	1			T139	1		T46	2		T44	3
all_values[12]	auto[0]	auto[0]	auto[0]	55	1			T44	1		T271	1		T240	1
all_values[12]	auto[0]	auto[0]	auto[1]	109	1			T139	1		T46	2		T44	4
all_values[12]	auto[0]	auto[1]	auto[0]	36	1			T139	3		T46	1		T54	1
all_values[12]	auto[0]	auto[1]	auto[1]	108	1			T46	1		T44	2		T45	4
all_values[12]	auto[1]	auto[0]	auto[1]	104	1			T139	1		T46	2		T44	3
all_values[12]	auto[1]	auto[1]	auto[1]	105	1			T139	2		T46	1		T44	1
all_values[13]	auto[0]	auto[0]	auto[0]	44	1			T268	1		T272	3		T275	2
all_values[13]	auto[0]	auto[0]	auto[1]	118	1			T139	1		T46	1		T44	6
all_values[13]	auto[0]	auto[1]	auto[0]	34	1			T46	1		T50	2		T240	5
all_values[13]	auto[0]	auto[1]	auto[1]	108	1			T139	1		T46	2		T44	2
all_values[13]	auto[1]	auto[0]	auto[1]	102	1			T139	1		T46	2		T44	2
all_values[13]	auto[1]	auto[1]	auto[1]	111	1			T139	4		T46	1		T44	1
all_values[14]	auto[0]	auto[0]	auto[0]	59	1			T139	1		T271	1		T204	2
all_values[14]	auto[0]	auto[0]	auto[1]	104	1			T139	2		T46	2		T44	2
all_values[14]	auto[0]	auto[1]	auto[0]	38	1			T204	2		T69	2		T70	1
all_values[14]	auto[0]	auto[1]	auto[1]	113	1			T139	2		T46	3		T44	2
all_values[14]	auto[1]	auto[0]	auto[1]	107	1			T139	1		T46	1		T44	5
all_values[14]	auto[1]	auto[1]	auto[1]	96	1			T139	1		T46	1		T44	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal