Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	906365	1			T1	3		T2	10		T3	227
all_values[1]	906365	1			T1	3		T2	10		T3	227
all_values[2]	906365	1			T1	3		T2	10		T3	227
all_values[3]	906365	1			T1	3		T2	10		T3	227
all_values[4]	906365	1			T1	3		T2	10		T3	227
all_values[5]	906365	1			T1	3		T2	10		T3	227
all_values[6]	906365	1			T1	3		T2	10		T3	227
all_values[7]	906365	1			T1	3		T2	10		T3	227
all_values[8]	906365	1			T1	3		T2	10		T3	227
all_values[9]	906365	1			T1	3		T2	10		T3	227
all_values[10]	906365	1			T1	3		T2	10		T3	227
all_values[11]	906365	1			T1	3		T2	10		T3	227
all_values[12]	906365	1			T1	3		T2	10		T3	227
all_values[13]	906365	1			T1	3		T2	10		T3	227
all_values[14]	906365	1			T1	3		T2	10		T3	227

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11128996

1

T1

38

T2

150

T3

2903

auto[1]

2466479

1

T1

7

T3

502

T4

52429

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11375228

1

T1

45

T2

150

T3

3405

auto[1]

2220247

1

T33

511

T41

68310

T132

6789

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	87375	1			T2	10		T3	3		T4	1153
all_values[0]	auto[0]	auto[1]	8540	1			T33	18		T41	170		T99	211
all_values[0]	auto[1]	auto[0]	689167	1			T1	3		T3	224		T4	16972
all_values[0]	auto[1]	auto[1]	121283	1			T33	17		T41	4383		T132	453
all_values[1]	auto[0]	auto[0]	769276	1			T1	3		T2	10		T3	227
all_values[1]	auto[0]	auto[1]	136680	1			T33	28		T41	4552		T132	447
all_values[1]	auto[1]	auto[0]	185	1			T80	3		T214	13		T32	24
all_values[1]	auto[1]	auto[1]	224	1			T33	6		T41	2		T132	6
all_values[2]	auto[0]	auto[0]	769423	1			T1	3		T2	10		T3	227
all_values[2]	auto[0]	auto[1]	136681	1			T33	29		T41	4551		T132	450
all_values[2]	auto[1]	auto[0]	50	1			T18	1		T128	1		T215	1
all_values[2]	auto[1]	auto[1]	211	1			T33	5		T41	4		T132	3
all_values[3]	auto[0]	auto[0]	758320	1			T1	3		T2	10		T3	227
all_values[3]	auto[0]	auto[1]	147791	1			T33	26		T41	4551		T132	451
all_values[3]	auto[1]	auto[1]	254	1			T33	6		T41	4		T132	1
all_values[4]	auto[0]	auto[0]	749027	1			T1	3		T2	10		T3	227
all_values[4]	auto[0]	auto[1]	157102	1			T33	29		T41	4551		T132	450
all_values[4]	auto[1]	auto[0]	21	1			T216	2		T217	1		T218	1
all_values[4]	auto[1]	auto[1]	215	1			T33	4		T41	4		T132	2
all_values[5]	auto[0]	auto[0]	748513	1			T1	3		T2	10		T3	227
all_values[5]	auto[0]	auto[1]	157587	1			T33	30		T41	4550		T132	449
all_values[5]	auto[1]	auto[1]	265	1			T33	4		T41	5		T132	4
all_values[6]	auto[0]	auto[0]	754800	1			T1	3		T2	10		T3	227
all_values[6]	auto[0]	auto[1]	151315	1			T33	25		T41	4554		T132	451
all_values[6]	auto[1]	auto[1]	250	1			T33	10		T132	2		T77	4
all_values[7]	auto[0]	auto[0]	739553	1			T1	3		T2	10		T3	187
all_values[7]	auto[0]	auto[1]	132923	1			T33	23		T41	4392		T132	393
all_values[7]	auto[1]	auto[0]	30089	1			T3	40		T4	189		T7	1
all_values[7]	auto[1]	auto[1]	3800	1			T33	10		T41	160		T132	60
all_values[8]	auto[0]	auto[0]	787445	1			T1	3		T2	10		T3	227
all_values[8]	auto[0]	auto[1]	118702	1			T33	27		T41	4552		T132	446
all_values[8]	auto[1]	auto[1]	218	1			T33	7		T41	3		T132	6
all_values[9]	auto[0]	auto[0]	168584	1			T1	2		T2	10		T3	213
all_values[9]	auto[0]	auto[1]	21645	1			T33	28		T41	549		T132	430
all_values[9]	auto[1]	auto[0]	579957	1			T1	1		T3	14		T4	17152
all_values[9]	auto[1]	auto[1]	136179	1			T33	6		T41	4004		T132	21
all_values[10]	auto[0]	auto[0]	748558	1			T1	3		T2	10		T3	227
all_values[10]	auto[0]	auto[1]	157595	1			T33	31		T41	4549		T132	448
all_values[10]	auto[1]	auto[1]	212	1			T33	4		T41	1		T132	5
all_values[11]	auto[0]	auto[0]	2670	1			T2	10		T3	3		T4	9
all_values[11]	auto[0]	auto[1]	507	1			T33	20		T41	17		T99	6
all_values[11]	auto[1]	auto[0]	746063	1			T1	3		T3	224		T4	18116
all_values[11]	auto[1]	auto[1]	157125	1			T33	15		T41	4538		T132	453
all_values[12]	auto[0]	auto[0]	748518	1			T1	3		T2	10		T3	227
all_values[12]	auto[0]	auto[1]	157626	1			T33	29		T41	4549		T132	448
all_values[12]	auto[1]	auto[0]	11	1			T215	1		T219	1		T186	1
all_values[12]	auto[1]	auto[1]	210	1			T33	4		T41	5		T132	5
all_values[13]	auto[0]	auto[0]	748887	1			T1	3		T2	10		T3	227
all_values[13]	auto[0]	auto[1]	157238	1			T33	30		T41	4552		T132	448
all_values[13]	auto[1]	auto[1]	240	1			T33	5		T41	3		T132	4
all_values[14]	auto[0]	auto[0]	748736	1			T1	3		T2	10		T3	227
all_values[14]	auto[0]	auto[1]	157379	1			T33	29		T41	4552		T132	447
all_values[14]	auto[1]	auto[1]	250	1			T33	6		T41	3		T132	6