Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	906365	1			T1	3		T2	10		T3	227
all_pins[1]	906365	1			T1	3		T2	10		T3	227
all_pins[2]	906365	1			T1	3		T2	10		T3	227
all_pins[3]	906365	1			T1	3		T2	10		T3	227
all_pins[4]	906365	1			T1	3		T2	10		T3	227
all_pins[5]	906365	1			T1	3		T2	10		T3	227
all_pins[6]	906365	1			T1	3		T2	10		T3	227
all_pins[7]	906365	1			T1	3		T2	10		T3	227
all_pins[8]	906365	1			T1	3		T2	10		T3	227
all_pins[9]	906365	1			T1	3		T2	10		T3	227
all_pins[10]	906365	1			T1	3		T2	10		T3	227
all_pins[11]	906365	1			T1	3		T2	10		T3	227
all_pins[12]	906365	1			T1	3		T2	10		T3	227
all_pins[13]	906365	1			T1	3		T2	10		T3	227
all_pins[14]	906365	1			T1	3		T2	10		T3	227

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11134677	1			T1	38		T2	150		T3	2901
values[0x1]	2460798	1			T1	7		T3	504		T4	52470
transitions[0x0=>0x1]	2460097	1			T1	7		T3	504		T4	52470
transitions[0x1=>0x0]	2458942	1			T1	6		T3	503		T4	52469

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99356	1			T2	10		T3	3		T4	1154
all_pins[0]	values[0x1]	807009	1			T1	3		T3	224		T4	16971
all_pins[0]	transitions[0x0=>0x1]	806749	1			T1	3		T3	224		T4	16971
all_pins[0]	transitions[0x1=>0x0]	91	1			T33	1		T41	1		T132	1
all_pins[1]	values[0x0]	906014	1			T1	3		T2	10		T3	227
all_pins[1]	values[0x1]	351	1			T33	2		T80	3		T214	17
all_pins[1]	transitions[0x0=>0x1]	314	1			T33	1		T80	3		T214	17
all_pins[1]	transitions[0x1=>0x0]	124	1			T33	2		T18	1		T128	1
all_pins[2]	values[0x0]	906204	1			T1	3		T2	10		T3	227
all_pins[2]	values[0x1]	161	1			T33	3		T18	1		T128	1
all_pins[2]	transitions[0x0=>0x1]	142	1			T33	3		T18	1		T128	1
all_pins[2]	transitions[0x1=>0x0]	103	1			T33	2		T41	3		T99	1
all_pins[3]	values[0x0]	906243	1			T1	3		T2	10		T3	227
all_pins[3]	values[0x1]	122	1			T33	2		T41	3		T99	2
all_pins[3]	transitions[0x0=>0x1]	101	1			T33	2		T41	1		T99	1
all_pins[3]	transitions[0x1=>0x0]	112	1			T33	1		T41	1		T132	1
all_pins[4]	values[0x0]	906232	1			T1	3		T2	10		T3	227
all_pins[4]	values[0x1]	133	1			T33	1		T41	3		T132	1
all_pins[4]	transitions[0x0=>0x1]	108	1			T41	2		T99	2		T77	1
all_pins[4]	transitions[0x1=>0x0]	106	1			T33	1		T41	3		T132	2
all_pins[5]	values[0x0]	906234	1			T1	3		T2	10		T3	227
all_pins[5]	values[0x1]	131	1			T33	2		T41	4		T132	3
all_pins[5]	transitions[0x0=>0x1]	101	1			T33	2		T41	4		T132	3
all_pins[5]	transitions[0x1=>0x0]	96	1			T33	1		T132	2		T77	2
all_pins[6]	values[0x0]	906239	1			T1	3		T2	10		T3	227
all_pins[6]	values[0x1]	126	1			T33	1		T132	2		T77	2
all_pins[6]	transitions[0x0=>0x1]	85	1			T33	1		T258	1		T251	1
all_pins[6]	transitions[0x1=>0x0]	36823	1			T3	42		T4	231		T7	1
all_pins[7]	values[0x0]	869501	1			T1	3		T2	10		T3	185
all_pins[7]	values[0x1]	36864	1			T3	42		T4	231		T7	1
all_pins[7]	transitions[0x0=>0x1]	36823	1			T3	42		T4	231		T7	1
all_pins[7]	transitions[0x1=>0x0]	82	1			T33	6		T41	1		T132	3
all_pins[8]	values[0x0]	906242	1			T1	3		T2	10		T3	227
all_pins[8]	values[0x1]	123	1			T33	6		T41	1		T132	6
all_pins[8]	transitions[0x0=>0x1]	100	1			T33	5		T41	1		T132	5
all_pins[8]	transitions[0x1=>0x0]	716017	1			T1	1		T3	14		T4	17152
all_pins[9]	values[0x0]	190325	1			T1	2		T2	10		T3	213
all_pins[9]	values[0x1]	716040	1			T1	1		T3	14		T4	17152
all_pins[9]	transitions[0x0=>0x1]	716024	1			T1	1		T3	14		T4	17152
all_pins[9]	transitions[0x1=>0x0]	88	1			T33	2		T132	2		T77	3
all_pins[10]	values[0x0]	906261	1			T1	3		T2	10		T3	227
all_pins[10]	values[0x1]	104	1			T33	3		T132	2		T99	1
all_pins[10]	transitions[0x0=>0x1]	72	1			T33	3		T99	1		T77	2
all_pins[10]	transitions[0x1=>0x0]	899243	1			T1	3		T3	224		T4	18116
all_pins[11]	values[0x0]	7090	1			T2	10		T3	3		T4	9
all_pins[11]	values[0x1]	899275	1			T1	3		T3	224		T4	18116
all_pins[11]	transitions[0x0=>0x1]	899227	1			T1	3		T3	224		T4	18116
all_pins[11]	transitions[0x1=>0x0]	71	1			T41	2		T77	2		T259	1
all_pins[12]	values[0x0]	906246	1			T1	3		T2	10		T3	227
all_pins[12]	values[0x1]	119	1			T18	1		T215	1		T41	2
all_pins[12]	transitions[0x0=>0x1]	96	1			T18	1		T215	1		T41	1
all_pins[12]	transitions[0x1=>0x0]	90	1			T33	3		T41	1		T99	1
all_pins[13]	values[0x0]	906252	1			T1	3		T2	10		T3	227
all_pins[13]	values[0x1]	113	1			T33	3		T41	2		T132	2
all_pins[13]	transitions[0x0=>0x1]	78	1			T33	2		T41	2		T132	2
all_pins[13]	transitions[0x1=>0x0]	92	1			T33	1		T132	3		T77	4
all_pins[14]	values[0x0]	906238	1			T1	3		T2	10		T3	227
all_pins[14]	values[0x1]	127	1			T33	2		T132	3		T99	2
all_pins[14]	transitions[0x0=>0x1]	77	1			T33	1		T132	1		T99	1
all_pins[14]	transitions[0x1=>0x0]	805804	1			T1	2		T3	223		T4	16970