Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	512	1			T33	11		T41	7		T132	7
all_values[1]	512	1			T33	11		T41	7		T132	7
all_values[2]	512	1			T33	11		T41	7		T132	7
all_values[3]	512	1			T33	11		T41	7		T132	7
all_values[4]	512	1			T33	11		T41	7		T132	7
all_values[5]	512	1			T33	11		T41	7		T132	7
all_values[6]	512	1			T33	11		T41	7		T132	7
all_values[7]	512	1			T33	11		T41	7		T132	7
all_values[8]	512	1			T33	11		T41	7		T132	7
all_values[9]	512	1			T33	11		T41	7		T132	7
all_values[10]	512	1			T33	11		T41	7		T132	7
all_values[11]	512	1			T33	11		T41	7		T132	7
all_values[12]	512	1			T33	11		T41	7		T132	7
all_values[13]	512	1			T33	11		T41	7		T132	7
all_values[14]	512	1			T33	11		T41	7		T132	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3940

1

T33

85

T41

56

T132

28

auto[1]

3740

1

T33

80

T41

49

T132

77

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T33

14

T41

15

T132

6

auto[1]

6502

1

T33

151

T41

90

T132

99

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4553

1

T33

89

T41

60

T132

52

auto[1]

3127

1

T33

76

T41

45

T132

53

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	53	1			T41	2		T77	2		T259	4
all_values[0]	auto[0]	auto[0]	auto[1]	102	1			T33	1		T41	2		T77	2
all_values[0]	auto[0]	auto[1]	auto[0]	41	1			T77	3		T259	2		T258	1
all_values[0]	auto[0]	auto[1]	auto[1]	120	1			T33	4		T41	2		T132	4
all_values[0]	auto[1]	auto[0]	auto[1]	106	1			T33	1		T41	1		T99	2
all_values[0]	auto[1]	auto[1]	auto[1]	90	1			T33	5		T132	3		T99	1
all_values[1]	auto[0]	auto[0]	auto[0]	36	1			T33	1		T259	1		T74	2
all_values[1]	auto[0]	auto[0]	auto[1]	104	1			T41	1		T99	1		T77	3
all_values[1]	auto[0]	auto[1]	auto[0]	32	1			T41	1		T258	1		T257	1
all_values[1]	auto[0]	auto[1]	auto[1]	119	1			T33	4		T41	3		T132	1
all_values[1]	auto[1]	auto[0]	auto[1]	109	1			T33	2		T41	1		T132	4
all_values[1]	auto[1]	auto[1]	auto[1]	112	1			T33	4		T41	1		T132	2
all_values[2]	auto[0]	auto[0]	auto[0]	43	1			T33	1		T110	6		T102	2
all_values[2]	auto[0]	auto[0]	auto[1]	103	1			T33	3		T41	2		T132	2
all_values[2]	auto[0]	auto[1]	auto[0]	39	1			T77	1		T259	1		T110	2
all_values[2]	auto[0]	auto[1]	auto[1]	116	1			T33	2		T41	1		T132	2
all_values[2]	auto[1]	auto[0]	auto[1]	113	1			T33	1		T41	3		T99	1
all_values[2]	auto[1]	auto[1]	auto[1]	98	1			T33	4		T41	1		T132	3
all_values[3]	auto[0]	auto[0]	auto[0]	46	1			T33	2		T77	1		T259	4
all_values[3]	auto[0]	auto[0]	auto[1]	98	1			T33	2		T41	3		T132	1
all_values[3]	auto[0]	auto[1]	auto[0]	36	1			T33	1		T132	1		T77	1
all_values[3]	auto[0]	auto[1]	auto[1]	125	1			T33	2		T41	1		T132	3
all_values[3]	auto[1]	auto[0]	auto[1]	116	1			T33	3		T41	2		T132	1
all_values[3]	auto[1]	auto[1]	auto[1]	91	1			T33	1		T41	1		T132	1
all_values[4]	auto[0]	auto[0]	auto[0]	45	1			T33	1		T77	1		T110	2
all_values[4]	auto[0]	auto[0]	auto[1]	111	1			T33	2		T132	4		T77	5
all_values[4]	auto[0]	auto[1]	auto[0]	31	1			T33	1		T132	1		T259	1
all_values[4]	auto[0]	auto[1]	auto[1]	110	1			T33	3		T41	3		T99	2
all_values[4]	auto[1]	auto[0]	auto[1]	112	1			T33	2		T41	1		T99	2
all_values[4]	auto[1]	auto[1]	auto[1]	103	1			T33	2		T41	3		T132	2
all_values[5]	auto[0]	auto[0]	auto[0]	40	1			T110	2		T258	1		T45	1
all_values[5]	auto[0]	auto[0]	auto[1]	106	1			T33	3		T99	1		T77	4
all_values[5]	auto[0]	auto[1]	auto[0]	20	1			T33	1		T251	1		T112	1
all_values[5]	auto[0]	auto[1]	auto[1]	116	1			T33	1		T41	3		T132	2
all_values[5]	auto[1]	auto[0]	auto[1]	125	1			T33	4		T41	2		T99	1
all_values[5]	auto[1]	auto[1]	auto[1]	105	1			T33	2		T41	2		T132	5
all_values[6]	auto[0]	auto[0]	auto[0]	34	1			T41	1		T99	1		T77	1
all_values[6]	auto[0]	auto[0]	auto[1]	108	1			T33	2		T41	1		T77	3
all_values[6]	auto[0]	auto[1]	auto[0]	35	1			T99	3		T77	1		T102	1
all_values[6]	auto[0]	auto[1]	auto[1]	121	1			T33	1		T41	2		T132	4
all_values[6]	auto[1]	auto[0]	auto[1]	121	1			T33	7		T41	1		T77	3
all_values[6]	auto[1]	auto[1]	auto[1]	93	1			T33	1		T41	2		T132	3
all_values[7]	auto[0]	auto[0]	auto[0]	45	1			T41	2		T99	2		T45	2
all_values[7]	auto[0]	auto[0]	auto[1]	97	1			T33	4		T41	2		T132	1
all_values[7]	auto[0]	auto[1]	auto[0]	49	1			T33	2		T41	1		T77	1
all_values[7]	auto[0]	auto[1]	auto[1]	118	1			T33	2		T41	1		T132	2
all_values[7]	auto[1]	auto[0]	auto[1]	115	1			T33	2		T41	1		T132	1
all_values[7]	auto[1]	auto[1]	auto[1]	88	1			T33	1		T132	3		T77	2
all_values[8]	auto[0]	auto[0]	auto[0]	56	1			T99	1		T77	4		T251	2
all_values[8]	auto[0]	auto[0]	auto[1]	103	1			T259	4		T110	3		T102	1
all_values[8]	auto[0]	auto[1]	auto[0]	33	1			T33	1		T132	1		T77	1
all_values[8]	auto[0]	auto[1]	auto[1]	133	1			T33	4		T41	1		T132	4
all_values[8]	auto[1]	auto[0]	auto[1]	98	1			T33	2		T41	2		T99	1
all_values[8]	auto[1]	auto[1]	auto[1]	89	1			T33	4		T41	4		T132	2
all_values[9]	auto[0]	auto[0]	auto[0]	44	1			T110	1		T260	1		T255	4
all_values[9]	auto[0]	auto[0]	auto[1]	123	1			T41	1		T99	1		T77	3
all_values[9]	auto[0]	auto[1]	auto[0]	37	1			T33	1		T41	2		T132	2
all_values[9]	auto[0]	auto[1]	auto[1]	110	1			T33	5		T41	1		T132	3
all_values[9]	auto[1]	auto[0]	auto[1]	111	1			T33	1		T41	3		T99	1
all_values[9]	auto[1]	auto[1]	auto[1]	87	1			T33	4		T132	2		T99	1
all_values[10]	auto[0]	auto[0]	auto[0]	55	1			T41	2		T99	1		T110	2
all_values[10]	auto[0]	auto[0]	auto[1]	107	1			T33	5		T41	1		T132	2
all_values[10]	auto[0]	auto[1]	auto[0]	35	1			T41	3		T102	1		T45	2
all_values[10]	auto[0]	auto[1]	auto[1]	103	1			T33	2		T77	1		T259	1
all_values[10]	auto[1]	auto[0]	auto[1]	115	1			T33	2		T41	1		T132	2
all_values[10]	auto[1]	auto[1]	auto[1]	97	1			T33	2		T132	3		T99	2
all_values[11]	auto[0]	auto[0]	auto[0]	50	1			T259	3		T110	2		T258	2
all_values[11]	auto[0]	auto[0]	auto[1]	117	1			T33	6		T41	3		T77	6
all_values[11]	auto[0]	auto[1]	auto[0]	22	1			T259	3		T261	1		T111	4
all_values[11]	auto[0]	auto[1]	auto[1]	113	1			T33	1		T132	2		T99	1
all_values[11]	auto[1]	auto[0]	auto[1]	99	1			T33	3		T41	3		T99	3
all_values[11]	auto[1]	auto[1]	auto[1]	111	1			T33	1		T41	1		T132	5
all_values[12]	auto[0]	auto[0]	auto[0]	44	1			T33	2		T41	1		T110	1
all_values[12]	auto[0]	auto[0]	auto[1]	87	1			T33	5		T132	1		T77	1
all_values[12]	auto[0]	auto[1]	auto[0]	30	1			T251	2		T45	2		T74	2
all_values[12]	auto[0]	auto[1]	auto[1]	141	1			T41	1		T132	1		T99	1
all_values[12]	auto[1]	auto[0]	auto[1]	109	1			T33	3		T41	3		T132	3
all_values[12]	auto[1]	auto[1]	auto[1]	101	1			T33	1		T41	2		T132	2
all_values[13]	auto[0]	auto[0]	auto[0]	39	1			T259	1		T102	1		T258	1
all_values[13]	auto[0]	auto[0]	auto[1]	122	1			T33	2		T41	2		T132	4
all_values[13]	auto[0]	auto[1]	auto[0]	35	1			T132	1		T259	1		T251	3
all_values[13]	auto[0]	auto[1]	auto[1]	114	1			T33	3		T41	3		T99	1
all_values[13]	auto[1]	auto[0]	auto[1]	112	1			T33	3		T99	1		T77	3
all_values[13]	auto[1]	auto[1]	auto[1]	90	1			T33	3		T41	2		T132	2
all_values[14]	auto[0]	auto[0]	auto[0]	41	1			T99	2		T102	1		T111	3
all_values[14]	auto[0]	auto[0]	auto[1]	113	1			T33	4		T41	4		T132	1
all_values[14]	auto[0]	auto[1]	auto[0]	32	1			T102	1		T258	1		T111	1
all_values[14]	auto[0]	auto[1]	auto[1]	115	1			T33	2		T41	1		T132	2
all_values[14]	auto[1]	auto[0]	auto[1]	107	1			T33	3		T41	2		T132	1
all_values[14]	auto[1]	auto[1]	auto[1]	104	1			T33	2		T132	3		T77	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal