Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	929173	1			T1	12		T2	1		T3	3
all_values[1]	929173	1			T1	12		T2	1		T3	3
all_values[2]	929173	1			T1	12		T2	1		T3	3
all_values[3]	929173	1			T1	12		T2	1		T3	3
all_values[4]	929173	1			T1	12		T2	1		T3	3
all_values[5]	929173	1			T1	12		T2	1		T3	3
all_values[6]	929173	1			T1	12		T2	1		T3	3
all_values[7]	929173	1			T1	12		T2	1		T3	3
all_values[8]	929173	1			T1	12		T2	1		T3	3
all_values[9]	929173	1			T1	12		T2	1		T3	3
all_values[10]	929173	1			T1	12		T2	1		T3	3
all_values[11]	929173	1			T1	12		T2	1		T3	3
all_values[12]	929173	1			T1	12		T2	1		T3	3
all_values[13]	929173	1			T1	12		T2	1		T3	3
all_values[14]	929173	1			T1	12		T2	1		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11431428

1

T1

180

T2

15

T3

39

auto[1]

2506167

1

T3

6

T4

4

T5

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11702092

1

T1

180

T2

15

T3

45

auto[1]

2235503

1

T48

126

T136

58475

T97

62008

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	86541	1			T1	12		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	17704	1			T136	112		T97	746		T110	72
all_values[0]	auto[1]	auto[0]	688038	1			T3	2		T4	2		T5	2
all_values[0]	auto[1]	auto[1]	136890	1			T136	3787		T97	4421		T110	874
all_values[1]	auto[0]	auto[0]	770227	1			T1	12		T2	1		T3	3
all_values[1]	auto[0]	auto[1]	158174	1			T48	9		T136	3891		T97	5165
all_values[1]	auto[1]	auto[0]	468	1			T106	3		T38	2		T243	2
all_values[1]	auto[1]	auto[1]	304	1			T48	1		T136	8		T97	3
all_values[2]	auto[0]	auto[0]	782450	1			T1	12		T2	1		T3	3
all_values[2]	auto[0]	auto[1]	146474	1			T48	10		T136	3893		T97	5165
all_values[2]	auto[1]	auto[0]	50	1			T18	1		T21	1		T244	1
all_values[2]	auto[1]	auto[1]	199	1			T48	2		T136	6		T97	3
all_values[3]	auto[0]	auto[0]	784871	1			T1	12		T2	1		T3	3
all_values[3]	auto[0]	auto[1]	144057	1			T48	8		T136	3894		T110	942
all_values[3]	auto[1]	auto[1]	245	1			T48	4		T136	5		T71	4
all_values[4]	auto[0]	auto[0]	799968	1			T1	12		T2	1		T3	3
all_values[4]	auto[0]	auto[1]	128954	1			T48	9		T136	3893		T110	944
all_values[4]	auto[1]	auto[0]	24	1			T42	1		T245	1		T246	4
all_values[4]	auto[1]	auto[1]	227	1			T48	3		T136	6		T110	3
all_values[5]	auto[0]	auto[0]	773756	1			T1	12		T2	1		T3	3
all_values[5]	auto[0]	auto[1]	155190	1			T136	3891		T97	5165		T110	945
all_values[5]	auto[1]	auto[1]	227	1			T136	6		T97	3		T110	1
all_values[6]	auto[0]	auto[0]	770729	1			T1	12		T2	1		T3	3
all_values[6]	auto[0]	auto[1]	158181	1			T136	3891		T97	5164		T110	945
all_values[6]	auto[1]	auto[1]	263	1			T136	5		T97	2		T110	1
all_values[7]	auto[0]	auto[0]	749250	1			T1	12		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	146759	1			T48	7		T136	3769		T97	4927
all_values[7]	auto[1]	auto[0]	29528	1			T3	1		T5	1		T6	1
all_values[7]	auto[1]	auto[1]	3636	1			T48	5		T136	128		T97	241
all_values[8]	auto[0]	auto[0]	791700	1			T1	12		T2	1		T3	3
all_values[8]	auto[0]	auto[1]	137219	1			T48	8		T136	3893		T97	5164
all_values[8]	auto[1]	auto[1]	254	1			T48	4		T136	6		T97	2
all_values[9]	auto[0]	auto[0]	192700	1			T1	12		T2	1		T3	2
all_values[9]	auto[0]	auto[1]	17635	1			T48	7		T136	127		T97	47
all_values[9]	auto[1]	auto[0]	577992	1			T3	1		T5	1		T6	1
all_values[9]	auto[1]	auto[1]	140846	1			T48	5		T136	3771		T97	5119
all_values[10]	auto[0]	auto[0]	770745	1			T1	12		T2	1		T3	3
all_values[10]	auto[0]	auto[1]	158212	1			T48	9		T136	3895		T97	5167
all_values[10]	auto[1]	auto[1]	216	1			T48	1		T136	4		T97	1
all_values[11]	auto[0]	auto[0]	2653	1			T1	12		T2	1		T3	1
all_values[11]	auto[0]	auto[1]	498	1			T136	16		T110	6		T71	39
all_values[11]	auto[1]	auto[0]	793871	1			T3	2		T4	2		T5	2
all_values[11]	auto[1]	auto[1]	132151	1			T48	12		T136	3881		T110	940
all_values[12]	auto[0]	auto[0]	791715	1			T1	12		T2	1		T3	3
all_values[12]	auto[0]	auto[1]	137236	1			T136	3894		T97	5167		T110	944
all_values[12]	auto[1]	auto[0]	14	1			T247	1		T248	1		T249	1
all_values[12]	auto[1]	auto[1]	208	1			T136	5		T97	1		T110	3
all_values[13]	auto[0]	auto[0]	771065	1			T1	12		T2	1		T3	3
all_values[13]	auto[0]	auto[1]	157851	1			T48	8		T136	3893		T97	5166
all_values[13]	auto[1]	auto[1]	257	1			T48	2		T136	6		T97	2
all_values[14]	auto[0]	auto[0]	773737	1			T1	12		T2	1		T3	3
all_values[14]	auto[0]	auto[1]	155177	1			T48	8		T136	3894		T97	5164
all_values[14]	auto[1]	auto[1]	259	1			T48	4		T136	5		T97	3