Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	929173	1			T1	12		T2	1		T3	3
all_pins[1]	929173	1			T1	12		T2	1		T3	3
all_pins[2]	929173	1			T1	12		T2	1		T3	3
all_pins[3]	929173	1			T1	12		T2	1		T3	3
all_pins[4]	929173	1			T1	12		T2	1		T3	3
all_pins[5]	929173	1			T1	12		T2	1		T3	3
all_pins[6]	929173	1			T1	12		T2	1		T3	3
all_pins[7]	929173	1			T1	12		T2	1		T3	3
all_pins[8]	929173	1			T1	12		T2	1		T3	3
all_pins[9]	929173	1			T1	12		T2	1		T3	3
all_pins[10]	929173	1			T1	12		T2	1		T3	3
all_pins[11]	929173	1			T1	12		T2	1		T3	3
all_pins[12]	929173	1			T1	12		T2	1		T3	3
all_pins[13]	929173	1			T1	12		T2	1		T3	3
all_pins[14]	929173	1			T1	12		T2	1		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11437255	1			T1	180		T2	15		T3	39
values[0x1]	2500340	1			T3	6		T4	4		T5	6
transitions[0x0=>0x1]	2499201	1			T3	6		T4	4		T5	6
transitions[0x1=>0x0]	2498052	1			T3	5		T4	3		T5	5

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	107952	1			T1	12		T2	1		T3	1
all_pins[0]	values[0x1]	821221	1			T3	2		T4	2		T5	2
all_pins[0]	transitions[0x0=>0x1]	820553	1			T3	2		T4	2		T5	2
all_pins[0]	transitions[0x1=>0x0]	88	1			T136	2		T110	2		T71	4
all_pins[1]	values[0x0]	928417	1			T1	12		T2	1		T3	3
all_pins[1]	values[0x1]	756	1			T106	3		T38	4		T243	2
all_pins[1]	transitions[0x0=>0x1]	733	1			T106	3		T38	4		T243	2
all_pins[1]	transitions[0x1=>0x0]	126	1			T18	1		T21	1		T244	1
all_pins[2]	values[0x0]	929024	1			T1	12		T2	1		T3	3
all_pins[2]	values[0x1]	149	1			T18	1		T21	1		T244	1
all_pins[2]	transitions[0x0=>0x1]	126	1			T18	1		T21	1		T244	1
all_pins[2]	transitions[0x1=>0x0]	105	1			T48	1		T136	2		T71	2
all_pins[3]	values[0x0]	929045	1			T1	12		T2	1		T3	3
all_pins[3]	values[0x1]	128	1			T48	2		T136	3		T71	2
all_pins[3]	transitions[0x0=>0x1]	106	1			T48	1		T136	2		T71	1
all_pins[3]	transitions[0x1=>0x0]	115	1			T48	1		T42	1		T136	1
all_pins[4]	values[0x0]	929036	1			T1	12		T2	1		T3	3
all_pins[4]	values[0x1]	137	1			T48	2		T42	1		T136	2
all_pins[4]	transitions[0x0=>0x1]	105	1			T48	2		T42	1		T136	1
all_pins[4]	transitions[0x1=>0x0]	96	1			T136	4		T110	1		T71	1
all_pins[5]	values[0x0]	929045	1			T1	12		T2	1		T3	3
all_pins[5]	values[0x1]	128	1			T136	5		T110	1		T71	1
all_pins[5]	transitions[0x0=>0x1]	88	1			T136	1		T110	1		T256	3
all_pins[5]	transitions[0x1=>0x0]	93	1			T136	1		T71	3		T256	5
all_pins[6]	values[0x0]	929040	1			T1	12		T2	1		T3	3
all_pins[6]	values[0x1]	133	1			T136	5		T71	4		T256	5
all_pins[6]	transitions[0x0=>0x1]	104	1			T136	2		T71	4		T256	5
all_pins[6]	transitions[0x1=>0x0]	36312	1			T3	1		T5	1		T6	1
all_pins[7]	values[0x0]	892832	1			T1	12		T2	1		T3	2
all_pins[7]	values[0x1]	36341	1			T3	1		T5	1		T6	1
all_pins[7]	transitions[0x0=>0x1]	36301	1			T3	1		T5	1		T6	1
all_pins[7]	transitions[0x1=>0x0]	90	1			T48	2		T136	3		T97	2
all_pins[8]	values[0x0]	929043	1			T1	12		T2	1		T3	3
all_pins[8]	values[0x1]	130	1			T48	2		T136	5		T97	2
all_pins[8]	transitions[0x0=>0x1]	90	1			T136	3		T71	3		T256	3
all_pins[8]	transitions[0x1=>0x0]	718721	1			T3	1		T5	1		T6	1
all_pins[9]	values[0x0]	210412	1			T1	12		T2	1		T3	2
all_pins[9]	values[0x1]	718761	1			T3	1		T5	1		T6	1
all_pins[9]	transitions[0x0=>0x1]	718732	1			T3	1		T5	1		T6	1
all_pins[9]	transitions[0x1=>0x0]	83	1			T136	1		T110	2		T71	1
all_pins[10]	values[0x0]	929061	1			T1	12		T2	1		T3	3
all_pins[10]	values[0x1]	112	1			T48	1		T136	1		T110	2
all_pins[10]	transitions[0x0=>0x1]	78	1			T48	1		T136	1		T110	1
all_pins[10]	transitions[0x1=>0x0]	921940	1			T3	2		T4	2		T5	2
all_pins[11]	values[0x0]	7199	1			T1	12		T2	1		T3	1
all_pins[11]	values[0x1]	921974	1			T3	2		T4	2		T5	2
all_pins[11]	transitions[0x0=>0x1]	921930	1			T3	2		T4	2		T5	2
all_pins[11]	transitions[0x1=>0x0]	65	1			T97	1		T256	1		T100	2
all_pins[12]	values[0x0]	929064	1			T1	12		T2	1		T3	3
all_pins[12]	values[0x1]	109	1			T21	1		T247	1		T248	1
all_pins[12]	transitions[0x0=>0x1]	76	1			T21	1		T247	1		T248	1
all_pins[12]	transitions[0x1=>0x0]	109	1			T48	2		T136	2		T71	1
all_pins[13]	values[0x0]	929031	1			T1	12		T2	1		T3	3
all_pins[13]	values[0x1]	142	1			T48	2		T136	2		T97	1
all_pins[13]	transitions[0x0=>0x1]	105	1			T136	2		T97	1		T256	6
all_pins[13]	transitions[0x1=>0x0]	82	1			T48	1		T136	3		T97	1
all_pins[14]	values[0x0]	929054	1			T1	12		T2	1		T3	3
all_pins[14]	values[0x1]	119	1			T48	3		T136	3		T97	1
all_pins[14]	transitions[0x0=>0x1]	74	1			T48	2		T136	1		T110	1
all_pins[14]	transitions[0x1=>0x0]	820027	1			T3	1		T4	1		T5	1