Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	518	1			T48	4		T136	11		T97	4
all_values[1]	518	1			T48	4		T136	11		T97	4
all_values[2]	518	1			T48	4		T136	11		T97	4
all_values[3]	518	1			T48	4		T136	11		T97	4
all_values[4]	518	1			T48	4		T136	11		T97	4
all_values[5]	518	1			T48	4		T136	11		T97	4
all_values[6]	518	1			T48	4		T136	11		T97	4
all_values[7]	518	1			T48	4		T136	11		T97	4
all_values[8]	518	1			T48	4		T136	11		T97	4
all_values[9]	518	1			T48	4		T136	11		T97	4
all_values[10]	518	1			T48	4		T136	11		T97	4
all_values[11]	518	1			T48	4		T136	11		T97	4
all_values[12]	518	1			T48	4		T136	11		T97	4
all_values[13]	518	1			T48	4		T136	11		T97	4
all_values[14]	518	1			T48	4		T136	11		T97	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4066

1

T48

29

T136

66

T97

27

auto[1]

3704

1

T48

31

T136

99

T97

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1181

1

T48

22

T136

10

T97

20

auto[1]

6589

1

T48

38

T136

155

T97

40

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4585

1

T48

40

T136

94

T97

41

auto[1]

3185

1

T48

20

T136

71

T97

19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	41	1			T48	2		T110	1		T256	1
all_values[0]	auto[0]	auto[0]	auto[1]	110	1			T136	4		T97	1		T110	1
all_values[0]	auto[0]	auto[1]	auto[0]	25	1			T48	2		T97	1		T265	2
all_values[0]	auto[0]	auto[1]	auto[1]	125	1			T136	1		T110	2		T71	6
all_values[0]	auto[1]	auto[0]	auto[1]	103	1			T136	1		T97	1		T110	1
all_values[0]	auto[1]	auto[1]	auto[1]	114	1			T136	5		T97	1		T110	2
all_values[1]	auto[0]	auto[0]	auto[0]	46	1			T48	2		T110	2		T71	1
all_values[1]	auto[0]	auto[0]	auto[1]	111	1			T48	1		T97	1		T71	5
all_values[1]	auto[0]	auto[1]	auto[0]	22	1			T110	1		T100	2		T112	2
all_values[1]	auto[0]	auto[1]	auto[1]	114	1			T136	6		T97	1		T110	2
all_values[1]	auto[1]	auto[0]	auto[1]	123	1			T48	1		T136	2		T97	1
all_values[1]	auto[1]	auto[1]	auto[1]	102	1			T136	3		T97	1		T110	1
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T110	1		T256	1		T168	2
all_values[2]	auto[0]	auto[0]	auto[1]	125	1			T97	1		T110	2		T71	1
all_values[2]	auto[0]	auto[1]	auto[0]	24	1			T100	2		T113	2		T72	2
all_values[2]	auto[0]	auto[1]	auto[1]	130	1			T48	2		T136	5		T110	2
all_values[2]	auto[1]	auto[0]	auto[1]	107	1			T136	2		T97	2		T71	2
all_values[2]	auto[1]	auto[1]	auto[1]	92	1			T48	2		T136	4		T97	1
all_values[3]	auto[0]	auto[0]	auto[0]	59	1			T97	2		T110	3		T71	6
all_values[3]	auto[0]	auto[0]	auto[1]	96	1			T48	1		T136	4		T71	1
all_values[3]	auto[0]	auto[1]	auto[0]	40	1			T97	2		T110	2		T71	4
all_values[3]	auto[0]	auto[1]	auto[1]	113	1			T48	2		T136	4		T110	1
all_values[3]	auto[1]	auto[0]	auto[1]	105	1			T136	1		T71	1		T256	5
all_values[3]	auto[1]	auto[1]	auto[1]	105	1			T48	1		T136	2		T110	1
all_values[4]	auto[0]	auto[0]	auto[0]	34	1			T71	1		T256	1		T112	1
all_values[4]	auto[0]	auto[0]	auto[1]	127	1			T136	4		T110	3		T71	3
all_values[4]	auto[0]	auto[1]	auto[0]	35	1			T97	4		T71	1		T112	1
all_values[4]	auto[0]	auto[1]	auto[1]	95	1			T48	1		T136	1		T110	1
all_values[4]	auto[1]	auto[0]	auto[1]	123	1			T48	2		T136	4		T110	2
all_values[4]	auto[1]	auto[1]	auto[1]	104	1			T48	1		T136	2		T110	1
all_values[5]	auto[0]	auto[0]	auto[0]	53	1			T48	1		T136	1		T110	1
all_values[5]	auto[0]	auto[0]	auto[1]	96	1			T136	1		T97	2		T71	4
all_values[5]	auto[0]	auto[1]	auto[0]	39	1			T48	3		T136	1		T71	1
all_values[5]	auto[0]	auto[1]	auto[1]	136	1			T136	4		T110	4		T71	4
all_values[5]	auto[1]	auto[0]	auto[1]	94	1			T136	1		T97	1		T71	3
all_values[5]	auto[1]	auto[1]	auto[1]	100	1			T136	3		T97	1		T110	2
all_values[6]	auto[0]	auto[0]	auto[0]	53	1			T48	1		T136	3		T110	1
all_values[6]	auto[0]	auto[0]	auto[1]	105	1			T136	1		T97	1		T71	4
all_values[6]	auto[0]	auto[1]	auto[0]	27	1			T48	3		T97	2		T112	1
all_values[6]	auto[0]	auto[1]	auto[1]	121	1			T136	4		T110	4		T71	2
all_values[6]	auto[1]	auto[0]	auto[1]	113	1			T136	1		T97	1		T110	2
all_values[6]	auto[1]	auto[1]	auto[1]	99	1			T136	2		T71	5		T256	3
all_values[7]	auto[0]	auto[0]	auto[0]	52	1			T136	1		T71	1		T103	3
all_values[7]	auto[0]	auto[0]	auto[1]	113	1			T48	1		T136	2		T97	2
all_values[7]	auto[0]	auto[1]	auto[0]	39	1			T136	1		T71	1		T112	1
all_values[7]	auto[0]	auto[1]	auto[1]	108	1			T136	4		T97	1		T110	2
all_values[7]	auto[1]	auto[0]	auto[1]	101	1			T48	1		T110	1		T71	4
all_values[7]	auto[1]	auto[1]	auto[1]	105	1			T48	2		T136	3		T97	1
all_values[8]	auto[0]	auto[0]	auto[0]	43	1			T256	1		T111	1		T72	1
all_values[8]	auto[0]	auto[0]	auto[1]	122	1			T48	1		T110	1		T71	4
all_values[8]	auto[0]	auto[1]	auto[0]	29	1			T97	2		T71	1		T100	1
all_values[8]	auto[0]	auto[1]	auto[1]	117	1			T48	1		T136	7		T97	1
all_values[8]	auto[1]	auto[0]	auto[1]	113	1			T48	2		T136	1		T110	2
all_values[8]	auto[1]	auto[1]	auto[1]	94	1			T136	3		T97	1		T71	4
all_values[9]	auto[0]	auto[0]	auto[0]	45	1			T136	1		T97	1		T110	2
all_values[9]	auto[0]	auto[0]	auto[1]	109	1			T136	1		T110	3		T71	1
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T97	1		T256	2		T266	3
all_values[9]	auto[0]	auto[1]	auto[1]	125	1			T48	2		T136	4		T97	1
all_values[9]	auto[1]	auto[0]	auto[1]	106	1			T48	1		T136	3		T71	1
all_values[9]	auto[1]	auto[1]	auto[1]	114	1			T48	1		T136	2		T97	1
all_values[10]	auto[0]	auto[0]	auto[0]	59	1			T48	2		T110	2		T256	1
all_values[10]	auto[0]	auto[0]	auto[1]	97	1			T136	2		T97	3		T71	3
all_values[10]	auto[0]	auto[1]	auto[0]	38	1			T256	1		T100	1		T111	2
all_values[10]	auto[0]	auto[1]	auto[1]	108	1			T48	1		T136	5		T110	3
all_values[10]	auto[1]	auto[0]	auto[1]	115	1			T48	1		T136	2		T71	8
all_values[10]	auto[1]	auto[1]	auto[1]	101	1			T136	2		T97	1		T110	2
all_values[11]	auto[0]	auto[0]	auto[0]	65	1			T97	3		T110	1		T256	1
all_values[11]	auto[0]	auto[0]	auto[1]	102	1			T48	2		T136	2		T71	2
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T136	2		T97	1		T265	2
all_values[11]	auto[0]	auto[1]	auto[1]	103	1			T136	3		T110	3		T71	6
all_values[11]	auto[1]	auto[0]	auto[1]	123	1			T48	1		T136	1		T71	1
all_values[11]	auto[1]	auto[1]	auto[1]	101	1			T48	1		T136	3		T110	3
all_values[12]	auto[0]	auto[0]	auto[0]	58	1			T48	4		T71	2		T111	3
all_values[12]	auto[0]	auto[0]	auto[1]	112	1			T136	5		T97	2		T110	2
all_values[12]	auto[0]	auto[1]	auto[0]	33	1			T71	3		T100	1		T111	1
all_values[12]	auto[0]	auto[1]	auto[1]	107	1			T136	1		T97	1		T110	2
all_values[12]	auto[1]	auto[0]	auto[1]	121	1			T136	3		T110	3		T71	3
all_values[12]	auto[1]	auto[1]	auto[1]	87	1			T136	2		T97	1		T71	1
all_values[13]	auto[0]	auto[0]	auto[0]	35	1			T48	1		T110	1		T256	2
all_values[13]	auto[0]	auto[0]	auto[1]	116	1			T136	2		T110	2		T71	3
all_values[13]	auto[0]	auto[1]	auto[0]	32	1			T48	1		T112	1		T265	1
all_values[13]	auto[0]	auto[1]	auto[1]	128	1			T48	1		T136	4		T97	2
all_values[13]	auto[1]	auto[0]	auto[1]	106	1			T136	4		T71	2		T256	3
all_values[13]	auto[1]	auto[1]	auto[1]	101	1			T48	1		T136	1		T97	2
all_values[14]	auto[0]	auto[0]	auto[0]	42	1			T110	2		T100	1		T265	2
all_values[14]	auto[0]	auto[0]	auto[1]	126	1			T136	2		T97	1		T110	1
all_values[14]	auto[0]	auto[1]	auto[0]	30	1			T97	1		T110	1		T71	2
all_values[14]	auto[0]	auto[1]	auto[1]	107	1			T48	2		T136	1		T71	3
all_values[14]	auto[1]	auto[0]	auto[1]	121	1			T48	1		T136	4		T97	1
all_values[14]	auto[1]	auto[1]	auto[1]	92	1			T48	1		T136	4		T97	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal