Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.06 96.69 89.76 97.22 70.83 93.76 98.44 90.74


Total test records in report: 1589
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T1516 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4037146805 Jun 26 04:50:56 PM PDT 24 Jun 26 04:51:00 PM PDT 24 146539160 ps
T178 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1281661919 Jun 26 04:51:01 PM PDT 24 Jun 26 04:51:06 PM PDT 24 94138257 ps
T1517 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1542514260 Jun 26 04:50:48 PM PDT 24 Jun 26 04:50:50 PM PDT 24 41799389 ps
T1518 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1778207653 Jun 26 04:50:31 PM PDT 24 Jun 26 04:50:35 PM PDT 24 49619203 ps
T1519 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2914507766 Jun 26 04:51:01 PM PDT 24 Jun 26 04:51:04 PM PDT 24 28303885 ps
T204 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.418099639 Jun 26 04:50:39 PM PDT 24 Jun 26 04:50:40 PM PDT 24 52043261 ps
T1520 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1254378077 Jun 26 04:50:27 PM PDT 24 Jun 26 04:50:31 PM PDT 24 136293947 ps
T1521 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2740728281 Jun 26 04:50:46 PM PDT 24 Jun 26 04:50:49 PM PDT 24 298942890 ps
T205 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.77894788 Jun 26 04:50:26 PM PDT 24 Jun 26 04:50:29 PM PDT 24 45708731 ps
T1522 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2459436086 Jun 26 04:50:28 PM PDT 24 Jun 26 04:50:36 PM PDT 24 8312309111 ps
T184 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3846549244 Jun 26 04:50:55 PM PDT 24 Jun 26 04:50:59 PM PDT 24 177222447 ps
T206 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2886465069 Jun 26 04:50:25 PM PDT 24 Jun 26 04:50:27 PM PDT 24 23656001 ps
T1523 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.620857889 Jun 26 04:50:44 PM PDT 24 Jun 26 04:50:47 PM PDT 24 46291464 ps
T1524 /workspace/coverage/cover_reg_top/43.i2c_intr_test.1955421947 Jun 26 04:51:03 PM PDT 24 Jun 26 04:51:07 PM PDT 24 15202583 ps
T1525 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.33571816 Jun 26 04:50:54 PM PDT 24 Jun 26 04:50:57 PM PDT 24 30602204 ps
T181 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.236516229 Jun 26 04:50:42 PM PDT 24 Jun 26 04:50:45 PM PDT 24 1312739824 ps
T182 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2514272442 Jun 26 04:50:42 PM PDT 24 Jun 26 04:50:45 PM PDT 24 338225045 ps
T207 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1070475267 Jun 26 04:50:38 PM PDT 24 Jun 26 04:50:39 PM PDT 24 36445065 ps
T1526 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1247773017 Jun 26 04:50:48 PM PDT 24 Jun 26 04:50:50 PM PDT 24 23946229 ps
T1527 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3821946775 Jun 26 04:50:41 PM PDT 24 Jun 26 04:50:43 PM PDT 24 39053231 ps
T1528 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2725729993 Jun 26 04:50:23 PM PDT 24 Jun 26 04:50:24 PM PDT 24 19098822 ps
T1529 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4169997806 Jun 26 04:50:54 PM PDT 24 Jun 26 04:50:59 PM PDT 24 498142134 ps
T1530 /workspace/coverage/cover_reg_top/9.i2c_intr_test.1775460373 Jun 26 04:50:48 PM PDT 24 Jun 26 04:50:50 PM PDT 24 17331874 ps
T1531 /workspace/coverage/cover_reg_top/0.i2c_intr_test.664949926 Jun 26 04:50:21 PM PDT 24 Jun 26 04:50:22 PM PDT 24 43057287 ps
T1532 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2057185112 Jun 26 04:50:26 PM PDT 24 Jun 26 04:50:29 PM PDT 24 69209186 ps
T1533 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1549067840 Jun 26 04:50:55 PM PDT 24 Jun 26 04:51:00 PM PDT 24 61548773 ps
T185 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1305528428 Jun 26 04:50:45 PM PDT 24 Jun 26 04:50:48 PM PDT 24 2084215389 ps
T1534 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2058362883 Jun 26 04:50:56 PM PDT 24 Jun 26 04:51:00 PM PDT 24 57655793 ps
T1535 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3484654149 Jun 26 04:50:45 PM PDT 24 Jun 26 04:50:47 PM PDT 24 100629974 ps
T1536 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2139376399 Jun 26 04:51:02 PM PDT 24 Jun 26 04:51:06 PM PDT 24 32174270 ps
T1537 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3793787951 Jun 26 04:50:56 PM PDT 24 Jun 26 04:50:59 PM PDT 24 55990346 ps
T1538 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3504613583 Jun 26 04:50:54 PM PDT 24 Jun 26 04:50:57 PM PDT 24 33445359 ps
T1539 /workspace/coverage/cover_reg_top/3.i2c_intr_test.2949981714 Jun 26 04:50:26 PM PDT 24 Jun 26 04:50:29 PM PDT 24 22019793 ps
T1540 /workspace/coverage/cover_reg_top/13.i2c_intr_test.1917578210 Jun 26 04:50:54 PM PDT 24 Jun 26 04:50:56 PM PDT 24 29432916 ps
T1541 /workspace/coverage/cover_reg_top/44.i2c_intr_test.817753341 Jun 26 04:51:01 PM PDT 24 Jun 26 04:51:03 PM PDT 24 18618083 ps
T1542 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1339630499 Jun 26 04:50:29 PM PDT 24 Jun 26 04:50:31 PM PDT 24 97922377 ps
T1543 /workspace/coverage/cover_reg_top/30.i2c_intr_test.1982077695 Jun 26 04:51:02 PM PDT 24 Jun 26 04:51:06 PM PDT 24 40559591 ps
T1544 /workspace/coverage/cover_reg_top/35.i2c_intr_test.4278928174 Jun 26 04:51:01 PM PDT 24 Jun 26 04:51:04 PM PDT 24 26071322 ps
T1545 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.198636607 Jun 26 04:50:53 PM PDT 24 Jun 26 04:50:56 PM PDT 24 85840823 ps
T1546 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1640845078 Jun 26 04:50:40 PM PDT 24 Jun 26 04:50:42 PM PDT 24 51407998 ps
T1547 /workspace/coverage/cover_reg_top/5.i2c_intr_test.1725773295 Jun 26 04:50:39 PM PDT 24 Jun 26 04:50:41 PM PDT 24 26390325 ps
T1548 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2693832011 Jun 26 04:50:46 PM PDT 24 Jun 26 04:50:48 PM PDT 24 56175801 ps
T208 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2595478101 Jun 26 04:50:34 PM PDT 24 Jun 26 04:50:37 PM PDT 24 268595587 ps
T1549 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2437616197 Jun 26 04:50:34 PM PDT 24 Jun 26 04:50:37 PM PDT 24 94211571 ps
T1550 /workspace/coverage/cover_reg_top/18.i2c_intr_test.3242034200 Jun 26 04:50:53 PM PDT 24 Jun 26 04:50:55 PM PDT 24 15440680 ps
T1551 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2952773808 Jun 26 04:50:47 PM PDT 24 Jun 26 04:50:49 PM PDT 24 56791118 ps
T1552 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1862435106 Jun 26 04:50:27 PM PDT 24 Jun 26 04:50:31 PM PDT 24 183684466 ps
T1553 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1128429761 Jun 26 04:50:55 PM PDT 24 Jun 26 04:50:59 PM PDT 24 96775879 ps
T1554 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1724889395 Jun 26 04:50:54 PM PDT 24 Jun 26 04:50:57 PM PDT 24 387528766 ps
T1555 /workspace/coverage/cover_reg_top/28.i2c_intr_test.298673916 Jun 26 04:51:02 PM PDT 24 Jun 26 04:51:06 PM PDT 24 98554892 ps
T1556 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.656973086 Jun 26 04:50:45 PM PDT 24 Jun 26 04:50:46 PM PDT 24 26680511 ps
T1557 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1768651820 Jun 26 04:51:00 PM PDT 24 Jun 26 04:51:02 PM PDT 24 55477256 ps
T179 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4175284721 Jun 26 04:50:58 PM PDT 24 Jun 26 04:51:02 PM PDT 24 246819942 ps
T1558 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2120994337 Jun 26 04:51:02 PM PDT 24 Jun 26 04:51:06 PM PDT 24 34420835 ps
T1559 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.568148875 Jun 26 04:50:36 PM PDT 24 Jun 26 04:50:37 PM PDT 24 28227552 ps
T1560 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1920212379 Jun 26 04:50:41 PM PDT 24 Jun 26 04:50:43 PM PDT 24 33837200 ps
T180 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.598054561 Jun 26 04:50:31 PM PDT 24 Jun 26 04:50:34 PM PDT 24 50511399 ps
T1561 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1991288190 Jun 26 04:50:54 PM PDT 24 Jun 26 04:50:57 PM PDT 24 38059110 ps
T1562 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1235467872 Jun 26 04:50:49 PM PDT 24 Jun 26 04:50:52 PM PDT 24 518776507 ps
T1563 /workspace/coverage/cover_reg_top/34.i2c_intr_test.4045961304 Jun 26 04:51:02 PM PDT 24 Jun 26 04:51:06 PM PDT 24 15870129 ps
T250 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1226012174 Jun 26 04:50:41 PM PDT 24 Jun 26 04:50:44 PM PDT 24 177438873 ps
T1564 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2569132054 Jun 26 04:50:53 PM PDT 24 Jun 26 04:50:55 PM PDT 24 23315366 ps
T1565 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2493517485 Jun 26 04:50:33 PM PDT 24 Jun 26 04:50:37 PM PDT 24 113593083 ps
T1566 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1666577447 Jun 26 04:50:31 PM PDT 24 Jun 26 04:50:32 PM PDT 24 44883517 ps
T1567 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1757520070 Jun 26 04:50:24 PM PDT 24 Jun 26 04:50:27 PM PDT 24 120308045 ps
T177 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3446009894 Jun 26 04:50:47 PM PDT 24 Jun 26 04:50:51 PM PDT 24 98457778 ps
T186 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.995211887 Jun 26 04:50:30 PM PDT 24 Jun 26 04:50:33 PM PDT 24 51247470 ps
T1568 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3743959004 Jun 26 04:50:54 PM PDT 24 Jun 26 04:50:58 PM PDT 24 96713888 ps
T1569 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1751205384 Jun 26 04:50:48 PM PDT 24 Jun 26 04:50:51 PM PDT 24 400966445 ps
T1570 /workspace/coverage/cover_reg_top/42.i2c_intr_test.464943776 Jun 26 04:51:01 PM PDT 24 Jun 26 04:51:04 PM PDT 24 69074216 ps
T1571 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3648140824 Jun 26 04:50:56 PM PDT 24 Jun 26 04:51:00 PM PDT 24 131208798 ps
T1572 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2658136866 Jun 26 04:51:01 PM PDT 24 Jun 26 04:51:05 PM PDT 24 110088406 ps
T1573 /workspace/coverage/cover_reg_top/20.i2c_intr_test.997281978 Jun 26 04:51:00 PM PDT 24 Jun 26 04:51:02 PM PDT 24 25361243 ps
T1574 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2282055891 Jun 26 04:51:03 PM PDT 24 Jun 26 04:51:07 PM PDT 24 41143928 ps
T1575 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1789476466 Jun 26 04:50:25 PM PDT 24 Jun 26 04:50:27 PM PDT 24 1003589940 ps
T1576 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1102282775 Jun 26 04:50:56 PM PDT 24 Jun 26 04:50:59 PM PDT 24 43048848 ps
T1577 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3053422085 Jun 26 04:50:44 PM PDT 24 Jun 26 04:50:48 PM PDT 24 270438402 ps
T1578 /workspace/coverage/cover_reg_top/46.i2c_intr_test.394316271 Jun 26 04:51:02 PM PDT 24 Jun 26 04:51:06 PM PDT 24 30971427 ps
T1579 /workspace/coverage/cover_reg_top/12.i2c_intr_test.22704595 Jun 26 04:50:47 PM PDT 24 Jun 26 04:50:49 PM PDT 24 29779996 ps
T1580 /workspace/coverage/cover_reg_top/7.i2c_intr_test.1849144308 Jun 26 04:50:43 PM PDT 24 Jun 26 04:50:45 PM PDT 24 28697394 ps
T1581 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.487058853 Jun 26 04:50:49 PM PDT 24 Jun 26 04:50:51 PM PDT 24 254549326 ps
T1582 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1062830042 Jun 26 04:51:01 PM PDT 24 Jun 26 04:51:04 PM PDT 24 25549989 ps
T1583 /workspace/coverage/cover_reg_top/2.i2c_intr_test.4147787458 Jun 26 04:50:25 PM PDT 24 Jun 26 04:50:27 PM PDT 24 60196080 ps
T1584 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1259493190 Jun 26 04:50:28 PM PDT 24 Jun 26 04:50:30 PM PDT 24 18402216 ps
T1585 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.4000348224 Jun 26 04:50:28 PM PDT 24 Jun 26 04:50:33 PM PDT 24 328628186 ps
T1586 /workspace/coverage/cover_reg_top/21.i2c_intr_test.1841224124 Jun 26 04:51:00 PM PDT 24 Jun 26 04:51:03 PM PDT 24 22045110 ps
T1587 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.953643853 Jun 26 04:50:52 PM PDT 24 Jun 26 04:50:54 PM PDT 24 34748219 ps
T1588 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2862975707 Jun 26 04:50:54 PM PDT 24 Jun 26 04:50:57 PM PDT 24 27436807 ps
T1589 /workspace/coverage/cover_reg_top/17.i2c_intr_test.273006443 Jun 26 04:50:55 PM PDT 24 Jun 26 04:50:58 PM PDT 24 18480896 ps

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2331554605
Short name T10
Test name
Test status
Simulation time 8956999579 ps
CPU time 52.74 seconds
Started Jun 26 04:57:06 PM PDT 24
Finished Jun 26 04:58:00 PM PDT 24
Peak memory 564420 kb
Host smart-87502aa4-d8f5-4f21-a493-cd363e5cd1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331554605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2331554605
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1850195417
Short name T28
Test name
Test status
Simulation time 1048482962 ps
CPU time 6.2 seconds
Started Jun 26 04:55:37 PM PDT 24
Finished Jun 26 04:55:47 PM PDT 24
Peak memory 213084 kb
Host smart-2a0dbf49-0af4-47b8-b306-3db1563dea3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850195417 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1850195417
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2193184147
Short name T16
Test name
Test status
Simulation time 6895802007 ps
CPU time 8.32 seconds
Started Jun 26 04:55:52 PM PDT 24
Finished Jun 26 04:56:02 PM PDT 24
Peak memory 213736 kb
Host smart-09c5b018-29f9-43ff-a2fa-5f2a524a2038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193184147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2193184147
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.3129237025
Short name T136
Test name
Test status
Simulation time 85321231219 ps
CPU time 3218.61 seconds
Started Jun 26 04:57:04 PM PDT 24
Finished Jun 26 05:50:44 PM PDT 24
Peak memory 5977272 kb
Host smart-651c1388-e8fe-4e1b-8d88-c1bea6fa651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129237025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.3129237025
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.3200987743
Short name T36
Test name
Test status
Simulation time 27152505609 ps
CPU time 1903.9 seconds
Started Jun 26 04:57:32 PM PDT 24
Finished Jun 26 05:29:19 PM PDT 24
Peak memory 4199408 kb
Host smart-8e4adcf0-1d68-4427-a70b-86358c998958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200987743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.3200987743
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.3952619053
Short name T92
Test name
Test status
Simulation time 39311012 ps
CPU time 0.95 seconds
Started Jun 26 04:50:30 PM PDT 24
Finished Jun 26 04:50:32 PM PDT 24
Peak memory 204436 kb
Host smart-6aae8359-2bab-46fc-8145-a4bc72d27f92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952619053 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.3952619053
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/42.i2c_host_override.918441899
Short name T229
Test name
Test status
Simulation time 16649642 ps
CPU time 0.64 seconds
Started Jun 26 05:02:43 PM PDT 24
Finished Jun 26 05:02:44 PM PDT 24
Peak memory 204572 kb
Host smart-c144e558-b92c-4d78-897b-d1174dbd44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918441899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.918441899
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.353978693
Short name T20
Test name
Test status
Simulation time 16293566232 ps
CPU time 31.28 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:57:50 PM PDT 24
Peak memory 611792 kb
Host smart-5008034b-765c-48ba-976d-7651b419b54e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353978693 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.353978693
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.1508371655
Short name T42
Test name
Test status
Simulation time 1086519236 ps
CPU time 8.83 seconds
Started Jun 26 04:55:56 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 204852 kb
Host smart-9f2ee7a6-6e24-4908-a3dc-ead83ebbd9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508371655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.1508371655
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.2977286776
Short name T48
Test name
Test status
Simulation time 59819120849 ps
CPU time 1323.8 seconds
Started Jun 26 04:58:05 PM PDT 24
Finished Jun 26 05:20:11 PM PDT 24
Peak memory 2896300 kb
Host smart-4f16abca-1b36-4290-873d-1c1b0d957f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977286776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.2977286776
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.4035053343
Short name T4
Test name
Test status
Simulation time 2285919325 ps
CPU time 1.44 seconds
Started Jun 26 04:56:57 PM PDT 24
Finished Jun 26 04:56:59 PM PDT 24
Peak memory 209948 kb
Host smart-318f1fc8-29ee-4cc4-8217-06ba9908c6f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035053343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.4035053343
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2528892520
Short name T162
Test name
Test status
Simulation time 411046741 ps
CPU time 0.92 seconds
Started Jun 26 04:55:54 PM PDT 24
Finished Jun 26 04:55:57 PM PDT 24
Peak memory 223136 kb
Host smart-10c432bf-f85b-45b0-93fe-9996707f7b9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528892520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2528892520
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_alert_test.1872245380
Short name T385
Test name
Test status
Simulation time 30462183 ps
CPU time 0.65 seconds
Started Jun 26 04:55:54 PM PDT 24
Finished Jun 26 04:55:56 PM PDT 24
Peak memory 204416 kb
Host smart-bb3d2577-fdd4-4cb9-bd3e-8a29f4ba21f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872245380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.1872245380
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.889474377
Short name T100
Test name
Test status
Simulation time 109050956812 ps
CPU time 323.64 seconds
Started Jun 26 05:01:37 PM PDT 24
Finished Jun 26 05:07:02 PM PDT 24
Peak memory 1862272 kb
Host smart-b3762f6b-47b4-44b4-ad35-4f4495600f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889474377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.889474377
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.1599658404
Short name T198
Test name
Test status
Simulation time 84703510 ps
CPU time 0.8 seconds
Started Jun 26 04:50:46 PM PDT 24
Finished Jun 26 04:50:47 PM PDT 24
Peak memory 204300 kb
Host smart-38fb7b79-dfce-45af-87a3-52eaba9883bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599658404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.1599658404
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.4085518412
Short name T87
Test name
Test status
Simulation time 166106818 ps
CPU time 2.72 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204448 kb
Host smart-d0dd6d17-95bc-428f-9ae3-7d2829d9725f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085518412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.4085518412
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.1277695708
Short name T189
Test name
Test status
Simulation time 3687708900 ps
CPU time 4.43 seconds
Started Jun 26 05:01:43 PM PDT 24
Finished Jun 26 05:01:49 PM PDT 24
Peak memory 213100 kb
Host smart-7104fc8f-044b-437a-b744-d7969df70e0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277695708 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.1277695708
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.709236559
Short name T45
Test name
Test status
Simulation time 53436182420 ps
CPU time 761.01 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 05:09:31 PM PDT 24
Peak memory 2376432 kb
Host smart-0952bdf9-9c0f-4b54-ba46-8159b64c1612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709236559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.709236559
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.303978922
Short name T46
Test name
Test status
Simulation time 136363996 ps
CPU time 4.05 seconds
Started Jun 26 04:57:47 PM PDT 24
Finished Jun 26 04:57:55 PM PDT 24
Peak memory 216736 kb
Host smart-7b7ba9fd-31a5-4ba6-abbc-e80dc0c15ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303978922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.303978922
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2044916375
Short name T221
Test name
Test status
Simulation time 88539555 ps
CPU time 0.87 seconds
Started Jun 26 04:57:54 PM PDT 24
Finished Jun 26 04:57:57 PM PDT 24
Peak memory 204752 kb
Host smart-8db3d28f-8e72-46a9-bd8b-d6fa1797c164
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044916375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2044916375
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3353512020
Short name T1498
Test name
Test status
Simulation time 410903421 ps
CPU time 2.29 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:05 PM PDT 24
Peak memory 204480 kb
Host smart-d7f41080-ee6f-4eb8-9772-556899d6443b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353512020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3353512020
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.4131199527
Short name T1412
Test name
Test status
Simulation time 18745879115 ps
CPU time 2282.13 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 05:35:36 PM PDT 24
Peak memory 3651920 kb
Host smart-2ac192f3-3db8-455a-b6d1-4f42f7de15ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131199527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.4131199527
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.2298934231
Short name T63
Test name
Test status
Simulation time 84384840 ps
CPU time 1.59 seconds
Started Jun 26 05:01:17 PM PDT 24
Finished Jun 26 05:01:21 PM PDT 24
Peak memory 213044 kb
Host smart-7aa3b093-0878-4c91-864b-66f9132f56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298934231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.2298934231
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1291617983
Short name T217
Test name
Test status
Simulation time 115732287 ps
CPU time 2.8 seconds
Started Jun 26 04:56:45 PM PDT 24
Finished Jun 26 04:56:49 PM PDT 24
Peak memory 204844 kb
Host smart-148baaba-8782-45d8-bbf4-c90243518fec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291617983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1291617983
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.443256673
Short name T34
Test name
Test status
Simulation time 4945380822 ps
CPU time 19.33 seconds
Started Jun 26 05:05:42 PM PDT 24
Finished Jun 26 05:06:03 PM PDT 24
Peak memory 342848 kb
Host smart-fe90c09d-b588-411a-b334-08cb95ce57c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443256673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.443256673
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.1204292186
Short name T216
Test name
Test status
Simulation time 19933425689 ps
CPU time 2814.91 seconds
Started Jun 26 04:57:19 PM PDT 24
Finished Jun 26 05:44:15 PM PDT 24
Peak memory 4080188 kb
Host smart-62b27bf9-8132-4660-8aef-2b5b3492be87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204292186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.1204292186
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.794664485
Short name T72
Test name
Test status
Simulation time 41324811595 ps
CPU time 652.23 seconds
Started Jun 26 05:02:24 PM PDT 24
Finished Jun 26 05:13:18 PM PDT 24
Peak memory 1136872 kb
Host smart-77ed2a6e-a01d-4e82-8429-816b094652d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794664485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.794664485
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.90032752
Short name T83
Test name
Test status
Simulation time 1324132016 ps
CPU time 18.21 seconds
Started Jun 26 04:58:41 PM PDT 24
Finished Jun 26 04:59:01 PM PDT 24
Peak memory 204872 kb
Host smart-ee0f09d6-033a-4d34-8cfc-96eef3a34e2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90032752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_targ
et_smoke.90032752
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_override.1915904729
Short name T123
Test name
Test status
Simulation time 83928784 ps
CPU time 0.65 seconds
Started Jun 26 04:57:08 PM PDT 24
Finished Jun 26 04:57:11 PM PDT 24
Peak memory 204484 kb
Host smart-6aa697fd-4a8e-4e64-a0ce-97f65ad8292c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915904729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.1915904729
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3846549244
Short name T184
Test name
Test status
Simulation time 177222447 ps
CPU time 1.36 seconds
Started Jun 26 04:50:55 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204436 kb
Host smart-9393bffb-c3ea-4814-9168-4634ba2263c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846549244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3846549244
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.3987810603
Short name T263
Test name
Test status
Simulation time 19329020455 ps
CPU time 2381.71 seconds
Started Jun 26 04:59:18 PM PDT 24
Finished Jun 26 05:39:03 PM PDT 24
Peak memory 3247448 kb
Host smart-1be5423f-bc51-4ad4-b2b0-c406be880a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987810603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.3987810603
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1699424759
Short name T249
Test name
Test status
Simulation time 590422042 ps
CPU time 3.15 seconds
Started Jun 26 04:57:54 PM PDT 24
Finished Jun 26 04:58:00 PM PDT 24
Peak memory 204720 kb
Host smart-6d707615-af8d-44c7-9ad7-599cc117c267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699424759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1699424759
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.80581303
Short name T271
Test name
Test status
Simulation time 212368001 ps
CPU time 1.27 seconds
Started Jun 26 04:59:14 PM PDT 24
Finished Jun 26 04:59:17 PM PDT 24
Peak memory 204732 kb
Host smart-24857fb3-658b-4bea-8092-10339ceca9de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80581303 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_acq.80581303
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3930024942
Short name T169
Test name
Test status
Simulation time 29091772570 ps
CPU time 589.05 seconds
Started Jun 26 05:01:38 PM PDT 24
Finished Jun 26 05:11:28 PM PDT 24
Peak memory 1784012 kb
Host smart-75963cb4-f0c2-4cde-9be2-57489fe44f20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930024942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3930024942
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.2901983434
Short name T240
Test name
Test status
Simulation time 9771724907 ps
CPU time 61.12 seconds
Started Jun 26 04:56:10 PM PDT 24
Finished Jun 26 04:57:13 PM PDT 24
Peak memory 492252 kb
Host smart-76b54b2f-d235-4f8f-a2ed-05c5de64943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901983434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2901983434
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2209007285
Short name T224
Test name
Test status
Simulation time 126113928 ps
CPU time 0.99 seconds
Started Jun 26 04:56:09 PM PDT 24
Finished Jun 26 04:56:13 PM PDT 24
Peak memory 204632 kb
Host smart-4d5c46e1-f594-4e7f-8abb-2f1b26fa7a04
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209007285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2209007285
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3716944443
Short name T97
Test name
Test status
Simulation time 17329680760 ps
CPU time 836.04 seconds
Started Jun 26 04:56:00 PM PDT 24
Finished Jun 26 05:09:59 PM PDT 24
Peak memory 2858620 kb
Host smart-0024c04b-7952-4ebf-9249-8253c925ce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716944443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3716944443
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.4175284721
Short name T179
Test name
Test status
Simulation time 246819942 ps
CPU time 2.26 seconds
Started Jun 26 04:50:58 PM PDT 24
Finished Jun 26 04:51:02 PM PDT 24
Peak memory 204428 kb
Host smart-d3de5cfa-5c56-4175-bae0-1af9e7a8ef86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175284721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.4175284721
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.621962964
Short name T226
Test name
Test status
Simulation time 7860019806 ps
CPU time 89.76 seconds
Started Jun 26 05:00:55 PM PDT 24
Finished Jun 26 05:02:26 PM PDT 24
Peak memory 359128 kb
Host smart-4c7654d0-be84-4995-bc42-582b99955222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621962964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.621962964
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.1018208432
Short name T274
Test name
Test status
Simulation time 76160968 ps
CPU time 0.75 seconds
Started Jun 26 04:50:28 PM PDT 24
Finished Jun 26 04:50:30 PM PDT 24
Peak memory 204424 kb
Host smart-1f544eac-6e6c-4023-87cd-85e1d67a67d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018208432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.1018208432
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.2885431453
Short name T133
Test name
Test status
Simulation time 78547272 ps
CPU time 1.69 seconds
Started Jun 26 04:50:24 PM PDT 24
Finished Jun 26 04:50:26 PM PDT 24
Peak memory 204448 kb
Host smart-b1f4d6d3-708a-498b-9747-a29da23b6dde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885431453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.2885431453
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3426610882
Short name T259
Test name
Test status
Simulation time 593384794 ps
CPU time 25.64 seconds
Started Jun 26 04:56:38 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 212948 kb
Host smart-04fc6518-105c-4f19-b9d7-f80cbe76c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426610882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3426610882
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.465702645
Short name T265
Test name
Test status
Simulation time 25013105565 ps
CPU time 996.18 seconds
Started Jun 26 04:56:56 PM PDT 24
Finished Jun 26 05:13:33 PM PDT 24
Peak memory 2221500 kb
Host smart-f3f10e53-4a90-4107-a2ff-bf62cf1d83e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465702645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.465702645
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.1819275962
Short name T1231
Test name
Test status
Simulation time 690191499 ps
CPU time 1.3 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:12 PM PDT 24
Peak memory 204500 kb
Host smart-951a70ee-997a-4bc6-82e0-fbbba1ae2dfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819275962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.1819275962
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.3023314925
Short name T257
Test name
Test status
Simulation time 5825614752 ps
CPU time 11.85 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:57:34 PM PDT 24
Peak memory 229420 kb
Host smart-da7e7f93-1f88-4ada-9a53-47ed414ada90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023314925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3023314925
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.232632078
Short name T620
Test name
Test status
Simulation time 1097301646 ps
CPU time 1.37 seconds
Started Jun 26 04:57:51 PM PDT 24
Finished Jun 26 04:57:53 PM PDT 24
Peak memory 212732 kb
Host smart-e67fd34a-7b8d-42c1-8ca0-47fa477a4cd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232632078 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_acq.232632078
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.3004841911
Short name T251
Test name
Test status
Simulation time 1465754687 ps
CPU time 21.8 seconds
Started Jun 26 04:58:07 PM PDT 24
Finished Jun 26 04:58:30 PM PDT 24
Peak memory 225804 kb
Host smart-1fbc2f5e-b0f3-41ff-b95a-4e91ec658788
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004841911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.3004841911
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1822720227
Short name T91
Test name
Test status
Simulation time 72037436 ps
CPU time 1.55 seconds
Started Jun 26 04:50:27 PM PDT 24
Finished Jun 26 04:50:30 PM PDT 24
Peak memory 204416 kb
Host smart-fa53b9ed-9341-4831-8d70-507b23206dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822720227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1822720227
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.3578722928
Short name T1508
Test name
Test status
Simulation time 101812020 ps
CPU time 1.56 seconds
Started Jun 26 04:50:20 PM PDT 24
Finished Jun 26 04:50:23 PM PDT 24
Peak memory 204484 kb
Host smart-c0de6d1d-08e2-453b-8d04-76efe159c2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578722928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.3578722928
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3446009894
Short name T177
Test name
Test status
Simulation time 98457778 ps
CPU time 2.36 seconds
Started Jun 26 04:50:47 PM PDT 24
Finished Jun 26 04:50:51 PM PDT 24
Peak memory 204436 kb
Host smart-491869e9-15ed-4d50-8c11-22d85d41f328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446009894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3446009894
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.3188771233
Short name T43
Test name
Test status
Simulation time 13512172778 ps
CPU time 713.63 seconds
Started Jun 26 04:58:47 PM PDT 24
Finished Jun 26 05:10:43 PM PDT 24
Peak memory 1950836 kb
Host smart-58b8e287-4e1d-4b43-ad8e-f5c7eb2fde5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188771233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.3188771233
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.558613177
Short name T197
Test name
Test status
Simulation time 697753674 ps
CPU time 2.13 seconds
Started Jun 26 04:50:22 PM PDT 24
Finished Jun 26 04:50:25 PM PDT 24
Peak memory 204464 kb
Host smart-2915208a-e8c1-410a-9613-f4d76ca8876c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558613177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.558613177
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1757520070
Short name T1567
Test name
Test status
Simulation time 120308045 ps
CPU time 2.92 seconds
Started Jun 26 04:50:24 PM PDT 24
Finished Jun 26 04:50:27 PM PDT 24
Peak memory 204460 kb
Host smart-34a1d648-8808-4512-8f31-ec5544ca2998
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757520070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1757520070
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.2725729993
Short name T1528
Test name
Test status
Simulation time 19098822 ps
CPU time 0.79 seconds
Started Jun 26 04:50:23 PM PDT 24
Finished Jun 26 04:50:24 PM PDT 24
Peak memory 204444 kb
Host smart-4dcdd370-11ba-4aa3-8ad4-f17d42129a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725729993 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.2725729993
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1666577447
Short name T1566
Test name
Test status
Simulation time 44883517 ps
CPU time 0.69 seconds
Started Jun 26 04:50:31 PM PDT 24
Finished Jun 26 04:50:32 PM PDT 24
Peak memory 204252 kb
Host smart-d90d41b2-cce1-4973-ba78-dcf0b75bc69b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666577447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1666577447
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.664949926
Short name T1531
Test name
Test status
Simulation time 43057287 ps
CPU time 0.65 seconds
Started Jun 26 04:50:21 PM PDT 24
Finished Jun 26 04:50:22 PM PDT 24
Peak memory 204328 kb
Host smart-090020c7-cf26-45ce-9b20-0b1522b9911f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664949926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.664949926
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2278100484
Short name T211
Test name
Test status
Simulation time 76509838 ps
CPU time 1.08 seconds
Started Jun 26 04:50:23 PM PDT 24
Finished Jun 26 04:50:25 PM PDT 24
Peak memory 204528 kb
Host smart-c6822854-d631-40b2-9e49-8c95eb1ad8f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278100484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2278100484
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.598054561
Short name T180
Test name
Test status
Simulation time 50511399 ps
CPU time 1.58 seconds
Started Jun 26 04:50:31 PM PDT 24
Finished Jun 26 04:50:34 PM PDT 24
Peak memory 204384 kb
Host smart-7f55483d-9612-487d-b28f-2c83f6a9d1a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598054561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.598054561
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.2493517485
Short name T1565
Test name
Test status
Simulation time 113593083 ps
CPU time 2.09 seconds
Started Jun 26 04:50:33 PM PDT 24
Finished Jun 26 04:50:37 PM PDT 24
Peak memory 204424 kb
Host smart-eadaf9a6-429e-4dd2-a60d-46ddbd3db9fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493517485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.2493517485
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2459436086
Short name T1522
Test name
Test status
Simulation time 8312309111 ps
CPU time 6.24 seconds
Started Jun 26 04:50:28 PM PDT 24
Finished Jun 26 04:50:36 PM PDT 24
Peak memory 204564 kb
Host smart-bc8db950-48bd-4527-9ef8-54e01eb6ddfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459436086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2459436086
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.916633117
Short name T202
Test name
Test status
Simulation time 30406448 ps
CPU time 0.67 seconds
Started Jun 26 04:50:16 PM PDT 24
Finished Jun 26 04:50:18 PM PDT 24
Peak memory 204360 kb
Host smart-39a946fa-3790-4736-8eee-6d1464f79367
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916633117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.916633117
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.2886465069
Short name T206
Test name
Test status
Simulation time 23656001 ps
CPU time 0.69 seconds
Started Jun 26 04:50:25 PM PDT 24
Finished Jun 26 04:50:27 PM PDT 24
Peak memory 204308 kb
Host smart-89915f59-ff85-433e-91e5-e8b188acd63f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886465069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.2886465069
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1241915777
Short name T1482
Test name
Test status
Simulation time 16265986 ps
CPU time 0.69 seconds
Started Jun 26 04:50:16 PM PDT 24
Finished Jun 26 04:50:17 PM PDT 24
Peak memory 204216 kb
Host smart-d5e0a74a-9f77-47e9-aaec-51df8f329691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241915777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1241915777
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1789476466
Short name T1575
Test name
Test status
Simulation time 1003589940 ps
CPU time 1.26 seconds
Started Jun 26 04:50:25 PM PDT 24
Finished Jun 26 04:50:27 PM PDT 24
Peak memory 204536 kb
Host smart-3ce891a0-74aa-4e00-bf93-82138c861df2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789476466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1789476466
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1778207653
Short name T1518
Test name
Test status
Simulation time 49619203 ps
CPU time 2.53 seconds
Started Jun 26 04:50:31 PM PDT 24
Finished Jun 26 04:50:35 PM PDT 24
Peak memory 204400 kb
Host smart-51294547-ac9b-4efd-a601-7c0a5cb9f637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778207653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1778207653
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.1991288190
Short name T1561
Test name
Test status
Simulation time 38059110 ps
CPU time 0.96 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:57 PM PDT 24
Peak memory 204408 kb
Host smart-c3db5363-82ce-49c6-acf3-c9706326594e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991288190 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.1991288190
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.2914507766
Short name T1519
Test name
Test status
Simulation time 28303885 ps
CPU time 0.84 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204320 kb
Host smart-4f79f58a-3e3c-472e-a3a1-435c035a99d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914507766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.2914507766
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.928862501
Short name T1494
Test name
Test status
Simulation time 49278331 ps
CPU time 0.71 seconds
Started Jun 26 04:50:46 PM PDT 24
Finished Jun 26 04:50:48 PM PDT 24
Peak memory 204324 kb
Host smart-c72e6ba1-2283-4b64-b0b9-58d35bbecc08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928862501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.928862501
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.2693832011
Short name T1548
Test name
Test status
Simulation time 56175801 ps
CPU time 1.2 seconds
Started Jun 26 04:50:46 PM PDT 24
Finished Jun 26 04:50:48 PM PDT 24
Peak memory 204520 kb
Host smart-4c49076c-28a7-43f2-9305-4552de25cf87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693832011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.2693832011
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1751205384
Short name T1569
Test name
Test status
Simulation time 400966445 ps
CPU time 1.36 seconds
Started Jun 26 04:50:48 PM PDT 24
Finished Jun 26 04:50:51 PM PDT 24
Peak memory 204532 kb
Host smart-cd23cc76-986e-473d-a860-4570c67df8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751205384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1751205384
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.815454642
Short name T94
Test name
Test status
Simulation time 1010668526 ps
CPU time 2.54 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204416 kb
Host smart-9b0b01a3-b1e2-429c-9d49-01e4061c027b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815454642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.815454642
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3743959004
Short name T1568
Test name
Test status
Simulation time 96713888 ps
CPU time 0.94 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:58 PM PDT 24
Peak memory 204372 kb
Host smart-1b604ba2-691e-4e8c-b5c3-96f613117dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743959004 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3743959004
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.1062830042
Short name T1582
Test name
Test status
Simulation time 25549989 ps
CPU time 0.83 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204316 kb
Host smart-2d90e9bf-1e54-4fed-b180-c97053b9637d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062830042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.1062830042
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.1216879691
Short name T1477
Test name
Test status
Simulation time 20381688 ps
CPU time 0.67 seconds
Started Jun 26 04:50:44 PM PDT 24
Finished Jun 26 04:50:46 PM PDT 24
Peak memory 204328 kb
Host smart-86fec9b0-3eb4-4127-8291-4da3de2da8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216879691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.1216879691
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.2658136866
Short name T1572
Test name
Test status
Simulation time 110088406 ps
CPU time 0.92 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:05 PM PDT 24
Peak memory 204416 kb
Host smart-34adddb9-8742-419f-9107-acfa6bcdc7a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658136866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.2658136866
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1366317626
Short name T173
Test name
Test status
Simulation time 119979158 ps
CPU time 1.66 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204516 kb
Host smart-b52a76cc-eb08-4fa5-85fc-a6a46ca8526b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366317626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1366317626
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.3222118510
Short name T176
Test name
Test status
Simulation time 82183540 ps
CPU time 0.98 seconds
Started Jun 26 04:50:48 PM PDT 24
Finished Jun 26 04:50:50 PM PDT 24
Peak memory 204356 kb
Host smart-bc528297-8f7f-47e2-91de-9f2bc8f3be1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222118510 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.3222118510
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.778527697
Short name T196
Test name
Test status
Simulation time 24161478 ps
CPU time 0.82 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204284 kb
Host smart-a839912f-159e-488d-bb9d-33684e5d396b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778527697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.778527697
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.22704595
Short name T1579
Test name
Test status
Simulation time 29779996 ps
CPU time 0.7 seconds
Started Jun 26 04:50:47 PM PDT 24
Finished Jun 26 04:50:49 PM PDT 24
Peak memory 204312 kb
Host smart-5b36ac6f-5ce6-4925-9512-bea2696b746f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22704595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.22704595
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2026791895
Short name T1500
Test name
Test status
Simulation time 33518726 ps
CPU time 0.9 seconds
Started Jun 26 04:50:45 PM PDT 24
Finished Jun 26 04:50:47 PM PDT 24
Peak memory 204284 kb
Host smart-3a977177-ed98-41c2-afad-305fa8e04831
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026791895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2026791895
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2740728281
Short name T1521
Test name
Test status
Simulation time 298942890 ps
CPU time 1.64 seconds
Started Jun 26 04:50:46 PM PDT 24
Finished Jun 26 04:50:49 PM PDT 24
Peak memory 204564 kb
Host smart-37d002b3-ebed-4819-bcbe-9ad3948b47be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740728281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2740728281
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1305528428
Short name T185
Test name
Test status
Simulation time 2084215389 ps
CPU time 2.3 seconds
Started Jun 26 04:50:45 PM PDT 24
Finished Jun 26 04:50:48 PM PDT 24
Peak memory 204452 kb
Host smart-57ff631b-68db-4687-9478-647877a0deb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305528428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1305528428
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2058362883
Short name T1534
Test name
Test status
Simulation time 57655793 ps
CPU time 0.93 seconds
Started Jun 26 04:50:56 PM PDT 24
Finished Jun 26 04:51:00 PM PDT 24
Peak memory 204412 kb
Host smart-909d74ab-9d07-48d8-8e95-4b7170247eb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058362883 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2058362883
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.3139486470
Short name T1515
Test name
Test status
Simulation time 38435827 ps
CPU time 0.69 seconds
Started Jun 26 04:50:52 PM PDT 24
Finished Jun 26 04:50:54 PM PDT 24
Peak memory 204376 kb
Host smart-4af02243-b623-405c-97ff-56db4cf649ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139486470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.3139486470
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.1917578210
Short name T1540
Test name
Test status
Simulation time 29432916 ps
CPU time 0.69 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:56 PM PDT 24
Peak memory 204308 kb
Host smart-445f7a76-226f-49f9-b6e0-daaaeea9e653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917578210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.1917578210
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3448619017
Short name T1513
Test name
Test status
Simulation time 35322122 ps
CPU time 0.92 seconds
Started Jun 26 04:50:53 PM PDT 24
Finished Jun 26 04:50:55 PM PDT 24
Peak memory 204316 kb
Host smart-abd34f7c-83f0-4d2b-b934-9433d7490730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448619017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3448619017
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1281661919
Short name T178
Test name
Test status
Simulation time 94138257 ps
CPU time 2.27 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204400 kb
Host smart-b45b4f93-ff85-484a-83a2-267612678af6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281661919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1281661919
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.1102282775
Short name T1576
Test name
Test status
Simulation time 43048848 ps
CPU time 0.84 seconds
Started Jun 26 04:50:56 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204464 kb
Host smart-1a38ff8b-fbbe-4466-9257-c59d4eab0899
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102282775 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.1102282775
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.953643853
Short name T1587
Test name
Test status
Simulation time 34748219 ps
CPU time 0.69 seconds
Started Jun 26 04:50:52 PM PDT 24
Finished Jun 26 04:50:54 PM PDT 24
Peak memory 204420 kb
Host smart-046a487c-24f6-436e-9e5c-247d6e90b48b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953643853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.953643853
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3504613583
Short name T1538
Test name
Test status
Simulation time 33445359 ps
CPU time 0.69 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:57 PM PDT 24
Peak memory 204208 kb
Host smart-83ce1747-00dc-4657-b99a-12d5be07f5f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504613583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3504613583
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2628219786
Short name T88
Test name
Test status
Simulation time 287357485 ps
CPU time 1.25 seconds
Started Jun 26 04:50:53 PM PDT 24
Finished Jun 26 04:50:56 PM PDT 24
Peak memory 204468 kb
Host smart-6ad9d540-4e70-4235-95a5-7ff08acb7303
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628219786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2628219786
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3025027225
Short name T86
Test name
Test status
Simulation time 160155701 ps
CPU time 2.78 seconds
Started Jun 26 04:50:55 PM PDT 24
Finished Jun 26 04:51:01 PM PDT 24
Peak memory 212804 kb
Host smart-3d43140f-2395-4527-a2e1-383f21a4c33f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025027225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3025027225
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.33571816
Short name T1525
Test name
Test status
Simulation time 30602204 ps
CPU time 1.31 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:57 PM PDT 24
Peak memory 204640 kb
Host smart-c4978610-ecc5-4072-8271-941c3e361b38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33571816 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.33571816
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.3793787951
Short name T1537
Test name
Test status
Simulation time 55990346 ps
CPU time 0.86 seconds
Started Jun 26 04:50:56 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204424 kb
Host smart-663db617-c7b5-48d2-a22d-bfb3227237f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793787951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.3793787951
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.671112411
Short name T1475
Test name
Test status
Simulation time 37389181 ps
CPU time 0.71 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:56 PM PDT 24
Peak memory 204204 kb
Host smart-f4b3af4b-4d49-4a0b-8206-33f6c8130202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671112411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.671112411
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.1674757003
Short name T93
Test name
Test status
Simulation time 280192585 ps
CPU time 1.37 seconds
Started Jun 26 04:50:53 PM PDT 24
Finished Jun 26 04:50:56 PM PDT 24
Peak memory 204432 kb
Host smart-3dd86aad-a21b-4632-bc49-bb87305fc569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674757003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.1674757003
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1549067840
Short name T1533
Test name
Test status
Simulation time 61548773 ps
CPU time 1.48 seconds
Started Jun 26 04:50:55 PM PDT 24
Finished Jun 26 04:51:00 PM PDT 24
Peak memory 204528 kb
Host smart-2c09514b-fcd5-4ca1-b9c5-5c92c555d034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549067840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1549067840
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.185432234
Short name T1509
Test name
Test status
Simulation time 157133264 ps
CPU time 2.44 seconds
Started Jun 26 04:50:53 PM PDT 24
Finished Jun 26 04:50:56 PM PDT 24
Peak memory 204504 kb
Host smart-a746d724-df7a-417b-b71c-507b8349130b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185432234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.185432234
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.586499318
Short name T1497
Test name
Test status
Simulation time 32257883 ps
CPU time 0.9 seconds
Started Jun 26 04:50:53 PM PDT 24
Finished Jun 26 04:50:55 PM PDT 24
Peak memory 204416 kb
Host smart-c0896add-d95f-4844-b66b-da2829f2d745
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586499318 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.586499318
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.2569132054
Short name T1564
Test name
Test status
Simulation time 23315366 ps
CPU time 0.73 seconds
Started Jun 26 04:50:53 PM PDT 24
Finished Jun 26 04:50:55 PM PDT 24
Peak memory 204296 kb
Host smart-63f1312d-bbbe-40ff-8016-6fd8e380a1cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569132054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.2569132054
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.4230713851
Short name T1484
Test name
Test status
Simulation time 47175001 ps
CPU time 0.64 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:57 PM PDT 24
Peak memory 204244 kb
Host smart-9a1f224f-fbfe-4a43-b23f-50104efdb800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230713851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.4230713851
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3963545650
Short name T209
Test name
Test status
Simulation time 25751119 ps
CPU time 0.94 seconds
Started Jun 26 04:50:52 PM PDT 24
Finished Jun 26 04:50:54 PM PDT 24
Peak memory 204416 kb
Host smart-62cb5f17-ec8e-4bd7-b9ee-be83837fc841
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963545650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3963545650
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.198636607
Short name T1545
Test name
Test status
Simulation time 85840823 ps
CPU time 1.78 seconds
Started Jun 26 04:50:53 PM PDT 24
Finished Jun 26 04:50:56 PM PDT 24
Peak memory 204488 kb
Host smart-72aa61ff-2f70-42cf-a4c8-6ac12ccda8aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198636607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.198636607
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.4169997806
Short name T1529
Test name
Test status
Simulation time 498142134 ps
CPU time 2.51 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204468 kb
Host smart-636a3b22-c935-4b75-b119-d28cbdaaa754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169997806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.4169997806
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.2862975707
Short name T1588
Test name
Test status
Simulation time 27436807 ps
CPU time 1.07 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:57 PM PDT 24
Peak memory 204524 kb
Host smart-3e545385-88f9-4101-a7fd-feec03828749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862975707 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.2862975707
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3648140824
Short name T1571
Test name
Test status
Simulation time 131208798 ps
CPU time 0.78 seconds
Started Jun 26 04:50:56 PM PDT 24
Finished Jun 26 04:51:00 PM PDT 24
Peak memory 204340 kb
Host smart-71cbc495-d360-4028-a4ec-388f22309d65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648140824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3648140824
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.273006443
Short name T1589
Test name
Test status
Simulation time 18480896 ps
CPU time 0.72 seconds
Started Jun 26 04:50:55 PM PDT 24
Finished Jun 26 04:50:58 PM PDT 24
Peak memory 204300 kb
Host smart-18b6e07e-847a-45f2-96f9-27ff8722d59e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273006443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.273006443
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4037146805
Short name T1516
Test name
Test status
Simulation time 146539160 ps
CPU time 1.17 seconds
Started Jun 26 04:50:56 PM PDT 24
Finished Jun 26 04:51:00 PM PDT 24
Peak memory 204484 kb
Host smart-445d4716-1a50-44e2-8ec4-f144b93c46d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037146805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.4037146805
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.1128429761
Short name T1553
Test name
Test status
Simulation time 96775879 ps
CPU time 1.42 seconds
Started Jun 26 04:50:55 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204596 kb
Host smart-cdfdb06e-5b0f-4160-8840-74c5b2b24d16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128429761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.1128429761
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2277355559
Short name T175
Test name
Test status
Simulation time 244148290 ps
CPU time 2.37 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204492 kb
Host smart-6dbe4323-62e6-4e7e-b42c-7b2070615d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277355559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2277355559
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.209894669
Short name T1502
Test name
Test status
Simulation time 42312938 ps
CPU time 1.08 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:58 PM PDT 24
Peak memory 204572 kb
Host smart-e95154fa-a9ba-4329-9546-f2ab762662a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209894669 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.209894669
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2927688499
Short name T203
Test name
Test status
Simulation time 96290108 ps
CPU time 0.71 seconds
Started Jun 26 04:50:56 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204424 kb
Host smart-db86a0d8-a4dd-438a-94f2-7db0e8857381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927688499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2927688499
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.3242034200
Short name T1550
Test name
Test status
Simulation time 15440680 ps
CPU time 0.65 seconds
Started Jun 26 04:50:53 PM PDT 24
Finished Jun 26 04:50:55 PM PDT 24
Peak memory 204220 kb
Host smart-0633f63f-076e-4aad-92aa-5e8fb426f796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242034200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.3242034200
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.2013956090
Short name T1492
Test name
Test status
Simulation time 54643424 ps
CPU time 0.8 seconds
Started Jun 26 04:50:52 PM PDT 24
Finished Jun 26 04:50:53 PM PDT 24
Peak memory 204388 kb
Host smart-726f04fe-e26e-425a-a4b4-418f76a2052f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013956090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.2013956090
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.43699352
Short name T89
Test name
Test status
Simulation time 302209105 ps
CPU time 1.75 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204572 kb
Host smart-2a21ef2b-f8ea-4f5e-b7b1-39bf6d2e4ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43699352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.43699352
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1896037545
Short name T1506
Test name
Test status
Simulation time 442924584 ps
CPU time 2.27 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:58 PM PDT 24
Peak memory 204484 kb
Host smart-84f292ac-b461-40fe-a3c7-ce04e028128e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896037545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1896037545
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.3682830179
Short name T90
Test name
Test status
Simulation time 128194482 ps
CPU time 0.98 seconds
Started Jun 26 04:50:55 PM PDT 24
Finished Jun 26 04:50:58 PM PDT 24
Peak memory 204492 kb
Host smart-3632704d-3556-4f52-8040-41bd7d40c37f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682830179 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.3682830179
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.109086702
Short name T1491
Test name
Test status
Simulation time 144279400 ps
CPU time 0.7 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:56 PM PDT 24
Peak memory 204364 kb
Host smart-620ea5d0-4d37-4097-9755-66c9c1ec92c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109086702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.109086702
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.2955909339
Short name T1481
Test name
Test status
Simulation time 39832519 ps
CPU time 0.66 seconds
Started Jun 26 04:50:55 PM PDT 24
Finished Jun 26 04:50:59 PM PDT 24
Peak memory 204280 kb
Host smart-39c153f7-acc7-4b95-b17d-4c8239cb9dfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955909339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.2955909339
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.591628944
Short name T1504
Test name
Test status
Simulation time 23490494 ps
CPU time 0.91 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:58 PM PDT 24
Peak memory 204320 kb
Host smart-520f1ad2-3565-4b2a-a188-67a633c5f639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591628944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_ou
tstanding.591628944
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.632541699
Short name T95
Test name
Test status
Simulation time 121427341 ps
CPU time 2.43 seconds
Started Jun 26 04:50:56 PM PDT 24
Finished Jun 26 04:51:01 PM PDT 24
Peak memory 204596 kb
Host smart-3c546c40-a830-459f-9af3-30ba896d23ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632541699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.632541699
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.2418321656
Short name T183
Test name
Test status
Simulation time 159486569 ps
CPU time 2.43 seconds
Started Jun 26 04:50:55 PM PDT 24
Finished Jun 26 04:51:01 PM PDT 24
Peak memory 204500 kb
Host smart-ff55e5d7-57a1-43e0-a77b-78a5aaea6a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418321656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.2418321656
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.77894788
Short name T205
Test name
Test status
Simulation time 45708731 ps
CPU time 1.97 seconds
Started Jun 26 04:50:26 PM PDT 24
Finished Jun 26 04:50:29 PM PDT 24
Peak memory 204460 kb
Host smart-0b3dc0c8-aff6-4c87-8e53-fcaa509dd5a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77894788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.77894788
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.4000348224
Short name T1585
Test name
Test status
Simulation time 328628186 ps
CPU time 3.41 seconds
Started Jun 26 04:50:28 PM PDT 24
Finished Jun 26 04:50:33 PM PDT 24
Peak memory 204476 kb
Host smart-72a78d41-90a0-4c36-8654-e80ed0091cfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000348224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.4000348224
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2057185112
Short name T1532
Test name
Test status
Simulation time 69209186 ps
CPU time 0.81 seconds
Started Jun 26 04:50:26 PM PDT 24
Finished Jun 26 04:50:29 PM PDT 24
Peak memory 204428 kb
Host smart-75d06f86-f909-4a45-b95b-3f81d9a288af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057185112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2057185112
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.1339630499
Short name T1542
Test name
Test status
Simulation time 97922377 ps
CPU time 1.25 seconds
Started Jun 26 04:50:29 PM PDT 24
Finished Jun 26 04:50:31 PM PDT 24
Peak memory 204516 kb
Host smart-f73ab15d-6f05-4cc7-a5b9-1f5ce3be568f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339630499 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.1339630499
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.1259493190
Short name T1584
Test name
Test status
Simulation time 18402216 ps
CPU time 0.71 seconds
Started Jun 26 04:50:28 PM PDT 24
Finished Jun 26 04:50:30 PM PDT 24
Peak memory 204348 kb
Host smart-03e2a2df-8111-4129-b0ea-5b6795815ac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259493190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.1259493190
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.4147787458
Short name T1583
Test name
Test status
Simulation time 60196080 ps
CPU time 0.66 seconds
Started Jun 26 04:50:25 PM PDT 24
Finished Jun 26 04:50:27 PM PDT 24
Peak memory 204324 kb
Host smart-2467a613-763c-4885-981e-7489038ccac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147787458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.4147787458
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.3650277241
Short name T134
Test name
Test status
Simulation time 35412564 ps
CPU time 0.86 seconds
Started Jun 26 04:50:25 PM PDT 24
Finished Jun 26 04:50:27 PM PDT 24
Peak memory 204332 kb
Host smart-6240326b-5aa1-4afd-be7a-bc138ed0f0b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650277241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.3650277241
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1862435106
Short name T1552
Test name
Test status
Simulation time 183684466 ps
CPU time 2.46 seconds
Started Jun 26 04:50:27 PM PDT 24
Finished Jun 26 04:50:31 PM PDT 24
Peak memory 204604 kb
Host smart-baf7ae3b-f683-49e1-86f4-981b3efe5684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862435106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1862435106
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.995211887
Short name T186
Test name
Test status
Simulation time 51247470 ps
CPU time 1.46 seconds
Started Jun 26 04:50:30 PM PDT 24
Finished Jun 26 04:50:33 PM PDT 24
Peak memory 204524 kb
Host smart-7fa01c19-4d38-426b-a8f1-f8eca49a16bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995211887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.995211887
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.997281978
Short name T1573
Test name
Test status
Simulation time 25361243 ps
CPU time 0.67 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:02 PM PDT 24
Peak memory 204312 kb
Host smart-57b4a1cd-ef7b-46ad-8042-7bfa162fbd1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997281978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.997281978
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.1841224124
Short name T1586
Test name
Test status
Simulation time 22045110 ps
CPU time 0.77 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:03 PM PDT 24
Peak memory 204328 kb
Host smart-06e9a4a7-9f62-40ca-baa0-aaa970337836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841224124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1841224124
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2139376399
Short name T1536
Test name
Test status
Simulation time 32174270 ps
CPU time 0.69 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204292 kb
Host smart-753f854f-32ed-46e2-a2f6-a596581792cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139376399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2139376399
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.1689530607
Short name T1489
Test name
Test status
Simulation time 16695355 ps
CPU time 0.72 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204248 kb
Host smart-f0e4109c-7093-4fef-af47-5603cfd392b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689530607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.1689530607
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.2075762115
Short name T1476
Test name
Test status
Simulation time 31836218 ps
CPU time 0.67 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204260 kb
Host smart-8daf635f-0cfc-4f33-94b7-15a6200b6558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075762115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.2075762115
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3318211485
Short name T1483
Test name
Test status
Simulation time 49821067 ps
CPU time 0.69 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:02 PM PDT 24
Peak memory 204304 kb
Host smart-5a628856-3ee6-48a7-86fb-3e252982ea9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318211485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3318211485
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.291941980
Short name T1501
Test name
Test status
Simulation time 75738610 ps
CPU time 0.68 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:03 PM PDT 24
Peak memory 204324 kb
Host smart-3c328a6c-98af-478d-b3b0-2f8beafa5bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291941980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.291941980
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.966579757
Short name T1480
Test name
Test status
Simulation time 15155295 ps
CPU time 0.73 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:05 PM PDT 24
Peak memory 204260 kb
Host smart-a1c21fbb-5311-4ff2-a894-d79c5ed2c904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966579757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.966579757
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.298673916
Short name T1555
Test name
Test status
Simulation time 98554892 ps
CPU time 0.7 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204288 kb
Host smart-cc988dae-11a1-40dc-99e3-038590b31eb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298673916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.298673916
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.4099036316
Short name T1487
Test name
Test status
Simulation time 22067139 ps
CPU time 0.7 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:12 PM PDT 24
Peak memory 204316 kb
Host smart-2d828a11-7383-4b94-a822-d4dd43de9e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099036316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4099036316
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2595478101
Short name T208
Test name
Test status
Simulation time 268595587 ps
CPU time 1.4 seconds
Started Jun 26 04:50:34 PM PDT 24
Finished Jun 26 04:50:37 PM PDT 24
Peak memory 204528 kb
Host smart-bccc9338-7901-412d-8592-ba24f2fb8d4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595478101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2595478101
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3053422085
Short name T1577
Test name
Test status
Simulation time 270438402 ps
CPU time 2.94 seconds
Started Jun 26 04:50:44 PM PDT 24
Finished Jun 26 04:50:48 PM PDT 24
Peak memory 204488 kb
Host smart-a4efd5aa-4ae5-4487-bdf8-f4bdbe6c7286
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053422085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3053422085
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1070475267
Short name T207
Test name
Test status
Simulation time 36445065 ps
CPU time 0.77 seconds
Started Jun 26 04:50:38 PM PDT 24
Finished Jun 26 04:50:39 PM PDT 24
Peak memory 204356 kb
Host smart-596f045e-9a8e-4970-bd9b-c0cc0fddefa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070475267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1070475267
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3873763878
Short name T1503
Test name
Test status
Simulation time 52698066 ps
CPU time 0.87 seconds
Started Jun 26 04:50:32 PM PDT 24
Finished Jun 26 04:50:34 PM PDT 24
Peak memory 204372 kb
Host smart-d94f8770-53e5-4814-9e9e-0776359947f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873763878 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3873763878
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.568148875
Short name T1559
Test name
Test status
Simulation time 28227552 ps
CPU time 0.85 seconds
Started Jun 26 04:50:36 PM PDT 24
Finished Jun 26 04:50:37 PM PDT 24
Peak memory 204348 kb
Host smart-54d2efc6-8940-46c9-99c6-1da457e85f2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568148875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.568148875
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.2949981714
Short name T1539
Test name
Test status
Simulation time 22019793 ps
CPU time 0.7 seconds
Started Jun 26 04:50:26 PM PDT 24
Finished Jun 26 04:50:29 PM PDT 24
Peak memory 204324 kb
Host smart-a97253e6-2c95-4a77-8999-cdede35c1057
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949981714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.2949981714
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1296170669
Short name T1505
Test name
Test status
Simulation time 134890041 ps
CPU time 0.95 seconds
Started Jun 26 04:50:38 PM PDT 24
Finished Jun 26 04:50:40 PM PDT 24
Peak memory 204380 kb
Host smart-7716950e-5c48-452e-a74c-1a3499bab42e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296170669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1296170669
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.1254378077
Short name T1520
Test name
Test status
Simulation time 136293947 ps
CPU time 2.41 seconds
Started Jun 26 04:50:27 PM PDT 24
Finished Jun 26 04:50:31 PM PDT 24
Peak memory 204528 kb
Host smart-72b032fa-f28b-4a50-86ab-175e0a27de10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254378077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.1254378077
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.1982077695
Short name T1543
Test name
Test status
Simulation time 40559591 ps
CPU time 0.7 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204240 kb
Host smart-016a853f-fd79-49e9-be63-00fba82dbeef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982077695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.1982077695
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.3028377237
Short name T1488
Test name
Test status
Simulation time 24626003 ps
CPU time 0.67 seconds
Started Jun 26 04:51:03 PM PDT 24
Finished Jun 26 04:51:07 PM PDT 24
Peak memory 204148 kb
Host smart-57e4cd2f-9c60-4b87-bfb2-66d4306ab03f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028377237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.3028377237
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2901033428
Short name T1490
Test name
Test status
Simulation time 50531092 ps
CPU time 0.68 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204232 kb
Host smart-5b5eb643-754b-4a33-b112-f6e9a38b5c70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901033428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2901033428
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.2558314723
Short name T1499
Test name
Test status
Simulation time 15399013 ps
CPU time 0.66 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204292 kb
Host smart-0f878cb7-4d7d-4b0e-b1ce-8db2bf175055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558314723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.2558314723
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.4045961304
Short name T1563
Test name
Test status
Simulation time 15870129 ps
CPU time 0.65 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204328 kb
Host smart-8b259430-9a80-4c50-86e0-01601ccd6c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045961304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.4045961304
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.4278928174
Short name T1544
Test name
Test status
Simulation time 26071322 ps
CPU time 0.72 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204256 kb
Host smart-12bcc829-8dcb-4196-9488-d41957b84594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278928174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.4278928174
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3244906148
Short name T1479
Test name
Test status
Simulation time 50793731 ps
CPU time 0.67 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:05 PM PDT 24
Peak memory 204324 kb
Host smart-682f14c5-4c82-474f-aa2e-12312f413cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244906148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3244906148
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1534748515
Short name T1511
Test name
Test status
Simulation time 26727886 ps
CPU time 0.7 seconds
Started Jun 26 04:51:03 PM PDT 24
Finished Jun 26 04:51:07 PM PDT 24
Peak memory 204248 kb
Host smart-6b0c6951-07ba-4ec7-a648-19ed0399224e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534748515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1534748515
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2282055891
Short name T1574
Test name
Test status
Simulation time 41143928 ps
CPU time 0.68 seconds
Started Jun 26 04:51:03 PM PDT 24
Finished Jun 26 04:51:07 PM PDT 24
Peak memory 204184 kb
Host smart-6165f6f0-4224-48a9-9435-c76e6e611062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282055891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2282055891
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.544942734
Short name T1485
Test name
Test status
Simulation time 21124295 ps
CPU time 0.73 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:02 PM PDT 24
Peak memory 204228 kb
Host smart-46915417-87df-4184-b5d1-19e09d3feb71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544942734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.544942734
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1266527558
Short name T200
Test name
Test status
Simulation time 159212135 ps
CPU time 1.89 seconds
Started Jun 26 04:50:40 PM PDT 24
Finished Jun 26 04:50:44 PM PDT 24
Peak memory 204476 kb
Host smart-6370c96d-9f3a-44c0-9aeb-7dcf41b8e09d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266527558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1266527558
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.418099639
Short name T204
Test name
Test status
Simulation time 52043261 ps
CPU time 0.76 seconds
Started Jun 26 04:50:39 PM PDT 24
Finished Jun 26 04:50:40 PM PDT 24
Peak memory 204316 kb
Host smart-9d79f87e-7d29-4dd0-9814-ed6115ad4a90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418099639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.418099639
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.1290502830
Short name T193
Test name
Test status
Simulation time 36748427 ps
CPU time 1.04 seconds
Started Jun 26 04:50:42 PM PDT 24
Finished Jun 26 04:50:44 PM PDT 24
Peak memory 204456 kb
Host smart-697bd0ad-d27f-4d34-b61f-09857debf4f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290502830 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.1290502830
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.656973086
Short name T1556
Test name
Test status
Simulation time 26680511 ps
CPU time 0.84 seconds
Started Jun 26 04:50:45 PM PDT 24
Finished Jun 26 04:50:46 PM PDT 24
Peak memory 204304 kb
Host smart-d9f6a6ee-be2b-4b4e-b499-728208690095
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656973086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.656973086
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.110288006
Short name T1493
Test name
Test status
Simulation time 49454622 ps
CPU time 0.67 seconds
Started Jun 26 04:50:34 PM PDT 24
Finished Jun 26 04:50:36 PM PDT 24
Peak memory 204332 kb
Host smart-cb458c3c-dfa0-44df-ad28-56c447687c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110288006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.110288006
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1640845078
Short name T1546
Test name
Test status
Simulation time 51407998 ps
CPU time 1.14 seconds
Started Jun 26 04:50:40 PM PDT 24
Finished Jun 26 04:50:42 PM PDT 24
Peak memory 204364 kb
Host smart-258be84b-5562-4d4b-a699-30eaaa5b94de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640845078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.1640845078
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2437616197
Short name T1549
Test name
Test status
Simulation time 94211571 ps
CPU time 1.4 seconds
Started Jun 26 04:50:34 PM PDT 24
Finished Jun 26 04:50:37 PM PDT 24
Peak memory 204612 kb
Host smart-59fe8bb2-b15f-42d2-a949-bd10608ddfc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437616197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2437616197
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.236516229
Short name T181
Test name
Test status
Simulation time 1312739824 ps
CPU time 2.36 seconds
Started Jun 26 04:50:42 PM PDT 24
Finished Jun 26 04:50:45 PM PDT 24
Peak memory 204800 kb
Host smart-203d18de-c849-4751-8cb9-a74c0d89fe00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236516229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.236516229
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3078891910
Short name T1486
Test name
Test status
Simulation time 23039943 ps
CPU time 0.69 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204200 kb
Host smart-e58bde10-03cc-4982-99ef-de7e9291cade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078891910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3078891910
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2120994337
Short name T1558
Test name
Test status
Simulation time 34420835 ps
CPU time 0.67 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204324 kb
Host smart-8f1a1114-0ad3-48c3-913a-8bacb2102fa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120994337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2120994337
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.464943776
Short name T1570
Test name
Test status
Simulation time 69074216 ps
CPU time 0.69 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204324 kb
Host smart-5b1daa6c-e428-4b52-99f3-f89b2bd966f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464943776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.464943776
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.1955421947
Short name T1524
Test name
Test status
Simulation time 15202583 ps
CPU time 0.66 seconds
Started Jun 26 04:51:03 PM PDT 24
Finished Jun 26 04:51:07 PM PDT 24
Peak memory 204236 kb
Host smart-300f0d15-2693-4b60-aaf9-b558afb92a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955421947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.1955421947
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.817753341
Short name T1541
Test name
Test status
Simulation time 18618083 ps
CPU time 0.64 seconds
Started Jun 26 04:51:01 PM PDT 24
Finished Jun 26 04:51:03 PM PDT 24
Peak memory 204300 kb
Host smart-536251e3-3d57-4415-93d0-b7345c86920b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817753341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.817753341
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.3971028197
Short name T1507
Test name
Test status
Simulation time 17916385 ps
CPU time 0.75 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204328 kb
Host smart-82284300-fb86-4598-854f-cd29019fca5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971028197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3971028197
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.394316271
Short name T1578
Test name
Test status
Simulation time 30971427 ps
CPU time 0.72 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204576 kb
Host smart-b01a59b1-8971-423a-901c-8794a7cab047
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394316271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.394316271
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1768651820
Short name T1557
Test name
Test status
Simulation time 55477256 ps
CPU time 0.65 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:02 PM PDT 24
Peak memory 204256 kb
Host smart-fbc01a9c-5ff8-464b-882c-9624250a552a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768651820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1768651820
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.3499317137
Short name T1478
Test name
Test status
Simulation time 19576217 ps
CPU time 0.68 seconds
Started Jun 26 04:51:09 PM PDT 24
Finished Jun 26 04:51:11 PM PDT 24
Peak memory 204328 kb
Host smart-3c7afe13-3dde-4eb0-a674-0f17a4d5582d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499317137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.3499317137
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2687366964
Short name T116
Test name
Test status
Simulation time 37483852 ps
CPU time 0.69 seconds
Started Jun 26 04:51:02 PM PDT 24
Finished Jun 26 04:51:06 PM PDT 24
Peak memory 204292 kb
Host smart-8aa1132d-bf6d-4d04-afad-fcf88734c9b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687366964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2687366964
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3821946775
Short name T1527
Test name
Test status
Simulation time 39053231 ps
CPU time 0.8 seconds
Started Jun 26 04:50:41 PM PDT 24
Finished Jun 26 04:50:43 PM PDT 24
Peak memory 204168 kb
Host smart-6fa82467-3719-4fde-bfe3-832e35bac56a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821946775 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3821946775
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1725773295
Short name T1547
Test name
Test status
Simulation time 26390325 ps
CPU time 0.72 seconds
Started Jun 26 04:50:39 PM PDT 24
Finished Jun 26 04:50:41 PM PDT 24
Peak memory 204320 kb
Host smart-7c39f00d-8dda-4228-b518-f4ed42563491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725773295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1725773295
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.1306626049
Short name T210
Test name
Test status
Simulation time 29034114 ps
CPU time 1.19 seconds
Started Jun 26 04:50:40 PM PDT 24
Finished Jun 26 04:50:42 PM PDT 24
Peak memory 204532 kb
Host smart-331e8d1a-d8b6-4605-9b0f-eb1ef8202970
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306626049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.1306626049
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.620857889
Short name T1523
Test name
Test status
Simulation time 46291464 ps
CPU time 1.28 seconds
Started Jun 26 04:50:44 PM PDT 24
Finished Jun 26 04:50:47 PM PDT 24
Peak memory 204544 kb
Host smart-420d7d6c-09de-4952-b859-f432ab16a10f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620857889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.620857889
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.1920212379
Short name T1560
Test name
Test status
Simulation time 33837200 ps
CPU time 1.22 seconds
Started Jun 26 04:50:41 PM PDT 24
Finished Jun 26 04:50:43 PM PDT 24
Peak memory 204280 kb
Host smart-555ed51c-a5b1-4940-b4fb-5114be3d52be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920212379 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.1920212379
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.203893641
Short name T201
Test name
Test status
Simulation time 25969318 ps
CPU time 0.82 seconds
Started Jun 26 04:50:43 PM PDT 24
Finished Jun 26 04:50:45 PM PDT 24
Peak memory 204288 kb
Host smart-a56ca0cd-a1b6-40ed-85f9-087c52183141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203893641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.203893641
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.2806446819
Short name T1496
Test name
Test status
Simulation time 18009515 ps
CPU time 0.67 seconds
Started Jun 26 04:50:43 PM PDT 24
Finished Jun 26 04:50:45 PM PDT 24
Peak memory 204244 kb
Host smart-70a16c9d-02d9-469d-a9a3-55c3fc5f982b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806446819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.2806446819
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.120778165
Short name T1512
Test name
Test status
Simulation time 20925181 ps
CPU time 0.82 seconds
Started Jun 26 04:50:38 PM PDT 24
Finished Jun 26 04:50:40 PM PDT 24
Peak memory 204408 kb
Host smart-52e6d0f1-ec15-4dca-a788-e5e3a06d42bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120778165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.120778165
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1919635266
Short name T187
Test name
Test status
Simulation time 98550436 ps
CPU time 1.44 seconds
Started Jun 26 04:50:40 PM PDT 24
Finished Jun 26 04:50:43 PM PDT 24
Peak memory 204528 kb
Host smart-7d9c139e-b76a-4f4d-aaa0-b6103b39f772
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919635266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1919635266
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2514272442
Short name T182
Test name
Test status
Simulation time 338225045 ps
CPU time 2.53 seconds
Started Jun 26 04:50:42 PM PDT 24
Finished Jun 26 04:50:45 PM PDT 24
Peak memory 204372 kb
Host smart-329dd8e2-ed9d-4567-ac01-5e7212b91be6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514272442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2514272442
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2479002819
Short name T135
Test name
Test status
Simulation time 72146600 ps
CPU time 0.8 seconds
Started Jun 26 04:50:51 PM PDT 24
Finished Jun 26 04:50:52 PM PDT 24
Peak memory 204464 kb
Host smart-0508b265-ca5c-4236-b6f6-a514f844ed05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479002819 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2479002819
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.2952773808
Short name T1551
Test name
Test status
Simulation time 56791118 ps
CPU time 0.68 seconds
Started Jun 26 04:50:47 PM PDT 24
Finished Jun 26 04:50:49 PM PDT 24
Peak memory 204280 kb
Host smart-52c70831-8118-419f-a91f-a574ce6438de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952773808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.2952773808
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.1849144308
Short name T1580
Test name
Test status
Simulation time 28697394 ps
CPU time 0.64 seconds
Started Jun 26 04:50:43 PM PDT 24
Finished Jun 26 04:50:45 PM PDT 24
Peak memory 204256 kb
Host smart-04e19da3-8477-4126-ba12-76eb604f1e36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849144308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.1849144308
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1247773017
Short name T1526
Test name
Test status
Simulation time 23946229 ps
CPU time 0.86 seconds
Started Jun 26 04:50:48 PM PDT 24
Finished Jun 26 04:50:50 PM PDT 24
Peak memory 204400 kb
Host smart-39dcd279-c075-4e4d-8b02-04b268e5684d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247773017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.1247773017
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3237523843
Short name T132
Test name
Test status
Simulation time 179615271 ps
CPU time 1.24 seconds
Started Jun 26 04:50:48 PM PDT 24
Finished Jun 26 04:50:51 PM PDT 24
Peak memory 204448 kb
Host smart-d914f937-574e-4698-8b5d-74dee7cd4035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237523843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3237523843
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1226012174
Short name T250
Test name
Test status
Simulation time 177438873 ps
CPU time 1.43 seconds
Started Jun 26 04:50:41 PM PDT 24
Finished Jun 26 04:50:44 PM PDT 24
Peak memory 204436 kb
Host smart-b3db538d-0c0d-43e8-afe1-0f1d02b0a28a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226012174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1226012174
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.1724889395
Short name T1554
Test name
Test status
Simulation time 387528766 ps
CPU time 0.93 seconds
Started Jun 26 04:50:54 PM PDT 24
Finished Jun 26 04:50:57 PM PDT 24
Peak memory 204344 kb
Host smart-1e26d56e-04bf-4bbd-b528-955bc4bf5047
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724889395 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.1724889395
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.297386424
Short name T1510
Test name
Test status
Simulation time 25767450 ps
CPU time 0.78 seconds
Started Jun 26 04:50:47 PM PDT 24
Finished Jun 26 04:50:48 PM PDT 24
Peak memory 204388 kb
Host smart-af1d2b9d-e78d-442e-a1f8-4fe45792b922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297386424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.297386424
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1542514260
Short name T1517
Test name
Test status
Simulation time 41799389 ps
CPU time 0.64 seconds
Started Jun 26 04:50:48 PM PDT 24
Finished Jun 26 04:50:50 PM PDT 24
Peak memory 204256 kb
Host smart-a56aede5-ba9f-4a19-9323-b61cdeeb7b70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542514260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1542514260
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.3261722421
Short name T1495
Test name
Test status
Simulation time 21230636 ps
CPU time 0.87 seconds
Started Jun 26 04:51:00 PM PDT 24
Finished Jun 26 04:51:04 PM PDT 24
Peak memory 204280 kb
Host smart-cb06cad4-6f84-4b11-b351-6d9ced9d9174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261722421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.3261722421
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.3484654149
Short name T1535
Test name
Test status
Simulation time 100629974 ps
CPU time 1.37 seconds
Started Jun 26 04:50:45 PM PDT 24
Finished Jun 26 04:50:47 PM PDT 24
Peak memory 204572 kb
Host smart-b2361cab-4a4c-4d80-b80f-bfbeb509dfa8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484654149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.3484654149
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4144292946
Short name T174
Test name
Test status
Simulation time 50008111 ps
CPU time 1.48 seconds
Started Jun 26 04:50:47 PM PDT 24
Finished Jun 26 04:50:50 PM PDT 24
Peak memory 204468 kb
Host smart-92870d59-e1d1-4bf8-a1a4-de3ea7738063
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144292946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.4144292946
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1235467872
Short name T1562
Test name
Test status
Simulation time 518776507 ps
CPU time 0.96 seconds
Started Jun 26 04:50:49 PM PDT 24
Finished Jun 26 04:50:52 PM PDT 24
Peak memory 204344 kb
Host smart-c1b9f14c-fd7c-41db-9608-d32cc60a899a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235467872 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1235467872
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.4185505482
Short name T199
Test name
Test status
Simulation time 19001365 ps
CPU time 0.81 seconds
Started Jun 26 04:50:46 PM PDT 24
Finished Jun 26 04:50:48 PM PDT 24
Peak memory 204380 kb
Host smart-68871dfb-57cf-4fd0-a945-630f3fca8194
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185505482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.4185505482
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.1775460373
Short name T1530
Test name
Test status
Simulation time 17331874 ps
CPU time 0.72 seconds
Started Jun 26 04:50:48 PM PDT 24
Finished Jun 26 04:50:50 PM PDT 24
Peak memory 204188 kb
Host smart-366f7652-b8a2-4985-86ca-4a6b1ef79029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775460373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.1775460373
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.162387963
Short name T1514
Test name
Test status
Simulation time 381705304 ps
CPU time 1.24 seconds
Started Jun 26 04:50:48 PM PDT 24
Finished Jun 26 04:50:50 PM PDT 24
Peak memory 204428 kb
Host smart-d470964e-bb76-4195-bc60-4e54c2ee28a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162387963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out
standing.162387963
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.487058853
Short name T1581
Test name
Test status
Simulation time 254549326 ps
CPU time 1.39 seconds
Started Jun 26 04:50:49 PM PDT 24
Finished Jun 26 04:50:51 PM PDT 24
Peak memory 204496 kb
Host smart-e294d514-3b64-4fee-ade3-cdf70508bcbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487058853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.487058853
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.2739489190
Short name T722
Test name
Test status
Simulation time 29550957 ps
CPU time 0.63 seconds
Started Jun 26 04:55:54 PM PDT 24
Finished Jun 26 04:55:57 PM PDT 24
Peak memory 204428 kb
Host smart-8803c45b-ac6f-49a9-bdf0-f5e0ef6bed20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739489190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.2739489190
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2187295838
Short name T69
Test name
Test status
Simulation time 536668901 ps
CPU time 2.74 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:53 PM PDT 24
Peak memory 227032 kb
Host smart-14089602-8de8-4922-b5aa-1aa2dbbc9ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187295838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2187295838
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3952815060
Short name T425
Test name
Test status
Simulation time 1785997593 ps
CPU time 10.76 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:56:01 PM PDT 24
Peak memory 247696 kb
Host smart-7cfc1516-821c-4e02-a43b-673da67fcbed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952815060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3952815060
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2388448617
Short name T1355
Test name
Test status
Simulation time 8428946903 ps
CPU time 143.15 seconds
Started Jun 26 04:55:54 PM PDT 24
Finished Jun 26 04:58:19 PM PDT 24
Peak memory 729468 kb
Host smart-931a25ba-f7f6-410a-abb7-ccc0fab022a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388448617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2388448617
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.334395934
Short name T733
Test name
Test status
Simulation time 16617540814 ps
CPU time 54.91 seconds
Started Jun 26 04:55:29 PM PDT 24
Finished Jun 26 04:56:31 PM PDT 24
Peak memory 663436 kb
Host smart-c353783f-0b0d-4699-bfd8-4fb79747fcf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334395934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.334395934
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.1578104226
Short name T1146
Test name
Test status
Simulation time 111397865 ps
CPU time 1.05 seconds
Started Jun 26 04:55:32 PM PDT 24
Finished Jun 26 04:55:40 PM PDT 24
Peak memory 204480 kb
Host smart-877e154f-de13-485d-90ce-090e5e5fe0a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578104226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.1578104226
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.3480694468
Short name T529
Test name
Test status
Simulation time 669125605 ps
CPU time 9.01 seconds
Started Jun 26 04:55:40 PM PDT 24
Finished Jun 26 04:55:52 PM PDT 24
Peak memory 234080 kb
Host smart-449adbfc-d55b-433d-8687-b47b4ede1fe6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480694468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
3480694468
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.2516123744
Short name T793
Test name
Test status
Simulation time 3650017441 ps
CPU time 77.19 seconds
Started Jun 26 04:55:38 PM PDT 24
Finished Jun 26 04:56:59 PM PDT 24
Peak memory 1040360 kb
Host smart-d5791287-c399-4afe-b944-3cabbce166b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516123744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.2516123744
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1572926405
Short name T932
Test name
Test status
Simulation time 435632408 ps
CPU time 6.65 seconds
Started Jun 26 04:55:52 PM PDT 24
Finished Jun 26 04:56:01 PM PDT 24
Peak memory 204868 kb
Host smart-412ded6c-3ff7-4b3d-8a1e-624dd2927dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572926405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1572926405
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3900718557
Short name T654
Test name
Test status
Simulation time 4019419460 ps
CPU time 95.97 seconds
Started Jun 26 04:55:46 PM PDT 24
Finished Jun 26 04:57:25 PM PDT 24
Peak memory 387356 kb
Host smart-6e1e42d6-5703-4ba1-8821-78c79d554bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900718557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3900718557
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.2650448325
Short name T1380
Test name
Test status
Simulation time 23799609 ps
CPU time 0.71 seconds
Started Jun 26 04:55:35 PM PDT 24
Finished Jun 26 04:55:41 PM PDT 24
Peak memory 204472 kb
Host smart-a066c2f4-c792-48ab-a1ca-ab66bedcedb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650448325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.2650448325
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.797438815
Short name T296
Test name
Test status
Simulation time 18472121009 ps
CPU time 72.76 seconds
Started Jun 26 04:55:43 PM PDT 24
Finished Jun 26 04:56:58 PM PDT 24
Peak memory 213196 kb
Host smart-5d888382-9c24-4cc3-9012-a9ba7c4fbc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797438815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.797438815
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.338731834
Short name T577
Test name
Test status
Simulation time 356639941 ps
CPU time 7.28 seconds
Started Jun 26 04:55:48 PM PDT 24
Finished Jun 26 04:55:58 PM PDT 24
Peak memory 205132 kb
Host smart-e0a0b416-cb7e-471a-82ba-6502319adede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338731834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.338731834
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1991183515
Short name T920
Test name
Test status
Simulation time 4655022190 ps
CPU time 28.38 seconds
Started Jun 26 04:55:34 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 379896 kb
Host smart-ae797ec4-2768-415c-83ab-72221a211146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991183515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1991183515
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.475294265
Short name T490
Test name
Test status
Simulation time 3265190734 ps
CPU time 9.58 seconds
Started Jun 26 04:55:50 PM PDT 24
Finished Jun 26 04:56:03 PM PDT 24
Peak memory 215516 kb
Host smart-4c974180-bc72-4212-9bad-669fc0e7a9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475294265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.475294265
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1789409719
Short name T926
Test name
Test status
Simulation time 650500223 ps
CPU time 3.41 seconds
Started Jun 26 04:55:46 PM PDT 24
Finished Jun 26 04:55:52 PM PDT 24
Peak memory 212960 kb
Host smart-5ce473e4-c7ec-4f19-9d0e-98b031b7ab46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789409719 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1789409719
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2557260604
Short name T122
Test name
Test status
Simulation time 353006122 ps
CPU time 0.77 seconds
Started Jun 26 04:55:37 PM PDT 24
Finished Jun 26 04:55:42 PM PDT 24
Peak memory 204624 kb
Host smart-295176a7-6849-4608-861b-8d0fbe03c2f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557260604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2557260604
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.4020168345
Short name T896
Test name
Test status
Simulation time 215583165 ps
CPU time 1.3 seconds
Started Jun 26 04:55:58 PM PDT 24
Finished Jun 26 04:56:03 PM PDT 24
Peak memory 204784 kb
Host smart-1d153614-797c-4729-9d06-c1c28ae33e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020168345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.4020168345
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.2561807044
Short name T1257
Test name
Test status
Simulation time 433441493 ps
CPU time 2.3 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:55:50 PM PDT 24
Peak memory 204748 kb
Host smart-1164723a-1ade-45eb-ae06-c64f68b21fd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561807044 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.2561807044
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.602125810
Short name T900
Test name
Test status
Simulation time 141930482 ps
CPU time 1.28 seconds
Started Jun 26 04:55:38 PM PDT 24
Finished Jun 26 04:55:43 PM PDT 24
Peak memory 204548 kb
Host smart-825fabaa-d937-4f13-b700-35c72e6dd2bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602125810 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.602125810
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.2262483184
Short name T717
Test name
Test status
Simulation time 351393064 ps
CPU time 2.52 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:53 PM PDT 24
Peak memory 204876 kb
Host smart-4d4d3eea-9fd0-4dda-92ab-87762a686cd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262483184 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.2262483184
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.941951005
Short name T1299
Test name
Test status
Simulation time 5225472267 ps
CPU time 7.02 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 213712 kb
Host smart-b8e8b9e8-1c67-431c-b30a-895797c8a2e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941951005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_intr_smoke.941951005
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.3110553562
Short name T172
Test name
Test status
Simulation time 23117020919 ps
CPU time 79.45 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:57:21 PM PDT 24
Peak memory 1035064 kb
Host smart-25eaf2dc-585f-4480-9767-b0874bec98c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110553562 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.3110553562
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.3290926953
Short name T504
Test name
Test status
Simulation time 933528839 ps
CPU time 9.02 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:55:56 PM PDT 24
Peak memory 204776 kb
Host smart-fd068878-7009-409b-9535-4a33d6fb0d6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290926953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.3290926953
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.734387556
Short name T455
Test name
Test status
Simulation time 2715037292 ps
CPU time 25.47 seconds
Started Jun 26 04:55:54 PM PDT 24
Finished Jun 26 04:56:21 PM PDT 24
Peak memory 222532 kb
Host smart-ed772384-cbc7-463f-8292-01f8709df18f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734387556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.734387556
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.97897510
Short name T371
Test name
Test status
Simulation time 29653258390 ps
CPU time 194.63 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:59:04 PM PDT 24
Peak memory 2499844 kb
Host smart-cabba431-a980-48d8-8990-7eea4bbbc0b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97897510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stress_wr.97897510
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.3986643421
Short name T929
Test name
Test status
Simulation time 38400318795 ps
CPU time 795.41 seconds
Started Jun 26 04:55:46 PM PDT 24
Finished Jun 26 05:09:04 PM PDT 24
Peak memory 2231124 kb
Host smart-be99eac1-afe9-4bae-82fb-6718fa331b49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986643421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.3986643421
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3968218216
Short name T903
Test name
Test status
Simulation time 198012961 ps
CPU time 2.74 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:53 PM PDT 24
Peak memory 213060 kb
Host smart-44290fe8-2762-4096-ac66-6f2363d2a451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968218216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3968218216
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.1578283245
Short name T277
Test name
Test status
Simulation time 497276693 ps
CPU time 7.2 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:55:54 PM PDT 24
Peak memory 271144 kb
Host smart-064540b3-c6af-4a5d-b175-12b2dc83623f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578283245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.1578283245
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.4124671261
Short name T1313
Test name
Test status
Simulation time 1610577849 ps
CPU time 95.28 seconds
Started Jun 26 04:55:56 PM PDT 24
Finished Jun 26 04:57:34 PM PDT 24
Peak memory 517928 kb
Host smart-c3c5609e-8d3e-49c1-8f61-4c5b858f9b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124671261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.4124671261
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2195549489
Short name T436
Test name
Test status
Simulation time 7002370486 ps
CPU time 128.16 seconds
Started Jun 26 04:55:43 PM PDT 24
Finished Jun 26 04:57:53 PM PDT 24
Peak memory 641852 kb
Host smart-6ffdcae2-f7e3-4a17-b90f-b8e376f433b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195549489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2195549489
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.4120266729
Short name T1176
Test name
Test status
Simulation time 1045965221 ps
CPU time 1 seconds
Started Jun 26 04:55:48 PM PDT 24
Finished Jun 26 04:55:52 PM PDT 24
Peak memory 204484 kb
Host smart-1e900bd7-93fb-464c-bb53-e62dcca5342d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120266729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.4120266729
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.1717292511
Short name T1429
Test name
Test status
Simulation time 857652772 ps
CPU time 2.96 seconds
Started Jun 26 04:55:49 PM PDT 24
Finished Jun 26 04:55:55 PM PDT 24
Peak memory 204768 kb
Host smart-7a91ccd5-f4bb-4e0a-858d-ba8560d14248
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717292511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
1717292511
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1357823072
Short name T894
Test name
Test status
Simulation time 18607184167 ps
CPU time 91.68 seconds
Started Jun 26 04:55:46 PM PDT 24
Finished Jun 26 04:57:21 PM PDT 24
Peak memory 1039972 kb
Host smart-5e68e9e3-4904-4ace-bb5d-0d1ecd03d489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357823072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1357823072
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.855194342
Short name T1352
Test name
Test status
Simulation time 614277473 ps
CPU time 13.21 seconds
Started Jun 26 04:55:51 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 204848 kb
Host smart-5ff6d9c5-fd81-4849-b7eb-a4f31824e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855194342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.855194342
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.298958814
Short name T35
Test name
Test status
Simulation time 8483506313 ps
CPU time 45.4 seconds
Started Jun 26 04:55:51 PM PDT 24
Finished Jun 26 04:56:39 PM PDT 24
Peak memory 470132 kb
Host smart-4da3731a-d48b-4552-b8ef-d90150a04357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298958814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.298958814
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.3658382277
Short name T1326
Test name
Test status
Simulation time 250035709 ps
CPU time 0.68 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:51 PM PDT 24
Peak memory 204484 kb
Host smart-b8bca66a-1741-43e0-98ce-eeeb6fe5a1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658382277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.3658382277
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.3581912892
Short name T684
Test name
Test status
Simulation time 99358907704 ps
CPU time 945.79 seconds
Started Jun 26 04:55:46 PM PDT 24
Finished Jun 26 05:11:34 PM PDT 24
Peak memory 2635260 kb
Host smart-15024ebb-6de7-4075-a09f-db82ee4efda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581912892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.3581912892
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.3602433285
Short name T697
Test name
Test status
Simulation time 1222896428 ps
CPU time 15.55 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:56:05 PM PDT 24
Peak memory 345504 kb
Host smart-d8da9876-2c60-4eb8-9a26-98aad7e15453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602433285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.3602433285
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3928885840
Short name T243
Test name
Test status
Simulation time 1220032404 ps
CPU time 58.71 seconds
Started Jun 26 04:55:44 PM PDT 24
Finished Jun 26 04:56:45 PM PDT 24
Peak memory 380012 kb
Host smart-2b677605-8d27-4f97-a4b6-3f62e4f13af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928885840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3928885840
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.2673741060
Short name T115
Test name
Test status
Simulation time 71929454256 ps
CPU time 515.68 seconds
Started Jun 26 04:55:56 PM PDT 24
Finished Jun 26 05:04:34 PM PDT 24
Peak memory 1037692 kb
Host smart-bcf9c52a-2836-402c-85fc-1d3d7bb40fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673741060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.2673741060
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.1034770062
Short name T341
Test name
Test status
Simulation time 2241928374 ps
CPU time 20.83 seconds
Started Jun 26 04:55:49 PM PDT 24
Finished Jun 26 04:56:13 PM PDT 24
Peak memory 213144 kb
Host smart-fa4e7b87-ccc5-431a-8888-70db4be36ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034770062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.1034770062
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.1352347703
Short name T159
Test name
Test status
Simulation time 59165751 ps
CPU time 0.95 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:51 PM PDT 24
Peak memory 223120 kb
Host smart-f3285e29-520c-42db-9158-972c329a8804
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352347703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.1352347703
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3413102765
Short name T879
Test name
Test status
Simulation time 1871333890 ps
CPU time 2.87 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:55:51 PM PDT 24
Peak memory 204816 kb
Host smart-b909e8c1-87b3-41f2-8d2e-e37179b69aa1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413102765 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3413102765
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2107921797
Short name T669
Test name
Test status
Simulation time 124340669 ps
CPU time 0.94 seconds
Started Jun 26 04:55:44 PM PDT 24
Finished Jun 26 04:55:47 PM PDT 24
Peak memory 204556 kb
Host smart-8d2ac605-a023-4527-a3ae-64f3ed412c55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107921797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2107921797
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.950632779
Short name T924
Test name
Test status
Simulation time 305456584 ps
CPU time 0.85 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:51 PM PDT 24
Peak memory 204588 kb
Host smart-c315b7f3-948f-40ba-9a6a-5ca5d7950b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950632779 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.950632779
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.3246152703
Short name T237
Test name
Test status
Simulation time 549431672 ps
CPU time 1.73 seconds
Started Jun 26 04:55:46 PM PDT 24
Finished Jun 26 04:55:51 PM PDT 24
Peak memory 204628 kb
Host smart-1776a74a-96d7-4a70-aff5-ab54feb66bdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246152703 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.3246152703
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.2033955729
Short name T695
Test name
Test status
Simulation time 1925622886 ps
CPU time 1.11 seconds
Started Jun 26 04:55:51 PM PDT 24
Finished Jun 26 04:55:55 PM PDT 24
Peak memory 204616 kb
Host smart-9787939d-e1c1-40a4-ae80-20a82d49590b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033955729 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.2033955729
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.2285556241
Short name T15
Test name
Test status
Simulation time 1873956352 ps
CPU time 9.53 seconds
Started Jun 26 04:55:52 PM PDT 24
Finished Jun 26 04:56:04 PM PDT 24
Peak memory 213580 kb
Host smart-32fb3eea-6c8e-4e07-8d69-fe2c8b800420
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285556241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.2285556241
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.67000270
Short name T998
Test name
Test status
Simulation time 3337334797 ps
CPU time 2.77 seconds
Started Jun 26 04:55:55 PM PDT 24
Finished Jun 26 04:56:00 PM PDT 24
Peak memory 204896 kb
Host smart-2b70e740-dd2e-4d5a-a453-9fb205e1dff8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67000270 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.i2c_target_hrst.67000270
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.1719028866
Short name T417
Test name
Test status
Simulation time 4905697786 ps
CPU time 6.81 seconds
Started Jun 26 04:55:50 PM PDT 24
Finished Jun 26 04:56:00 PM PDT 24
Peak memory 217196 kb
Host smart-4da021e0-92c5-4539-b27a-9bf3a42a8119
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719028866 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.1719028866
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2225276452
Short name T398
Test name
Test status
Simulation time 18115196759 ps
CPU time 344.48 seconds
Started Jun 26 04:55:43 PM PDT 24
Finished Jun 26 05:01:29 PM PDT 24
Peak memory 4338080 kb
Host smart-1a245e65-b02e-4014-93a7-6b5da44839f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225276452 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2225276452
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.2226056706
Short name T1168
Test name
Test status
Simulation time 695850757 ps
CPU time 25.75 seconds
Started Jun 26 04:55:38 PM PDT 24
Finished Jun 26 04:56:08 PM PDT 24
Peak memory 204740 kb
Host smart-0c032056-5a2a-4f0b-b99a-9c41465f1d58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226056706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.2226056706
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1827204259
Short name T762
Test name
Test status
Simulation time 1229880760 ps
CPU time 5.53 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 204796 kb
Host smart-c3277139-7e89-4242-b678-1371a56861f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827204259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1827204259
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.880261971
Short name T1415
Test name
Test status
Simulation time 60237010348 ps
CPU time 1990.32 seconds
Started Jun 26 04:55:55 PM PDT 24
Finished Jun 26 05:29:08 PM PDT 24
Peak memory 10172788 kb
Host smart-04c0d13b-5b36-4b42-bc03-f4cb7199bb96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880261971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_
target_stress_wr.880261971
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3318461082
Short name T710
Test name
Test status
Simulation time 39613252111 ps
CPU time 2635.79 seconds
Started Jun 26 04:55:44 PM PDT 24
Finished Jun 26 05:39:43 PM PDT 24
Peak memory 9355348 kb
Host smart-75d25749-9db5-4d38-b919-a6b54e8e0913
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318461082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3318461082
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.443916271
Short name T764
Test name
Test status
Simulation time 1282985849 ps
CPU time 7.46 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:55:55 PM PDT 24
Peak memory 219496 kb
Host smart-1168ff29-95c5-4d58-b47c-268a065e570b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443916271 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_timeout.443916271
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.976712882
Short name T737
Test name
Test status
Simulation time 39041754 ps
CPU time 0.64 seconds
Started Jun 26 04:56:39 PM PDT 24
Finished Jun 26 04:56:42 PM PDT 24
Peak memory 204424 kb
Host smart-7e092662-d595-43bf-90c3-c20838f16cd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976712882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.976712882
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1244889120
Short name T52
Test name
Test status
Simulation time 358103088 ps
CPU time 3.09 seconds
Started Jun 26 04:56:43 PM PDT 24
Finished Jun 26 04:56:48 PM PDT 24
Peak memory 236252 kb
Host smart-119393ea-2cb4-4520-a2c3-29bc897a06dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244889120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1244889120
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.3519489190
Short name T303
Test name
Test status
Simulation time 225490395 ps
CPU time 10.72 seconds
Started Jun 26 04:56:40 PM PDT 24
Finished Jun 26 04:56:52 PM PDT 24
Peak memory 248632 kb
Host smart-e782ff9e-36eb-4169-8c7b-952047625718
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519489190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.3519489190
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1338595951
Short name T1194
Test name
Test status
Simulation time 1763978473 ps
CPU time 46.35 seconds
Started Jun 26 04:56:43 PM PDT 24
Finished Jun 26 04:57:31 PM PDT 24
Peak memory 457164 kb
Host smart-ca754f66-2d64-4ebd-86f4-ed0508f89303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338595951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1338595951
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.398280459
Short name T753
Test name
Test status
Simulation time 2464986851 ps
CPU time 82.01 seconds
Started Jun 26 04:56:39 PM PDT 24
Finished Jun 26 04:58:03 PM PDT 24
Peak memory 795896 kb
Host smart-7ce7d40a-e8fb-42d0-89c4-8ff729cd795f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398280459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.398280459
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3284061401
Short name T1433
Test name
Test status
Simulation time 183582130 ps
CPU time 0.96 seconds
Started Jun 26 04:56:39 PM PDT 24
Finished Jun 26 04:56:42 PM PDT 24
Peak memory 204460 kb
Host smart-9426d222-ca2f-4b24-9ff0-8d0c79f5e123
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284061401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3284061401
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.3230654125
Short name T1094
Test name
Test status
Simulation time 215553722 ps
CPU time 11.61 seconds
Started Jun 26 04:56:39 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 246064 kb
Host smart-828c51f3-30b9-4543-8053-e3ea5920bd62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230654125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.3230654125
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.1670084334
Short name T299
Test name
Test status
Simulation time 6351743561 ps
CPU time 203.94 seconds
Started Jun 26 04:56:40 PM PDT 24
Finished Jun 26 05:00:06 PM PDT 24
Peak memory 966260 kb
Host smart-19832abf-ca56-4963-919f-5df9356cc8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670084334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.1670084334
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2548050804
Short name T41
Test name
Test status
Simulation time 1635053985 ps
CPU time 5.95 seconds
Started Jun 26 04:56:40 PM PDT 24
Finished Jun 26 04:56:48 PM PDT 24
Peak memory 204796 kb
Host smart-162a04a0-7821-4652-9718-39c678ae5ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548050804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2548050804
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.3625693811
Short name T765
Test name
Test status
Simulation time 1308838996 ps
CPU time 59.91 seconds
Started Jun 26 04:56:39 PM PDT 24
Finished Jun 26 04:57:40 PM PDT 24
Peak memory 346868 kb
Host smart-5e159ce1-7b6f-441e-86dc-df437e185c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625693811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.3625693811
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.164462124
Short name T1228
Test name
Test status
Simulation time 52216915 ps
CPU time 0.72 seconds
Started Jun 26 04:56:38 PM PDT 24
Finished Jun 26 04:56:40 PM PDT 24
Peak memory 204564 kb
Host smart-d6b7c04f-e047-46dc-afe4-4cbacf4c08f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164462124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.164462124
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.4199306200
Short name T1225
Test name
Test status
Simulation time 7193498279 ps
CPU time 74.98 seconds
Started Jun 26 04:56:39 PM PDT 24
Finished Jun 26 04:57:56 PM PDT 24
Peak memory 221568 kb
Host smart-f9c4a7cf-88dd-4f9d-8112-7a2cec4f68ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199306200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.4199306200
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.1763967736
Short name T940
Test name
Test status
Simulation time 196326516 ps
CPU time 3.27 seconds
Started Jun 26 04:56:38 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 204996 kb
Host smart-a6a1ee3a-8006-42de-93da-7e9878daf1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763967736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.1763967736
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.234800468
Short name T106
Test name
Test status
Simulation time 1179920171 ps
CPU time 20.47 seconds
Started Jun 26 04:56:44 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 277844 kb
Host smart-67bde8aa-470a-4a8d-8a97-993270f50bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234800468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.234800468
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3576747831
Short name T54
Test name
Test status
Simulation time 11803507702 ps
CPU time 465.99 seconds
Started Jun 26 04:56:43 PM PDT 24
Finished Jun 26 05:04:31 PM PDT 24
Peak memory 1272952 kb
Host smart-90b1379a-a772-4fd9-9e09-9248d36152d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576747831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3576747831
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1730501782
Short name T117
Test name
Test status
Simulation time 848679930 ps
CPU time 3.95 seconds
Started Jun 26 04:56:40 PM PDT 24
Finished Jun 26 04:56:46 PM PDT 24
Peak memory 213084 kb
Host smart-15b05837-2bfe-4eec-bf2e-bf6b59f296e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730501782 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1730501782
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1598234816
Short name T750
Test name
Test status
Simulation time 354225353 ps
CPU time 1.13 seconds
Started Jun 26 04:56:42 PM PDT 24
Finished Jun 26 04:56:44 PM PDT 24
Peak memory 204552 kb
Host smart-71229f09-bcbf-40f1-a94e-6ac287f3ad56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598234816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1598234816
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3756554962
Short name T532
Test name
Test status
Simulation time 145900517 ps
CPU time 1.01 seconds
Started Jun 26 04:56:40 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 204592 kb
Host smart-3bc976fb-30c6-4084-b9c6-41f6c6e31a77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756554962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3756554962
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.2966381921
Short name T580
Test name
Test status
Simulation time 584284006 ps
CPU time 3.11 seconds
Started Jun 26 04:56:39 PM PDT 24
Finished Jun 26 04:56:44 PM PDT 24
Peak memory 204820 kb
Host smart-2bccfe70-00ba-46e9-ad01-e14d63280d76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966381921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.2966381921
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.4108986582
Short name T871
Test name
Test status
Simulation time 590651921 ps
CPU time 1.18 seconds
Started Jun 26 04:56:40 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 204640 kb
Host smart-017c67b5-f3ce-42bb-9863-3d37a879996d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108986582 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.4108986582
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.757068542
Short name T474
Test name
Test status
Simulation time 1648513876 ps
CPU time 5.16 seconds
Started Jun 26 04:56:44 PM PDT 24
Finished Jun 26 04:56:51 PM PDT 24
Peak memory 214204 kb
Host smart-911c0968-d26b-49bf-99a7-abe864b5a910
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757068542 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.757068542
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.501623145
Short name T1366
Test name
Test status
Simulation time 14604066133 ps
CPU time 109.69 seconds
Started Jun 26 04:56:41 PM PDT 24
Finished Jun 26 04:58:32 PM PDT 24
Peak memory 2123408 kb
Host smart-350257f7-05bd-4f78-bd62-8f09afcc685a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501623145 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.501623145
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2004485537
Short name T468
Test name
Test status
Simulation time 4369739375 ps
CPU time 41.17 seconds
Started Jun 26 04:56:43 PM PDT 24
Finished Jun 26 04:57:26 PM PDT 24
Peak memory 204760 kb
Host smart-ab1b935e-93a2-4ab5-aa80-b0c1ffcf003c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004485537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2004485537
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.2523018332
Short name T711
Test name
Test status
Simulation time 239056763 ps
CPU time 3.66 seconds
Started Jun 26 04:56:38 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 204780 kb
Host smart-107a1f15-a351-4f6f-87bc-38c5e833d2d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523018332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.2523018332
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3310093122
Short name T1466
Test name
Test status
Simulation time 9003790483 ps
CPU time 2.84 seconds
Started Jun 26 04:56:37 PM PDT 24
Finished Jun 26 04:56:41 PM PDT 24
Peak memory 204876 kb
Host smart-9abf6220-528a-4221-98ce-95ee28d4eb7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310093122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3310093122
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1757531951
Short name T234
Test name
Test status
Simulation time 2448481772 ps
CPU time 123.26 seconds
Started Jun 26 04:56:42 PM PDT 24
Finished Jun 26 04:58:46 PM PDT 24
Peak memory 688204 kb
Host smart-234e7b31-2f09-4909-a04c-1371ca6b3695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757531951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1757531951
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3457610706
Short name T1443
Test name
Test status
Simulation time 1414153013 ps
CPU time 7.92 seconds
Started Jun 26 04:56:44 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 212760 kb
Host smart-c6108ff4-307b-4e87-b4fa-58d3f1833ca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457610706 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3457610706
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.4000998919
Short name T325
Test name
Test status
Simulation time 66090268 ps
CPU time 0.63 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:56:51 PM PDT 24
Peak memory 204476 kb
Host smart-39bac1c9-d9a0-46cc-8e88-135133204c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000998919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.4000998919
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.2670880612
Short name T516
Test name
Test status
Simulation time 373740036 ps
CPU time 1.85 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:56:54 PM PDT 24
Peak memory 213112 kb
Host smart-f95dd0b0-7016-4b61-a38e-0b29bb4175fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670880612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.2670880612
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2723383639
Short name T108
Test name
Test status
Simulation time 514841383 ps
CPU time 26.7 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:57:19 PM PDT 24
Peak memory 314492 kb
Host smart-b658c215-31fb-4b35-b9f4-2b46aec9d282
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723383639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2723383639
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.2842025331
Short name T75
Test name
Test status
Simulation time 1821786682 ps
CPU time 128.58 seconds
Started Jun 26 04:56:46 PM PDT 24
Finished Jun 26 04:58:56 PM PDT 24
Peak memory 651652 kb
Host smart-ba12d155-c4a5-4585-9f6c-d9c26ae2e5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842025331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.2842025331
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.913745171
Short name T1186
Test name
Test status
Simulation time 9449426403 ps
CPU time 80.31 seconds
Started Jun 26 04:56:40 PM PDT 24
Finished Jun 26 04:58:02 PM PDT 24
Peak memory 773204 kb
Host smart-55a3f558-663d-4a2c-bbb8-611ee278837a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913745171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.913745171
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2010562529
Short name T977
Test name
Test status
Simulation time 542325801 ps
CPU time 1.13 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 204540 kb
Host smart-8999ee2a-0df6-401f-8076-1c9d04e619d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010562529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2010562529
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.896820458
Short name T704
Test name
Test status
Simulation time 598842648 ps
CPU time 3.25 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 204808 kb
Host smart-175f6569-e968-44c4-abda-374151615be1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896820458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx.
896820458
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2264832562
Short name T1260
Test name
Test status
Simulation time 5168718962 ps
CPU time 129.93 seconds
Started Jun 26 04:56:38 PM PDT 24
Finished Jun 26 04:58:50 PM PDT 24
Peak memory 1447996 kb
Host smart-c0f8888b-d02e-4a93-a397-893707353639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264832562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2264832562
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.156661966
Short name T830
Test name
Test status
Simulation time 575587017 ps
CPU time 3.84 seconds
Started Jun 26 04:56:49 PM PDT 24
Finished Jun 26 04:56:55 PM PDT 24
Peak memory 204844 kb
Host smart-aa182d5b-7898-4a4a-b8b7-ad8c42cdb94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156661966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.156661966
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.4107164824
Short name T1269
Test name
Test status
Simulation time 5640038660 ps
CPU time 66.18 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:57:58 PM PDT 24
Peak memory 363324 kb
Host smart-6aeccbd4-898d-4dd6-a7f3-7e8e8d23b5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107164824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.4107164824
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.4175801086
Short name T1156
Test name
Test status
Simulation time 94014232 ps
CPU time 0.64 seconds
Started Jun 26 04:56:38 PM PDT 24
Finished Jun 26 04:56:41 PM PDT 24
Peak memory 204560 kb
Host smart-43abb7f5-b794-4806-9dd6-e1804adb7352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175801086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.4175801086
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.535765294
Short name T1458
Test name
Test status
Simulation time 52128948693 ps
CPU time 319 seconds
Started Jun 26 04:56:47 PM PDT 24
Finished Jun 26 05:02:08 PM PDT 24
Peak memory 757436 kb
Host smart-2d9439ac-c80f-4f8c-8f36-e98f9ea66e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535765294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.535765294
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.3489162260
Short name T487
Test name
Test status
Simulation time 51896479 ps
CPU time 1.38 seconds
Started Jun 26 04:56:49 PM PDT 24
Finished Jun 26 04:56:52 PM PDT 24
Peak memory 205132 kb
Host smart-aec9a97c-695c-4835-8a24-77e97f1adb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489162260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.3489162260
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.3560358994
Short name T1409
Test name
Test status
Simulation time 1272169583 ps
CPU time 21.46 seconds
Started Jun 26 04:56:42 PM PDT 24
Finished Jun 26 04:57:05 PM PDT 24
Peak memory 261700 kb
Host smart-d186893d-5bdc-4f06-9a78-40f89bb76cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560358994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.3560358994
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.4024099838
Short name T745
Test name
Test status
Simulation time 1809375878 ps
CPU time 11.61 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:57:02 PM PDT 24
Peak memory 212920 kb
Host smart-e36843b4-2e6d-446f-a3ed-50735310f339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024099838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.4024099838
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.1544299942
Short name T439
Test name
Test status
Simulation time 811325904 ps
CPU time 4.01 seconds
Started Jun 26 04:56:47 PM PDT 24
Finished Jun 26 04:56:52 PM PDT 24
Peak memory 213020 kb
Host smart-acbcf785-d696-4ea4-b867-b0022af5b7ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544299942 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.1544299942
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.2896713099
Short name T575
Test name
Test status
Simulation time 953583783 ps
CPU time 1.32 seconds
Started Jun 26 04:56:46 PM PDT 24
Finished Jun 26 04:56:49 PM PDT 24
Peak memory 204804 kb
Host smart-c3de6855-227c-4059-8820-7f2309b04e6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896713099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.2896713099
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1737964990
Short name T1056
Test name
Test status
Simulation time 257980880 ps
CPU time 1.38 seconds
Started Jun 26 04:56:51 PM PDT 24
Finished Jun 26 04:56:54 PM PDT 24
Peak memory 204632 kb
Host smart-7db9b670-c759-4ab0-9592-8d586b0a607d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737964990 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1737964990
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.700090642
Short name T592
Test name
Test status
Simulation time 898376747 ps
CPU time 2.41 seconds
Started Jun 26 04:56:49 PM PDT 24
Finished Jun 26 04:56:54 PM PDT 24
Peak memory 204752 kb
Host smart-66b8bac6-4a5d-4844-b4b8-a88d7e1b886f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700090642 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.700090642
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.2726500739
Short name T1297
Test name
Test status
Simulation time 704063745 ps
CPU time 1.26 seconds
Started Jun 26 04:56:49 PM PDT 24
Finished Jun 26 04:56:52 PM PDT 24
Peak memory 204512 kb
Host smart-3258d0a8-732e-4604-8148-a0e9fcd6f163
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726500739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.2726500739
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.2244437953
Short name T1455
Test name
Test status
Simulation time 287712149 ps
CPU time 2.64 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:56:52 PM PDT 24
Peak memory 204756 kb
Host smart-c8047485-7021-4059-aa4d-6dab73face13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244437953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.2244437953
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1127219833
Short name T788
Test name
Test status
Simulation time 4257877319 ps
CPU time 4.94 seconds
Started Jun 26 04:56:47 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 213140 kb
Host smart-2167299f-8b90-4894-bb51-e00c84a48111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127219833 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1127219833
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.2406075495
Short name T1070
Test name
Test status
Simulation time 7249649717 ps
CPU time 100.35 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:58:30 PM PDT 24
Peak memory 1907212 kb
Host smart-415f3e98-b8d2-4ab6-acb1-b65483c61952
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406075495 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.2406075495
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.2637708391
Short name T1037
Test name
Test status
Simulation time 4773283952 ps
CPU time 46.17 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:57:36 PM PDT 24
Peak memory 204964 kb
Host smart-d6496ded-4ad2-47ff-9263-a2b8d8bbd46a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637708391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.2637708391
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.3001233297
Short name T362
Test name
Test status
Simulation time 1524565024 ps
CPU time 31.22 seconds
Started Jun 26 04:56:46 PM PDT 24
Finished Jun 26 04:57:19 PM PDT 24
Peak memory 204808 kb
Host smart-de2cd802-0a62-4456-bf2f-7092dea81839
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001233297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.3001233297
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.2845502817
Short name T1390
Test name
Test status
Simulation time 12032626081 ps
CPU time 13.08 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:57:05 PM PDT 24
Peak memory 204864 kb
Host smart-2432c62e-a71a-43d8-89c3-76264c9bb706
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845502817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_wr.2845502817
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1857022170
Short name T955
Test name
Test status
Simulation time 17372130237 ps
CPU time 2329.01 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 05:35:39 PM PDT 24
Peak memory 4300956 kb
Host smart-a364f97c-5f88-4180-b6b3-1dcf98bd21f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857022170 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1857022170
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.4166844111
Short name T631
Test name
Test status
Simulation time 1281426352 ps
CPU time 6.72 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:56:57 PM PDT 24
Peak memory 213044 kb
Host smart-6883b871-178d-4015-aa52-602097d51ca1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166844111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.4166844111
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3588040703
Short name T629
Test name
Test status
Simulation time 18527913 ps
CPU time 0.66 seconds
Started Jun 26 04:57:01 PM PDT 24
Finished Jun 26 04:57:03 PM PDT 24
Peak memory 204484 kb
Host smart-f170fb65-0a2b-4638-9814-31eb620a1a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588040703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3588040703
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3813543387
Short name T551
Test name
Test status
Simulation time 352502910 ps
CPU time 4.43 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:56:56 PM PDT 24
Peak memory 245412 kb
Host smart-6988c5b8-60fd-4da2-937a-9069626426c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813543387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3813543387
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.896405376
Short name T302
Test name
Test status
Simulation time 605816104 ps
CPU time 5.58 seconds
Started Jun 26 04:56:46 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 267768 kb
Host smart-31e3329b-b304-4e52-8573-e7baf5398a41
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896405376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_empt
y.896405376
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.1645350661
Short name T1393
Test name
Test status
Simulation time 12343693387 ps
CPU time 83.44 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:58:14 PM PDT 24
Peak memory 687760 kb
Host smart-4afa4c16-9b06-43b1-b5a2-dbf179b9ff98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645350661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.1645350661
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.4179700955
Short name T443
Test name
Test status
Simulation time 2166369776 ps
CPU time 158.2 seconds
Started Jun 26 04:56:48 PM PDT 24
Finished Jun 26 04:59:29 PM PDT 24
Peak memory 741732 kb
Host smart-5bf217d3-2e56-4d5c-a6f7-fe614f457653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179700955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.4179700955
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.922904804
Short name T348
Test name
Test status
Simulation time 96284383 ps
CPU time 0.87 seconds
Started Jun 26 04:56:45 PM PDT 24
Finished Jun 26 04:56:47 PM PDT 24
Peak memory 204472 kb
Host smart-d6e547a1-495d-406d-bafd-4ff5484febd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922904804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_fm
t.922904804
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1945230639
Short name T1274
Test name
Test status
Simulation time 4545141574 ps
CPU time 309.71 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 05:02:01 PM PDT 24
Peak memory 1280364 kb
Host smart-505de1bd-5b43-411e-8677-38c28865f3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945230639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1945230639
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.10500806
Short name T352
Test name
Test status
Simulation time 2985234505 ps
CPU time 8.86 seconds
Started Jun 26 04:56:59 PM PDT 24
Finished Jun 26 04:57:09 PM PDT 24
Peak memory 204952 kb
Host smart-cc1f4c5b-be1f-4a68-b3bb-180079212d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10500806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.10500806
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.24102601
Short name T1030
Test name
Test status
Simulation time 10668012227 ps
CPU time 28.64 seconds
Started Jun 26 04:57:02 PM PDT 24
Finished Jun 26 04:57:32 PM PDT 24
Peak memory 377688 kb
Host smart-db0bf8c4-c9fc-4048-b284-79b1847cff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24102601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.24102601
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.1688795236
Short name T70
Test name
Test status
Simulation time 30462376 ps
CPU time 0.7 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 204752 kb
Host smart-de58207d-950c-49f6-a2fb-fa4ba180a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688795236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1688795236
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.2285876137
Short name T1322
Test name
Test status
Simulation time 5133752486 ps
CPU time 27.02 seconds
Started Jun 26 04:56:52 PM PDT 24
Finished Jun 26 04:57:20 PM PDT 24
Peak memory 364468 kb
Host smart-33c1b668-79a2-4818-8707-e4c4fb2ca22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285876137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.2285876137
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.1323539189
Short name T1111
Test name
Test status
Simulation time 61815465 ps
CPU time 1.61 seconds
Started Jun 26 04:56:46 PM PDT 24
Finished Jun 26 04:56:49 PM PDT 24
Peak memory 205384 kb
Host smart-7906e486-8497-4ef6-8675-a8528fe288af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323539189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.1323539189
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1908414128
Short name T1121
Test name
Test status
Simulation time 7582123432 ps
CPU time 89.95 seconds
Started Jun 26 04:56:49 PM PDT 24
Finished Jun 26 04:58:21 PM PDT 24
Peak memory 378692 kb
Host smart-1e0ed563-e263-49e8-85bd-d6e6bf5bd3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908414128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1908414128
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.169035325
Short name T168
Test name
Test status
Simulation time 7296956982 ps
CPU time 317.94 seconds
Started Jun 26 04:56:47 PM PDT 24
Finished Jun 26 05:02:07 PM PDT 24
Peak memory 1687288 kb
Host smart-b2781d1b-b6ce-4400-8656-4712e800baff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169035325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.169035325
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3683613127
Short name T1128
Test name
Test status
Simulation time 1644721813 ps
CPU time 13.67 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 221112 kb
Host smart-70b28dc2-63ef-4a62-ada6-accadb8c440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683613127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3683613127
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.3517265508
Short name T902
Test name
Test status
Simulation time 1935252473 ps
CPU time 4.86 seconds
Started Jun 26 04:57:04 PM PDT 24
Finished Jun 26 04:57:10 PM PDT 24
Peak memory 213784 kb
Host smart-5b31ee82-d045-4d30-88cd-9c66904a8ad9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517265508 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.3517265508
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.586953014
Short name T849
Test name
Test status
Simulation time 191056798 ps
CPU time 0.92 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:57:00 PM PDT 24
Peak memory 204524 kb
Host smart-3bbb85b5-a18d-415d-87c0-6df58fb03018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586953014 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.i2c_target_fifo_reset_tx.586953014
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.400542118
Short name T1183
Test name
Test status
Simulation time 1108848248 ps
CPU time 2.79 seconds
Started Jun 26 04:56:57 PM PDT 24
Finished Jun 26 04:57:01 PM PDT 24
Peak memory 204748 kb
Host smart-7f399565-763a-48c7-99c4-6e7a5dcc83be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400542118 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.400542118
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.503285883
Short name T1189
Test name
Test status
Simulation time 126597917 ps
CPU time 0.91 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:57:00 PM PDT 24
Peak memory 204552 kb
Host smart-103e9693-12d9-497f-b191-4ec1932da035
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503285883 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.503285883
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.4120439082
Short name T227
Test name
Test status
Simulation time 306423040 ps
CPU time 3.74 seconds
Started Jun 26 04:56:57 PM PDT 24
Finished Jun 26 04:57:02 PM PDT 24
Peak memory 204824 kb
Host smart-c5528e67-1663-40bd-8cfa-378fdee116a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120439082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_hrst.4120439082
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.3438000084
Short name T1303
Test name
Test status
Simulation time 742164018 ps
CPU time 4.86 seconds
Started Jun 26 04:56:50 PM PDT 24
Finished Jun 26 04:56:57 PM PDT 24
Peak memory 211368 kb
Host smart-2d8b021d-1980-4176-8a1e-cc964cdfe30b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438000084 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.3438000084
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1384351275
Short name T238
Test name
Test status
Simulation time 29209580925 ps
CPU time 39.56 seconds
Started Jun 26 04:57:01 PM PDT 24
Finished Jun 26 04:57:42 PM PDT 24
Peak memory 881472 kb
Host smart-434e8718-5e09-4b7d-a361-3a5b66ba208a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384351275 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1384351275
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.1487283449
Short name T542
Test name
Test status
Simulation time 4586516039 ps
CPU time 14.83 seconds
Started Jun 26 04:56:49 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 204940 kb
Host smart-839e1fbd-a339-4520-8f39-a1cc5947e109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487283449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.1487283449
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3686017430
Short name T403
Test name
Test status
Simulation time 1375709353 ps
CPU time 32.22 seconds
Started Jun 26 04:56:46 PM PDT 24
Finished Jun 26 04:57:20 PM PDT 24
Peak memory 204780 kb
Host smart-691d4538-d599-4800-9866-f87fbf2b1740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686017430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3686017430
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.438449140
Short name T469
Test name
Test status
Simulation time 22481709765 ps
CPU time 53.16 seconds
Started Jun 26 04:56:49 PM PDT 24
Finished Jun 26 04:57:44 PM PDT 24
Peak memory 619108 kb
Host smart-56304285-2948-4d2f-ac55-194fb63f7619
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438449140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_wr.438449140
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.2178199894
Short name T1172
Test name
Test status
Simulation time 36573183287 ps
CPU time 662.57 seconds
Started Jun 26 04:56:46 PM PDT 24
Finished Jun 26 05:07:50 PM PDT 24
Peak memory 1991472 kb
Host smart-c0866d43-b61a-49b5-b4b5-04ec700a558c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178199894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.2178199894
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3948341267
Short name T1471
Test name
Test status
Simulation time 5558068023 ps
CPU time 7.51 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 221876 kb
Host smart-83e8f072-3ee0-4013-a221-73a4f19ae455
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948341267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3948341267
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2691658255
Short name T539
Test name
Test status
Simulation time 59042277 ps
CPU time 0.6 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:11 PM PDT 24
Peak memory 204340 kb
Host smart-31534be0-91a2-41e2-b8f3-16765ad34ee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691658255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2691658255
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.39328363
Short name T714
Test name
Test status
Simulation time 347382642 ps
CPU time 4.32 seconds
Started Jun 26 04:57:02 PM PDT 24
Finished Jun 26 04:57:07 PM PDT 24
Peak memory 230840 kb
Host smart-eee437f9-5995-4162-bf95-d05bb1b38000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39328363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.39328363
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1328097271
Short name T331
Test name
Test status
Simulation time 1074552998 ps
CPU time 12.82 seconds
Started Jun 26 04:57:02 PM PDT 24
Finished Jun 26 04:57:16 PM PDT 24
Peak memory 240756 kb
Host smart-bf003b3f-39b1-4ee1-b345-f2296357597e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328097271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1328097271
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.397610735
Short name T864
Test name
Test status
Simulation time 12292720198 ps
CPU time 90.11 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:58:29 PM PDT 24
Peak memory 848832 kb
Host smart-5d5b73b0-a73b-4ec5-b843-845dd8031063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397610735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.397610735
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3509999947
Short name T1342
Test name
Test status
Simulation time 1814443044 ps
CPU time 56.88 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:57:56 PM PDT 24
Peak memory 619036 kb
Host smart-cc56f15c-1849-4f89-b683-0022370f7c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509999947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3509999947
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2978336462
Short name T7
Test name
Test status
Simulation time 284635878 ps
CPU time 0.89 seconds
Started Jun 26 04:57:00 PM PDT 24
Finished Jun 26 04:57:02 PM PDT 24
Peak memory 204560 kb
Host smart-c63c7aa8-63c9-4bf6-a267-9762dcbed7dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978336462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2978336462
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.3391054321
Short name T523
Test name
Test status
Simulation time 3233811490 ps
CPU time 4.29 seconds
Started Jun 26 04:57:03 PM PDT 24
Finished Jun 26 04:57:08 PM PDT 24
Peak memory 236704 kb
Host smart-41e7d9b0-df8d-4473-b170-04587b071ab0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391054321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.3391054321
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.3946433600
Short name T1293
Test name
Test status
Simulation time 21683664550 ps
CPU time 180.1 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:59:59 PM PDT 24
Peak memory 1554624 kb
Host smart-fdd307f0-ebc2-43a5-870a-09dc13454694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946433600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.3946433600
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1756648276
Short name T1285
Test name
Test status
Simulation time 3109028800 ps
CPU time 9.98 seconds
Started Jun 26 04:57:07 PM PDT 24
Finished Jun 26 04:57:19 PM PDT 24
Peak memory 205004 kb
Host smart-bf6fa601-ff38-421c-b422-eeb9425fd846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756648276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1756648276
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.571634547
Short name T613
Test name
Test status
Simulation time 1332940867 ps
CPU time 21.1 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:57:21 PM PDT 24
Peak memory 313232 kb
Host smart-89b31326-fd68-415a-84df-cadb7ed5149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571634547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.571634547
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.3521580896
Short name T610
Test name
Test status
Simulation time 28162986 ps
CPU time 0.67 seconds
Started Jun 26 04:56:59 PM PDT 24
Finished Jun 26 04:57:01 PM PDT 24
Peak memory 204424 kb
Host smart-cb3b32e6-5446-4826-8ce1-c75c008f8ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521580896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.3521580896
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.66508152
Short name T578
Test name
Test status
Simulation time 28924627007 ps
CPU time 233.57 seconds
Started Jun 26 04:57:00 PM PDT 24
Finished Jun 26 05:00:55 PM PDT 24
Peak memory 1515564 kb
Host smart-96ccfe82-6637-445f-9d7d-bd38bd4cc80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66508152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.66508152
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.4009757358
Short name T1349
Test name
Test status
Simulation time 83337040 ps
CPU time 2.94 seconds
Started Jun 26 04:56:59 PM PDT 24
Finished Jun 26 04:57:03 PM PDT 24
Peak memory 218068 kb
Host smart-abdc739b-d04f-4f4e-bc1d-3b0f3852cfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009757358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.4009757358
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.2352073500
Short name T290
Test name
Test status
Simulation time 8029867150 ps
CPU time 91.86 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:58:31 PM PDT 24
Peak memory 292824 kb
Host smart-30f89629-8cd8-4cb3-b9d4-fece28acc818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352073500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.2352073500
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.1004819017
Short name T1468
Test name
Test status
Simulation time 2168046850 ps
CPU time 14.19 seconds
Started Jun 26 04:57:01 PM PDT 24
Finished Jun 26 04:57:17 PM PDT 24
Peak memory 221256 kb
Host smart-d764b939-fca2-44df-b0db-56f5770d346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004819017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.1004819017
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3816326907
Short name T588
Test name
Test status
Simulation time 1130696599 ps
CPU time 3.57 seconds
Started Jun 26 04:57:01 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 204840 kb
Host smart-65727b1d-e630-4c03-9c66-177d0fb74b8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816326907 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3816326907
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1589470489
Short name T1446
Test name
Test status
Simulation time 528964162 ps
CPU time 1.18 seconds
Started Jun 26 04:57:04 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 204620 kb
Host smart-2d717afb-4ef6-452d-8250-52ead8b0a514
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589470489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1589470489
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3178936436
Short name T706
Test name
Test status
Simulation time 169945162 ps
CPU time 1.06 seconds
Started Jun 26 04:57:04 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 204624 kb
Host smart-6c76e400-2707-4403-8176-ddd8dd3d7329
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178936436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3178936436
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.2449750888
Short name T471
Test name
Test status
Simulation time 1245431851 ps
CPU time 1.34 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:13 PM PDT 24
Peak memory 204612 kb
Host smart-a524716b-61e5-4930-a389-bba2b7002a72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449750888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.2449750888
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.1409668247
Short name T1204
Test name
Test status
Simulation time 2050838476 ps
CPU time 5.93 seconds
Started Jun 26 04:57:00 PM PDT 24
Finished Jun 26 04:57:07 PM PDT 24
Peak memory 215448 kb
Host smart-ffbeaf0b-656f-4163-9fad-fa7f7d6ead9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409668247 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.1409668247
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.4276652231
Short name T1411
Test name
Test status
Simulation time 3124398198 ps
CPU time 3.83 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:57:03 PM PDT 24
Peak memory 204900 kb
Host smart-b09cd535-7a44-42d7-901e-e5b633593e2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276652231 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.4276652231
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2727099006
Short name T1452
Test name
Test status
Simulation time 9383581392 ps
CPU time 15.62 seconds
Started Jun 26 04:57:00 PM PDT 24
Finished Jun 26 04:57:16 PM PDT 24
Peak memory 204880 kb
Host smart-5fd9b221-5670-45ff-b050-37da337a80fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727099006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2727099006
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.616406338
Short name T1096
Test name
Test status
Simulation time 765996935 ps
CPU time 12 seconds
Started Jun 26 04:57:02 PM PDT 24
Finished Jun 26 04:57:15 PM PDT 24
Peak memory 211756 kb
Host smart-59d2b1f1-9fac-4a1e-ba0a-5def1db6ce42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616406338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.616406338
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.2397075097
Short name T591
Test name
Test status
Simulation time 21479924724 ps
CPU time 41.99 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:57:41 PM PDT 24
Peak memory 464568 kb
Host smart-431ce660-8e3d-4a3a-bd01-ee04ad378a48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397075097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.2397075097
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.1863682314
Short name T1426
Test name
Test status
Simulation time 24098705436 ps
CPU time 301.22 seconds
Started Jun 26 04:57:01 PM PDT 24
Finished Jun 26 05:02:04 PM PDT 24
Peak memory 1214920 kb
Host smart-0d206e9f-e9c3-46f1-83af-852c36f72ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863682314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.1863682314
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.4176909928
Short name T430
Test name
Test status
Simulation time 11217001842 ps
CPU time 7.47 seconds
Started Jun 26 04:56:57 PM PDT 24
Finished Jun 26 04:57:05 PM PDT 24
Peak memory 204924 kb
Host smart-4b41f026-4eaa-41d9-9c22-1c0afc8c15be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176909928 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.4176909928
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3794608121
Short name T883
Test name
Test status
Simulation time 19385213 ps
CPU time 0.69 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:11 PM PDT 24
Peak memory 204508 kb
Host smart-621fd2c8-6e3d-42bd-a49a-33058a3e389e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794608121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3794608121
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.1824060403
Short name T1014
Test name
Test status
Simulation time 363584968 ps
CPU time 6.05 seconds
Started Jun 26 04:57:07 PM PDT 24
Finished Jun 26 04:57:14 PM PDT 24
Peak memory 234300 kb
Host smart-29955de3-b3ab-4fa8-9dec-4bc320af92de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824060403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.1824060403
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.3574729200
Short name T461
Test name
Test status
Simulation time 2629371832 ps
CPU time 9.96 seconds
Started Jun 26 04:57:06 PM PDT 24
Finished Jun 26 04:57:17 PM PDT 24
Peak memory 327764 kb
Host smart-395849cc-77d0-4eca-982f-b484eb1bd714
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574729200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.3574729200
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2512425955
Short name T460
Test name
Test status
Simulation time 5438033705 ps
CPU time 86.4 seconds
Started Jun 26 04:57:07 PM PDT 24
Finished Jun 26 04:58:35 PM PDT 24
Peak memory 500564 kb
Host smart-354bcdb6-8508-43a6-98d5-ced19c6245b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512425955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2512425955
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.1795408207
Short name T1075
Test name
Test status
Simulation time 155680650 ps
CPU time 0.86 seconds
Started Jun 26 04:57:06 PM PDT 24
Finished Jun 26 04:57:08 PM PDT 24
Peak memory 204780 kb
Host smart-c2250610-a100-40d6-92ee-24ca0e950bef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795408207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.1795408207
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.116458602
Short name T1135
Test name
Test status
Simulation time 1338029589 ps
CPU time 5.41 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:18 PM PDT 24
Peak memory 240224 kb
Host smart-870fae6b-7891-425b-a8f9-84b96b0e4520
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116458602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx.
116458602
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2567622648
Short name T1420
Test name
Test status
Simulation time 14174505157 ps
CPU time 100.64 seconds
Started Jun 26 04:57:10 PM PDT 24
Finished Jun 26 04:58:53 PM PDT 24
Peak memory 1048768 kb
Host smart-d8e5c763-7d8c-4823-968c-00e226d5fa8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567622648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2567622648
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.253412612
Short name T863
Test name
Test status
Simulation time 450612689 ps
CPU time 18.33 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:32 PM PDT 24
Peak memory 204768 kb
Host smart-9565501e-6e70-4fa5-90e7-a3d4c1db1f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253412612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.253412612
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.2405154588
Short name T1244
Test name
Test status
Simulation time 2233893465 ps
CPU time 37.76 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:50 PM PDT 24
Peak memory 448652 kb
Host smart-c56e01da-695e-4172-9a53-59758c2673be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405154588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.2405154588
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_perf.2176292917
Short name T1006
Test name
Test status
Simulation time 7591763012 ps
CPU time 45.2 seconds
Started Jun 26 04:57:06 PM PDT 24
Finished Jun 26 04:57:52 PM PDT 24
Peak memory 226240 kb
Host smart-06226c43-8bea-429d-9372-5a90ff7aff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176292917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.2176292917
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.1599718095
Short name T738
Test name
Test status
Simulation time 277290023 ps
CPU time 1.75 seconds
Started Jun 26 04:57:08 PM PDT 24
Finished Jun 26 04:57:11 PM PDT 24
Peak memory 213336 kb
Host smart-81156774-9d4e-4ec4-b005-0ae3bf439cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599718095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.1599718095
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.338739800
Short name T1289
Test name
Test status
Simulation time 7059905992 ps
CPU time 35.71 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:47 PM PDT 24
Peak memory 352392 kb
Host smart-5913c881-4945-4a05-a024-4afc83846a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338739800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.338739800
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.865726809
Short name T298
Test name
Test status
Simulation time 1584386412 ps
CPU time 40.37 seconds
Started Jun 26 04:57:07 PM PDT 24
Finished Jun 26 04:57:49 PM PDT 24
Peak memory 212976 kb
Host smart-d9b137dc-ea94-4b5e-89f3-509c9bf356ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865726809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.865726809
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1329139531
Short name T484
Test name
Test status
Simulation time 2688360979 ps
CPU time 4.11 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:17 PM PDT 24
Peak memory 205204 kb
Host smart-6fd24efa-5525-48e3-89c5-a66ac7b9842c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329139531 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1329139531
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2436001673
Short name T624
Test name
Test status
Simulation time 113783254 ps
CPU time 0.85 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:14 PM PDT 24
Peak memory 204632 kb
Host smart-9afdad97-0b68-4b83-aa99-db536ef8572a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436001673 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2436001673
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.2780112691
Short name T835
Test name
Test status
Simulation time 227002976 ps
CPU time 1.37 seconds
Started Jun 26 04:57:08 PM PDT 24
Finished Jun 26 04:57:10 PM PDT 24
Peak memory 204624 kb
Host smart-e8ec079e-56ce-4bfb-bc2c-c9b2ba800abd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780112691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.2780112691
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.3310633440
Short name T21
Test name
Test status
Simulation time 440755986 ps
CPU time 2.61 seconds
Started Jun 26 04:57:10 PM PDT 24
Finished Jun 26 04:57:15 PM PDT 24
Peak memory 204460 kb
Host smart-bfb4e6b9-b106-4caf-9f5b-7972903dcd08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310633440 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.3310633440
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.4091408931
Short name T31
Test name
Test status
Simulation time 111198676 ps
CPU time 1.12 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:14 PM PDT 24
Peak memory 204552 kb
Host smart-d571136d-4959-4aa1-85d9-01b5742d781e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091408931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.4091408931
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3255565377
Short name T1404
Test name
Test status
Simulation time 1787452642 ps
CPU time 4.65 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:16 PM PDT 24
Peak memory 204848 kb
Host smart-8fc90214-ec4d-4fec-b550-eb76de80c6d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255565377 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3255565377
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.2370756396
Short name T1241
Test name
Test status
Simulation time 38197244615 ps
CPU time 14.3 seconds
Started Jun 26 04:57:08 PM PDT 24
Finished Jun 26 04:57:23 PM PDT 24
Peak memory 415932 kb
Host smart-10319d8a-75d3-4cb3-acc3-857f0602c708
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370756396 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.2370756396
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.532623096
Short name T1392
Test name
Test status
Simulation time 2481893255 ps
CPU time 51.51 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:58:02 PM PDT 24
Peak memory 204952 kb
Host smart-bba2efbe-ba93-4b09-9638-ad4000ba5a6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532623096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.532623096
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.4214297189
Short name T622
Test name
Test status
Simulation time 656381462 ps
CPU time 14.32 seconds
Started Jun 26 04:57:08 PM PDT 24
Finished Jun 26 04:57:24 PM PDT 24
Peak memory 204776 kb
Host smart-4c47b168-e297-4782-9e3d-9753dcd442ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214297189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.4214297189
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.3749556207
Short name T1373
Test name
Test status
Simulation time 41032249379 ps
CPU time 646.48 seconds
Started Jun 26 04:57:08 PM PDT 24
Finished Jun 26 05:07:56 PM PDT 24
Peak memory 5319920 kb
Host smart-40118557-43c3-427a-a259-f214272a3eaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749556207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.3749556207
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1427131256
Short name T626
Test name
Test status
Simulation time 25871019770 ps
CPU time 513.82 seconds
Started Jun 26 04:57:07 PM PDT 24
Finished Jun 26 05:05:43 PM PDT 24
Peak memory 3177212 kb
Host smart-fc7d854a-5b05-4b40-ba8c-180ab6b186b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427131256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1427131256
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1131985698
Short name T1081
Test name
Test status
Simulation time 5435379453 ps
CPU time 7.37 seconds
Started Jun 26 04:57:07 PM PDT 24
Finished Jun 26 04:57:15 PM PDT 24
Peak memory 221176 kb
Host smart-623644cc-baa7-4f8f-874a-0f46a347ead7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131985698 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1131985698
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.4276443784
Short name T1344
Test name
Test status
Simulation time 73084747 ps
CPU time 0.63 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:57:24 PM PDT 24
Peak memory 204464 kb
Host smart-b0dad17b-18a4-45f2-8946-bc9ff6f2ea81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276443784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.4276443784
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.500850131
Short name T898
Test name
Test status
Simulation time 113872475 ps
CPU time 2.18 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:15 PM PDT 24
Peak memory 213092 kb
Host smart-2200b6b5-26b0-453e-8aea-81b25b2a5703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500850131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.500850131
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2606038910
Short name T927
Test name
Test status
Simulation time 1042780361 ps
CPU time 5.89 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:16 PM PDT 24
Peak memory 255660 kb
Host smart-95b8cb6f-c3be-40a2-a167-d4bddaca8a70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606038910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2606038910
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.4227873757
Short name T188
Test name
Test status
Simulation time 2375424920 ps
CPU time 76.12 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:58:29 PM PDT 24
Peak memory 772436 kb
Host smart-b5843e61-8395-4759-b077-4efb815bb186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227873757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.4227873757
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2102503783
Short name T374
Test name
Test status
Simulation time 1878641684 ps
CPU time 141.15 seconds
Started Jun 26 04:57:07 PM PDT 24
Finished Jun 26 04:59:30 PM PDT 24
Peak memory 660700 kb
Host smart-5aaa7185-c28e-4938-beda-e270d173d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102503783 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2102503783
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1626035997
Short name T56
Test name
Test status
Simulation time 1077139840 ps
CPU time 1.34 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:13 PM PDT 24
Peak memory 204676 kb
Host smart-704cc9fb-d4af-4c45-aafd-0c8b6f4222da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626035997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1626035997
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.3144411507
Short name T219
Test name
Test status
Simulation time 529316442 ps
CPU time 3.31 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:17 PM PDT 24
Peak memory 204768 kb
Host smart-571fd104-053c-49bf-87f2-effc6b5b597f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144411507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.3144411507
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.1955288496
Short name T810
Test name
Test status
Simulation time 3319302390 ps
CPU time 71.22 seconds
Started Jun 26 04:57:08 PM PDT 24
Finished Jun 26 04:58:21 PM PDT 24
Peak memory 1007992 kb
Host smart-d3ffcc37-ec25-4548-80cd-347dde99cacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955288496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.1955288496
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1293291934
Short name T1323
Test name
Test status
Simulation time 214677423 ps
CPU time 2.94 seconds
Started Jun 26 04:57:19 PM PDT 24
Finished Jun 26 04:57:24 PM PDT 24
Peak memory 204768 kb
Host smart-9e38138a-4d51-48b1-adb2-9dab9e8828cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293291934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1293291934
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1374889011
Short name T589
Test name
Test status
Simulation time 8986195247 ps
CPU time 119.42 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:59:22 PM PDT 24
Peak memory 488980 kb
Host smart-c7f729b6-69aa-4f6d-823d-5bfe90271827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374889011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1374889011
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.4047233128
Short name T131
Test name
Test status
Simulation time 53029571 ps
CPU time 0.68 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 04:57:12 PM PDT 24
Peak memory 204752 kb
Host smart-c66bff69-635d-4275-9f6b-daeadb134bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047233128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.4047233128
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.3224198679
Short name T1148
Test name
Test status
Simulation time 5058361642 ps
CPU time 23.15 seconds
Started Jun 26 04:57:12 PM PDT 24
Finished Jun 26 04:57:37 PM PDT 24
Peak memory 461992 kb
Host smart-2a0dc255-9111-4aa2-86dc-88c487dec628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224198679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.3224198679
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.1717474873
Short name T609
Test name
Test status
Simulation time 54695645 ps
CPU time 1.09 seconds
Started Jun 26 04:57:07 PM PDT 24
Finished Jun 26 04:57:10 PM PDT 24
Peak memory 222444 kb
Host smart-a17632fd-3514-4852-bd99-f308444ed842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717474873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.1717474873
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.4158236812
Short name T648
Test name
Test status
Simulation time 925043329 ps
CPU time 42.42 seconds
Started Jun 26 04:57:11 PM PDT 24
Finished Jun 26 04:57:56 PM PDT 24
Peak memory 302080 kb
Host smart-cc52ade0-fb89-440d-bb93-26892235a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158236812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.4158236812
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.3634332705
Short name T1063
Test name
Test status
Simulation time 6260166270 ps
CPU time 442.63 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 05:04:34 PM PDT 24
Peak memory 1159440 kb
Host smart-f3ee0d5a-b7d0-4a37-82f5-b032b9b1ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634332705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.3634332705
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.3091019086
Short name T1312
Test name
Test status
Simulation time 668302748 ps
CPU time 11.41 seconds
Started Jun 26 04:57:10 PM PDT 24
Finished Jun 26 04:57:24 PM PDT 24
Peak memory 221192 kb
Host smart-0d817e57-5de5-48b5-bcf3-c5df7992f988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091019086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.3091019086
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.4216993072
Short name T1062
Test name
Test status
Simulation time 774207221 ps
CPU time 4.54 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:57:23 PM PDT 24
Peak memory 213020 kb
Host smart-05444d0c-4fdc-4169-a1d3-b621bda1eb3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216993072 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.4216993072
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.803286847
Short name T301
Test name
Test status
Simulation time 148117050 ps
CPU time 0.97 seconds
Started Jun 26 04:57:18 PM PDT 24
Finished Jun 26 04:57:21 PM PDT 24
Peak memory 204632 kb
Host smart-28b1cfb1-92e2-459d-884c-2c8f2027c6a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803286847 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_acq.803286847
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.4107301160
Short name T1335
Test name
Test status
Simulation time 271061831 ps
CPU time 1.59 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:57:19 PM PDT 24
Peak memory 205316 kb
Host smart-591a0894-f30d-4cd7-b802-a72d660cbf86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107301160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.4107301160
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.3982588607
Short name T1389
Test name
Test status
Simulation time 443454291 ps
CPU time 2.42 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:57:26 PM PDT 24
Peak memory 203992 kb
Host smart-c8fe4bc2-8653-4edc-bf10-372e43c82588
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982588607 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.3982588607
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.2767018518
Short name T1287
Test name
Test status
Simulation time 139238967 ps
CPU time 1.29 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:57:24 PM PDT 24
Peak memory 204628 kb
Host smart-72c0d79a-2990-48cb-8f4b-57d107531732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767018518 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.2767018518
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.2600570486
Short name T1125
Test name
Test status
Simulation time 1753215541 ps
CPU time 3.77 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:57:23 PM PDT 24
Peak memory 204752 kb
Host smart-13574089-7c54-42d5-b829-b119390893c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600570486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_hrst.2600570486
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.35056219
Short name T964
Test name
Test status
Simulation time 936394285 ps
CPU time 4.91 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:57:23 PM PDT 24
Peak memory 208888 kb
Host smart-9a3d0aed-82b4-4820-b240-09fb257930af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35056219 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.35056219
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.574540558
Short name T687
Test name
Test status
Simulation time 19707688998 ps
CPU time 43.76 seconds
Started Jun 26 04:57:18 PM PDT 24
Finished Jun 26 04:58:03 PM PDT 24
Peak memory 815268 kb
Host smart-70387db7-0a8d-4d6d-b8ce-6fa22c37f486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574540558 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.574540558
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.1703336904
Short name T604
Test name
Test status
Simulation time 9359175994 ps
CPU time 22.99 seconds
Started Jun 26 04:57:14 PM PDT 24
Finished Jun 26 04:57:38 PM PDT 24
Peak memory 204956 kb
Host smart-0f54ada0-8eaf-49c5-8306-fd0eb4c2a728
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703336904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.1703336904
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2005404130
Short name T452
Test name
Test status
Simulation time 3565247331 ps
CPU time 28.25 seconds
Started Jun 26 04:57:10 PM PDT 24
Finished Jun 26 04:57:40 PM PDT 24
Peak memory 204940 kb
Host smart-72dd9d87-de61-4af3-a01d-0ed112bf897e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005404130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2005404130
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.473316319
Short name T628
Test name
Test status
Simulation time 31401828039 ps
CPU time 227.04 seconds
Started Jun 26 04:57:09 PM PDT 24
Finished Jun 26 05:00:57 PM PDT 24
Peak memory 2845892 kb
Host smart-c6b79f51-83f7-41ae-8c44-68c61ff45fcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473316319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c
_target_stress_wr.473316319
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2106608683
Short name T747
Test name
Test status
Simulation time 41618516093 ps
CPU time 438.18 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 05:04:37 PM PDT 24
Peak memory 1588388 kb
Host smart-a6495192-0f42-486d-937f-32075d266566
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106608683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2106608683
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.3909916868
Short name T1440
Test name
Test status
Simulation time 1662488034 ps
CPU time 8.53 seconds
Started Jun 26 04:57:19 PM PDT 24
Finished Jun 26 04:57:29 PM PDT 24
Peak memory 213076 kb
Host smart-e1ce04ca-63e0-478e-8a5f-fdcbf71ab9b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909916868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.3909916868
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2161536204
Short name T574
Test name
Test status
Simulation time 33708156 ps
CPU time 0.6 seconds
Started Jun 26 04:57:25 PM PDT 24
Finished Jun 26 04:57:28 PM PDT 24
Peak memory 204476 kb
Host smart-1b0cdac4-b794-4776-a595-54e2ac93f2af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161536204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2161536204
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1238839697
Short name T724
Test name
Test status
Simulation time 150024354 ps
CPU time 1.33 seconds
Started Jun 26 04:57:23 PM PDT 24
Finished Jun 26 04:57:26 PM PDT 24
Peak memory 213092 kb
Host smart-af433389-4ec0-4807-b770-c5fe386be88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238839697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1238839697
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2855668219
Short name T526
Test name
Test status
Simulation time 2220760538 ps
CPU time 4.25 seconds
Started Jun 26 04:57:18 PM PDT 24
Finished Jun 26 04:57:24 PM PDT 24
Peak memory 245148 kb
Host smart-96b2faec-2b50-473d-8005-46b4a8e58227
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855668219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2855668219
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.360525417
Short name T1036
Test name
Test status
Simulation time 34251210989 ps
CPU time 205.91 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 05:00:49 PM PDT 24
Peak memory 892104 kb
Host smart-a65c9217-7447-4181-8d8c-facf45008707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360525417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.360525417
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.2259881349
Short name T690
Test name
Test status
Simulation time 2007435545 ps
CPU time 68.77 seconds
Started Jun 26 04:57:19 PM PDT 24
Finished Jun 26 04:58:30 PM PDT 24
Peak memory 695488 kb
Host smart-5f2ea90f-08e2-427d-8937-5ba60c86e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259881349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.2259881349
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.723784985
Short name T1044
Test name
Test status
Simulation time 786847375 ps
CPU time 1.15 seconds
Started Jun 26 04:57:16 PM PDT 24
Finished Jun 26 04:57:18 PM PDT 24
Peak memory 204744 kb
Host smart-49bce17a-1dba-4142-a890-98bbbf2bc832
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723784985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.723784985
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.1508110442
Short name T779
Test name
Test status
Simulation time 166458585 ps
CPU time 3.84 seconds
Started Jun 26 04:57:20 PM PDT 24
Finished Jun 26 04:57:26 PM PDT 24
Peak memory 231004 kb
Host smart-b9f50b82-146f-45f3-8fcf-bb9ed0ac9951
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508110442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.1508110442
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.1643281717
Short name T101
Test name
Test status
Simulation time 5451106481 ps
CPU time 128.72 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:59:27 PM PDT 24
Peak memory 1389588 kb
Host smart-e38a5489-59bb-479b-a19c-c1452f968b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643281717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.1643281717
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2904410895
Short name T395
Test name
Test status
Simulation time 825239092 ps
CPU time 23.22 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:57:47 PM PDT 24
Peak memory 204840 kb
Host smart-ce91f2a6-249d-4ed2-8911-5e0c64620917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904410895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2904410895
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.2593018374
Short name T1350
Test name
Test status
Simulation time 2517657243 ps
CPU time 66.12 seconds
Started Jun 26 04:57:20 PM PDT 24
Finished Jun 26 04:58:28 PM PDT 24
Peak memory 332600 kb
Host smart-56d10332-2076-4348-a827-30eab2026595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593018374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.2593018374
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.573646424
Short name T498
Test name
Test status
Simulation time 25005989 ps
CPU time 0.7 seconds
Started Jun 26 04:57:18 PM PDT 24
Finished Jun 26 04:57:20 PM PDT 24
Peak memory 204480 kb
Host smart-0d38badd-a5de-4464-b265-e07441db48f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573646424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.573646424
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.1996997492
Short name T1068
Test name
Test status
Simulation time 42959443 ps
CPU time 1.31 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:57:19 PM PDT 24
Peak memory 224252 kb
Host smart-db8ec69f-c7a6-4256-a68a-f4fd11903cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996997492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.1996997492
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.289657611
Short name T1376
Test name
Test status
Simulation time 6083588933 ps
CPU time 66.67 seconds
Started Jun 26 04:57:25 PM PDT 24
Finished Jun 26 04:58:33 PM PDT 24
Peak memory 276368 kb
Host smart-e0d6d5e8-9d43-4115-a5fb-62d8a162a810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289657611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.289657611
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.704066269
Short name T1052
Test name
Test status
Simulation time 3458769920 ps
CPU time 4.45 seconds
Started Jun 26 04:57:23 PM PDT 24
Finished Jun 26 04:57:29 PM PDT 24
Peak memory 204908 kb
Host smart-2a424080-05ec-4591-bb09-c10c9c006065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704066269 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.704066269
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2499614273
Short name T375
Test name
Test status
Simulation time 204794531 ps
CPU time 1.34 seconds
Started Jun 26 04:57:20 PM PDT 24
Finished Jun 26 04:57:23 PM PDT 24
Peak memory 204784 kb
Host smart-be469748-da5a-428c-b9ee-37a19175c887
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499614273 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2499614273
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2718273735
Short name T754
Test name
Test status
Simulation time 216636961 ps
CPU time 1.39 seconds
Started Jun 26 04:57:20 PM PDT 24
Finished Jun 26 04:57:23 PM PDT 24
Peak memory 204816 kb
Host smart-95b4f92a-e7ba-43a8-81ba-2b381426a9cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718273735 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2718273735
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.1312169225
Short name T495
Test name
Test status
Simulation time 2424226687 ps
CPU time 3.1 seconds
Started Jun 26 04:57:18 PM PDT 24
Finished Jun 26 04:57:22 PM PDT 24
Peak memory 204928 kb
Host smart-857cf536-8e15-4fcb-abae-f4e621558e9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312169225 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.1312169225
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.1365062956
Short name T727
Test name
Test status
Simulation time 337542715 ps
CPU time 1.22 seconds
Started Jun 26 04:57:23 PM PDT 24
Finished Jun 26 04:57:26 PM PDT 24
Peak memory 204612 kb
Host smart-42a8d41f-3db4-4940-978e-d66f3b682915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365062956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.1365062956
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.933525311
Short name T462
Test name
Test status
Simulation time 323976209 ps
CPU time 2.57 seconds
Started Jun 26 04:57:18 PM PDT 24
Finished Jun 26 04:57:22 PM PDT 24
Peak memory 204856 kb
Host smart-9effc30c-f3e2-495f-8b10-cd58f8f00cf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933525311 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.933525311
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.1836909714
Short name T635
Test name
Test status
Simulation time 914311207 ps
CPU time 5.02 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:57:28 PM PDT 24
Peak memory 213120 kb
Host smart-0e5bbb6e-b88f-4e7a-9c26-a689ad38c0ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836909714 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.1836909714
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.695944658
Short name T1414
Test name
Test status
Simulation time 898131283 ps
CPU time 13.18 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:57:31 PM PDT 24
Peak memory 204756 kb
Host smart-ab4acd8a-7028-48a0-98bd-4dd31cce7b48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695944658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.695944658
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.2815784301
Short name T882
Test name
Test status
Simulation time 2972258206 ps
CPU time 11.84 seconds
Started Jun 26 04:57:26 PM PDT 24
Finished Jun 26 04:57:40 PM PDT 24
Peak memory 214776 kb
Host smart-67a3ceba-0058-4050-b36f-4942044c51cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815784301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.2815784301
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1947940187
Short name T780
Test name
Test status
Simulation time 17015002582 ps
CPU time 31.16 seconds
Started Jun 26 04:57:22 PM PDT 24
Finished Jun 26 04:57:55 PM PDT 24
Peak memory 204920 kb
Host smart-b7a6005f-daea-4c53-8646-f594010d6189
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947940187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1947940187
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.3367299299
Short name T1046
Test name
Test status
Simulation time 2673935934 ps
CPU time 7.63 seconds
Started Jun 26 04:57:19 PM PDT 24
Finished Jun 26 04:57:28 PM PDT 24
Peak memory 218192 kb
Host smart-565585ec-4d91-451e-909c-ca32c4501f7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367299299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.3367299299
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.3417703255
Short name T158
Test name
Test status
Simulation time 83462887 ps
CPU time 0.63 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:31 PM PDT 24
Peak memory 204424 kb
Host smart-59eda419-43a2-4b03-b19c-3bc9e6b893fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417703255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.3417703255
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.3228992183
Short name T612
Test name
Test status
Simulation time 345376395 ps
CPU time 1.9 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:32 PM PDT 24
Peak memory 213072 kb
Host smart-309cb827-e4f4-40bb-af0f-61f56109e60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228992183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.3228992183
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.467686110
Short name T634
Test name
Test status
Simulation time 395112556 ps
CPU time 4.24 seconds
Started Jun 26 04:57:26 PM PDT 24
Finished Jun 26 04:57:33 PM PDT 24
Peak memory 242136 kb
Host smart-71ffed33-90c2-44aa-84d1-6474b9da7553
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467686110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.467686110
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3799392477
Short name T537
Test name
Test status
Simulation time 1312800950 ps
CPU time 44.13 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:58:07 PM PDT 24
Peak memory 531652 kb
Host smart-bebbedf4-4fa2-42a7-a6c3-87419df524cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799392477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3799392477
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.923959530
Short name T854
Test name
Test status
Simulation time 10274826234 ps
CPU time 132.85 seconds
Started Jun 26 04:57:26 PM PDT 24
Finished Jun 26 04:59:40 PM PDT 24
Peak memory 642172 kb
Host smart-c1da2a69-f1b0-4f64-bbdb-ca06e932a809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923959530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.923959530
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.919193748
Short name T988
Test name
Test status
Simulation time 446332921 ps
CPU time 0.91 seconds
Started Jun 26 04:57:26 PM PDT 24
Finished Jun 26 04:57:29 PM PDT 24
Peak memory 204536 kb
Host smart-69cba375-08b7-4b53-aa69-e52b3b1b1f4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919193748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.919193748
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1260094438
Short name T473
Test name
Test status
Simulation time 1711336654 ps
CPU time 7.45 seconds
Started Jun 26 04:57:17 PM PDT 24
Finished Jun 26 04:57:25 PM PDT 24
Peak memory 226924 kb
Host smart-4a15a5a7-8c9e-4894-9039-524e3f8eae53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260094438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1260094438
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.1336538567
Short name T1164
Test name
Test status
Simulation time 19783464167 ps
CPU time 121.73 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:59:25 PM PDT 24
Peak memory 1191616 kb
Host smart-adc27ac0-1192-4d6e-9b71-814a36e4de17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336538567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.1336538567
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1146364568
Short name T1053
Test name
Test status
Simulation time 390100290 ps
CPU time 15.37 seconds
Started Jun 26 04:57:38 PM PDT 24
Finished Jun 26 04:57:57 PM PDT 24
Peak memory 204856 kb
Host smart-bcb4c81d-1bdc-4c5f-8aea-fcb9b13b79e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146364568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1146364568
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3994538038
Short name T60
Test name
Test status
Simulation time 4805770785 ps
CPU time 63.5 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:58:35 PM PDT 24
Peak memory 331648 kb
Host smart-38214c9e-7eff-4e57-8f6f-a104d3146066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994538038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3994538038
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1041136377
Short name T1091
Test name
Test status
Simulation time 27320488 ps
CPU time 0.64 seconds
Started Jun 26 04:57:23 PM PDT 24
Finished Jun 26 04:57:25 PM PDT 24
Peak memory 204536 kb
Host smart-761ab48f-b3b5-44a1-bd1f-765dd9f663ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041136377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1041136377
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.2143500796
Short name T723
Test name
Test status
Simulation time 6279148554 ps
CPU time 86.69 seconds
Started Jun 26 04:57:26 PM PDT 24
Finished Jun 26 04:58:54 PM PDT 24
Peak memory 560572 kb
Host smart-d69b7a07-79ba-4152-b9e0-912ce16ba909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143500796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.2143500796
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.2056619398
Short name T1470
Test name
Test status
Simulation time 69051560 ps
CPU time 1.45 seconds
Started Jun 26 04:57:20 PM PDT 24
Finished Jun 26 04:57:23 PM PDT 24
Peak memory 222564 kb
Host smart-4b5f52ff-c045-4e7f-a668-4195c10b7444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056619398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.2056619398
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1974606038
Short name T347
Test name
Test status
Simulation time 6632936921 ps
CPU time 23.47 seconds
Started Jun 26 04:57:21 PM PDT 24
Finished Jun 26 04:57:47 PM PDT 24
Peak memory 305668 kb
Host smart-2009eb82-8fd0-4aa3-b904-d8c84c802e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974606038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1974606038
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.325986035
Short name T1058
Test name
Test status
Simulation time 686125916 ps
CPU time 30.63 seconds
Started Jun 26 04:57:30 PM PDT 24
Finished Jun 26 04:58:03 PM PDT 24
Peak memory 213052 kb
Host smart-cdc9364c-1f4e-4fc6-9210-e427cb1a3b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325986035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.325986035
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.1441034844
Short name T1004
Test name
Test status
Simulation time 2634316897 ps
CPU time 2.87 seconds
Started Jun 26 04:57:32 PM PDT 24
Finished Jun 26 04:57:38 PM PDT 24
Peak memory 213184 kb
Host smart-9b39a2c6-f241-48fb-b4e5-81181b41d202
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441034844 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.1441034844
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3787951881
Short name T848
Test name
Test status
Simulation time 132057353 ps
CPU time 1 seconds
Started Jun 26 04:57:30 PM PDT 24
Finished Jun 26 04:57:34 PM PDT 24
Peak memory 204552 kb
Host smart-27c628ef-7c71-4020-86e3-71e8829cfb83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787951881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3787951881
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.1874090274
Short name T1001
Test name
Test status
Simulation time 382409487 ps
CPU time 1.4 seconds
Started Jun 26 04:57:30 PM PDT 24
Finished Jun 26 04:57:34 PM PDT 24
Peak memory 204820 kb
Host smart-e771676b-8d29-49c6-86d7-af3c82335a2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874090274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.1874090274
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.1432478860
Short name T656
Test name
Test status
Simulation time 1009787609 ps
CPU time 2.64 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 04:57:36 PM PDT 24
Peak memory 204656 kb
Host smart-3865c374-8b46-4461-932c-e9975f615ac8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432478860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.1432478860
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.516764926
Short name T952
Test name
Test status
Simulation time 188578375 ps
CPU time 1.25 seconds
Started Jun 26 04:57:27 PM PDT 24
Finished Jun 26 04:57:30 PM PDT 24
Peak memory 204592 kb
Host smart-0650e018-0e7d-425a-b1ab-6c00c2bf9d7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516764926 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.516764926
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.62187125
Short name T712
Test name
Test status
Simulation time 382784072 ps
CPU time 3.09 seconds
Started Jun 26 04:57:38 PM PDT 24
Finished Jun 26 04:57:45 PM PDT 24
Peak memory 204840 kb
Host smart-f42394d5-2e05-4885-8faf-3b6651924199
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62187125 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 17.i2c_target_hrst.62187125
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2140581453
Short name T824
Test name
Test status
Simulation time 2019845068 ps
CPU time 5.57 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:36 PM PDT 24
Peak memory 214160 kb
Host smart-76a8b147-75c1-44ba-b8a7-f1c5e7df9089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140581453 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2140581453
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.717887289
Short name T1079
Test name
Test status
Simulation time 6367837905 ps
CPU time 3.45 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:34 PM PDT 24
Peak memory 204884 kb
Host smart-05ded86f-1c15-469c-8350-10dac138b8df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717887289 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.717887289
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.1417350615
Short name T85
Test name
Test status
Simulation time 2620224867 ps
CPU time 24.58 seconds
Started Jun 26 04:57:27 PM PDT 24
Finished Jun 26 04:57:54 PM PDT 24
Peak memory 204952 kb
Host smart-bad14706-a532-4025-ac43-2b7493d516a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417350615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.1417350615
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.453082691
Short name T1023
Test name
Test status
Simulation time 852283649 ps
CPU time 35.05 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 04:58:09 PM PDT 24
Peak memory 204820 kb
Host smart-8811dc16-68b3-41a9-b751-aab9daae4eaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453082691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_rd.453082691
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.2375415301
Short name T332
Test name
Test status
Simulation time 9674470624 ps
CPU time 5.27 seconds
Started Jun 26 04:57:27 PM PDT 24
Finished Jun 26 04:57:35 PM PDT 24
Peak memory 204964 kb
Host smart-2353e415-2714-4ab9-b2e9-37e05fdf0bc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375415301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.2375415301
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1503441027
Short name T606
Test name
Test status
Simulation time 36539367677 ps
CPU time 2237.86 seconds
Started Jun 26 04:57:26 PM PDT 24
Finished Jun 26 05:34:47 PM PDT 24
Peak memory 8700416 kb
Host smart-554c4772-e333-4100-926a-a444371032a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503441027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1503441027
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3858851474
Short name T1308
Test name
Test status
Simulation time 5462330316 ps
CPU time 6.6 seconds
Started Jun 26 04:57:27 PM PDT 24
Finished Jun 26 04:57:36 PM PDT 24
Peak memory 204980 kb
Host smart-42a3f302-efeb-42dd-b8c6-c91b8e21e860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858851474 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3858851474
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3549046670
Short name T454
Test name
Test status
Simulation time 54389391 ps
CPU time 0.61 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:31 PM PDT 24
Peak memory 204500 kb
Host smart-b8131b85-6ebc-420b-92fb-5c1f5f2447c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549046670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3549046670
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.456157545
Short name T861
Test name
Test status
Simulation time 498511634 ps
CPU time 1.88 seconds
Started Jun 26 04:57:43 PM PDT 24
Finished Jun 26 04:57:46 PM PDT 24
Peak memory 213092 kb
Host smart-90608f12-f64a-4ee6-82d3-37943d2fd2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456157545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.456157545
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.3521086251
Short name T638
Test name
Test status
Simulation time 372110036 ps
CPU time 20.16 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:51 PM PDT 24
Peak memory 284936 kb
Host smart-364488b4-6bad-4e6e-ada5-a2fca60c3bad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521086251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.3521086251
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1879141781
Short name T1377
Test name
Test status
Simulation time 11853693519 ps
CPU time 84 seconds
Started Jun 26 04:57:30 PM PDT 24
Finished Jun 26 04:58:57 PM PDT 24
Peak memory 859296 kb
Host smart-2c6b5907-5d74-4e2f-82de-b786031272e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879141781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1879141781
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2139178534
Short name T1205
Test name
Test status
Simulation time 1598208510 ps
CPU time 45.14 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:58:16 PM PDT 24
Peak memory 596360 kb
Host smart-81412876-c84f-4d75-8420-27c9c2d34e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139178534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2139178534
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2182822603
Short name T1283
Test name
Test status
Simulation time 331265076 ps
CPU time 0.83 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 04:57:35 PM PDT 24
Peak memory 204560 kb
Host smart-ed21491b-ca21-4812-90fd-ee027f3b5f72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182822603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2182822603
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.984930399
Short name T816
Test name
Test status
Simulation time 889643992 ps
CPU time 3.43 seconds
Started Jun 26 04:57:38 PM PDT 24
Finished Jun 26 04:57:45 PM PDT 24
Peak memory 204828 kb
Host smart-c14f1110-341c-4af2-854d-7291c8be47ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984930399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx.
984930399
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.4202948962
Short name T608
Test name
Test status
Simulation time 6495485788 ps
CPU time 83.87 seconds
Started Jun 26 04:57:25 PM PDT 24
Finished Jun 26 04:58:51 PM PDT 24
Peak memory 972944 kb
Host smart-8e5d9d8a-d926-49ab-a612-87061be8b5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202948962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.4202948962
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.1414723460
Short name T1137
Test name
Test status
Simulation time 944953929 ps
CPU time 5.63 seconds
Started Jun 26 04:57:32 PM PDT 24
Finished Jun 26 04:57:40 PM PDT 24
Peak memory 204828 kb
Host smart-8b39c770-1439-468f-8c15-2cfee2caa51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414723460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1414723460
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.3101054851
Short name T941
Test name
Test status
Simulation time 6309623023 ps
CPU time 30.03 seconds
Started Jun 26 04:57:30 PM PDT 24
Finished Jun 26 04:58:03 PM PDT 24
Peak memory 343164 kb
Host smart-13f595c6-6cfd-4072-bcb3-2cfc67edd88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101054851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.3101054851
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.3714016228
Short name T126
Test name
Test status
Simulation time 52707582 ps
CPU time 0.63 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 04:57:35 PM PDT 24
Peak memory 204560 kb
Host smart-d6a4e045-95d8-4489-9723-eb1cb7223dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714016228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.3714016228
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.1819857281
Short name T599
Test name
Test status
Simulation time 3071618618 ps
CPU time 14.73 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:46 PM PDT 24
Peak memory 222248 kb
Host smart-b93084da-5fb4-4918-9d96-a2376ca93c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819857281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.1819857281
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.2102328497
Short name T450
Test name
Test status
Simulation time 323658103 ps
CPU time 1.36 seconds
Started Jun 26 04:57:29 PM PDT 24
Finished Jun 26 04:57:33 PM PDT 24
Peak memory 213208 kb
Host smart-6a49352d-7ec4-44c5-ab68-a7da6f549429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102328497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.2102328497
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.4064007218
Short name T637
Test name
Test status
Simulation time 6791725199 ps
CPU time 30.21 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:58:01 PM PDT 24
Peak memory 295492 kb
Host smart-bf7affe3-6d53-413c-9b15-3ec1f0896443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064007218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.4064007218
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.544292685
Short name T144
Test name
Test status
Simulation time 782619914 ps
CPU time 6.55 seconds
Started Jun 26 04:57:29 PM PDT 24
Finished Jun 26 04:57:39 PM PDT 24
Peak memory 220272 kb
Host smart-eb82edd3-8032-4aaf-9005-5567bddd7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544292685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.544292685
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.3693599747
Short name T645
Test name
Test status
Simulation time 2407095446 ps
CPU time 4.55 seconds
Started Jun 26 04:57:27 PM PDT 24
Finished Jun 26 04:57:34 PM PDT 24
Peak memory 213172 kb
Host smart-e822936c-9a35-40dc-b113-92bc8d6d36dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693599747 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.3693599747
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.531635603
Short name T865
Test name
Test status
Simulation time 209420599 ps
CPU time 1.28 seconds
Started Jun 26 04:57:32 PM PDT 24
Finished Jun 26 04:57:36 PM PDT 24
Peak memory 204616 kb
Host smart-dcf0a626-4b6f-446d-892a-6048d06a8f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531635603 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.531635603
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.405138315
Short name T399
Test name
Test status
Simulation time 344526181 ps
CPU time 1.13 seconds
Started Jun 26 04:57:29 PM PDT 24
Finished Jun 26 04:57:33 PM PDT 24
Peak memory 204492 kb
Host smart-8fe44bab-2c70-4d50-8509-b733aad0fac5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405138315 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.i2c_target_fifo_reset_tx.405138315
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.980065976
Short name T937
Test name
Test status
Simulation time 1583214293 ps
CPU time 1.97 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 04:57:36 PM PDT 24
Peak memory 204808 kb
Host smart-aa612663-8902-4aab-83ab-bb2ce1117585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980065976 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.980065976
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.929002070
Short name T324
Test name
Test status
Simulation time 203597094 ps
CPU time 0.83 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:32 PM PDT 24
Peak memory 204620 kb
Host smart-11e4938e-8011-428e-bfb7-694164f1be66
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929002070 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.929002070
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.3009948317
Short name T584
Test name
Test status
Simulation time 741438104 ps
CPU time 3.31 seconds
Started Jun 26 04:57:27 PM PDT 24
Finished Jun 26 04:57:33 PM PDT 24
Peak memory 204788 kb
Host smart-eb36eaf6-389b-4273-af4b-c1b797a25be7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009948317 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.3009948317
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.3859588399
Short name T1141
Test name
Test status
Simulation time 1207339879 ps
CPU time 6.49 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 04:57:40 PM PDT 24
Peak memory 217704 kb
Host smart-bc63021c-f051-427c-b7f6-5d90da69be42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859588399 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.3859588399
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2786214365
Short name T239
Test name
Test status
Simulation time 14842025733 ps
CPU time 20.04 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:51 PM PDT 24
Peak memory 604228 kb
Host smart-9908c35e-ec35-4092-868c-9a99424e314d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786214365 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2786214365
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.270545265
Short name T716
Test name
Test status
Simulation time 3361197801 ps
CPU time 10.32 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 04:57:44 PM PDT 24
Peak memory 204696 kb
Host smart-4b9d7c6c-26af-48f4-9ec3-28b59d71be5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270545265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.270545265
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.4139076231
Short name T792
Test name
Test status
Simulation time 1391017623 ps
CPU time 22.5 seconds
Started Jun 26 04:58:13 PM PDT 24
Finished Jun 26 04:58:38 PM PDT 24
Peak memory 217652 kb
Host smart-5401f9aa-4a28-495a-98d9-fb1f3a9c3e5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139076231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.4139076231
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1507961850
Short name T453
Test name
Test status
Simulation time 11060724750 ps
CPU time 6.41 seconds
Started Jun 26 04:57:26 PM PDT 24
Finished Jun 26 04:57:34 PM PDT 24
Peak memory 204936 kb
Host smart-a50b44f6-6d05-4ca5-a7a3-a2f15ea6d508
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507961850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1507961850
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1676718340
Short name T1159
Test name
Test status
Simulation time 9727504248 ps
CPU time 860.14 seconds
Started Jun 26 04:57:31 PM PDT 24
Finished Jun 26 05:11:54 PM PDT 24
Peak memory 2401292 kb
Host smart-0aa513b0-e107-4ec5-8302-3d90e8f6a241
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676718340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1676718340
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.2679652567
Short name T1351
Test name
Test status
Simulation time 1354674129 ps
CPU time 7.14 seconds
Started Jun 26 04:57:28 PM PDT 24
Finished Jun 26 04:57:38 PM PDT 24
Peak memory 212520 kb
Host smart-61903cac-8bc1-4f0a-aa6b-ab35534734e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679652567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.2679652567
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1383218775
Short name T503
Test name
Test status
Simulation time 46793222 ps
CPU time 0.62 seconds
Started Jun 26 04:57:47 PM PDT 24
Finished Jun 26 04:57:51 PM PDT 24
Peak memory 204512 kb
Host smart-1b3e42df-cbeb-4f0e-a12a-b4af8df30e9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383218775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1383218775
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.375867870
Short name T992
Test name
Test status
Simulation time 318758849 ps
CPU time 2.64 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 04:57:39 PM PDT 24
Peak memory 213116 kb
Host smart-1710e519-c390-4fcf-938e-67fafdcdadfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375867870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.375867870
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1065998852
Short name T772
Test name
Test status
Simulation time 989553356 ps
CPU time 6.12 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 04:57:43 PM PDT 24
Peak memory 258008 kb
Host smart-c5dc2d02-8015-46d5-8577-784cdfaf9b63
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065998852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1065998852
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.884268267
Short name T857
Test name
Test status
Simulation time 8321019817 ps
CPU time 134.16 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:59:54 PM PDT 24
Peak memory 683144 kb
Host smart-d3e68ec9-a351-4f4f-82f3-f9eafcff9806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884268267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.884268267
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.3615029020
Short name T1295
Test name
Test status
Simulation time 31167281592 ps
CPU time 169.7 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 05:00:26 PM PDT 24
Peak memory 747908 kb
Host smart-caf44df7-f786-4813-b1dd-901cd0191c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615029020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.3615029020
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.951856976
Short name T346
Test name
Test status
Simulation time 491585163 ps
CPU time 1.04 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 04:57:38 PM PDT 24
Peak memory 204560 kb
Host smart-dec5b7f1-02ad-42c6-8866-9366577276d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951856976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fm
t.951856976
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.368835464
Short name T1281
Test name
Test status
Simulation time 635068857 ps
CPU time 4.08 seconds
Started Jun 26 04:57:38 PM PDT 24
Finished Jun 26 04:57:46 PM PDT 24
Peak memory 233780 kb
Host smart-538a9263-1c62-47ab-af5f-4c701013a18d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368835464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
368835464
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.1942163918
Short name T99
Test name
Test status
Simulation time 3293796828 ps
CPU time 70.79 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 04:58:47 PM PDT 24
Peak memory 1023988 kb
Host smart-b34b09a1-9780-495e-bc2c-0276abe3233b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942163918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.1942163918
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.7184211
Short name T400
Test name
Test status
Simulation time 1780036264 ps
CPU time 5.59 seconds
Started Jun 26 04:57:47 PM PDT 24
Finished Jun 26 04:57:56 PM PDT 24
Peak memory 204864 kb
Host smart-d445ef57-db18-46ad-9c9f-d0700e569e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7184211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.7184211
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2448053688
Short name T267
Test name
Test status
Simulation time 14704632841 ps
CPU time 45.73 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:58:27 PM PDT 24
Peak memory 519484 kb
Host smart-a051e746-0deb-4155-a645-32c661efa9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448053688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2448053688
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.1177275292
Short name T1247
Test name
Test status
Simulation time 89665326 ps
CPU time 0.66 seconds
Started Jun 26 04:57:39 PM PDT 24
Finished Jun 26 04:57:43 PM PDT 24
Peak memory 204560 kb
Host smart-5ffb1ecd-de67-4d9d-a835-73588ba8bd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177275292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1177275292
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.8286934
Short name T958
Test name
Test status
Simulation time 25416392488 ps
CPU time 1218.31 seconds
Started Jun 26 04:57:34 PM PDT 24
Finished Jun 26 05:17:54 PM PDT 24
Peak memory 438720 kb
Host smart-deb497f7-5701-4494-8602-59144f8e2df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8286934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.8286934
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.1325270716
Short name T1089
Test name
Test status
Simulation time 176284374 ps
CPU time 1.61 seconds
Started Jun 26 04:57:36 PM PDT 24
Finished Jun 26 04:57:40 PM PDT 24
Peak memory 212952 kb
Host smart-bd482182-0d26-4e9a-a8d3-8305d354f74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325270716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.1325270716
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.4202771203
Short name T1428
Test name
Test status
Simulation time 2060476361 ps
CPU time 98.57 seconds
Started Jun 26 04:57:38 PM PDT 24
Finished Jun 26 04:59:20 PM PDT 24
Peak memory 335204 kb
Host smart-c73abd3e-a47f-44bb-aad9-3a25d11cec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202771203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.4202771203
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3662353061
Short name T691
Test name
Test status
Simulation time 972562697 ps
CPU time 7.9 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 04:57:44 PM PDT 24
Peak memory 214452 kb
Host smart-2ca26118-89dc-4651-81be-924b197c8b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662353061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3662353061
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1967868644
Short name T355
Test name
Test status
Simulation time 1526582098 ps
CPU time 4.02 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 04:57:41 PM PDT 24
Peak memory 204824 kb
Host smart-2b0c9995-263d-4981-91de-b4fcbe6c0e4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967868644 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1967868644
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.2196883865
Short name T13
Test name
Test status
Simulation time 734520819 ps
CPU time 1.27 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:57:42 PM PDT 24
Peak memory 204732 kb
Host smart-4fe2195d-229f-4c4f-91fa-5f5dc6520158
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196883865 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.2196883865
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1526510219
Short name T1213
Test name
Test status
Simulation time 216321325 ps
CPU time 1.33 seconds
Started Jun 26 04:57:39 PM PDT 24
Finished Jun 26 04:57:44 PM PDT 24
Peak memory 204796 kb
Host smart-abcf2377-d9c7-4234-90f8-2884759f121e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526510219 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1526510219
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.3874256770
Short name T719
Test name
Test status
Simulation time 638829032 ps
CPU time 2.8 seconds
Started Jun 26 04:57:34 PM PDT 24
Finished Jun 26 04:57:39 PM PDT 24
Peak memory 204820 kb
Host smart-8d657372-992f-446a-ad97-8996a116be26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874256770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.3874256770
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.4112237854
Short name T29
Test name
Test status
Simulation time 465134268 ps
CPU time 1.17 seconds
Started Jun 26 04:57:34 PM PDT 24
Finished Jun 26 04:57:37 PM PDT 24
Peak memory 204636 kb
Host smart-26456868-fe7d-4909-a65e-4ee283e7c4ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112237854 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.4112237854
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.3408675983
Short name T190
Test name
Test status
Simulation time 1983212065 ps
CPU time 3.98 seconds
Started Jun 26 04:57:38 PM PDT 24
Finished Jun 26 04:57:45 PM PDT 24
Peak memory 204788 kb
Host smart-af347cec-552d-4bbb-ab14-2e3065b420b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408675983 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.3408675983
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.4293390203
Short name T26
Test name
Test status
Simulation time 14722500044 ps
CPU time 145.22 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 05:00:02 PM PDT 24
Peak memory 2040944 kb
Host smart-ecb343ce-f708-48e0-936f-c78be9a68cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293390203 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.4293390203
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.552892689
Short name T499
Test name
Test status
Simulation time 1719920550 ps
CPU time 12.73 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 04:58:02 PM PDT 24
Peak memory 204860 kb
Host smart-8cddd133-37ef-4284-b059-d13e20549b92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552892689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.552892689
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.3026795627
Short name T1265
Test name
Test status
Simulation time 1138607528 ps
CPU time 20.56 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:58:09 PM PDT 24
Peak memory 213952 kb
Host smart-ad589b65-454f-41af-a20f-c99ce7eb8273
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026795627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.3026795627
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1218509055
Short name T508
Test name
Test status
Simulation time 44489411617 ps
CPU time 23.55 seconds
Started Jun 26 04:57:36 PM PDT 24
Finished Jun 26 04:58:01 PM PDT 24
Peak memory 536140 kb
Host smart-0e0d3be6-38a6-466d-979d-22a6c88026e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218509055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1218509055
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.212675824
Short name T1339
Test name
Test status
Simulation time 40048369007 ps
CPU time 726.29 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 05:09:47 PM PDT 24
Peak memory 4647596 kb
Host smart-203f91f4-e557-46bf-8b93-596c1cf6c294
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212675824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_t
arget_stretch.212675824
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2314567691
Short name T825
Test name
Test status
Simulation time 5158641758 ps
CPU time 7.04 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:57:47 PM PDT 24
Peak memory 217716 kb
Host smart-370d6999-a3d2-4fa9-8e93-6b40fa0959cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314567691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2314567691
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.4226348815
Short name T458
Test name
Test status
Simulation time 31423390 ps
CPU time 0.67 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:51 PM PDT 24
Peak memory 204448 kb
Host smart-7dd1a821-082f-415b-80a9-6e98810b9a39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226348815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.4226348815
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.1995653433
Short name T485
Test name
Test status
Simulation time 142660052 ps
CPU time 1.88 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:04 PM PDT 24
Peak memory 212964 kb
Host smart-2e489023-4a39-4c01-9428-53a185fa1b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995653433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.1995653433
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2616238427
Short name T433
Test name
Test status
Simulation time 549235399 ps
CPU time 2.74 seconds
Started Jun 26 04:55:52 PM PDT 24
Finished Jun 26 04:55:57 PM PDT 24
Peak memory 227984 kb
Host smart-56100321-f68d-4095-86ad-fe94d272c19b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616238427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2616238427
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3215707840
Short name T560
Test name
Test status
Simulation time 2102707882 ps
CPU time 146.04 seconds
Started Jun 26 04:55:48 PM PDT 24
Finished Jun 26 04:58:17 PM PDT 24
Peak memory 705968 kb
Host smart-172a6ea2-15ac-4884-8af5-6555f7cedd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215707840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3215707840
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.2166215158
Short name T787
Test name
Test status
Simulation time 13638856674 ps
CPU time 116.95 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:57:58 PM PDT 24
Peak memory 616760 kb
Host smart-4e2abbce-4434-4797-8279-c9b680aba48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166215158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.2166215158
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.133915192
Short name T1264
Test name
Test status
Simulation time 178856226 ps
CPU time 0.85 seconds
Started Jun 26 04:55:51 PM PDT 24
Finished Jun 26 04:55:54 PM PDT 24
Peak memory 204576 kb
Host smart-35b54b3f-289b-4433-af42-0e97d3573f32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133915192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.133915192
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3163551057
Short name T862
Test name
Test status
Simulation time 981731964 ps
CPU time 10.17 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:16 PM PDT 24
Peak memory 236416 kb
Host smart-a8ba885a-1e29-49f8-999a-42cc040b2bbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163551057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3163551057
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3827544291
Short name T96
Test name
Test status
Simulation time 23683852967 ps
CPU time 135.44 seconds
Started Jun 26 04:55:51 PM PDT 24
Finished Jun 26 04:58:09 PM PDT 24
Peak memory 1459820 kb
Host smart-d6d1088e-2978-4af8-9bdf-beebfa731db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827544291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3827544291
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.3624328339
Short name T868
Test name
Test status
Simulation time 1067468124 ps
CPU time 6.53 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:57 PM PDT 24
Peak memory 204836 kb
Host smart-10ed91c0-89a7-4bd1-8999-8a557ed90400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624328339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.3624328339
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.3045501536
Short name T1263
Test name
Test status
Simulation time 2432150422 ps
CPU time 51.44 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:56:41 PM PDT 24
Peak memory 467932 kb
Host smart-f970baca-3ea0-4ea8-91e5-9215f0be831d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045501536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.3045501536
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.822851231
Short name T1291
Test name
Test status
Simulation time 18483934 ps
CPU time 0.67 seconds
Started Jun 26 04:55:51 PM PDT 24
Finished Jun 26 04:55:54 PM PDT 24
Peak memory 204472 kb
Host smart-1a9c1459-269b-4ac4-b6ff-26efbee0141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822851231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.822851231
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1242746196
Short name T832
Test name
Test status
Simulation time 2644339606 ps
CPU time 23.29 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:25 PM PDT 24
Peak memory 445088 kb
Host smart-1ca332f9-5433-4574-95da-93f40cb769c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242746196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1242746196
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.1313561880
Short name T357
Test name
Test status
Simulation time 2556925931 ps
CPU time 24.46 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:56:14 PM PDT 24
Peak memory 222436 kb
Host smart-2eb8f186-4266-47cd-9b5f-28b06a08acda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313561880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.1313561880
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.3542265470
Short name T1026
Test name
Test status
Simulation time 4681239823 ps
CPU time 15.01 seconds
Started Jun 26 04:55:52 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 264532 kb
Host smart-dbcc78fe-8f5b-4cc7-bf1f-4354d5cece6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542265470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.3542265470
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.193851067
Short name T53
Test name
Test status
Simulation time 215870065783 ps
CPU time 895.28 seconds
Started Jun 26 04:55:50 PM PDT 24
Finished Jun 26 05:10:48 PM PDT 24
Peak memory 3212952 kb
Host smart-f754e7e8-695e-4e50-ac6c-6844ae03ef47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193851067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.193851067
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3892127264
Short name T1400
Test name
Test status
Simulation time 1677303160 ps
CPU time 38.68 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:56:29 PM PDT 24
Peak memory 213028 kb
Host smart-0b9b83c2-b9be-4b9e-b31a-f1cffaa76fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892127264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3892127264
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.471046670
Short name T161
Test name
Test status
Simulation time 302069009 ps
CPU time 0.94 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:55:49 PM PDT 24
Peak memory 223236 kb
Host smart-d0b5656b-24df-400d-8a4b-2ce542c9d722
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471046670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.471046670
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.2344509828
Short name T24
Test name
Test status
Simulation time 1348051035 ps
CPU time 3.36 seconds
Started Jun 26 04:55:55 PM PDT 24
Finished Jun 26 04:56:01 PM PDT 24
Peak memory 213040 kb
Host smart-d6926c9d-d9c5-45ed-be1f-1aa29d4e82b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344509828 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.2344509828
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.2239555155
Short name T225
Test name
Test status
Simulation time 175998554 ps
CPU time 1.1 seconds
Started Jun 26 04:55:55 PM PDT 24
Finished Jun 26 04:55:58 PM PDT 24
Peak memory 204628 kb
Host smart-cc8bfb18-b0c5-47f3-a78a-92cbe72f670e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239555155 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.2239555155
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.2337522051
Short name T1129
Test name
Test status
Simulation time 346741226 ps
CPU time 0.91 seconds
Started Jun 26 04:55:53 PM PDT 24
Finished Jun 26 04:55:55 PM PDT 24
Peak memory 204632 kb
Host smart-cc3afc1a-b7ab-43a3-bf62-56adf4877de8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337522051 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.2337522051
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.2089204050
Short name T701
Test name
Test status
Simulation time 6252472962 ps
CPU time 2.65 seconds
Started Jun 26 04:55:56 PM PDT 24
Finished Jun 26 04:56:01 PM PDT 24
Peak memory 204852 kb
Host smart-ee9931ac-a0ed-43ba-9620-55b5f82adeee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089204050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.2089204050
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.2673799439
Short name T1151
Test name
Test status
Simulation time 96291557 ps
CPU time 0.98 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:03 PM PDT 24
Peak memory 204608 kb
Host smart-5f0d8248-6de7-458e-9299-abe967fa4cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673799439 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.2673799439
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.2972983736
Short name T496
Test name
Test status
Simulation time 901286492 ps
CPU time 2.23 seconds
Started Jun 26 04:55:49 PM PDT 24
Finished Jun 26 04:55:54 PM PDT 24
Peak memory 204856 kb
Host smart-0c8992f0-1bed-496a-bedf-ecbbf108c138
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972983736 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.2972983736
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2825061121
Short name T1278
Test name
Test status
Simulation time 2351255129 ps
CPU time 6.94 seconds
Started Jun 26 04:55:48 PM PDT 24
Finished Jun 26 04:55:58 PM PDT 24
Peak memory 214988 kb
Host smart-80d4a33f-2a17-4b2b-920b-05e64b52ea54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825061121 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2825061121
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.4277440196
Short name T1103
Test name
Test status
Simulation time 12621659122 ps
CPU time 5.8 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:55:54 PM PDT 24
Peak memory 307504 kb
Host smart-a2510732-73e8-4f68-a75f-45ad08688d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277440196 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.4277440196
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1060459477
Short name T137
Test name
Test status
Simulation time 909446981 ps
CPU time 14.13 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 204560 kb
Host smart-c3095717-7982-4a70-8ecf-bc0c84ba068b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060459477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1060459477
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1944578137
Short name T377
Test name
Test status
Simulation time 4029500798 ps
CPU time 43.94 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:45 PM PDT 24
Peak memory 205292 kb
Host smart-59ad0164-bf4d-439d-a061-e0f8eb294362
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944578137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1944578137
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1662838409
Short name T306
Test name
Test status
Simulation time 10754521393 ps
CPU time 18.63 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:56:06 PM PDT 24
Peak memory 204932 kb
Host smart-e8acee44-23b7-4f64-af4d-24a986766d71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662838409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1662838409
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.4101417228
Short name T383
Test name
Test status
Simulation time 4116848305 ps
CPU time 92.97 seconds
Started Jun 26 04:55:51 PM PDT 24
Finished Jun 26 04:57:27 PM PDT 24
Peak memory 1097076 kb
Host smart-55749c3b-7a4c-42c3-a5f2-cfe143dd8e28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101417228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.4101417228
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3053587370
Short name T1077
Test name
Test status
Simulation time 1225511087 ps
CPU time 7.38 seconds
Started Jun 26 04:55:52 PM PDT 24
Finished Jun 26 04:56:01 PM PDT 24
Peak memory 221044 kb
Host smart-6ec17f0c-58d7-4877-b220-e6cbe9c1e6f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053587370 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3053587370
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3552572405
Short name T653
Test name
Test status
Simulation time 14930412 ps
CPU time 0.64 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:57:48 PM PDT 24
Peak memory 204424 kb
Host smart-18160134-27f9-4d83-b4bb-66fd9916bd45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552572405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3552572405
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1132770291
Short name T963
Test name
Test status
Simulation time 355088169 ps
CPU time 18.4 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 04:57:56 PM PDT 24
Peak memory 278908 kb
Host smart-37f103ba-a730-4f91-a331-c95b982587fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132770291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1132770291
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.3072055916
Short name T870
Test name
Test status
Simulation time 2606924512 ps
CPU time 66.76 seconds
Started Jun 26 04:57:38 PM PDT 24
Finished Jun 26 04:58:48 PM PDT 24
Peak memory 472784 kb
Host smart-42534380-5834-405a-9918-ff10c94931d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072055916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.3072055916
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2165777138
Short name T573
Test name
Test status
Simulation time 2357764971 ps
CPU time 85.41 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 04:59:03 PM PDT 24
Peak memory 794080 kb
Host smart-32653317-b64b-4da2-9595-23bea5c93a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165777138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2165777138
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.587779242
Short name T1453
Test name
Test status
Simulation time 117990361 ps
CPU time 1.1 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:57:42 PM PDT 24
Peak memory 204344 kb
Host smart-831239a4-5ebc-4299-b521-eaa19ca6dbe2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587779242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fm
t.587779242
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.2207834322
Short name T1093
Test name
Test status
Simulation time 181843006 ps
CPU time 9.72 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:57:51 PM PDT 24
Peak memory 237448 kb
Host smart-a7a03459-2c4e-4de1-9bda-8ca80710ca11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207834322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.2207834322
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.431346466
Short name T953
Test name
Test status
Simulation time 3863829506 ps
CPU time 89.36 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:59:10 PM PDT 24
Peak memory 1121400 kb
Host smart-43504f7c-4651-47a9-84ad-90b1ba33bcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431346466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.431346466
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.3958044485
Short name T698
Test name
Test status
Simulation time 1854450987 ps
CPU time 5.65 seconds
Started Jun 26 04:57:47 PM PDT 24
Finished Jun 26 04:57:55 PM PDT 24
Peak memory 204800 kb
Host smart-b0213dff-7545-41be-a4cb-1bf8800b835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958044485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.3958044485
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.3881462898
Short name T1025
Test name
Test status
Simulation time 41643889196 ps
CPU time 53.1 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:58:41 PM PDT 24
Peak memory 472756 kb
Host smart-c7d48e24-8211-458f-9a87-0c0b015f8898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881462898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.3881462898
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2708846709
Short name T1394
Test name
Test status
Simulation time 102779485 ps
CPU time 0.71 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:57:42 PM PDT 24
Peak memory 204476 kb
Host smart-0add5e6b-ba98-47bc-bb8e-d56a235eef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708846709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2708846709
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.2810631381
Short name T1003
Test name
Test status
Simulation time 7507424406 ps
CPU time 68.85 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:58:50 PM PDT 24
Peak memory 222340 kb
Host smart-1e0a5823-605a-4ae8-8879-4b7c20762cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810631381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.2810631381
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.3856041221
Short name T38
Test name
Test status
Simulation time 2650013132 ps
CPU time 28.42 seconds
Started Jun 26 04:57:36 PM PDT 24
Finished Jun 26 04:58:07 PM PDT 24
Peak memory 222804 kb
Host smart-9a08e3aa-ed78-4769-867d-57504d64ea44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856041221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.3856041221
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1937926721
Short name T1101
Test name
Test status
Simulation time 6128755376 ps
CPU time 29.37 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:58:09 PM PDT 24
Peak memory 429188 kb
Host smart-28803a2c-2a7f-405b-bf59-1fa55857f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937926721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1937926721
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3381915482
Short name T266
Test name
Test status
Simulation time 101966629490 ps
CPU time 357.9 seconds
Started Jun 26 04:57:35 PM PDT 24
Finished Jun 26 05:03:35 PM PDT 24
Peak memory 977616 kb
Host smart-560bd4c3-d682-4a74-b6ba-1e06087c4eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381915482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3381915482
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.3923224221
Short name T261
Test name
Test status
Simulation time 1282997487 ps
CPU time 26.18 seconds
Started Jun 26 04:57:40 PM PDT 24
Finished Jun 26 04:58:09 PM PDT 24
Peak memory 213064 kb
Host smart-a341ba25-87ac-4b51-b4aa-fbacc4bfcbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923224221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.3923224221
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3629363856
Short name T166
Test name
Test status
Simulation time 929820581 ps
CPU time 3.07 seconds
Started Jun 26 04:57:43 PM PDT 24
Finished Jun 26 04:57:47 PM PDT 24
Peak memory 204796 kb
Host smart-05e629cf-2f64-4520-936d-1831a56b5555
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629363856 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3629363856
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.417610859
Short name T155
Test name
Test status
Simulation time 166572541 ps
CPU time 1.12 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 04:57:50 PM PDT 24
Peak memory 204544 kb
Host smart-74fcca4e-ffa9-4812-9733-3f98aed0acd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417610859 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.417610859
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.2287910072
Short name T1005
Test name
Test status
Simulation time 646642375 ps
CPU time 1.31 seconds
Started Jun 26 04:57:43 PM PDT 24
Finished Jun 26 04:57:46 PM PDT 24
Peak memory 204860 kb
Host smart-ef29806b-87b8-43c2-a225-f837a5eb13d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287910072 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.2287910072
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.3646011918
Short name T291
Test name
Test status
Simulation time 495453314 ps
CPU time 2.43 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:57:50 PM PDT 24
Peak memory 204764 kb
Host smart-a052732f-57f9-40a3-8312-8902111b878f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646011918 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.3646011918
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.2362036154
Short name T904
Test name
Test status
Simulation time 217576767 ps
CPU time 1.07 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:57:49 PM PDT 24
Peak memory 204592 kb
Host smart-d1163dcf-199f-4c48-b4ef-02a246f68139
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362036154 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.2362036154
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.297266740
Short name T1271
Test name
Test status
Simulation time 604045254 ps
CPU time 2.45 seconds
Started Jun 26 04:57:44 PM PDT 24
Finished Jun 26 04:57:50 PM PDT 24
Peak memory 204860 kb
Host smart-ad4b4c04-a3ae-43b4-bd84-a6e4ab3963e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297266740 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_hrst.297266740
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.2024372380
Short name T440
Test name
Test status
Simulation time 1299252980 ps
CPU time 3.74 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:57:44 PM PDT 24
Peak memory 204776 kb
Host smart-fd3308af-7795-4683-9b79-092c87909a57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024372380 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.2024372380
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2085496629
Short name T1055
Test name
Test status
Simulation time 7791421952 ps
CPU time 16.27 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:57:56 PM PDT 24
Peak memory 258288 kb
Host smart-86b287e7-7bd8-469b-9ae9-05adf1b9fb65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085496629 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2085496629
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.1092975101
Short name T153
Test name
Test status
Simulation time 3364957479 ps
CPU time 10.89 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:58:00 PM PDT 24
Peak memory 204984 kb
Host smart-609bacc2-295a-4d75-8c40-5add4f3bd94e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092975101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.1092975101
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.438854544
Short name T1223
Test name
Test status
Simulation time 1031062888 ps
CPU time 12.47 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 04:57:54 PM PDT 24
Peak memory 204744 kb
Host smart-842109f9-ecf9-457a-8f0d-fbc311da7e7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438854544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_rd.438854544
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.1107832280
Short name T1095
Test name
Test status
Simulation time 58407801885 ps
CPU time 439.2 seconds
Started Jun 26 04:57:39 PM PDT 24
Finished Jun 26 05:05:02 PM PDT 24
Peak memory 4084044 kb
Host smart-84ffe880-6cda-4c1d-992e-96badac69810
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107832280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.1107832280
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3598577624
Short name T1120
Test name
Test status
Simulation time 20599866175 ps
CPU time 915.09 seconds
Started Jun 26 04:57:37 PM PDT 24
Finished Jun 26 05:12:55 PM PDT 24
Peak memory 2516136 kb
Host smart-ab095fce-fac3-4bc8-8290-25e8cdcf81a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598577624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3598577624
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.306121781
Short name T838
Test name
Test status
Simulation time 3467513390 ps
CPU time 6.9 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 04:57:57 PM PDT 24
Peak memory 214040 kb
Host smart-ce2f140b-4956-45d6-83ae-15afbaac39bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306121781 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.306121781
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.293007906
Short name T761
Test name
Test status
Simulation time 17789426 ps
CPU time 0.62 seconds
Started Jun 26 04:57:50 PM PDT 24
Finished Jun 26 04:57:52 PM PDT 24
Peak memory 204500 kb
Host smart-b64b2f02-ad99-479f-9b21-e960abd6fa19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293007906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.293007906
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.2658537160
Short name T1123
Test name
Test status
Simulation time 753787270 ps
CPU time 5.36 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:57:54 PM PDT 24
Peak memory 232848 kb
Host smart-9198c322-2295-4f9f-86de-1028a3b24398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658537160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.2658537160
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.3761656897
Short name T1170
Test name
Test status
Simulation time 249820157 ps
CPU time 4.67 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:57:53 PM PDT 24
Peak memory 233640 kb
Host smart-4a13981c-6dba-4542-9d70-766ef492b7d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761656897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.3761656897
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3682540945
Short name T44
Test name
Test status
Simulation time 5640593498 ps
CPU time 100.55 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 04:59:30 PM PDT 24
Peak memory 849472 kb
Host smart-68dd17f1-f353-42ae-8c6a-90b2640eb4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682540945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3682540945
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.3406022927
Short name T387
Test name
Test status
Simulation time 2074656538 ps
CPU time 159.42 seconds
Started Jun 26 04:57:49 PM PDT 24
Finished Jun 26 05:00:30 PM PDT 24
Peak memory 682972 kb
Host smart-fb37ef19-eae5-477d-9286-f3d691d54d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406022927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.3406022927
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2376046879
Short name T536
Test name
Test status
Simulation time 85928146 ps
CPU time 0.95 seconds
Started Jun 26 04:57:43 PM PDT 24
Finished Jun 26 04:57:46 PM PDT 24
Peak memory 204184 kb
Host smart-dc184054-874f-42d4-a3e2-a7f8464d991a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376046879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2376046879
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3489612518
Short name T146
Test name
Test status
Simulation time 509423644 ps
CPU time 3.27 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 04:57:53 PM PDT 24
Peak memory 224020 kb
Host smart-e61da214-af2d-4b16-b9b2-2655a97df602
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489612518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3489612518
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.2235414641
Short name T840
Test name
Test status
Simulation time 5968564170 ps
CPU time 337.72 seconds
Started Jun 26 04:57:44 PM PDT 24
Finished Jun 26 05:03:25 PM PDT 24
Peak memory 1254856 kb
Host smart-30916233-2505-4517-be27-686675272f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235414641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.2235414641
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.3726582594
Short name T557
Test name
Test status
Simulation time 428541157 ps
CPU time 18.14 seconds
Started Jun 26 04:57:54 PM PDT 24
Finished Jun 26 04:58:15 PM PDT 24
Peak memory 204804 kb
Host smart-3be4ac27-c5d8-4ff2-854a-1df41a31035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726582594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.3726582594
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.1849438456
Short name T416
Test name
Test status
Simulation time 8420491904 ps
CPU time 110.49 seconds
Started Jun 26 04:57:54 PM PDT 24
Finished Jun 26 04:59:47 PM PDT 24
Peak memory 482360 kb
Host smart-cef59225-d5c6-47e8-899c-3e245f9dcd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849438456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.1849438456
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.3853853929
Short name T980
Test name
Test status
Simulation time 48156466 ps
CPU time 0.65 seconds
Started Jun 26 04:57:43 PM PDT 24
Finished Jun 26 04:57:46 PM PDT 24
Peak memory 204544 kb
Host smart-b37bc0f0-1c4a-4aec-80bd-0af0f20a4491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853853929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.3853853929
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1466291688
Short name T353
Test name
Test status
Simulation time 5364999447 ps
CPU time 16.37 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:58:04 PM PDT 24
Peak memory 205128 kb
Host smart-c8717461-7a2b-4c75-8066-b1c3b6d132cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466291688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1466291688
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.3588186272
Short name T313
Test name
Test status
Simulation time 6011317183 ps
CPU time 121.32 seconds
Started Jun 26 04:57:44 PM PDT 24
Finished Jun 26 04:59:49 PM PDT 24
Peak memory 213128 kb
Host smart-52dd9402-a4fb-4dab-b6d3-adbac04add50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588186272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3588186272
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1546058102
Short name T1357
Test name
Test status
Simulation time 5248804445 ps
CPU time 50.33 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 04:58:39 PM PDT 24
Peak memory 261696 kb
Host smart-e0325f9f-f139-4476-b1e0-382884c78762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546058102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1546058102
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.872096794
Short name T71
Test name
Test status
Simulation time 17923604821 ps
CPU time 2273.29 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 05:35:43 PM PDT 24
Peak memory 3121688 kb
Host smart-57582583-9d32-4b33-9aae-2263fbda4f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872096794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.872096794
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3848340757
Short name T639
Test name
Test status
Simulation time 1416060745 ps
CPU time 26.89 seconds
Started Jun 26 04:57:44 PM PDT 24
Finished Jun 26 04:58:13 PM PDT 24
Peak memory 212980 kb
Host smart-304933d5-bb66-4bba-9384-1238c2792cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848340757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3848340757
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.4155199583
Short name T540
Test name
Test status
Simulation time 1945943766 ps
CPU time 3.86 seconds
Started Jun 26 04:57:53 PM PDT 24
Finished Jun 26 04:57:59 PM PDT 24
Peak memory 213004 kb
Host smart-1750fcc3-774e-4177-87e2-604dd5865128
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155199583 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.4155199583
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.4165529398
Short name T771
Test name
Test status
Simulation time 175182963 ps
CPU time 1.09 seconds
Started Jun 26 04:57:43 PM PDT 24
Finished Jun 26 04:57:46 PM PDT 24
Peak memory 204312 kb
Host smart-c8d661a7-d5ac-4a34-9511-beb007f9be22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165529398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.4165529398
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.89718089
Short name T478
Test name
Test status
Simulation time 135592709 ps
CPU time 1.06 seconds
Started Jun 26 04:57:47 PM PDT 24
Finished Jun 26 04:57:51 PM PDT 24
Peak memory 204560 kb
Host smart-0dbbbaab-e124-4547-a0e9-f6b5606c7ee7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89718089 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.i2c_target_fifo_reset_tx.89718089
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.1456477874
Short name T965
Test name
Test status
Simulation time 336913623 ps
CPU time 1.96 seconds
Started Jun 26 04:57:52 PM PDT 24
Finished Jun 26 04:57:55 PM PDT 24
Peak memory 204800 kb
Host smart-a127ab93-d645-4866-8dfd-5e9607420874
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456477874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.1456477874
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1479678172
Short name T1461
Test name
Test status
Simulation time 145286324 ps
CPU time 0.91 seconds
Started Jun 26 04:57:52 PM PDT 24
Finished Jun 26 04:57:55 PM PDT 24
Peak memory 204628 kb
Host smart-d7c9aabf-2d37-48fb-9323-0105d5645205
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479678172 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1479678172
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.2159561264
Short name T841
Test name
Test status
Simulation time 1465794515 ps
CPU time 4.22 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:57:53 PM PDT 24
Peak memory 204816 kb
Host smart-554894de-deed-4daf-94c9-8dd198c020b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159561264 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.2159561264
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.3682628244
Short name T1399
Test name
Test status
Simulation time 3232962804 ps
CPU time 11.4 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 04:58:01 PM PDT 24
Peak memory 538988 kb
Host smart-efd9844c-9cd3-4755-abc4-7a1265df7dca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682628244 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.3682628244
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.3850764873
Short name T746
Test name
Test status
Simulation time 8631461843 ps
CPU time 47.7 seconds
Started Jun 26 04:57:44 PM PDT 24
Finished Jun 26 04:58:34 PM PDT 24
Peak memory 204964 kb
Host smart-f1eb20b1-a67a-49ca-a160-c2540ca23cfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850764873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.3850764873
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.1845559374
Short name T283
Test name
Test status
Simulation time 895224425 ps
CPU time 13.03 seconds
Started Jun 26 04:57:46 PM PDT 24
Finished Jun 26 04:58:02 PM PDT 24
Peak memory 214068 kb
Host smart-d5acc462-2796-4307-b758-e5705588f23f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845559374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.1845559374
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.137486867
Short name T424
Test name
Test status
Simulation time 37563714602 ps
CPU time 63.99 seconds
Started Jun 26 04:57:44 PM PDT 24
Finished Jun 26 04:58:50 PM PDT 24
Peak memory 1111112 kb
Host smart-e59bbab8-d9df-4fd3-8b43-82989e085d78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137486867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_wr.137486867
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.2570648357
Short name T1028
Test name
Test status
Simulation time 32077005007 ps
CPU time 22.36 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:58:11 PM PDT 24
Peak memory 327616 kb
Host smart-4a9c75e1-3cbb-4a6a-8c33-b2891e122f05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570648357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.2570648357
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2639212826
Short name T1000
Test name
Test status
Simulation time 7739512968 ps
CPU time 7.16 seconds
Started Jun 26 04:57:45 PM PDT 24
Finished Jun 26 04:57:56 PM PDT 24
Peak memory 213264 kb
Host smart-74047791-42c2-461c-8117-f50a2ec2c2b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639212826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2639212826
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.2018228743
Short name T1083
Test name
Test status
Simulation time 17965141 ps
CPU time 0.63 seconds
Started Jun 26 04:57:52 PM PDT 24
Finished Jun 26 04:57:55 PM PDT 24
Peak memory 204468 kb
Host smart-94d050c9-80cb-4c75-bada-0030edfae779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018228743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.2018228743
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.1042256400
Short name T382
Test name
Test status
Simulation time 235003804 ps
CPU time 1.4 seconds
Started Jun 26 04:57:53 PM PDT 24
Finished Jun 26 04:57:57 PM PDT 24
Peak memory 213124 kb
Host smart-bcdef28d-601f-4635-93ad-5c8d149acf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042256400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.1042256400
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.968612187
Short name T1080
Test name
Test status
Simulation time 1531001002 ps
CPU time 8.64 seconds
Started Jun 26 04:57:58 PM PDT 24
Finished Jun 26 04:58:08 PM PDT 24
Peak memory 291756 kb
Host smart-615b95c2-2113-4386-8fe4-847abf5cd61f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968612187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_empt
y.968612187
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2011169720
Short name T786
Test name
Test status
Simulation time 3644668711 ps
CPU time 48.58 seconds
Started Jun 26 04:57:53 PM PDT 24
Finished Jun 26 04:58:44 PM PDT 24
Peak memory 454716 kb
Host smart-4622df6b-d5cf-4ac0-a80d-14309536e715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011169720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2011169720
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.485814268
Short name T167
Test name
Test status
Simulation time 2436382446 ps
CPU time 73.11 seconds
Started Jun 26 04:57:58 PM PDT 24
Finished Jun 26 04:59:12 PM PDT 24
Peak memory 787044 kb
Host smart-27910968-3157-402b-9a0b-f1b084a8a3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485814268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.485814268
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.949794907
Short name T794
Test name
Test status
Simulation time 568213176 ps
CPU time 7.93 seconds
Started Jun 26 04:57:52 PM PDT 24
Finished Jun 26 04:58:03 PM PDT 24
Peak memory 227952 kb
Host smart-11e09401-358a-4864-8931-b7479a25c132
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949794907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx.
949794907
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.3374674667
Short name T107
Test name
Test status
Simulation time 5640435093 ps
CPU time 174.92 seconds
Started Jun 26 04:57:55 PM PDT 24
Finished Jun 26 05:00:52 PM PDT 24
Peak memory 909424 kb
Host smart-28de0fd3-9839-4751-8593-ede02f3ac234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374674667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.3374674667
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.2609456867
Short name T1126
Test name
Test status
Simulation time 358326798 ps
CPU time 5.26 seconds
Started Jun 26 04:57:55 PM PDT 24
Finished Jun 26 04:58:03 PM PDT 24
Peak memory 204724 kb
Host smart-ef3dba3d-f472-4b1b-a5cc-e1fc388639f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609456867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.2609456867
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.652155506
Short name T242
Test name
Test status
Simulation time 3805717438 ps
CPU time 37.06 seconds
Started Jun 26 04:57:53 PM PDT 24
Finished Jun 26 04:58:33 PM PDT 24
Peak memory 372468 kb
Host smart-75fd8594-a16d-48a3-876f-ec3c9dae6640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652155506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.652155506
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2076163065
Short name T905
Test name
Test status
Simulation time 26834731 ps
CPU time 0.67 seconds
Started Jun 26 04:57:52 PM PDT 24
Finished Jun 26 04:57:55 PM PDT 24
Peak memory 204468 kb
Host smart-9d60d584-b5eb-4438-a7c7-1cf18b25f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076163065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2076163065
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.1077264656
Short name T59
Test name
Test status
Simulation time 12941205568 ps
CPU time 741.17 seconds
Started Jun 26 04:57:55 PM PDT 24
Finished Jun 26 05:10:19 PM PDT 24
Peak memory 1405712 kb
Host smart-58198c6c-4059-4cbe-b723-1adfd52a5bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077264656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.1077264656
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.3590574805
Short name T1130
Test name
Test status
Simulation time 61576309 ps
CPU time 1.07 seconds
Started Jun 26 04:57:52 PM PDT 24
Finished Jun 26 04:57:55 PM PDT 24
Peak memory 204744 kb
Host smart-7e8f9abd-260f-4997-8203-df845a06a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590574805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3590574805
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.394612739
Short name T1444
Test name
Test status
Simulation time 3115501754 ps
CPU time 32.66 seconds
Started Jun 26 04:57:54 PM PDT 24
Finished Jun 26 04:58:29 PM PDT 24
Peak memory 370356 kb
Host smart-f09c0d7e-4d94-46c8-a123-75aeef65d532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394612739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.394612739
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.304890008
Short name T58
Test name
Test status
Simulation time 56370642093 ps
CPU time 2967.22 seconds
Started Jun 26 04:57:55 PM PDT 24
Finished Jun 26 05:47:25 PM PDT 24
Peak memory 1820052 kb
Host smart-0b186415-440d-4838-b8bc-0e2d732aaca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304890008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.304890008
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.4109206478
Short name T534
Test name
Test status
Simulation time 437022162 ps
CPU time 8.49 seconds
Started Jun 26 04:57:53 PM PDT 24
Finished Jun 26 04:58:04 PM PDT 24
Peak memory 213048 kb
Host smart-1dbb3b54-ae27-4747-af9d-f443394b174f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109206478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.4109206478
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.3105337820
Short name T500
Test name
Test status
Simulation time 612471226 ps
CPU time 3.3 seconds
Started Jun 26 04:57:56 PM PDT 24
Finished Jun 26 04:58:01 PM PDT 24
Peak memory 204828 kb
Host smart-4444e983-258c-40ef-865d-2cefce9ed7dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105337820 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.3105337820
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1288561506
Short name T1302
Test name
Test status
Simulation time 248265598 ps
CPU time 1.44 seconds
Started Jun 26 04:57:55 PM PDT 24
Finished Jun 26 04:57:59 PM PDT 24
Peak memory 204604 kb
Host smart-6f6ce2e8-20ca-41c8-98b8-d7f8fefc486c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288561506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1288561506
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.2891769188
Short name T804
Test name
Test status
Simulation time 150283110 ps
CPU time 0.9 seconds
Started Jun 26 04:57:56 PM PDT 24
Finished Jun 26 04:57:59 PM PDT 24
Peak memory 204500 kb
Host smart-3a8379d2-256f-4a7d-b4d9-90129146b34e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891769188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.2891769188
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.549551260
Short name T1307
Test name
Test status
Simulation time 1580358604 ps
CPU time 2.66 seconds
Started Jun 26 04:57:53 PM PDT 24
Finished Jun 26 04:57:58 PM PDT 24
Peak memory 204852 kb
Host smart-fc08aa67-b574-4c75-960a-b0979037803c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549551260 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.549551260
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.2732936611
Short name T1158
Test name
Test status
Simulation time 3502522844 ps
CPU time 4.82 seconds
Started Jun 26 04:57:53 PM PDT 24
Finished Jun 26 04:58:00 PM PDT 24
Peak memory 213196 kb
Host smart-eaa2139d-fc94-40a5-845e-7f9fcc2f04f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732936611 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.2732936611
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.516746271
Short name T402
Test name
Test status
Simulation time 7457399862 ps
CPU time 96.07 seconds
Started Jun 26 04:57:54 PM PDT 24
Finished Jun 26 04:59:33 PM PDT 24
Peak memory 1878056 kb
Host smart-74740429-8a24-4667-8fee-6b7b98d9731d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516746271 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.516746271
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3602981007
Short name T150
Test name
Test status
Simulation time 3052136117 ps
CPU time 27.7 seconds
Started Jun 26 04:57:52 PM PDT 24
Finished Jun 26 04:58:22 PM PDT 24
Peak memory 204896 kb
Host smart-4025866d-21fe-43a7-a81b-1f4aa4ca40d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602981007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3602981007
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.3096180995
Short name T363
Test name
Test status
Simulation time 1882021987 ps
CPU time 21.96 seconds
Started Jun 26 04:57:51 PM PDT 24
Finished Jun 26 04:58:14 PM PDT 24
Peak memory 204828 kb
Host smart-dcbf8822-7f80-41a4-9bb4-2d7882d2fb95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096180995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.3096180995
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1698216273
Short name T769
Test name
Test status
Simulation time 11506241925 ps
CPU time 20.54 seconds
Started Jun 26 04:57:52 PM PDT 24
Finished Jun 26 04:58:15 PM PDT 24
Peak memory 204936 kb
Host smart-e3b454cd-8c69-45c3-b6f9-2562c8cefb61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698216273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1698216273
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2566615637
Short name T366
Test name
Test status
Simulation time 1204279853 ps
CPU time 6.57 seconds
Started Jun 26 04:57:56 PM PDT 24
Finished Jun 26 04:58:05 PM PDT 24
Peak memory 204792 kb
Host smart-b5acab4b-8b49-4e9a-862a-9876f823996a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566615637 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2566615637
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1526106112
Short name T647
Test name
Test status
Simulation time 40775045 ps
CPU time 0.61 seconds
Started Jun 26 04:58:08 PM PDT 24
Finished Jun 26 04:58:10 PM PDT 24
Peak memory 204452 kb
Host smart-ccdf1b4c-ee85-4a15-b8bc-b06efbc889c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526106112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1526106112
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.3553829090
Short name T50
Test name
Test status
Simulation time 298373675 ps
CPU time 1.62 seconds
Started Jun 26 04:58:11 PM PDT 24
Finished Jun 26 04:58:16 PM PDT 24
Peak memory 213060 kb
Host smart-e37ddcf6-f06d-487c-bb8a-f366243fc235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553829090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.3553829090
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.755691133
Short name T1407
Test name
Test status
Simulation time 320392332 ps
CPU time 16.58 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 04:58:20 PM PDT 24
Peak memory 271320 kb
Host smart-702fbb12-be37-4bb2-8b68-bb6de9543e9c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755691133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.755691133
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1405120057
Short name T1454
Test name
Test status
Simulation time 23348729926 ps
CPU time 136.54 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 05:00:20 PM PDT 24
Peak memory 670688 kb
Host smart-c0f69030-f08c-4068-b80f-e323331bf0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405120057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1405120057
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.785463356
Short name T996
Test name
Test status
Simulation time 3075903172 ps
CPU time 95.61 seconds
Started Jun 26 04:57:55 PM PDT 24
Finished Jun 26 04:59:33 PM PDT 24
Peak memory 523628 kb
Host smart-e027cf44-6d01-470a-8eb1-d5c935abeee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785463356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.785463356
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.3314337330
Short name T713
Test name
Test status
Simulation time 364347877 ps
CPU time 0.89 seconds
Started Jun 26 04:58:04 PM PDT 24
Finished Jun 26 04:58:07 PM PDT 24
Peak memory 204552 kb
Host smart-74f113c5-e0d3-4084-96dc-d1c52cd4be31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314337330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.3314337330
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.1136692677
Short name T1456
Test name
Test status
Simulation time 595998353 ps
CPU time 8.22 seconds
Started Jun 26 04:58:07 PM PDT 24
Finished Jun 26 04:58:17 PM PDT 24
Peak memory 204780 kb
Host smart-9047e332-27f5-4a75-8e23-4a6af99bbd25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136692677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.1136692677
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3591870443
Short name T475
Test name
Test status
Simulation time 3985072999 ps
CPU time 156.26 seconds
Started Jun 26 04:57:55 PM PDT 24
Finished Jun 26 05:00:34 PM PDT 24
Peak memory 831936 kb
Host smart-f5513f9b-2a54-4c5d-bf2c-a91fd7058936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591870443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3591870443
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.3877393602
Short name T464
Test name
Test status
Simulation time 749041172 ps
CPU time 14.73 seconds
Started Jun 26 04:58:03 PM PDT 24
Finished Jun 26 04:58:20 PM PDT 24
Peak memory 204756 kb
Host smart-a0d52d37-d71d-41a0-9335-a1806b62d870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877393602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.3877393602
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.2823342797
Short name T61
Test name
Test status
Simulation time 1309375726 ps
CPU time 20.95 seconds
Started Jun 26 04:58:03 PM PDT 24
Finished Jun 26 04:58:26 PM PDT 24
Peak memory 316528 kb
Host smart-ff1f2128-f080-4761-9d89-3a64a1476056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823342797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.2823342797
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.3680289422
Short name T1064
Test name
Test status
Simulation time 27511300 ps
CPU time 0.69 seconds
Started Jun 26 04:57:56 PM PDT 24
Finished Jun 26 04:57:59 PM PDT 24
Peak memory 204472 kb
Host smart-7ad3454e-5164-450e-b43d-89b6cf4a9fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680289422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.3680289422
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.3560666646
Short name T907
Test name
Test status
Simulation time 7994104856 ps
CPU time 84.73 seconds
Started Jun 26 04:58:00 PM PDT 24
Finished Jun 26 04:59:26 PM PDT 24
Peak memory 265340 kb
Host smart-701b2a01-9fcb-41be-839e-9e20f6c9588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560666646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.3560666646
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.2235832300
Short name T566
Test name
Test status
Simulation time 151262754 ps
CPU time 5.52 seconds
Started Jun 26 04:58:04 PM PDT 24
Finished Jun 26 04:58:12 PM PDT 24
Peak memory 204828 kb
Host smart-a678af26-7521-4c60-93c3-57c459b14358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235832300 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.2235832300
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2500074900
Short name T1057
Test name
Test status
Simulation time 1108160846 ps
CPU time 18.74 seconds
Started Jun 26 04:57:54 PM PDT 24
Finished Jun 26 04:58:15 PM PDT 24
Peak memory 263556 kb
Host smart-cbe3da4b-76d1-40cf-aae2-b228ea94461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500074900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2500074900
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.181646221
Short name T1050
Test name
Test status
Simulation time 2395390957 ps
CPU time 6.35 seconds
Started Jun 26 04:58:02 PM PDT 24
Finished Jun 26 04:58:10 PM PDT 24
Peak memory 213140 kb
Host smart-18be29a0-962a-4c67-98c0-ce79ccf82fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181646221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.181646221
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.4280433734
Short name T731
Test name
Test status
Simulation time 2820609449 ps
CPU time 3.1 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 04:58:05 PM PDT 24
Peak memory 204916 kb
Host smart-d50037be-8991-4c34-b806-28030fd7f5eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280433734 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.4280433734
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.585244567
Short name T441
Test name
Test status
Simulation time 414272979 ps
CPU time 1.01 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 04:58:03 PM PDT 24
Peak memory 204596 kb
Host smart-203111a7-1f5c-42e9-94eb-edbdc49fcce6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585244567 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.585244567
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.141013869
Short name T30
Test name
Test status
Simulation time 1585344692 ps
CPU time 1.52 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 04:58:05 PM PDT 24
Peak memory 206368 kb
Host smart-d4b8e8f9-8566-49a5-907b-131007e30473
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141013869 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.i2c_target_fifo_reset_tx.141013869
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.3190471554
Short name T1272
Test name
Test status
Simulation time 611757163 ps
CPU time 1.14 seconds
Started Jun 26 04:58:03 PM PDT 24
Finished Jun 26 04:58:06 PM PDT 24
Peak memory 204540 kb
Host smart-5256f5e3-7c61-4011-af8e-dfda93c9873c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190471554 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.3190471554
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.2063781253
Short name T308
Test name
Test status
Simulation time 190573429 ps
CPU time 1.2 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 04:58:04 PM PDT 24
Peak memory 204592 kb
Host smart-844cb3fc-e40a-4da8-ab3c-f9acd017b474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063781253 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.2063781253
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.3065291897
Short name T270
Test name
Test status
Simulation time 3161625325 ps
CPU time 3.96 seconds
Started Jun 26 04:58:03 PM PDT 24
Finished Jun 26 04:58:09 PM PDT 24
Peak memory 204872 kb
Host smart-5ae1aae0-524a-4b25-bfda-1b32441020cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065291897 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.3065291897
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.519529259
Short name T480
Test name
Test status
Simulation time 15585735311 ps
CPU time 39.03 seconds
Started Jun 26 04:58:03 PM PDT 24
Finished Jun 26 04:58:44 PM PDT 24
Peak memory 975108 kb
Host smart-365f874e-98e0-48d4-abca-78cde4be7fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519529259 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.519529259
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2088313161
Short name T457
Test name
Test status
Simulation time 1873890008 ps
CPU time 26.4 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 04:58:29 PM PDT 24
Peak memory 204844 kb
Host smart-0e91ffb6-e0d3-468c-b503-e9bfce2742ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088313161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2088313161
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3682348670
Short name T670
Test name
Test status
Simulation time 26823505488 ps
CPU time 121.96 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 05:00:05 PM PDT 24
Peak memory 1756992 kb
Host smart-bf22bc39-2dcf-45a6-ba93-ceaab2642564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682348670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3682348670
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.334916218
Short name T456
Test name
Test status
Simulation time 26579060493 ps
CPU time 1303.92 seconds
Started Jun 26 04:58:04 PM PDT 24
Finished Jun 26 05:19:50 PM PDT 24
Peak memory 3149084 kb
Host smart-9fde19b9-966f-4dca-acac-4dfb80593dc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334916218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_t
arget_stretch.334916218
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3670543838
Short name T339
Test name
Test status
Simulation time 1596183418 ps
CPU time 8.23 seconds
Started Jun 26 04:58:08 PM PDT 24
Finished Jun 26 04:58:19 PM PDT 24
Peak memory 217448 kb
Host smart-5d5ba8bb-7626-4b74-bf73-dc0bff40bd0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670543838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3670543838
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3777143709
Short name T741
Test name
Test status
Simulation time 36711921 ps
CPU time 0.66 seconds
Started Jun 26 04:58:10 PM PDT 24
Finished Jun 26 04:58:12 PM PDT 24
Peak memory 204492 kb
Host smart-d33f58d2-68c5-4d83-8ac6-a71bfad3d258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777143709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3777143709
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.2968356842
Short name T477
Test name
Test status
Simulation time 134674476 ps
CPU time 5.53 seconds
Started Jun 26 04:58:02 PM PDT 24
Finished Jun 26 04:58:10 PM PDT 24
Peak memory 221048 kb
Host smart-67efce4c-3d6f-44d6-a025-1bbae6cdfe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968356842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.2968356842
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.2013616133
Short name T860
Test name
Test status
Simulation time 1968718501 ps
CPU time 5.88 seconds
Started Jun 26 04:58:00 PM PDT 24
Finished Jun 26 04:58:07 PM PDT 24
Peak memory 255904 kb
Host smart-3d6b76b5-130c-4669-a1a2-31570578ad64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013616133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.2013616133
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.4247032266
Short name T1174
Test name
Test status
Simulation time 2216361532 ps
CPU time 59.51 seconds
Started Jun 26 04:58:05 PM PDT 24
Finished Jun 26 04:59:06 PM PDT 24
Peak memory 599140 kb
Host smart-527751ad-689e-4a3a-8321-e0463703a63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247032266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.4247032266
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.381919985
Short name T1210
Test name
Test status
Simulation time 4191867209 ps
CPU time 57.23 seconds
Started Jun 26 04:58:06 PM PDT 24
Finished Jun 26 04:59:05 PM PDT 24
Peak memory 647976 kb
Host smart-f5c61ac4-654f-4de7-acc6-becfc181d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381919985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.381919985
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.3470164707
Short name T220
Test name
Test status
Simulation time 429495180 ps
CPU time 1.01 seconds
Started Jun 26 04:58:04 PM PDT 24
Finished Jun 26 04:58:07 PM PDT 24
Peak memory 204480 kb
Host smart-a8071454-e8dd-4373-80fa-bd340e1529df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470164707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.3470164707
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.3927067622
Short name T1090
Test name
Test status
Simulation time 560567349 ps
CPU time 7.84 seconds
Started Jun 26 04:58:02 PM PDT 24
Finished Jun 26 04:58:12 PM PDT 24
Peak memory 204804 kb
Host smart-8f0052ef-b1dc-4d0f-bd51-43f2f88262d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927067622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.3927067622
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2892745214
Short name T102
Test name
Test status
Simulation time 17526268717 ps
CPU time 74.3 seconds
Started Jun 26 04:58:03 PM PDT 24
Finished Jun 26 04:59:20 PM PDT 24
Peak memory 1001128 kb
Host smart-cbb4fbdd-8909-462d-bd1a-fcc1cd48e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892745214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2892745214
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.407018713
Short name T517
Test name
Test status
Simulation time 712592663 ps
CPU time 10.34 seconds
Started Jun 26 04:58:08 PM PDT 24
Finished Jun 26 04:58:21 PM PDT 24
Peak memory 204832 kb
Host smart-6318da4b-859c-44a6-a40c-2f7779667f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407018713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.407018713
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.1805265009
Short name T590
Test name
Test status
Simulation time 4990940720 ps
CPU time 24.9 seconds
Started Jun 26 04:58:11 PM PDT 24
Finished Jun 26 04:58:40 PM PDT 24
Peak memory 360632 kb
Host smart-251bcc91-621a-4d14-83b3-071e2440d773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805265009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.1805265009
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1776384973
Short name T1438
Test name
Test status
Simulation time 57186184 ps
CPU time 0.68 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 04:58:04 PM PDT 24
Peak memory 204484 kb
Host smart-69c5f0ed-430a-4f93-970c-333a83ed816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776384973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1776384973
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1019571577
Short name T1451
Test name
Test status
Simulation time 2795315307 ps
CPU time 164.11 seconds
Started Jun 26 04:58:03 PM PDT 24
Finished Jun 26 05:00:49 PM PDT 24
Peak memory 769408 kb
Host smart-dfc11aff-ffb6-4e6d-ae1e-4460bb077807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019571577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1019571577
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.3629283240
Short name T1218
Test name
Test status
Simulation time 24772913562 ps
CPU time 67.84 seconds
Started Jun 26 04:58:05 PM PDT 24
Finished Jun 26 04:59:14 PM PDT 24
Peak memory 204876 kb
Host smart-41ee4a87-7f50-4c85-9d18-599ba0893900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629283240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.3629283240
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.47262899
Short name T1345
Test name
Test status
Simulation time 8202917665 ps
CPU time 31.08 seconds
Started Jun 26 04:58:04 PM PDT 24
Finished Jun 26 04:58:37 PM PDT 24
Peak memory 324796 kb
Host smart-fcded5b7-e498-41dd-b812-1a1462515d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47262899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.47262899
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.2305218370
Short name T103
Test name
Test status
Simulation time 83062673241 ps
CPU time 1224.49 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 05:18:28 PM PDT 24
Peak memory 4057056 kb
Host smart-b4bbc9a1-e19c-4a75-a48b-341c059bd658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305218370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2305218370
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.3772327758
Short name T1425
Test name
Test status
Simulation time 2745432805 ps
CPU time 11.07 seconds
Started Jun 26 04:58:01 PM PDT 24
Finished Jun 26 04:58:15 PM PDT 24
Peak memory 214384 kb
Host smart-24f00087-ff6f-4897-9f7b-50a4cea6e797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772327758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.3772327758
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.3543948047
Short name T970
Test name
Test status
Simulation time 791424602 ps
CPU time 4.34 seconds
Started Jun 26 04:58:10 PM PDT 24
Finished Jun 26 04:58:18 PM PDT 24
Peak memory 204884 kb
Host smart-1b721f41-ada6-48db-afab-927f86a37e1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543948047 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.3543948047
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.551668542
Short name T767
Test name
Test status
Simulation time 213872981 ps
CPU time 1.24 seconds
Started Jun 26 04:58:13 PM PDT 24
Finished Jun 26 04:58:18 PM PDT 24
Peak memory 204564 kb
Host smart-3e043cb0-6053-4312-b909-76bf0cc296e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551668542 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_acq.551668542
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2449123063
Short name T311
Test name
Test status
Simulation time 664090488 ps
CPU time 1.09 seconds
Started Jun 26 04:58:10 PM PDT 24
Finished Jun 26 04:58:13 PM PDT 24
Peak memory 204556 kb
Host smart-9fd8075a-5b30-460d-8f7a-aa3990621f8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449123063 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2449123063
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.3784758293
Short name T18
Test name
Test status
Simulation time 404893671 ps
CPU time 2.1 seconds
Started Jun 26 04:58:12 PM PDT 24
Finished Jun 26 04:58:17 PM PDT 24
Peak memory 204808 kb
Host smart-a5b0b18e-7937-469e-b590-be6f3db92fd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784758293 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.3784758293
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.3548619600
Short name T709
Test name
Test status
Simulation time 85026417 ps
CPU time 0.93 seconds
Started Jun 26 04:58:14 PM PDT 24
Finished Jun 26 04:58:18 PM PDT 24
Peak memory 204584 kb
Host smart-a6fbb169-a22d-4680-8ed1-d41b5cd40814
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548619600 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.3548619600
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.184281641
Short name T1432
Test name
Test status
Simulation time 1417482434 ps
CPU time 3.47 seconds
Started Jun 26 04:58:13 PM PDT 24
Finished Jun 26 04:58:19 PM PDT 24
Peak memory 204824 kb
Host smart-9ac663cd-7779-47b0-a996-3fb5dce19466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184281641 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.i2c_target_hrst.184281641
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.2657185302
Short name T827
Test name
Test status
Simulation time 1455230600 ps
CPU time 4.04 seconds
Started Jun 26 04:58:02 PM PDT 24
Finished Jun 26 04:58:08 PM PDT 24
Peak memory 204748 kb
Host smart-895a286a-44b8-4f0e-a80e-3f4afce7da45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657185302 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.2657185302
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.4007121748
Short name T1242
Test name
Test status
Simulation time 10566629611 ps
CPU time 19.94 seconds
Started Jun 26 04:58:04 PM PDT 24
Finished Jun 26 04:58:26 PM PDT 24
Peak memory 514004 kb
Host smart-e69cf56f-6240-4c41-8209-260fe7195e9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007121748 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.4007121748
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.792522310
Short name T1027
Test name
Test status
Simulation time 3245289403 ps
CPU time 17.64 seconds
Started Jun 26 04:58:03 PM PDT 24
Finished Jun 26 04:58:23 PM PDT 24
Peak memory 204880 kb
Host smart-370cd8e3-516c-410c-987b-8139687be085
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792522310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_tar
get_smoke.792522310
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2723100734
Short name T236
Test name
Test status
Simulation time 1390018598 ps
CPU time 28.22 seconds
Started Jun 26 04:58:05 PM PDT 24
Finished Jun 26 04:58:35 PM PDT 24
Peak memory 204828 kb
Host smart-a27679dd-8769-47cd-b8be-5e77aef5a11a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723100734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2723100734
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.3788310961
Short name T27
Test name
Test status
Simulation time 45640360066 ps
CPU time 855.29 seconds
Started Jun 26 04:58:02 PM PDT 24
Finished Jun 26 05:12:20 PM PDT 24
Peak memory 6491156 kb
Host smart-c81db1ed-b7f1-4aaa-8b59-e39552f5c43b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788310961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.3788310961
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.557845383
Short name T818
Test name
Test status
Simulation time 29085193194 ps
CPU time 1771.75 seconds
Started Jun 26 04:58:00 PM PDT 24
Finished Jun 26 05:27:34 PM PDT 24
Peak memory 6984480 kb
Host smart-3b1dafb7-bddc-4d24-a7ba-2aad2648ec5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557845383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_t
arget_stretch.557845383
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2176338797
Short name T1212
Test name
Test status
Simulation time 7183278325 ps
CPU time 6.91 seconds
Started Jun 26 04:58:00 PM PDT 24
Finished Jun 26 04:58:08 PM PDT 24
Peak memory 221160 kb
Host smart-2cb89829-6d64-44ff-aca1-8ec708151c5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176338797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2176338797
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2632509706
Short name T1382
Test name
Test status
Simulation time 20639530 ps
CPU time 0.62 seconds
Started Jun 26 04:58:27 PM PDT 24
Finished Jun 26 04:58:31 PM PDT 24
Peak memory 204468 kb
Host smart-92a25f5b-6f14-4762-a49d-0913cb79910f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632509706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2632509706
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.3867231212
Short name T852
Test name
Test status
Simulation time 713611299 ps
CPU time 2.77 seconds
Started Jun 26 04:58:10 PM PDT 24
Finished Jun 26 04:58:16 PM PDT 24
Peak memory 216896 kb
Host smart-6fe24446-a26c-4fc3-8e57-5a33d7f5ac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867231212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.3867231212
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2494110373
Short name T1132
Test name
Test status
Simulation time 1000638752 ps
CPU time 8.21 seconds
Started Jun 26 04:58:14 PM PDT 24
Finished Jun 26 04:58:26 PM PDT 24
Peak memory 285680 kb
Host smart-dccca11a-673f-43c3-a437-95d160900564
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494110373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2494110373
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2573142291
Short name T1045
Test name
Test status
Simulation time 3668268586 ps
CPU time 206.16 seconds
Started Jun 26 04:58:10 PM PDT 24
Finished Jun 26 05:01:39 PM PDT 24
Peak memory 858652 kb
Host smart-df06e52c-39a9-49e2-ac5e-006275033fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573142291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2573142291
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.3772947817
Short name T486
Test name
Test status
Simulation time 2076587350 ps
CPU time 139.41 seconds
Started Jun 26 04:58:09 PM PDT 24
Finished Jun 26 05:00:31 PM PDT 24
Peak memory 658320 kb
Host smart-4699676b-05bf-4136-bb8d-267cf10ad9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772947817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.3772947817
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3647434373
Short name T1320
Test name
Test status
Simulation time 497717851 ps
CPU time 1.09 seconds
Started Jun 26 04:58:15 PM PDT 24
Finished Jun 26 04:58:18 PM PDT 24
Peak memory 204472 kb
Host smart-cb1dda53-2f07-49df-a2b2-f93596c87972
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647434373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3647434373
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3871768587
Short name T930
Test name
Test status
Simulation time 791912843 ps
CPU time 3.71 seconds
Started Jun 26 04:58:13 PM PDT 24
Finished Jun 26 04:58:20 PM PDT 24
Peak memory 204768 kb
Host smart-268e9ae8-ba7b-45ed-b0f0-ccabfc13cda7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871768587 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3871768587
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3566537846
Short name T1369
Test name
Test status
Simulation time 20971019432 ps
CPU time 154.76 seconds
Started Jun 26 04:58:13 PM PDT 24
Finished Jun 26 05:00:51 PM PDT 24
Peak memory 1460316 kb
Host smart-0c33af9e-452b-469a-a5d5-0f382d2b066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566537846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3566537846
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3300248560
Short name T636
Test name
Test status
Simulation time 1665993294 ps
CPU time 5.94 seconds
Started Jun 26 04:58:17 PM PDT 24
Finished Jun 26 04:58:25 PM PDT 24
Peak memory 204756 kb
Host smart-6a59db22-7cd2-4a75-aec8-abe8f4a1d444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300248560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3300248560
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.3038475582
Short name T643
Test name
Test status
Simulation time 1996685207 ps
CPU time 30.52 seconds
Started Jun 26 04:58:30 PM PDT 24
Finished Jun 26 04:59:04 PM PDT 24
Peak memory 311260 kb
Host smart-a0f3305f-7f8e-4391-b550-c6c5b1026864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038475582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.3038475582
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2668237481
Short name T130
Test name
Test status
Simulation time 20176653 ps
CPU time 0.66 seconds
Started Jun 26 04:58:08 PM PDT 24
Finished Jun 26 04:58:11 PM PDT 24
Peak memory 204524 kb
Host smart-7db01ef6-3449-4952-8ddf-f4f036005bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668237481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2668237481
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.592536345
Short name T37
Test name
Test status
Simulation time 5398998268 ps
CPU time 81.28 seconds
Started Jun 26 04:58:12 PM PDT 24
Finished Jun 26 04:59:36 PM PDT 24
Peak memory 860492 kb
Host smart-fb485cb0-05cc-4e26-8836-986496e417f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592536345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.592536345
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.3759147271
Short name T1031
Test name
Test status
Simulation time 1834091298 ps
CPU time 20.71 seconds
Started Jun 26 04:58:10 PM PDT 24
Finished Jun 26 04:58:33 PM PDT 24
Peak memory 251036 kb
Host smart-f979115f-e209-412a-872b-288bbc9b76f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759147271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.3759147271
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.636400492
Short name T1435
Test name
Test status
Simulation time 9298350861 ps
CPU time 83.18 seconds
Started Jun 26 04:58:10 PM PDT 24
Finished Jun 26 04:59:37 PM PDT 24
Peak memory 362968 kb
Host smart-ca84b322-c3cf-45a8-918f-415a01dd8939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636400492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.636400492
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1332461810
Short name T194
Test name
Test status
Simulation time 1563679085 ps
CPU time 21.03 seconds
Started Jun 26 04:58:09 PM PDT 24
Finished Jun 26 04:58:33 PM PDT 24
Peak memory 213012 kb
Host smart-7575938b-b2b3-4f98-aad8-8293868bb79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332461810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1332461810
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.1855495624
Short name T553
Test name
Test status
Simulation time 681336475 ps
CPU time 3.75 seconds
Started Jun 26 04:58:15 PM PDT 24
Finished Jun 26 04:58:22 PM PDT 24
Peak memory 212988 kb
Host smart-c25c6535-c24e-4bf5-873d-d01f421d3e4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855495624 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.1855495624
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3010332084
Short name T1337
Test name
Test status
Simulation time 495870644 ps
CPU time 0.9 seconds
Started Jun 26 04:58:12 PM PDT 24
Finished Jun 26 04:58:16 PM PDT 24
Peak memory 204076 kb
Host smart-40c9149a-346e-478f-b3ca-3dad886df68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010332084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3010332084
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2346808435
Short name T1042
Test name
Test status
Simulation time 867671348 ps
CPU time 1.59 seconds
Started Jun 26 04:58:15 PM PDT 24
Finished Jun 26 04:58:19 PM PDT 24
Peak memory 218460 kb
Host smart-ecc230d3-9f5a-40cf-bede-c806d0448484
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346808435 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2346808435
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.66654554
Short name T435
Test name
Test status
Simulation time 1134536681 ps
CPU time 2.75 seconds
Started Jun 26 04:58:17 PM PDT 24
Finished Jun 26 04:58:22 PM PDT 24
Peak memory 204780 kb
Host smart-9055e341-d36e-4455-9796-3fc7a7569f53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66654554 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.66654554
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.1695337019
Short name T1405
Test name
Test status
Simulation time 200159630 ps
CPU time 1.44 seconds
Started Jun 26 04:58:27 PM PDT 24
Finished Jun 26 04:58:32 PM PDT 24
Peak memory 204592 kb
Host smart-bc52d46f-0571-436d-88d0-c39ad54da265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695337019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.1695337019
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.4203505313
Short name T300
Test name
Test status
Simulation time 359414435 ps
CPU time 3.62 seconds
Started Jun 26 04:58:25 PM PDT 24
Finished Jun 26 04:58:32 PM PDT 24
Peak memory 204816 kb
Host smart-f81f899e-d34e-4992-bb23-38afae9cd232
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203505313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.4203505313
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1170360965
Short name T826
Test name
Test status
Simulation time 673681668 ps
CPU time 4.2 seconds
Started Jun 26 04:58:14 PM PDT 24
Finished Jun 26 04:58:21 PM PDT 24
Peak memory 204804 kb
Host smart-6572023c-ee94-49c2-9b58-0c7fd426ac6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170360965 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1170360965
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3305393916
Short name T1138
Test name
Test status
Simulation time 16410458960 ps
CPU time 194.57 seconds
Started Jun 26 04:58:09 PM PDT 24
Finished Jun 26 05:01:26 PM PDT 24
Peak memory 2452308 kb
Host smart-3602dff1-52b6-4ada-adff-0617721329b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305393916 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3305393916
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1318499274
Short name T618
Test name
Test status
Simulation time 5097710301 ps
CPU time 16.32 seconds
Started Jun 26 04:58:11 PM PDT 24
Finished Jun 26 04:58:31 PM PDT 24
Peak memory 204876 kb
Host smart-b818543b-36de-474d-bd10-a9f11b273494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318499274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1318499274
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1057882559
Short name T1403
Test name
Test status
Simulation time 685640766 ps
CPU time 11.73 seconds
Started Jun 26 04:58:09 PM PDT 24
Finished Jun 26 04:58:23 PM PDT 24
Peak memory 206772 kb
Host smart-994bef00-db6b-442f-be4c-fdaeb7a55e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057882559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1057882559
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.373062847
Short name T1067
Test name
Test status
Simulation time 14830630089 ps
CPU time 27.39 seconds
Started Jun 26 04:58:11 PM PDT 24
Finished Jun 26 04:58:41 PM PDT 24
Peak memory 204872 kb
Host smart-6a1c2820-6020-4216-b039-8e1cf3af364f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373062847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_wr.373062847
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.3557310836
Short name T752
Test name
Test status
Simulation time 20721882595 ps
CPU time 609.55 seconds
Started Jun 26 04:58:12 PM PDT 24
Finished Jun 26 05:08:25 PM PDT 24
Peak memory 4242456 kb
Host smart-7abece8f-ddab-481d-8a04-4c1ee37a4549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557310836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.3557310836
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.3794854772
Short name T17
Test name
Test status
Simulation time 4672070967 ps
CPU time 6.35 seconds
Started Jun 26 04:58:14 PM PDT 24
Finished Jun 26 04:58:23 PM PDT 24
Peak memory 204960 kb
Host smart-2213762a-9316-4113-9397-9e70593f55a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794854772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.3794854772
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.38869054
Short name T156
Test name
Test status
Simulation time 42624911 ps
CPU time 0.68 seconds
Started Jun 26 04:58:29 PM PDT 24
Finished Jun 26 04:58:34 PM PDT 24
Peak memory 204408 kb
Host smart-ce736843-4b23-41af-9db1-b877953aa030
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38869054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.38869054
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.3474647264
Short name T39
Test name
Test status
Simulation time 119004440 ps
CPU time 1.97 seconds
Started Jun 26 04:58:25 PM PDT 24
Finished Jun 26 04:58:31 PM PDT 24
Peak memory 213092 kb
Host smart-7d9b232a-de47-4ab0-85bb-2221d22fc652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474647264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.3474647264
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.960056125
Short name T376
Test name
Test status
Simulation time 314950610 ps
CPU time 4.65 seconds
Started Jun 26 04:58:26 PM PDT 24
Finished Jun 26 04:58:35 PM PDT 24
Peak memory 255324 kb
Host smart-62155815-06e3-4e26-8dbf-f73b2309e6c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960056125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_empt
y.960056125
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.1762291522
Short name T74
Test name
Test status
Simulation time 5029397968 ps
CPU time 97.11 seconds
Started Jun 26 04:58:25 PM PDT 24
Finished Jun 26 05:00:05 PM PDT 24
Peak memory 567200 kb
Host smart-221e51e7-ff7a-4d31-a3d7-bc09410fbab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762291522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.1762291522
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.522253625
Short name T373
Test name
Test status
Simulation time 5509370007 ps
CPU time 104.61 seconds
Started Jun 26 04:58:16 PM PDT 24
Finished Jun 26 05:00:03 PM PDT 24
Peak memory 573764 kb
Host smart-d3210acd-4afc-4095-ba4b-ee40ebc29490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522253625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.522253625
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.948777703
Short name T1333
Test name
Test status
Simulation time 433630880 ps
CPU time 0.9 seconds
Started Jun 26 04:58:26 PM PDT 24
Finished Jun 26 04:58:30 PM PDT 24
Peak memory 204528 kb
Host smart-8931e3ea-5941-4697-afa3-40713ef7b499
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948777703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.948777703
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2001998321
Short name T448
Test name
Test status
Simulation time 502407857 ps
CPU time 4.25 seconds
Started Jun 26 04:58:25 PM PDT 24
Finished Jun 26 04:58:32 PM PDT 24
Peak memory 204828 kb
Host smart-57dd2914-3ce2-444a-9e3a-c91433cfee3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001998321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2001998321
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.4014966553
Short name T98
Test name
Test status
Simulation time 13104978954 ps
CPU time 80.51 seconds
Started Jun 26 04:58:24 PM PDT 24
Finished Jun 26 04:59:46 PM PDT 24
Peak memory 1087196 kb
Host smart-47ae3237-4168-4b1c-b6d2-20c161532654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014966553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.4014966553
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.3305612088
Short name T1360
Test name
Test status
Simulation time 421498584 ps
CPU time 6.77 seconds
Started Jun 26 05:01:13 PM PDT 24
Finished Jun 26 05:01:21 PM PDT 24
Peak memory 204856 kb
Host smart-c817adb7-51dd-489d-8c8c-de54e0a54497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305612088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.3305612088
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.3492961593
Short name T791
Test name
Test status
Simulation time 8027730637 ps
CPU time 107.82 seconds
Started Jun 26 04:58:36 PM PDT 24
Finished Jun 26 05:00:25 PM PDT 24
Peak memory 496576 kb
Host smart-6bafd076-8e18-4785-b618-6fe4709743f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492961593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.3492961593
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.2616127901
Short name T1386
Test name
Test status
Simulation time 24226042 ps
CPU time 0.69 seconds
Started Jun 26 04:58:18 PM PDT 24
Finished Jun 26 04:58:21 PM PDT 24
Peak memory 204560 kb
Host smart-14ea8664-9943-4854-bb30-0c662bbadc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616127901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.2616127901
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.272963197
Short name T552
Test name
Test status
Simulation time 14605689783 ps
CPU time 15.2 seconds
Started Jun 26 04:58:23 PM PDT 24
Finished Jun 26 04:58:40 PM PDT 24
Peak memory 221396 kb
Host smart-9115f4a1-d914-42b0-835b-dfc868434a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272963197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.272963197
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.3378322339
Short name T138
Test name
Test status
Simulation time 24731780067 ps
CPU time 96.6 seconds
Started Jun 26 04:58:38 PM PDT 24
Finished Jun 26 05:00:16 PM PDT 24
Peak memory 781540 kb
Host smart-65dfc540-0955-42d9-b3a9-2358c7ee432b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378322339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3378322339
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.1893523528
Short name T975
Test name
Test status
Simulation time 5574552624 ps
CPU time 69.2 seconds
Started Jun 26 04:58:27 PM PDT 24
Finished Jun 26 04:59:41 PM PDT 24
Peak memory 343376 kb
Host smart-20db8f7f-4f8b-4c8c-94c9-4ec01f83e830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893523528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.1893523528
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.1874890549
Short name T616
Test name
Test status
Simulation time 940026562 ps
CPU time 18.03 seconds
Started Jun 26 04:58:27 PM PDT 24
Finished Jun 26 04:58:49 PM PDT 24
Peak memory 219820 kb
Host smart-055fc9a2-0b91-4071-a27e-02f83cf1cd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874890549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.1874890549
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.2548980164
Short name T897
Test name
Test status
Simulation time 2221670151 ps
CPU time 3.12 seconds
Started Jun 26 04:58:31 PM PDT 24
Finished Jun 26 04:58:37 PM PDT 24
Peak memory 213068 kb
Host smart-d81bd6b0-cfb5-4276-8fa9-c1e1b02b23ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548980164 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.2548980164
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3451691374
Short name T805
Test name
Test status
Simulation time 494942704 ps
CPU time 1.13 seconds
Started Jun 26 04:58:24 PM PDT 24
Finished Jun 26 04:58:29 PM PDT 24
Peak memory 204728 kb
Host smart-44aeb8db-d78f-46da-9b97-a6e51d30d715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451691374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3451691374
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.4062802458
Short name T1072
Test name
Test status
Simulation time 388729538 ps
CPU time 0.84 seconds
Started Jun 26 04:58:37 PM PDT 24
Finished Jun 26 04:58:40 PM PDT 24
Peak memory 215232 kb
Host smart-68b46e2a-e1f7-48d7-8057-e98a241f747d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062802458 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.4062802458
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.2356114397
Short name T819
Test name
Test status
Simulation time 4592383561 ps
CPU time 3.05 seconds
Started Jun 26 04:58:35 PM PDT 24
Finished Jun 26 04:58:39 PM PDT 24
Peak memory 204960 kb
Host smart-596f6f96-efc8-4486-bfd1-c1756fb2195f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356114397 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.2356114397
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.3039784980
Short name T846
Test name
Test status
Simulation time 75311275 ps
CPU time 0.92 seconds
Started Jun 26 04:58:37 PM PDT 24
Finished Jun 26 04:58:39 PM PDT 24
Peak memory 204604 kb
Host smart-10818ed2-102d-469d-938f-fdea09760bac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039784980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.3039784980
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3887352140
Short name T515
Test name
Test status
Simulation time 3677892222 ps
CPU time 4.52 seconds
Started Jun 26 04:58:25 PM PDT 24
Finished Jun 26 04:58:33 PM PDT 24
Peak memory 207112 kb
Host smart-0d529a8d-78dd-4ff6-a403-d7287ebd7c38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887352140 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3887352140
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2955638750
Short name T527
Test name
Test status
Simulation time 14770589347 ps
CPU time 16.8 seconds
Started Jun 26 04:58:25 PM PDT 24
Finished Jun 26 04:58:46 PM PDT 24
Peak memory 432968 kb
Host smart-4cd43f7d-c082-4380-bd54-9d98b611cee9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955638750 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2955638750
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.3992165833
Short name T973
Test name
Test status
Simulation time 6335439195 ps
CPU time 47.04 seconds
Started Jun 26 04:58:26 PM PDT 24
Finished Jun 26 04:59:17 PM PDT 24
Peak memory 204940 kb
Host smart-419ed263-103b-4629-986b-72a999181e35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992165833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.3992165833
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1574472166
Short name T728
Test name
Test status
Simulation time 557529598 ps
CPU time 23.91 seconds
Started Jun 26 04:58:22 PM PDT 24
Finished Jun 26 04:58:47 PM PDT 24
Peak memory 204772 kb
Host smart-fc90df71-9781-47d0-af46-adfa4867e08b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574472166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1574472166
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.954527974
Short name T1160
Test name
Test status
Simulation time 45039459416 ps
CPU time 790.67 seconds
Started Jun 26 04:58:24 PM PDT 24
Finished Jun 26 05:11:39 PM PDT 24
Peak memory 6152344 kb
Host smart-ba14946c-ddd8-45f1-8050-eab7eb2fc517
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954527974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.954527974
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1025425976
Short name T1117
Test name
Test status
Simulation time 19954088160 ps
CPU time 388.82 seconds
Started Jun 26 04:58:38 PM PDT 24
Finished Jun 26 05:05:09 PM PDT 24
Peak memory 2544328 kb
Host smart-e8eaeb08-ac83-4e0b-8a1b-40ab6c9f01c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025425976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1025425976
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.335956062
Short name T164
Test name
Test status
Simulation time 3107337934 ps
CPU time 7.79 seconds
Started Jun 26 04:58:30 PM PDT 24
Finished Jun 26 04:58:41 PM PDT 24
Peak memory 213160 kb
Host smart-41cb6a88-d82f-4d64-bf26-11196fa09d7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335956062 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_timeout.335956062
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3687540103
Short name T1256
Test name
Test status
Simulation time 40101374 ps
CPU time 0.6 seconds
Started Jun 26 04:58:48 PM PDT 24
Finished Jun 26 04:58:51 PM PDT 24
Peak memory 204464 kb
Host smart-cd8cb7f3-a204-43a2-89df-c900e52e36c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687540103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3687540103
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.1934910216
Short name T934
Test name
Test status
Simulation time 126923032 ps
CPU time 2.13 seconds
Started Jun 26 04:58:40 PM PDT 24
Finished Jun 26 04:58:44 PM PDT 24
Peak memory 215496 kb
Host smart-bf7c1116-b814-46cd-bdbd-30382553196f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934910216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.1934910216
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.1063965764
Short name T1288
Test name
Test status
Simulation time 337890359 ps
CPU time 16.48 seconds
Started Jun 26 04:58:38 PM PDT 24
Finished Jun 26 04:58:56 PM PDT 24
Peak memory 259100 kb
Host smart-cc551943-4dfc-4861-a01f-07670e6837c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063965764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.1063965764
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1417547621
Short name T1379
Test name
Test status
Simulation time 13448467940 ps
CPU time 80.45 seconds
Started Jun 26 04:58:37 PM PDT 24
Finished Jun 26 04:59:59 PM PDT 24
Peak memory 701920 kb
Host smart-419d1f1b-91ed-4db3-8e82-02afc33a4a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417547621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1417547621
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.2330785310
Short name T1418
Test name
Test status
Simulation time 4587769586 ps
CPU time 88.73 seconds
Started Jun 26 04:58:30 PM PDT 24
Finished Jun 26 05:00:02 PM PDT 24
Peak memory 505396 kb
Host smart-ec1a0fa0-3618-4480-9713-eb9c9a4014ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330785310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.2330785310
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.531049777
Short name T705
Test name
Test status
Simulation time 678315773 ps
CPU time 1 seconds
Started Jun 26 04:58:36 PM PDT 24
Finished Jun 26 04:58:38 PM PDT 24
Peak memory 204520 kb
Host smart-c04d53d8-ec28-4b8e-9a03-73261b084328
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531049777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_fm
t.531049777
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3723275707
Short name T822
Test name
Test status
Simulation time 415386606 ps
CPU time 6.19 seconds
Started Jun 26 04:58:30 PM PDT 24
Finished Jun 26 04:58:39 PM PDT 24
Peak memory 220664 kb
Host smart-7c679a57-6fed-40e0-b442-f1a9fcdfe50e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723275707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3723275707
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1306192806
Short name T1370
Test name
Test status
Simulation time 4655745242 ps
CPU time 138.04 seconds
Started Jun 26 04:58:32 PM PDT 24
Finished Jun 26 05:00:53 PM PDT 24
Peak memory 1353264 kb
Host smart-a13ad871-ff70-4f22-a475-f5531cd0ea14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306192806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1306192806
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.3965788683
Short name T1410
Test name
Test status
Simulation time 241213747 ps
CPU time 7.74 seconds
Started Jun 26 04:58:39 PM PDT 24
Finished Jun 26 04:58:49 PM PDT 24
Peak memory 204860 kb
Host smart-1f4ce370-4df4-4134-9abb-7168af4102f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965788683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.3965788683
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.3579563457
Short name T1402
Test name
Test status
Simulation time 3182726589 ps
CPU time 70.85 seconds
Started Jun 26 04:58:40 PM PDT 24
Finished Jun 26 04:59:53 PM PDT 24
Peak memory 295944 kb
Host smart-73701927-717e-4bab-b4b1-b67b92ee3e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579563457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.3579563457
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.1461274412
Short name T1261
Test name
Test status
Simulation time 19582919 ps
CPU time 0.67 seconds
Started Jun 26 04:58:37 PM PDT 24
Finished Jun 26 04:58:39 PM PDT 24
Peak memory 204536 kb
Host smart-e9bbb172-0e1a-46b4-b555-1c661cc39cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461274412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.1461274412
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.146873037
Short name T755
Test name
Test status
Simulation time 7307034128 ps
CPU time 256.83 seconds
Started Jun 26 04:58:39 PM PDT 24
Finished Jun 26 05:02:58 PM PDT 24
Peak memory 1398920 kb
Host smart-dbf0bd29-6e89-494b-b4c1-9d283af2b52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146873037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.146873037
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.1328211297
Short name T1061
Test name
Test status
Simulation time 176141929 ps
CPU time 2.52 seconds
Started Jun 26 04:58:38 PM PDT 24
Finished Jun 26 04:58:43 PM PDT 24
Peak memory 212936 kb
Host smart-cd040146-a22c-4c36-8951-4b1a3b5ca1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328211297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.1328211297
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3369080154
Short name T1009
Test name
Test status
Simulation time 3684998429 ps
CPU time 47.94 seconds
Started Jun 26 04:58:36 PM PDT 24
Finished Jun 26 04:59:25 PM PDT 24
Peak memory 297692 kb
Host smart-6c3c9b11-e8b7-4bef-a6bd-bd00172305ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369080154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3369080154
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.1082987655
Short name T111
Test name
Test status
Simulation time 13340573306 ps
CPU time 295.49 seconds
Started Jun 26 04:58:41 PM PDT 24
Finished Jun 26 05:03:38 PM PDT 24
Peak memory 1385376 kb
Host smart-022f6c8e-d891-4333-8537-14b30953b902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082987655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.1082987655
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.1729410400
Short name T561
Test name
Test status
Simulation time 15769792124 ps
CPU time 12.21 seconds
Started Jun 26 04:58:45 PM PDT 24
Finished Jun 26 04:58:58 PM PDT 24
Peak memory 229272 kb
Host smart-493d2341-e7a2-4a30-a441-ef600801c005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729410400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.1729410400
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.4189805200
Short name T554
Test name
Test status
Simulation time 878674886 ps
CPU time 4.05 seconds
Started Jun 26 04:58:43 PM PDT 24
Finished Jun 26 04:58:49 PM PDT 24
Peak memory 204912 kb
Host smart-39970dac-573b-47b0-92db-3d530520186a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189805200 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.4189805200
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.73779852
Short name T530
Test name
Test status
Simulation time 193219802 ps
CPU time 1.18 seconds
Started Jun 26 04:58:42 PM PDT 24
Finished Jun 26 04:58:44 PM PDT 24
Peak memory 204552 kb
Host smart-08d37d81-b7b0-4593-ad8a-53d128b09b06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73779852 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_acq.73779852
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3030107870
Short name T434
Test name
Test status
Simulation time 523903287 ps
CPU time 0.99 seconds
Started Jun 26 04:58:43 PM PDT 24
Finished Jun 26 04:58:46 PM PDT 24
Peak memory 204640 kb
Host smart-a135f7cf-1d0a-4534-a45b-5893fd48ed44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030107870 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3030107870
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.852861843
Short name T145
Test name
Test status
Simulation time 399342608 ps
CPU time 2.19 seconds
Started Jun 26 04:58:48 PM PDT 24
Finished Jun 26 04:58:51 PM PDT 24
Peak memory 204764 kb
Host smart-c070682f-8ac0-450d-8c85-9064914c83f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852861843 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.852861843
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.3677498560
Short name T1277
Test name
Test status
Simulation time 131502190 ps
CPU time 1.17 seconds
Started Jun 26 04:58:50 PM PDT 24
Finished Jun 26 04:58:53 PM PDT 24
Peak memory 204592 kb
Host smart-a46ff35c-13ff-40ef-8461-a2747a461166
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677498560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.3677498560
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.148516047
Short name T1011
Test name
Test status
Simulation time 746006213 ps
CPU time 2.66 seconds
Started Jun 26 04:58:40 PM PDT 24
Finished Jun 26 04:58:45 PM PDT 24
Peak memory 204848 kb
Host smart-cc1d2b8a-0ce8-440f-a984-7d6927805a40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148516047 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 27.i2c_target_hrst.148516047
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.4284357051
Short name T446
Test name
Test status
Simulation time 5098091759 ps
CPU time 4.12 seconds
Started Jun 26 04:58:42 PM PDT 24
Finished Jun 26 04:58:48 PM PDT 24
Peak memory 206592 kb
Host smart-392fec5a-3e3b-4a67-94a0-28b25218c7e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284357051 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.4284357051
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1848478241
Short name T1325
Test name
Test status
Simulation time 17432746641 ps
CPU time 43.42 seconds
Started Jun 26 04:58:38 PM PDT 24
Finished Jun 26 04:59:23 PM PDT 24
Peak memory 1081024 kb
Host smart-b7672649-80b2-485e-b307-6da23f465d92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848478241 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1848478241
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3009542236
Short name T815
Test name
Test status
Simulation time 1811894254 ps
CPU time 11.75 seconds
Started Jun 26 04:58:39 PM PDT 24
Finished Jun 26 04:58:53 PM PDT 24
Peak memory 204744 kb
Host smart-1a578687-ce9a-4b53-bedc-b170a5bd9999
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009542236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3009542236
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1497142549
Short name T596
Test name
Test status
Simulation time 34204346966 ps
CPU time 56.86 seconds
Started Jun 26 04:58:41 PM PDT 24
Finished Jun 26 04:59:40 PM PDT 24
Peak memory 1046244 kb
Host smart-227e680d-df03-463f-bbec-629e8c548dec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497142549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1497142549
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.4231152997
Short name T1462
Test name
Test status
Simulation time 10740277583 ps
CPU time 86.17 seconds
Started Jun 26 04:58:38 PM PDT 24
Finished Jun 26 05:00:06 PM PDT 24
Peak memory 1314404 kb
Host smart-5df1e239-39d3-4dc0-ae47-88aa10d3cf1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231152997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.4231152997
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.4134186657
Short name T677
Test name
Test status
Simulation time 2103277859 ps
CPU time 6.22 seconds
Started Jun 26 04:58:40 PM PDT 24
Finished Jun 26 04:58:48 PM PDT 24
Peak memory 220124 kb
Host smart-e375ea16-dbf7-44da-84d6-b245bafdd994
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134186657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.4134186657
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.1929552105
Short name T833
Test name
Test status
Simulation time 19320679 ps
CPU time 0.64 seconds
Started Jun 26 04:59:00 PM PDT 24
Finished Jun 26 04:59:02 PM PDT 24
Peak memory 204452 kb
Host smart-01961178-c8f4-4973-b819-532f62877530
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929552105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.1929552105
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.17481301
Short name T1152
Test name
Test status
Simulation time 408806419 ps
CPU time 3.47 seconds
Started Jun 26 04:58:55 PM PDT 24
Finished Jun 26 04:59:00 PM PDT 24
Peak memory 229372 kb
Host smart-f3ed78c9-a6c4-42fe-9a55-536b6a248c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17481301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.17481301
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.1745527852
Short name T1224
Test name
Test status
Simulation time 705361044 ps
CPU time 4.63 seconds
Started Jun 26 04:58:47 PM PDT 24
Finished Jun 26 04:58:53 PM PDT 24
Peak memory 240976 kb
Host smart-688e9151-ceb3-425c-b9c2-83de34b54ea5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745527852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.1745527852
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3305596951
Short name T413
Test name
Test status
Simulation time 2653288349 ps
CPU time 96.56 seconds
Started Jun 26 04:58:49 PM PDT 24
Finished Jun 26 05:00:27 PM PDT 24
Peak memory 853088 kb
Host smart-bb159630-e835-4c43-a878-34f088879758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305596951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3305596951
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.2815096453
Short name T379
Test name
Test status
Simulation time 2770808833 ps
CPU time 103.9 seconds
Started Jun 26 04:58:50 PM PDT 24
Finished Jun 26 05:00:35 PM PDT 24
Peak memory 897780 kb
Host smart-cb7c3b44-e0f7-4df1-bada-4e8b820bba55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815096453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2815096453
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2255030388
Short name T423
Test name
Test status
Simulation time 159242190 ps
CPU time 1.05 seconds
Started Jun 26 04:58:47 PM PDT 24
Finished Jun 26 04:58:50 PM PDT 24
Peak memory 204528 kb
Host smart-d2d434b9-55c3-405a-b035-85279bc1dfa2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255030388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2255030388
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1022102440
Short name T1180
Test name
Test status
Simulation time 551277203 ps
CPU time 6.63 seconds
Started Jun 26 04:58:50 PM PDT 24
Finished Jun 26 04:58:58 PM PDT 24
Peak memory 204764 kb
Host smart-43c74dd7-f1f3-45e6-a8b2-b117bc3e8971
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022102440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1022102440
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.1462182652
Short name T1098
Test name
Test status
Simulation time 21784524544 ps
CPU time 146.13 seconds
Started Jun 26 04:58:47 PM PDT 24
Finished Jun 26 05:01:15 PM PDT 24
Peak memory 1370408 kb
Host smart-bd357553-801f-4561-a688-1ad6a7aa2ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462182652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.1462182652
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.4077287406
Short name T679
Test name
Test status
Simulation time 452628403 ps
CPU time 5.97 seconds
Started Jun 26 04:59:00 PM PDT 24
Finished Jun 26 04:59:07 PM PDT 24
Peak memory 204820 kb
Host smart-e3c577d1-f183-4cb4-b2e0-19882551e352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077287406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.4077287406
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1489651263
Short name T915
Test name
Test status
Simulation time 1801913319 ps
CPU time 85.15 seconds
Started Jun 26 04:58:54 PM PDT 24
Finished Jun 26 05:00:21 PM PDT 24
Peak memory 400628 kb
Host smart-07a199c8-cb04-4a4f-9383-64ef6fc20f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489651263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1489651263
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1228428767
Short name T1088
Test name
Test status
Simulation time 28226918 ps
CPU time 0.69 seconds
Started Jun 26 04:58:46 PM PDT 24
Finished Jun 26 04:58:48 PM PDT 24
Peak memory 204548 kb
Host smart-162bc117-c85c-47f2-b5f9-f76e9fe966bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228428767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1228428767
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3944112676
Short name T57
Test name
Test status
Simulation time 7109947733 ps
CPU time 612.47 seconds
Started Jun 26 04:58:49 PM PDT 24
Finished Jun 26 05:09:03 PM PDT 24
Peak memory 1760368 kb
Host smart-5d2f2317-7f58-43e5-8b73-31e478ad23c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944112676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3944112676
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.1444194057
Short name T1384
Test name
Test status
Simulation time 74093354 ps
CPU time 2.03 seconds
Started Jun 26 04:58:51 PM PDT 24
Finished Jun 26 04:58:54 PM PDT 24
Peak memory 204776 kb
Host smart-9047c9c9-2ff0-4a33-bf60-cea63ade1322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444194057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.1444194057
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.213736072
Short name T936
Test name
Test status
Simulation time 2745109439 ps
CPU time 22.81 seconds
Started Jun 26 04:58:46 PM PDT 24
Finished Jun 26 04:59:10 PM PDT 24
Peak memory 361440 kb
Host smart-c3df2579-59df-4670-b6fd-01d49eb440f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213736072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.213736072
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.3960418023
Short name T264
Test name
Test status
Simulation time 3350528699 ps
CPU time 16.95 seconds
Started Jun 26 04:58:54 PM PDT 24
Finished Jun 26 04:59:12 PM PDT 24
Peak memory 220840 kb
Host smart-958f51c4-5bca-47d7-a51c-cd0bfdebb541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960418023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.3960418023
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1153741589
Short name T1182
Test name
Test status
Simulation time 771806815 ps
CPU time 4.42 seconds
Started Jun 26 04:58:55 PM PDT 24
Finished Jun 26 04:59:01 PM PDT 24
Peak memory 213116 kb
Host smart-dae82e33-e4c4-4da2-a368-1d19b7245bf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153741589 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1153741589
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.2210087175
Short name T890
Test name
Test status
Simulation time 406960720 ps
CPU time 1.03 seconds
Started Jun 26 04:58:56 PM PDT 24
Finished Jun 26 04:58:59 PM PDT 24
Peak memory 204556 kb
Host smart-5e8961de-b7b3-40fc-8fbe-b60e0b8409be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210087175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.2210087175
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.1240809548
Short name T807
Test name
Test status
Simulation time 403880314 ps
CPU time 1.7 seconds
Started Jun 26 04:58:56 PM PDT 24
Finished Jun 26 04:59:00 PM PDT 24
Peak memory 207524 kb
Host smart-2e5c107d-5abb-4a45-821d-957532e3de84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240809548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.1240809548
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.1272848759
Short name T1196
Test name
Test status
Simulation time 504132992 ps
CPU time 2.73 seconds
Started Jun 26 04:58:56 PM PDT 24
Finished Jun 26 04:59:01 PM PDT 24
Peak memory 204816 kb
Host smart-7495641c-49ae-469d-a87b-d19996a294a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272848759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.1272848759
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.3173928894
Short name T1102
Test name
Test status
Simulation time 272897712 ps
CPU time 0.91 seconds
Started Jun 26 04:58:57 PM PDT 24
Finished Jun 26 04:59:00 PM PDT 24
Peak memory 204552 kb
Host smart-4246fe41-4a1f-4f95-9ad4-20d6dd15988f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173928894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.3173928894
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2462829452
Short name T945
Test name
Test status
Simulation time 321000334 ps
CPU time 2.59 seconds
Started Jun 26 04:58:59 PM PDT 24
Finished Jun 26 04:59:03 PM PDT 24
Peak memory 204808 kb
Host smart-847da26f-7eaa-4c59-b625-7c8820bbcbc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462829452 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2462829452
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.4113673161
Short name T1230
Test name
Test status
Simulation time 12975029326 ps
CPU time 6.98 seconds
Started Jun 26 04:58:50 PM PDT 24
Finished Jun 26 04:58:59 PM PDT 24
Peak memory 205796 kb
Host smart-44ba855b-09e6-4949-9eb0-9a830b9b47e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113673161 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.4113673161
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.3653805001
Short name T305
Test name
Test status
Simulation time 9620971617 ps
CPU time 48.58 seconds
Started Jun 26 04:58:54 PM PDT 24
Finished Jun 26 04:59:44 PM PDT 24
Peak memory 1212728 kb
Host smart-0eca45c5-916f-4489-bedf-bd6ddeb708e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653805001 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.3653805001
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.185118232
Short name T627
Test name
Test status
Simulation time 5812693360 ps
CPU time 53.56 seconds
Started Jun 26 04:58:46 PM PDT 24
Finished Jun 26 04:59:41 PM PDT 24
Peak memory 204976 kb
Host smart-2d0ce40c-7124-473b-b1b2-5362df5ef1f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185118232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_tar
get_smoke.185118232
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.2211034891
Short name T1012
Test name
Test status
Simulation time 2965903198 ps
CPU time 12.19 seconds
Started Jun 26 04:58:49 PM PDT 24
Finished Jun 26 04:59:02 PM PDT 24
Peak memory 219444 kb
Host smart-0e20fd65-6894-4960-a25f-3bc8fe13307d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211034891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.2211034891
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3040502778
Short name T438
Test name
Test status
Simulation time 23019690952 ps
CPU time 13.39 seconds
Started Jun 26 04:58:47 PM PDT 24
Finished Jun 26 04:59:01 PM PDT 24
Peak memory 247636 kb
Host smart-e3c6ed02-9fa8-4916-9f20-504cf788fb71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040502778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3040502778
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2753643377
Short name T570
Test name
Test status
Simulation time 12466067083 ps
CPU time 51.19 seconds
Started Jun 26 04:58:50 PM PDT 24
Finished Jun 26 04:59:42 PM PDT 24
Peak memory 690784 kb
Host smart-1ad8be61-e9fe-495d-b552-246537f8bf9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753643377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2753643377
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1353119919
Short name T1169
Test name
Test status
Simulation time 1393912004 ps
CPU time 7.58 seconds
Started Jun 26 04:58:55 PM PDT 24
Finished Jun 26 04:59:05 PM PDT 24
Peak memory 220196 kb
Host smart-1d2f452b-7c07-415c-b34d-2806a4e2ec0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353119919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1353119919
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1788886296
Short name T1192
Test name
Test status
Simulation time 37935456 ps
CPU time 0.61 seconds
Started Jun 26 04:59:17 PM PDT 24
Finished Jun 26 04:59:21 PM PDT 24
Peak memory 204456 kb
Host smart-ba754ce8-da42-48d5-93d3-8a526c714b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788886296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1788886296
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3576669214
Short name T49
Test name
Test status
Simulation time 700400142 ps
CPU time 6.29 seconds
Started Jun 26 04:59:09 PM PDT 24
Finished Jun 26 04:59:16 PM PDT 24
Peak memory 250732 kb
Host smart-54386f10-4cfc-4803-88de-3d24f03436d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576669214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3576669214
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.65196585
Short name T814
Test name
Test status
Simulation time 319751409 ps
CPU time 16.64 seconds
Started Jun 26 04:59:06 PM PDT 24
Finished Jun 26 04:59:24 PM PDT 24
Peak memory 274492 kb
Host smart-c5561084-86cd-447f-98ac-b2dae816d1f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65196585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empty
.65196585
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.1087467516
Short name T1460
Test name
Test status
Simulation time 2683346587 ps
CPU time 62.28 seconds
Started Jun 26 04:59:06 PM PDT 24
Finished Jun 26 05:00:09 PM PDT 24
Peak memory 490176 kb
Host smart-a6d8394c-cf34-4de7-b1e0-9ae0e2940782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087467516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.1087467516
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1045031848
Short name T64
Test name
Test status
Simulation time 9339936961 ps
CPU time 36.28 seconds
Started Jun 26 04:59:08 PM PDT 24
Finished Jun 26 04:59:46 PM PDT 24
Peak memory 530504 kb
Host smart-73b80c25-2d7a-4518-97c9-c5802ab4dc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045031848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1045031848
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.1192072482
Short name T1424
Test name
Test status
Simulation time 1347704117 ps
CPU time 0.95 seconds
Started Jun 26 04:59:07 PM PDT 24
Finished Jun 26 04:59:09 PM PDT 24
Peak memory 204468 kb
Host smart-daef46b9-b724-4379-9cdb-fc927e9a6e25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192072482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.1192072482
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.3380310261
Short name T1017
Test name
Test status
Simulation time 110776888 ps
CPU time 6.48 seconds
Started Jun 26 04:59:07 PM PDT 24
Finished Jun 26 04:59:14 PM PDT 24
Peak memory 222596 kb
Host smart-8fcb73c4-0e33-4bce-a0db-9de1cb7d817e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380310261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.3380310261
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3721601896
Short name T143
Test name
Test status
Simulation time 4484854928 ps
CPU time 308.14 seconds
Started Jun 26 04:58:56 PM PDT 24
Finished Jun 26 05:04:06 PM PDT 24
Peak memory 1214912 kb
Host smart-34ec109d-3eb2-43b2-9946-1882b3f44b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721601896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3721601896
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.761986002
Short name T427
Test name
Test status
Simulation time 2287315591 ps
CPU time 6.59 seconds
Started Jun 26 04:59:18 PM PDT 24
Finished Jun 26 04:59:28 PM PDT 24
Peak memory 204976 kb
Host smart-772ccbe4-668d-44f2-ab0e-0837f04278d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761986002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.761986002
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.4235296006
Short name T1145
Test name
Test status
Simulation time 5881661022 ps
CPU time 28.44 seconds
Started Jun 26 04:59:20 PM PDT 24
Finished Jun 26 04:59:51 PM PDT 24
Peak memory 412384 kb
Host smart-a64c8f1f-4e1f-473f-abc0-c049cccf4e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235296006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.4235296006
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.4281927278
Short name T128
Test name
Test status
Simulation time 46345689 ps
CPU time 0.64 seconds
Started Jun 26 04:58:56 PM PDT 24
Finished Jun 26 04:58:59 PM PDT 24
Peak memory 204560 kb
Host smart-3541018c-9741-48df-9c13-38e6f8aeaabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281927278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.4281927278
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.2205153204
Short name T922
Test name
Test status
Simulation time 766837362 ps
CPU time 3.93 seconds
Started Jun 26 04:59:06 PM PDT 24
Finished Jun 26 04:59:11 PM PDT 24
Peak memory 229520 kb
Host smart-992bed83-d746-486f-9458-ba7e5907ec63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205153204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.2205153204
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.3800911293
Short name T1113
Test name
Test status
Simulation time 91835878 ps
CPU time 3.62 seconds
Started Jun 26 04:59:08 PM PDT 24
Finished Jun 26 04:59:13 PM PDT 24
Peak memory 222712 kb
Host smart-3ea151bc-0426-4fc7-8b61-b4aadcea8c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800911293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.3800911293
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3715718492
Short name T663
Test name
Test status
Simulation time 1147115223 ps
CPU time 17.7 seconds
Started Jun 26 04:58:55 PM PDT 24
Finished Jun 26 04:59:15 PM PDT 24
Peak memory 317516 kb
Host smart-50c86238-45d9-42d3-bd8f-5176aadf9a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715718492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3715718492
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.4261012192
Short name T223
Test name
Test status
Simulation time 16153636541 ps
CPU time 892.04 seconds
Started Jun 26 04:59:07 PM PDT 24
Finished Jun 26 05:14:01 PM PDT 24
Peak memory 3779880 kb
Host smart-a4f7851b-9cbd-4b9d-acab-224ed3b4cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261012192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.4261012192
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.554553472
Short name T1464
Test name
Test status
Simulation time 1244342587 ps
CPU time 11.23 seconds
Started Jun 26 04:59:10 PM PDT 24
Finished Jun 26 04:59:22 PM PDT 24
Peak memory 221072 kb
Host smart-a1d9c25d-e38d-4520-bd48-8c0911163f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554553472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.554553472
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.4240399500
Short name T718
Test name
Test status
Simulation time 1218139409 ps
CPU time 6.54 seconds
Started Jun 26 04:59:14 PM PDT 24
Finished Jun 26 04:59:22 PM PDT 24
Peak memory 216136 kb
Host smart-df1be087-5c69-4953-b3bd-bec5d859d471
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240399500 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.4240399500
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.95780695
Short name T1467
Test name
Test status
Simulation time 398593261 ps
CPU time 1.51 seconds
Started Jun 26 04:59:19 PM PDT 24
Finished Jun 26 04:59:24 PM PDT 24
Peak memory 212992 kb
Host smart-79971a16-70b5-4b7f-a167-b14347f026b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95780695 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.i2c_target_fifo_reset_tx.95780695
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.3397239666
Short name T244
Test name
Test status
Simulation time 343745160 ps
CPU time 1.29 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 04:59:21 PM PDT 24
Peak memory 204540 kb
Host smart-6a0a6959-434f-4b38-8dc2-a9339ca3f522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397239666 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.3397239666
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2037978310
Short name T1162
Test name
Test status
Simulation time 151396894 ps
CPU time 1.24 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 04:59:21 PM PDT 24
Peak memory 204820 kb
Host smart-e455b5af-2215-44a5-b238-6e7a36d542dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037978310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2037978310
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.136817753
Short name T32
Test name
Test status
Simulation time 1189916570 ps
CPU time 3.32 seconds
Started Jun 26 04:59:15 PM PDT 24
Finished Jun 26 04:59:20 PM PDT 24
Peak memory 204728 kb
Host smart-207ac584-f30a-4c5a-b053-36f3047d7fba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136817753 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.136817753
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.900140084
Short name T293
Test name
Test status
Simulation time 1348665725 ps
CPU time 6.78 seconds
Started Jun 26 04:59:08 PM PDT 24
Finished Jun 26 04:59:17 PM PDT 24
Peak memory 217428 kb
Host smart-1644f4ad-020d-420b-85c0-a5e9703936bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900140084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.900140084
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2703420441
Short name T1286
Test name
Test status
Simulation time 16722096066 ps
CPU time 37.16 seconds
Started Jun 26 04:59:12 PM PDT 24
Finished Jun 26 04:59:49 PM PDT 24
Peak memory 942940 kb
Host smart-72676265-0395-4fb9-a29b-f09002de7287
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703420441 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2703420441
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2239599499
Short name T1284
Test name
Test status
Simulation time 3853265949 ps
CPU time 32.57 seconds
Started Jun 26 04:59:07 PM PDT 24
Finished Jun 26 04:59:41 PM PDT 24
Peak memory 204904 kb
Host smart-0f92b3fe-65a7-4115-9525-6fee12278d07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239599499 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2239599499
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1913633730
Short name T356
Test name
Test status
Simulation time 2344079117 ps
CPU time 9.98 seconds
Started Jun 26 04:59:07 PM PDT 24
Finished Jun 26 04:59:18 PM PDT 24
Peak memory 206024 kb
Host smart-c18611a8-cebf-4c1b-970e-25f043aa3c11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913633730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1913633730
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2953930896
Short name T1371
Test name
Test status
Simulation time 11275576154 ps
CPU time 7.06 seconds
Started Jun 26 04:59:09 PM PDT 24
Finished Jun 26 04:59:17 PM PDT 24
Peak memory 204936 kb
Host smart-f2125cd7-34e2-4973-bf3c-a7b12ed79212
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953930896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2953930896
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.2952315067
Short name T1388
Test name
Test status
Simulation time 35153130814 ps
CPU time 2150.92 seconds
Started Jun 26 04:59:08 PM PDT 24
Finished Jun 26 05:35:00 PM PDT 24
Peak memory 8347680 kb
Host smart-71e20266-8dfe-4b32-9756-f76b4a550bb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952315067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.2952315067
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2814553694
Short name T449
Test name
Test status
Simulation time 2139993999 ps
CPU time 6.36 seconds
Started Jun 26 04:59:05 PM PDT 24
Finished Jun 26 04:59:12 PM PDT 24
Peak memory 213172 kb
Host smart-1902f5be-ccd5-4ca0-a1a4-1c082dda1dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814553694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2814553694
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.1000704155
Short name T157
Test name
Test status
Simulation time 18067288 ps
CPU time 0.64 seconds
Started Jun 26 04:55:56 PM PDT 24
Finished Jun 26 04:55:59 PM PDT 24
Peak memory 204428 kb
Host smart-19c83e8b-a149-49e6-88aa-04a5062e8c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000704155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.1000704155
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.3756940572
Short name T966
Test name
Test status
Simulation time 232794759 ps
CPU time 3.83 seconds
Started Jun 26 04:56:01 PM PDT 24
Finished Jun 26 04:56:08 PM PDT 24
Peak memory 221052 kb
Host smart-57869113-85b9-46d3-8d2e-d1607e35150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756940572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.3756940572
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2662140862
Short name T661
Test name
Test status
Simulation time 1199859423 ps
CPU time 5.88 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:13 PM PDT 24
Peak memory 259616 kb
Host smart-e00f668a-bd47-4eff-adce-abd7bf40672a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662140862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2662140862
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.2143557241
Short name T139
Test name
Test status
Simulation time 1906519612 ps
CPU time 125.83 seconds
Started Jun 26 04:55:53 PM PDT 24
Finished Jun 26 04:58:01 PM PDT 24
Peak memory 660720 kb
Host smart-59f1c92d-976d-49ec-86cd-6095888a1aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143557241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.2143557241
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.791798950
Short name T360
Test name
Test status
Simulation time 3965274508 ps
CPU time 132.96 seconds
Started Jun 26 04:56:00 PM PDT 24
Finished Jun 26 04:58:16 PM PDT 24
Peak memory 680144 kb
Host smart-f5237eb2-1e61-4840-892d-6f4be078175e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791798950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.791798950
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.838426352
Short name T1236
Test name
Test status
Simulation time 127778749 ps
CPU time 1.02 seconds
Started Jun 26 04:55:45 PM PDT 24
Finished Jun 26 04:55:48 PM PDT 24
Peak memory 204484 kb
Host smart-a1d1913b-6bc1-4e01-a492-06ecf84068ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838426352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fmt
.838426352
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.4201265313
Short name T617
Test name
Test status
Simulation time 1677243472 ps
CPU time 3.2 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 204076 kb
Host smart-ced99f61-e32e-4cee-ac0d-77cb8077deac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201265313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
4201265313
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.3547376254
Short name T1215
Test name
Test status
Simulation time 42554466323 ps
CPU time 298.22 seconds
Started Jun 26 04:55:49 PM PDT 24
Finished Jun 26 05:00:50 PM PDT 24
Peak memory 1269224 kb
Host smart-89c0c2a3-18d0-46ff-a6c6-ad1a2cf43768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547376254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.3547376254
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.761940522
Short name T1398
Test name
Test status
Simulation time 1483912123 ps
CPU time 63.97 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:57:06 PM PDT 24
Peak memory 278908 kb
Host smart-a19d6ad0-b9ca-45b2-9304-09fe03e49dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761940522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.761940522
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.779363483
Short name T678
Test name
Test status
Simulation time 85662378 ps
CPU time 0.74 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:55:51 PM PDT 24
Peak memory 204504 kb
Host smart-46ebb4eb-00fd-472a-97d6-7a2cda661d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779363483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.779363483
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1838123120
Short name T615
Test name
Test status
Simulation time 2869991367 ps
CPU time 33.24 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:39 PM PDT 24
Peak memory 337468 kb
Host smart-fef0d52e-4db9-4cfa-a010-6de73e88163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838123120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1838123120
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.980234563
Short name T326
Test name
Test status
Simulation time 2374024705 ps
CPU time 30.01 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:36 PM PDT 24
Peak memory 326888 kb
Host smart-ea7b48d1-6cca-4620-b0e0-9a58ce1466a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980234563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.980234563
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.1514194762
Short name T1406
Test name
Test status
Simulation time 5855201538 ps
CPU time 29.67 seconds
Started Jun 26 04:55:47 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 430492 kb
Host smart-42350c26-fb5a-47e5-94db-0ba96397bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514194762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.1514194762
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.130151750
Short name T1144
Test name
Test status
Simulation time 19231977800 ps
CPU time 247.09 seconds
Started Jun 26 04:56:04 PM PDT 24
Finished Jun 26 05:00:15 PM PDT 24
Peak memory 1357760 kb
Host smart-76eab88f-bb29-4a38-a698-f8f0f8c7efd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130151750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.130151750
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.1153380984
Short name T260
Test name
Test status
Simulation time 2278599511 ps
CPU time 31.19 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:37 PM PDT 24
Peak memory 212548 kb
Host smart-298ed6c2-bc1e-459a-99e1-7fb66fb08102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153380984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.1153380984
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.548455860
Short name T160
Test name
Test status
Simulation time 39844258 ps
CPU time 0.86 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 222092 kb
Host smart-c90b873b-45e3-4648-add8-265005ed1cca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548455860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.548455860
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.71180935
Short name T607
Test name
Test status
Simulation time 1213657486 ps
CPU time 3.66 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:05 PM PDT 24
Peak memory 213012 kb
Host smart-f886ad80-e7d2-47a8-acdd-ea6e605cbf40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71180935 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_bad_addr.71180935
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.2899155195
Short name T555
Test name
Test status
Simulation time 174981682 ps
CPU time 1.05 seconds
Started Jun 26 04:55:57 PM PDT 24
Finished Jun 26 04:56:00 PM PDT 24
Peak memory 212824 kb
Host smart-12ea6303-36a9-447b-9bbf-b0f18d05850a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899155195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.2899155195
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.484941426
Short name T782
Test name
Test status
Simulation time 174367904 ps
CPU time 1.03 seconds
Started Jun 26 04:56:06 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 204632 kb
Host smart-14590757-eebb-4b08-9122-4759f1b27371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484941426 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.i2c_target_fifo_reset_tx.484941426
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.2597688917
Short name T1273
Test name
Test status
Simulation time 2400317920 ps
CPU time 2.91 seconds
Started Jun 26 04:55:55 PM PDT 24
Finished Jun 26 04:56:00 PM PDT 24
Peak memory 204888 kb
Host smart-ae6c2da3-e3db-418d-ad50-76e11960d4a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597688917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.2597688917
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.4150375739
Short name T1107
Test name
Test status
Simulation time 264988884 ps
CPU time 1.13 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 204628 kb
Host smart-7982948a-21c3-4df2-b5f4-7e2badeb8da2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150375739 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.4150375739
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1244481524
Short name T276
Test name
Test status
Simulation time 993512121 ps
CPU time 4.52 seconds
Started Jun 26 04:55:58 PM PDT 24
Finished Jun 26 04:56:05 PM PDT 24
Peak memory 204856 kb
Host smart-fbcac9b5-a001-4b83-81a4-a0a36a303608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244481524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1244481524
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.4209685565
Short name T1099
Test name
Test status
Simulation time 2284799225 ps
CPU time 3.09 seconds
Started Jun 26 04:56:04 PM PDT 24
Finished Jun 26 04:56:10 PM PDT 24
Peak memory 204908 kb
Host smart-ca2b2868-492b-46ae-a11b-862e35090245
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209685565 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.4209685565
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3133486631
Short name T528
Test name
Test status
Simulation time 13879237122 ps
CPU time 27.98 seconds
Started Jun 26 04:55:54 PM PDT 24
Finished Jun 26 04:56:24 PM PDT 24
Peak memory 828656 kb
Host smart-68e3f6ee-8bc1-4944-ba3e-13522c288965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133486631 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3133486631
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.1296902156
Short name T968
Test name
Test status
Simulation time 1543623063 ps
CPU time 28.82 seconds
Started Jun 26 04:56:16 PM PDT 24
Finished Jun 26 04:56:47 PM PDT 24
Peak memory 204736 kb
Host smart-ecc60d5e-62a1-4dbe-8017-5d5303eaf6f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296902156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.1296902156
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2276948206
Short name T906
Test name
Test status
Simulation time 1082664943 ps
CPU time 45.07 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:51 PM PDT 24
Peak memory 205604 kb
Host smart-a40a6cba-29c7-43a2-9cf1-59701ed89af0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276948206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2276948206
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3092295951
Short name T790
Test name
Test status
Simulation time 31951775568 ps
CPU time 101.69 seconds
Started Jun 26 04:56:00 PM PDT 24
Finished Jun 26 04:57:45 PM PDT 24
Peak memory 1591800 kb
Host smart-fbe28094-ea48-43f2-812c-c9f9a42584da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092295951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3092295951
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1695422554
Short name T1232
Test name
Test status
Simulation time 13851974574 ps
CPU time 190.96 seconds
Started Jun 26 04:56:00 PM PDT 24
Finished Jun 26 04:59:15 PM PDT 24
Peak memory 872160 kb
Host smart-d3c6505c-96ea-4b8d-a38b-5b37f34b52f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695422554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1695422554
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.80229829
Short name T887
Test name
Test status
Simulation time 5230450877 ps
CPU time 7.2 seconds
Started Jun 26 04:55:57 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 221184 kb
Host smart-5a9236aa-77f7-4271-b945-aa4c8ec73edc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80229829 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_timeout.80229829
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1530096136
Short name T1306
Test name
Test status
Simulation time 42253596 ps
CPU time 0.66 seconds
Started Jun 26 04:59:27 PM PDT 24
Finished Jun 26 04:59:29 PM PDT 24
Peak memory 204500 kb
Host smart-a60a7281-d8d2-4883-acd2-430cbab86f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530096136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1530096136
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.699630032
Short name T67
Test name
Test status
Simulation time 808457640 ps
CPU time 3 seconds
Started Jun 26 04:59:20 PM PDT 24
Finished Jun 26 04:59:26 PM PDT 24
Peak memory 213132 kb
Host smart-b854299f-b2a3-439a-832c-efa61b30f302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699630032 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.699630032
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.2234491849
Short name T318
Test name
Test status
Simulation time 4653690699 ps
CPU time 5.9 seconds
Started Jun 26 04:59:19 PM PDT 24
Finished Jun 26 04:59:28 PM PDT 24
Peak memory 275836 kb
Host smart-212ad84f-3db8-4e95-b76b-3839a718c4d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234491849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.2234491849
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.868494727
Short name T981
Test name
Test status
Simulation time 10465045760 ps
CPU time 77.78 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 05:00:37 PM PDT 24
Peak memory 779980 kb
Host smart-cbb6b52a-5b4c-4d34-94b5-88b40994eb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868494727 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.868494727
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.65185504
Short name T1181
Test name
Test status
Simulation time 2238937684 ps
CPU time 71.24 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 05:00:30 PM PDT 24
Peak memory 701880 kb
Host smart-224b97f9-6f29-4562-a7e9-9a2f9379351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65185504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.65185504
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.2406430009
Short name T918
Test name
Test status
Simulation time 617075320 ps
CPU time 0.84 seconds
Started Jun 26 04:59:15 PM PDT 24
Finished Jun 26 04:59:19 PM PDT 24
Peak memory 204556 kb
Host smart-97c3be70-51fd-42c0-8eb1-9005c298b1cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406430009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.2406430009
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.3882711963
Short name T140
Test name
Test status
Simulation time 943725876 ps
CPU time 5.14 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 04:59:25 PM PDT 24
Peak memory 204792 kb
Host smart-5fff4116-e728-4fd1-9435-83cd78ce86d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882711963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.3882711963
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3289720478
Short name T1227
Test name
Test status
Simulation time 35211630326 ps
CPU time 380.01 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 05:05:39 PM PDT 24
Peak memory 1410524 kb
Host smart-0e065dcd-06e4-4436-8f25-e87302eab43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289720478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3289720478
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1465571585
Short name T778
Test name
Test status
Simulation time 920920593 ps
CPU time 16.82 seconds
Started Jun 26 04:59:30 PM PDT 24
Finished Jun 26 04:59:48 PM PDT 24
Peak memory 204844 kb
Host smart-f8c669cb-daf2-44d0-aca1-04eab332f9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465571585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1465571585
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.895655358
Short name T1108
Test name
Test status
Simulation time 3325688438 ps
CPU time 26 seconds
Started Jun 26 04:59:24 PM PDT 24
Finished Jun 26 04:59:52 PM PDT 24
Peak memory 347764 kb
Host smart-646ab6ba-ba4d-4b70-8d3e-c9e687bcba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895655358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.895655358
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.3840929744
Short name T437
Test name
Test status
Simulation time 47627165 ps
CPU time 0.65 seconds
Started Jun 26 04:59:20 PM PDT 24
Finished Jun 26 04:59:24 PM PDT 24
Peak memory 204472 kb
Host smart-a861f0ff-622c-4d55-9b6e-2647200798b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840929744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.3840929744
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.415298968
Short name T1177
Test name
Test status
Simulation time 6275814582 ps
CPU time 248.14 seconds
Started Jun 26 04:59:19 PM PDT 24
Finished Jun 26 05:03:30 PM PDT 24
Peak memory 236172 kb
Host smart-a9c8bf95-8d1e-43fc-9f10-aa6685a02cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415298968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.415298968
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.3843858398
Short name T431
Test name
Test status
Simulation time 2305962245 ps
CPU time 23.06 seconds
Started Jun 26 04:59:20 PM PDT 24
Finished Jun 26 04:59:46 PM PDT 24
Peak memory 204960 kb
Host smart-2669b97c-6b40-49f0-9e5d-0d929f650fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843858398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.3843858398
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1276901596
Short name T327
Test name
Test status
Simulation time 1568297174 ps
CPU time 73.79 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 05:00:33 PM PDT 24
Peak memory 339792 kb
Host smart-53d75bb8-5bdd-4e6e-99fe-7d1f9c571e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276901596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1276901596
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1312543522
Short name T1029
Test name
Test status
Simulation time 1475467746 ps
CPU time 31.75 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 04:59:51 PM PDT 24
Peak memory 213076 kb
Host smart-bf87886a-03a3-44e8-8f9f-94c05a0a6b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312543522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1312543522
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.885239936
Short name T1332
Test name
Test status
Simulation time 4385415059 ps
CPU time 5.88 seconds
Started Jun 26 04:59:26 PM PDT 24
Finished Jun 26 04:59:34 PM PDT 24
Peak memory 217524 kb
Host smart-fc43e9fb-5365-4315-8c7a-a9a4c430b54a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885239936 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.885239936
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.808506479
Short name T1248
Test name
Test status
Simulation time 176469496 ps
CPU time 1.24 seconds
Started Jun 26 04:59:30 PM PDT 24
Finished Jun 26 04:59:32 PM PDT 24
Peak memory 204592 kb
Host smart-6fc004d4-dd76-4130-bdd5-a2e36cc96cb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808506479 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.808506479
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.879277202
Short name T269
Test name
Test status
Simulation time 170762470 ps
CPU time 1.19 seconds
Started Jun 26 04:59:25 PM PDT 24
Finished Jun 26 04:59:29 PM PDT 24
Peak memory 204744 kb
Host smart-c28c9b05-9c65-468d-b40e-dd42411045e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879277202 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.i2c_target_fifo_reset_tx.879277202
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.440170240
Short name T1155
Test name
Test status
Simulation time 546618247 ps
CPU time 1.68 seconds
Started Jun 26 04:59:24 PM PDT 24
Finished Jun 26 04:59:27 PM PDT 24
Peak memory 204760 kb
Host smart-19139df5-c571-4abb-a646-463b71e7edbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440170240 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.440170240
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.1698526
Short name T518
Test name
Test status
Simulation time 461522223 ps
CPU time 1.1 seconds
Started Jun 26 04:59:24 PM PDT 24
Finished Jun 26 04:59:26 PM PDT 24
Peak memory 204540 kb
Host smart-6e8bfb83-7cdd-47f6-940a-3cf4d5fc9c09
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698526 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.1698526
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2460111299
Short name T708
Test name
Test status
Simulation time 849080597 ps
CPU time 4.8 seconds
Started Jun 26 04:59:25 PM PDT 24
Finished Jun 26 04:59:32 PM PDT 24
Peak memory 204828 kb
Host smart-c870371b-9a19-489c-ae74-5d2683b5aa9f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460111299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2460111299
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.4108243251
Short name T1073
Test name
Test status
Simulation time 4845256619 ps
CPU time 4.54 seconds
Started Jun 26 04:59:19 PM PDT 24
Finished Jun 26 04:59:27 PM PDT 24
Peak memory 213184 kb
Host smart-8c650bf2-5b2f-4662-8ed6-73108a114494
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108243251 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.4108243251
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.3306222573
Short name T1396
Test name
Test status
Simulation time 5208368971 ps
CPU time 5.83 seconds
Started Jun 26 04:59:18 PM PDT 24
Finished Jun 26 04:59:27 PM PDT 24
Peak memory 204988 kb
Host smart-7061fa52-0a6c-45a6-965f-22210d66bb17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306222573 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.3306222573
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.1766865381
Short name T1343
Test name
Test status
Simulation time 6026864983 ps
CPU time 56.52 seconds
Started Jun 26 04:59:17 PM PDT 24
Finished Jun 26 05:00:17 PM PDT 24
Peak memory 204960 kb
Host smart-2001d2e7-8684-4003-a043-949291622c08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766865381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.1766865381
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3735873107
Short name T418
Test name
Test status
Simulation time 750515541 ps
CPU time 11.12 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 04:59:31 PM PDT 24
Peak memory 211384 kb
Host smart-d4d0e8c2-c5f2-4ea1-8e73-6529243953a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735873107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3735873107
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.4247134184
Short name T933
Test name
Test status
Simulation time 45630607045 ps
CPU time 113.06 seconds
Started Jun 26 04:59:18 PM PDT 24
Finished Jun 26 05:01:14 PM PDT 24
Peak memory 1651144 kb
Host smart-333f2991-c393-47e4-a0e1-46bffbd04284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247134184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.4247134184
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.1903012053
Short name T872
Test name
Test status
Simulation time 4056732227 ps
CPU time 22.04 seconds
Started Jun 26 04:59:16 PM PDT 24
Finished Jun 26 04:59:41 PM PDT 24
Peak memory 452012 kb
Host smart-bfdfa521-c457-48ef-ba76-c1ac99f221c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903012053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.1903012053
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.3698285772
Short name T319
Test name
Test status
Simulation time 1145296987 ps
CPU time 6.37 seconds
Started Jun 26 04:59:19 PM PDT 24
Finished Jun 26 04:59:29 PM PDT 24
Peak memory 204792 kb
Host smart-440720eb-51fe-4130-b457-bba42b8bdc18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698285772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.3698285772
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.2804607241
Short name T1136
Test name
Test status
Simulation time 166331568 ps
CPU time 0.62 seconds
Started Jun 26 04:59:44 PM PDT 24
Finished Jun 26 04:59:46 PM PDT 24
Peak memory 204464 kb
Host smart-479b2620-0ed3-40cc-a1cf-bd20ea9cc72e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804607241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.2804607241
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.4119908556
Short name T707
Test name
Test status
Simulation time 476914161 ps
CPU time 1.78 seconds
Started Jun 26 04:59:36 PM PDT 24
Finished Jun 26 04:59:39 PM PDT 24
Peak memory 213040 kb
Host smart-5550a7a6-aa5d-4356-b4b5-fea3b0af1d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119908556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.4119908556
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.1436322679
Short name T289
Test name
Test status
Simulation time 1676383289 ps
CPU time 8.48 seconds
Started Jun 26 04:59:35 PM PDT 24
Finished Jun 26 04:59:44 PM PDT 24
Peak memory 281356 kb
Host smart-b19b2d7d-4073-446d-a28d-d301bc7e2ea0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436322679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.1436322679
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.1900299354
Short name T1074
Test name
Test status
Simulation time 5167694598 ps
CPU time 84.09 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 05:00:59 PM PDT 24
Peak memory 461384 kb
Host smart-576e96f3-c790-45a9-81fa-e465893828b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900299354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.1900299354
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.3209951559
Short name T5
Test name
Test status
Simulation time 1366800785 ps
CPU time 37.69 seconds
Started Jun 26 04:59:30 PM PDT 24
Finished Jun 26 05:00:09 PM PDT 24
Peak memory 542080 kb
Host smart-93f16a51-043b-4419-a1c3-56adf10569c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209951559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.3209951559
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.383278370
Short name T409
Test name
Test status
Simulation time 117615193 ps
CPU time 0.78 seconds
Started Jun 26 04:59:29 PM PDT 24
Finished Jun 26 04:59:31 PM PDT 24
Peak memory 204564 kb
Host smart-9670f222-fc47-44b8-b098-30c67ea582c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383278370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.383278370
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1190688654
Short name T845
Test name
Test status
Simulation time 650482283 ps
CPU time 8.72 seconds
Started Jun 26 04:59:33 PM PDT 24
Finished Jun 26 04:59:43 PM PDT 24
Peak memory 204780 kb
Host smart-208f44d4-227d-4860-b0bd-a640292064a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190688654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1190688654
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1690996601
Short name T62
Test name
Test status
Simulation time 3021100225 ps
CPU time 188.95 seconds
Started Jun 26 04:59:25 PM PDT 24
Finished Jun 26 05:02:36 PM PDT 24
Peak memory 898272 kb
Host smart-0c9e0e9d-57c5-44af-8c71-79d1a5d285ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690996601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1690996601
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2771934135
Short name T740
Test name
Test status
Simulation time 5618929634 ps
CPU time 11.77 seconds
Started Jun 26 04:59:38 PM PDT 24
Finished Jun 26 04:59:50 PM PDT 24
Peak memory 204864 kb
Host smart-61fc9064-71e9-48da-9153-451e1ff2eb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771934135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2771934135
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.1652353381
Short name T587
Test name
Test status
Simulation time 1851282828 ps
CPU time 27.87 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 05:00:03 PM PDT 24
Peak memory 340256 kb
Host smart-2782f344-ccfe-4e17-b9a5-325155fbd303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652353381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.1652353381
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.38620023
Short name T1040
Test name
Test status
Simulation time 47409065 ps
CPU time 0.65 seconds
Started Jun 26 04:59:25 PM PDT 24
Finished Jun 26 04:59:27 PM PDT 24
Peak memory 204528 kb
Host smart-3f865bc1-9111-4a49-83f8-3b3edb05b71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38620023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.38620023
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3058118416
Short name T213
Test name
Test status
Simulation time 26711786041 ps
CPU time 64.88 seconds
Started Jun 26 04:59:36 PM PDT 24
Finished Jun 26 05:00:42 PM PDT 24
Peak memory 204972 kb
Host smart-0faee81f-4038-4518-abb8-516be97aeccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058118416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3058118416
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.2947868890
Short name T1346
Test name
Test status
Simulation time 186006879 ps
CPU time 2.38 seconds
Started Jun 26 04:59:39 PM PDT 24
Finished Jun 26 04:59:42 PM PDT 24
Peak memory 229112 kb
Host smart-16a79179-0902-44b3-8f54-62f1aae5f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947868890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.2947868890
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.1351488488
Short name T1193
Test name
Test status
Simulation time 2223040900 ps
CPU time 101.46 seconds
Started Jun 26 04:59:25 PM PDT 24
Finished Jun 26 05:01:09 PM PDT 24
Peak memory 345772 kb
Host smart-34fdd3b0-4803-4e5d-a451-0096cecc71a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351488488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.1351488488
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.3658037737
Short name T1314
Test name
Test status
Simulation time 30824248332 ps
CPU time 2479.18 seconds
Started Jun 26 04:59:42 PM PDT 24
Finished Jun 26 05:41:03 PM PDT 24
Peak memory 3178232 kb
Host smart-84414b61-6912-41b5-9174-86009c657933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658037737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.3658037737
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.1256418035
Short name T877
Test name
Test status
Simulation time 663126545 ps
CPU time 29.73 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 05:00:05 PM PDT 24
Peak memory 213052 kb
Host smart-83f2589c-f7cb-4614-af67-28fbba805cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256418035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.1256418035
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.3872416584
Short name T642
Test name
Test status
Simulation time 2238674467 ps
CPU time 4.74 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 04:59:40 PM PDT 24
Peak memory 213196 kb
Host smart-dc2f4000-324e-4282-8a9e-ced86af9936a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872416584 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.3872416584
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.2838291284
Short name T734
Test name
Test status
Simulation time 554858755 ps
CPU time 1.28 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 04:59:36 PM PDT 24
Peak memory 204636 kb
Host smart-1b2826c5-7581-4585-8f86-385d2c7d5b07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838291284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.2838291284
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.2479654859
Short name T658
Test name
Test status
Simulation time 183459648 ps
CPU time 1.22 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 04:59:37 PM PDT 24
Peak memory 205032 kb
Host smart-901fd03e-37cb-4edb-912b-12781c9766ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479654859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.2479654859
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.1649537756
Short name T1142
Test name
Test status
Simulation time 328579666 ps
CPU time 1.82 seconds
Started Jun 26 04:59:43 PM PDT 24
Finished Jun 26 04:59:47 PM PDT 24
Peak memory 204764 kb
Host smart-c898807a-55f6-4dfd-9e55-26023d37d539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649537756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.1649537756
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.135943995
Short name T795
Test name
Test status
Simulation time 71274641 ps
CPU time 0.79 seconds
Started Jun 26 04:59:42 PM PDT 24
Finished Jun 26 04:59:44 PM PDT 24
Peak memory 204640 kb
Host smart-751dcf36-ab89-4b09-8877-b6a067b9c6d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135943995 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.135943995
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1968695254
Short name T422
Test name
Test status
Simulation time 1048676498 ps
CPU time 6 seconds
Started Jun 26 04:59:37 PM PDT 24
Finished Jun 26 04:59:44 PM PDT 24
Peak memory 205020 kb
Host smart-25eb107a-3c50-4ca0-b9bc-d7f7fd43af0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968695254 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1968695254
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1876684463
Short name T12
Test name
Test status
Simulation time 17095111554 ps
CPU time 27.77 seconds
Started Jun 26 04:59:36 PM PDT 24
Finished Jun 26 05:00:05 PM PDT 24
Peak memory 782784 kb
Host smart-475ff466-9931-4e62-8bec-b2b18d5a5f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876684463 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1876684463
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2102229081
Short name T1131
Test name
Test status
Simulation time 5440595001 ps
CPU time 35.72 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 05:00:10 PM PDT 24
Peak memory 204860 kb
Host smart-ebf8af51-d407-4ab1-9ea2-4b2785647ca3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102229081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2102229081
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.398817667
Short name T317
Test name
Test status
Simulation time 7097057799 ps
CPU time 27.93 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 05:00:03 PM PDT 24
Peak memory 233276 kb
Host smart-cecb7759-5c90-4193-a690-4176d6cde6da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398817667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_rd.398817667
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.2948563950
Short name T808
Test name
Test status
Simulation time 55697748266 ps
CPU time 1539.69 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 05:25:14 PM PDT 24
Peak memory 9152700 kb
Host smart-3502bb3a-3999-432b-8638-7dd064ffc879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948563950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.2948563950
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.3005961045
Short name T1190
Test name
Test status
Simulation time 28113160952 ps
CPU time 323.45 seconds
Started Jun 26 04:59:34 PM PDT 24
Finished Jun 26 05:04:58 PM PDT 24
Peak memory 2283184 kb
Host smart-f992ba51-9757-4a45-a4ec-31426dd47ea2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005961045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.3005961045
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3133666577
Short name T682
Test name
Test status
Simulation time 18127254303 ps
CPU time 6.41 seconds
Started Jun 26 04:59:35 PM PDT 24
Finished Jun 26 04:59:42 PM PDT 24
Peak memory 220188 kb
Host smart-b2a4280d-0724-4f67-97f9-3240067b5830
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133666577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3133666577
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.4106753659
Short name T1015
Test name
Test status
Simulation time 152606018 ps
CPU time 0.62 seconds
Started Jun 26 04:59:56 PM PDT 24
Finished Jun 26 04:59:58 PM PDT 24
Peak memory 204516 kb
Host smart-cc066e06-bef0-4852-a7d7-0295c29087f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106753659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.4106753659
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3345144839
Short name T601
Test name
Test status
Simulation time 861211921 ps
CPU time 6.58 seconds
Started Jun 26 04:59:40 PM PDT 24
Finished Jun 26 04:59:48 PM PDT 24
Peak memory 213124 kb
Host smart-64a7e85f-5a43-4c31-9682-68a61e365b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345144839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3345144839
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2340593401
Short name T514
Test name
Test status
Simulation time 279282539 ps
CPU time 6.1 seconds
Started Jun 26 04:59:43 PM PDT 24
Finished Jun 26 04:59:52 PM PDT 24
Peak memory 261292 kb
Host smart-9bcbb626-24ba-400b-815a-e2ff6f882e36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340593401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2340593401
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2537597796
Short name T742
Test name
Test status
Simulation time 1710251523 ps
CPU time 44.96 seconds
Started Jun 26 04:59:54 PM PDT 24
Finished Jun 26 05:00:40 PM PDT 24
Peak memory 543312 kb
Host smart-34cfddf1-e41d-41ca-9b95-fda7ecef29db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537597796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2537597796
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.1179306617
Short name T344
Test name
Test status
Simulation time 3983675577 ps
CPU time 89.63 seconds
Started Jun 26 04:59:43 PM PDT 24
Finished Jun 26 05:01:15 PM PDT 24
Peak memory 533260 kb
Host smart-df537964-f81b-47ef-a7fd-f931092b904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179306617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.1179306617
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3757247460
Short name T1434
Test name
Test status
Simulation time 547876004 ps
CPU time 0.96 seconds
Started Jun 26 04:59:54 PM PDT 24
Finished Jun 26 04:59:56 PM PDT 24
Peak memory 204456 kb
Host smart-9f1e45c0-3abd-4f1a-847c-9a2ab1cae616
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757247460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3757247460
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3062719164
Short name T799
Test name
Test status
Simulation time 609688254 ps
CPU time 8.67 seconds
Started Jun 26 04:59:42 PM PDT 24
Finished Jun 26 04:59:53 PM PDT 24
Peak memory 231568 kb
Host smart-c5d3d51d-ccf3-44c8-b913-a29f819525ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062719164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3062719164
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2777772728
Short name T763
Test name
Test status
Simulation time 15634034480 ps
CPU time 268.17 seconds
Started Jun 26 04:59:54 PM PDT 24
Finished Jun 26 05:04:23 PM PDT 24
Peak memory 1115800 kb
Host smart-fee98cc3-391d-4634-96c7-0293d6033532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777772728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2777772728
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.335469194
Short name T1430
Test name
Test status
Simulation time 2781834407 ps
CPU time 9.79 seconds
Started Jun 26 04:59:58 PM PDT 24
Finished Jun 26 05:00:09 PM PDT 24
Peak memory 204928 kb
Host smart-20ef70d9-571b-4dbb-8c21-09b3aee8e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335469194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.335469194
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.695794166
Short name T991
Test name
Test status
Simulation time 3369659512 ps
CPU time 83.98 seconds
Started Jun 26 04:59:49 PM PDT 24
Finished Jun 26 05:01:14 PM PDT 24
Peak memory 317684 kb
Host smart-7a148907-3df5-44be-888a-a928a55e99d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695794166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.695794166
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.2086966122
Short name T411
Test name
Test status
Simulation time 30923958 ps
CPU time 0.69 seconds
Started Jun 26 04:59:43 PM PDT 24
Finished Jun 26 04:59:46 PM PDT 24
Peak memory 204528 kb
Host smart-e050a592-385d-4835-adcd-b59f1c367255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086966122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.2086966122
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1138833470
Short name T967
Test name
Test status
Simulation time 3744901811 ps
CPU time 11.24 seconds
Started Jun 26 04:59:45 PM PDT 24
Finished Jun 26 04:59:58 PM PDT 24
Peak memory 205444 kb
Host smart-55e570fe-0e46-494d-a352-c3a7a71afffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138833470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1138833470
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.2901903391
Short name T1097
Test name
Test status
Simulation time 24273545597 ps
CPU time 1264.31 seconds
Started Jun 26 04:59:42 PM PDT 24
Finished Jun 26 05:20:49 PM PDT 24
Peak memory 892664 kb
Host smart-7c0720b7-7fe3-49ab-ae5f-927d8b4639bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901903391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.2901903391
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.1936868827
Short name T623
Test name
Test status
Simulation time 6098303438 ps
CPU time 73.06 seconds
Started Jun 26 04:59:43 PM PDT 24
Finished Jun 26 05:00:58 PM PDT 24
Peak memory 299336 kb
Host smart-95a95203-68ec-437d-b23c-cc9dc819f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936868827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.1936868827
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.2638330659
Short name T114
Test name
Test status
Simulation time 3061374737 ps
CPU time 73.19 seconds
Started Jun 26 04:59:45 PM PDT 24
Finished Jun 26 05:00:59 PM PDT 24
Peak memory 686360 kb
Host smart-bbef0e2e-2516-4530-84ab-9f99cf82cb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638330659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.2638330659
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.135047524
Short name T1319
Test name
Test status
Simulation time 3316402018 ps
CPU time 12.21 seconds
Started Jun 26 04:59:43 PM PDT 24
Finished Jun 26 04:59:57 PM PDT 24
Peak memory 229456 kb
Host smart-c98e6a4e-a443-4213-a1fe-8ebed8295837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135047524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.135047524
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.982046164
Short name T1165
Test name
Test status
Simulation time 3021641291 ps
CPU time 4 seconds
Started Jun 26 04:59:51 PM PDT 24
Finished Jun 26 04:59:56 PM PDT 24
Peak memory 204888 kb
Host smart-ae64e9e2-2a22-44de-a2e9-05112ef66940
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982046164 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.982046164
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.4053298145
Short name T142
Test name
Test status
Simulation time 302797395 ps
CPU time 0.99 seconds
Started Jun 26 04:59:50 PM PDT 24
Finished Jun 26 04:59:52 PM PDT 24
Peak memory 204824 kb
Host smart-b0d77510-3b42-43a4-82b6-6c4442c648fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053298145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.4053298145
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2556705414
Short name T776
Test name
Test status
Simulation time 123334963 ps
CPU time 0.95 seconds
Started Jun 26 04:59:52 PM PDT 24
Finished Jun 26 04:59:54 PM PDT 24
Peak memory 204820 kb
Host smart-da90e17c-21c4-40cd-9c8e-8e2bffe955f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556705414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2556705414
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.1626841730
Short name T1201
Test name
Test status
Simulation time 508628705 ps
CPU time 2.9 seconds
Started Jun 26 04:59:56 PM PDT 24
Finished Jun 26 05:00:00 PM PDT 24
Peak memory 204820 kb
Host smart-1145e9fe-1f3a-463b-a3ca-668ea150f585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626841730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.1626841730
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.2612595881
Short name T491
Test name
Test status
Simulation time 387446709 ps
CPU time 1.06 seconds
Started Jun 26 04:59:58 PM PDT 24
Finished Jun 26 05:00:00 PM PDT 24
Peak memory 204572 kb
Host smart-ed9fb703-9e33-4175-8445-e8e989a65479
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612595881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.2612595881
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.2541929631
Short name T171
Test name
Test status
Simulation time 3685530260 ps
CPU time 8.51 seconds
Started Jun 26 04:59:50 PM PDT 24
Finished Jun 26 04:59:59 PM PDT 24
Peak memory 221184 kb
Host smart-ec5681a2-70b1-40d8-b98b-eab3e15b4965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541929631 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.2541929631
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.2278396411
Short name T993
Test name
Test status
Simulation time 8624957573 ps
CPU time 25.24 seconds
Started Jun 26 04:59:47 PM PDT 24
Finished Jun 26 05:00:13 PM PDT 24
Peak memory 517368 kb
Host smart-e563984a-35a8-4eea-9c9a-98fe1fc8a898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278396411 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.2278396411
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.3195928719
Short name T1085
Test name
Test status
Simulation time 1153474287 ps
CPU time 43.82 seconds
Started Jun 26 04:59:42 PM PDT 24
Finished Jun 26 05:00:27 PM PDT 24
Peak memory 204840 kb
Host smart-e1ca70d5-08be-48d5-815c-2f3c78fbce0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195928719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.3195928719
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.2420187251
Short name T1043
Test name
Test status
Simulation time 267578884 ps
CPU time 10.74 seconds
Started Jun 26 04:59:44 PM PDT 24
Finished Jun 26 04:59:56 PM PDT 24
Peak memory 204808 kb
Host smart-a3561349-eb12-478b-8948-8adbc6e4b481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420187251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.2420187251
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.3149946967
Short name T1441
Test name
Test status
Simulation time 60726893083 ps
CPU time 214.23 seconds
Started Jun 26 04:59:54 PM PDT 24
Finished Jun 26 05:03:29 PM PDT 24
Peak memory 2569952 kb
Host smart-94f3c0af-478d-4b6d-bdfa-9dbb20c0e6ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149946967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.3149946967
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.2854713127
Short name T235
Test name
Test status
Simulation time 32494283430 ps
CPU time 667.49 seconds
Started Jun 26 04:59:49 PM PDT 24
Finished Jun 26 05:10:58 PM PDT 24
Peak memory 2025608 kb
Host smart-ec7bcb0b-ba53-44f7-9499-a0635a4ff853
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854713127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.2854713127
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.4290484385
Short name T1171
Test name
Test status
Simulation time 1299516687 ps
CPU time 7.16 seconds
Started Jun 26 04:59:48 PM PDT 24
Finished Jun 26 04:59:57 PM PDT 24
Peak memory 221092 kb
Host smart-e35b51f2-dafd-4cf1-86f0-938e6a19c868
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290484385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.4290484385
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.2226839422
Short name T1310
Test name
Test status
Simulation time 27411020 ps
CPU time 0.62 seconds
Started Jun 26 05:00:12 PM PDT 24
Finished Jun 26 05:00:15 PM PDT 24
Peak memory 204492 kb
Host smart-a9be9c9e-fca0-4f3c-808c-3f834d914240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226839422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.2226839422
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.1470370357
Short name T923
Test name
Test status
Simulation time 691511375 ps
CPU time 2.49 seconds
Started Jun 26 05:00:10 PM PDT 24
Finished Jun 26 05:00:14 PM PDT 24
Peak memory 215820 kb
Host smart-54ea4d7a-14b4-4b8b-9131-1190a0e977e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470370357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.1470370357
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.749133649
Short name T105
Test name
Test status
Simulation time 596548392 ps
CPU time 14.05 seconds
Started Jun 26 04:59:59 PM PDT 24
Finished Jun 26 05:00:14 PM PDT 24
Peak memory 255384 kb
Host smart-5d5a2cf7-adc8-4270-bb9c-ee3227df52d8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749133649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_empt
y.749133649
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.1807904493
Short name T550
Test name
Test status
Simulation time 6435472752 ps
CPU time 35.4 seconds
Started Jun 26 04:59:59 PM PDT 24
Finished Jun 26 05:00:35 PM PDT 24
Peak memory 399520 kb
Host smart-55dd33a4-f59b-41cf-b0be-cecb6bc93c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807904493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.1807904493
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2131284454
Short name T1270
Test name
Test status
Simulation time 2009654153 ps
CPU time 150.58 seconds
Started Jun 26 04:59:55 PM PDT 24
Finished Jun 26 05:02:27 PM PDT 24
Peak memory 673820 kb
Host smart-af684abb-201e-4bb7-aca2-eff5d4e6fc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131284454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2131284454
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1933955367
Short name T531
Test name
Test status
Simulation time 221913044 ps
CPU time 0.9 seconds
Started Jun 26 04:59:58 PM PDT 24
Finished Jun 26 05:00:00 PM PDT 24
Peak memory 204548 kb
Host smart-ffc0fef9-6366-4b84-a208-e7ead4a18b65
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933955367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1933955367
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.486007436
Short name T463
Test name
Test status
Simulation time 228602355 ps
CPU time 12.43 seconds
Started Jun 26 04:59:56 PM PDT 24
Finished Jun 26 05:00:10 PM PDT 24
Peak memory 247920 kb
Host smart-3d7b1c09-41bf-46ee-b157-de741a655f36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486007436 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.
486007436
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.386396819
Short name T1134
Test name
Test status
Simulation time 4120376547 ps
CPU time 288.7 seconds
Started Jun 26 04:59:57 PM PDT 24
Finished Jun 26 05:04:47 PM PDT 24
Peak memory 1230936 kb
Host smart-d7ad6883-592a-4b98-b9ac-bb385901764a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386396819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.386396819
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.3635696282
Short name T675
Test name
Test status
Simulation time 4074817994 ps
CPU time 26.17 seconds
Started Jun 26 05:00:06 PM PDT 24
Finished Jun 26 05:00:34 PM PDT 24
Peak memory 205032 kb
Host smart-b888c2c2-1c1e-488d-9c0b-92654d15de8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635696282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.3635696282
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.2294228003
Short name T1245
Test name
Test status
Simulation time 1888697954 ps
CPU time 22.15 seconds
Started Jun 26 05:00:03 PM PDT 24
Finished Jun 26 05:00:27 PM PDT 24
Peak memory 343604 kb
Host smart-99a514a8-bc36-4c96-9ff0-dff660b000e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294228003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.2294228003
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.4021082230
Short name T1178
Test name
Test status
Simulation time 30009882 ps
CPU time 0.67 seconds
Started Jun 26 05:00:00 PM PDT 24
Finished Jun 26 05:00:02 PM PDT 24
Peak memory 204488 kb
Host smart-3b20dfad-1477-4d87-a013-56c7eab545cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021082230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.4021082230
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.3778337812
Short name T951
Test name
Test status
Simulation time 6220720507 ps
CPU time 146.52 seconds
Started Jun 26 04:59:55 PM PDT 24
Finished Jun 26 05:02:22 PM PDT 24
Peak memory 419880 kb
Host smart-84c8ced0-0cd4-4522-ada2-5818276c4ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778337812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.3778337812
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.4198844149
Short name T513
Test name
Test status
Simulation time 320207942 ps
CPU time 1.32 seconds
Started Jun 26 04:59:55 PM PDT 24
Finished Jun 26 04:59:58 PM PDT 24
Peak memory 204836 kb
Host smart-9fb36d0d-3701-43c9-af35-c33ca8674de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198844149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.4198844149
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3189481035
Short name T1133
Test name
Test status
Simulation time 6581430119 ps
CPU time 38.77 seconds
Started Jun 26 04:59:56 PM PDT 24
Finished Jun 26 05:00:36 PM PDT 24
Peak memory 419024 kb
Host smart-8724f12e-ac39-45ad-8d95-1952d32e7ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189481035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3189481035
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.2508308154
Short name T258
Test name
Test status
Simulation time 42452785727 ps
CPU time 269.24 seconds
Started Jun 26 05:00:05 PM PDT 24
Finished Jun 26 05:04:36 PM PDT 24
Peak memory 882804 kb
Host smart-74eec43a-3f82-4afa-bca5-d6dae480b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508308154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.2508308154
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2939916750
Short name T1140
Test name
Test status
Simulation time 3616001730 ps
CPU time 40.46 seconds
Started Jun 26 05:00:04 PM PDT 24
Finished Jun 26 05:00:46 PM PDT 24
Peak memory 213120 kb
Host smart-b576301a-7793-4658-b24e-dd20047e544b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939916750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2939916750
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.443355047
Short name T777
Test name
Test status
Simulation time 954637754 ps
CPU time 2.5 seconds
Started Jun 26 05:00:06 PM PDT 24
Finished Jun 26 05:00:10 PM PDT 24
Peak memory 204876 kb
Host smart-acfad83c-6cb5-4440-8aaa-4ae367bbe742
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443355047 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.443355047
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.2536035133
Short name T1457
Test name
Test status
Simulation time 167205097 ps
CPU time 1.03 seconds
Started Jun 26 05:00:04 PM PDT 24
Finished Jun 26 05:00:07 PM PDT 24
Peak memory 204580 kb
Host smart-4c7d701a-3e62-4b15-96f2-bdb23b2794bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536035133 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.2536035133
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1104450991
Short name T960
Test name
Test status
Simulation time 277709921 ps
CPU time 1.71 seconds
Started Jun 26 05:00:05 PM PDT 24
Finished Jun 26 05:00:09 PM PDT 24
Peak memory 219916 kb
Host smart-0c43f8e2-e440-41f7-95c8-17fddbf4a5b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104450991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1104450991
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.716617194
Short name T1258
Test name
Test status
Simulation time 1087953504 ps
CPU time 2.73 seconds
Started Jun 26 05:00:02 PM PDT 24
Finished Jun 26 05:00:06 PM PDT 24
Peak memory 204760 kb
Host smart-f4880406-1e52-40a0-bd72-9795f3e183de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716617194 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.716617194
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.8614414
Short name T944
Test name
Test status
Simulation time 115573358 ps
CPU time 1.15 seconds
Started Jun 26 05:00:03 PM PDT 24
Finished Jun 26 05:00:06 PM PDT 24
Peak memory 204584 kb
Host smart-a0612467-b55c-491c-b6e2-1dba0f88a249
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8614414 -assert nopostproc +UVM_TESTNAME=i2c_base_t
est +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.8614414
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1366707301
Short name T1275
Test name
Test status
Simulation time 4087085294 ps
CPU time 3.13 seconds
Started Jun 26 05:00:01 PM PDT 24
Finished Jun 26 05:00:06 PM PDT 24
Peak memory 204916 kb
Host smart-483dddb6-84af-4b11-9399-8394c8365578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366707301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1366707301
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.2045468887
Short name T421
Test name
Test status
Simulation time 807583203 ps
CPU time 5.06 seconds
Started Jun 26 05:00:05 PM PDT 24
Finished Jun 26 05:00:12 PM PDT 24
Peak memory 215576 kb
Host smart-6819176c-d999-4332-8457-5ab8e916153b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045468887 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.2045468887
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.804927147
Short name T602
Test name
Test status
Simulation time 8056104869 ps
CPU time 9.33 seconds
Started Jun 26 05:00:03 PM PDT 24
Finished Jun 26 05:00:15 PM PDT 24
Peak memory 204924 kb
Host smart-f4b6751d-cbbf-4b27-a424-5fac4e41af7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804927147 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.804927147
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.2385257140
Short name T979
Test name
Test status
Simulation time 3922464490 ps
CPU time 15.63 seconds
Started Jun 26 05:00:05 PM PDT 24
Finished Jun 26 05:00:23 PM PDT 24
Peak memory 204948 kb
Host smart-d97de82a-0ef7-44f3-8068-8f9ebf7ebffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385257140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.2385257140
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3941285898
Short name T538
Test name
Test status
Simulation time 5977630744 ps
CPU time 25.54 seconds
Started Jun 26 05:00:06 PM PDT 24
Finished Jun 26 05:00:33 PM PDT 24
Peak memory 231104 kb
Host smart-7374162e-007a-423c-b377-64b4d9cba089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941285898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3941285898
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1409286539
Short name T586
Test name
Test status
Simulation time 46316482648 ps
CPU time 849.47 seconds
Started Jun 26 05:00:04 PM PDT 24
Finished Jun 26 05:14:16 PM PDT 24
Peak memory 6837964 kb
Host smart-1a8e6db9-5686-4477-a8a8-7efb15c0d8fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409286539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1409286539
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.3525703191
Short name T976
Test name
Test status
Simulation time 12208254658 ps
CPU time 7.18 seconds
Started Jun 26 05:00:05 PM PDT 24
Finished Jun 26 05:00:14 PM PDT 24
Peak memory 221100 kb
Host smart-b3c6c113-75d4-4015-87f4-4dfb212a0900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525703191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.3525703191
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.346083633
Short name T335
Test name
Test status
Simulation time 42493607 ps
CPU time 0.64 seconds
Started Jun 26 05:00:25 PM PDT 24
Finished Jun 26 05:00:28 PM PDT 24
Peak memory 204420 kb
Host smart-8a34059f-82a8-4f63-a9fd-9d9fcdfd7969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346083633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.346083633
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1177258541
Short name T1309
Test name
Test status
Simulation time 388080672 ps
CPU time 1.65 seconds
Started Jun 26 05:00:12 PM PDT 24
Finished Jun 26 05:00:16 PM PDT 24
Peak memory 213112 kb
Host smart-aedb8c95-d101-45ca-9d9f-67dbf67a339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177258541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1177258541
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1106134433
Short name T1203
Test name
Test status
Simulation time 1670576385 ps
CPU time 17.05 seconds
Started Jun 26 05:00:12 PM PDT 24
Finished Jun 26 05:00:30 PM PDT 24
Peak memory 272060 kb
Host smart-b9bd8c3f-322d-4bc4-8aaa-dc9f51fdd62c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106134433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1106134433
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.3238203387
Short name T1239
Test name
Test status
Simulation time 3041245465 ps
CPU time 98.89 seconds
Started Jun 26 05:00:10 PM PDT 24
Finished Jun 26 05:01:50 PM PDT 24
Peak memory 574404 kb
Host smart-25328b78-a477-4321-a902-61c5e0c11ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238203387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.3238203387
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.1713029156
Short name T1211
Test name
Test status
Simulation time 3599539445 ps
CPU time 48.41 seconds
Started Jun 26 05:00:16 PM PDT 24
Finished Jun 26 05:01:05 PM PDT 24
Peak memory 574004 kb
Host smart-dd82f9e0-fe12-4ea9-a20f-84cb0187a404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713029156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.1713029156
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.4219192897
Short name T8
Test name
Test status
Simulation time 96747243 ps
CPU time 1 seconds
Started Jun 26 05:00:15 PM PDT 24
Finished Jun 26 05:00:17 PM PDT 24
Peak memory 204484 kb
Host smart-48aa0fee-1675-4531-8bc3-5d61c3fa8e9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219192897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.4219192897
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.3603444803
Short name T369
Test name
Test status
Simulation time 186989598 ps
CPU time 9.28 seconds
Started Jun 26 05:00:15 PM PDT 24
Finished Jun 26 05:00:26 PM PDT 24
Peak memory 204772 kb
Host smart-e2a280c6-e41d-4409-89cc-a8f97620e8a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603444803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.3603444803
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.2607912534
Short name T1450
Test name
Test status
Simulation time 18117216347 ps
CPU time 71.69 seconds
Started Jun 26 05:00:12 PM PDT 24
Finished Jun 26 05:01:26 PM PDT 24
Peak memory 882276 kb
Host smart-fa8a8a9f-6664-470c-b37d-35dccc09a773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607912534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.2607912534
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1364803608
Short name T479
Test name
Test status
Simulation time 480660981 ps
CPU time 7.53 seconds
Started Jun 26 05:00:22 PM PDT 24
Finished Jun 26 05:00:31 PM PDT 24
Peak memory 204820 kb
Host smart-14f1ad47-9a34-42d2-b0fa-4535eb18caa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364803608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1364803608
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.2265781400
Short name T66
Test name
Test status
Simulation time 5881279421 ps
CPU time 23.61 seconds
Started Jun 26 05:00:21 PM PDT 24
Finished Jun 26 05:00:46 PM PDT 24
Peak memory 333800 kb
Host smart-937053e1-7846-455b-a362-0c878cfb797a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265781400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.2265781400
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.180474828
Short name T125
Test name
Test status
Simulation time 60790761 ps
CPU time 0.65 seconds
Started Jun 26 05:00:11 PM PDT 24
Finished Jun 26 05:00:12 PM PDT 24
Peak memory 204504 kb
Host smart-66eee17b-dae8-4cd4-b51a-b51efcc119fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180474828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.180474828
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.3910903953
Short name T919
Test name
Test status
Simulation time 6371153237 ps
CPU time 62.42 seconds
Started Jun 26 05:00:11 PM PDT 24
Finished Jun 26 05:01:15 PM PDT 24
Peak memory 204968 kb
Host smart-376916ad-8f11-49a8-beeb-b987c8c73a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910903953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.3910903953
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.455875863
Short name T916
Test name
Test status
Simulation time 254023742 ps
CPU time 2.11 seconds
Started Jun 26 05:00:10 PM PDT 24
Finished Jun 26 05:00:13 PM PDT 24
Peak memory 212976 kb
Host smart-03eed087-6ce9-4aa7-946b-c4083dc41ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455875863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.455875863
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.1174306380
Short name T279
Test name
Test status
Simulation time 1695795744 ps
CPU time 29.34 seconds
Started Jun 26 05:00:10 PM PDT 24
Finished Jun 26 05:00:40 PM PDT 24
Peak memory 382292 kb
Host smart-8db29808-1543-49f7-b202-31c63d994d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174306380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.1174306380
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.3978017091
Short name T866
Test name
Test status
Simulation time 12062238297 ps
CPU time 1127.1 seconds
Started Jun 26 05:00:12 PM PDT 24
Finished Jun 26 05:19:01 PM PDT 24
Peak memory 2300480 kb
Host smart-c49aedf8-73aa-491f-a971-7e2eba2a92df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978017091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.3978017091
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.344962567
Short name T522
Test name
Test status
Simulation time 6744650562 ps
CPU time 13.56 seconds
Started Jun 26 05:00:10 PM PDT 24
Finished Jun 26 05:00:25 PM PDT 24
Peak memory 220988 kb
Host smart-7d12b4e7-7328-49a6-848c-6bc644192593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344962567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.344962567
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1471819904
Short name T655
Test name
Test status
Simulation time 468641423 ps
CPU time 3 seconds
Started Jun 26 05:00:19 PM PDT 24
Finished Jun 26 05:00:23 PM PDT 24
Peak memory 204848 kb
Host smart-a8132841-bd66-44fe-a3f3-efb28397f13b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471819904 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1471819904
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.3011013442
Short name T582
Test name
Test status
Simulation time 558342039 ps
CPU time 1.31 seconds
Started Jun 26 05:00:19 PM PDT 24
Finished Jun 26 05:00:21 PM PDT 24
Peak memory 204764 kb
Host smart-70976951-8f9d-450c-b889-e36ed39a95f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011013442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.3011013442
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.2769385845
Short name T867
Test name
Test status
Simulation time 107318641 ps
CPU time 0.78 seconds
Started Jun 26 05:00:23 PM PDT 24
Finished Jun 26 05:00:25 PM PDT 24
Peak memory 204628 kb
Host smart-05de72eb-c0c0-4880-98aa-26a1fe8a45d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769385845 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.2769385845
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.2314645991
Short name T489
Test name
Test status
Simulation time 297539475 ps
CPU time 1.76 seconds
Started Jun 26 05:00:23 PM PDT 24
Finished Jun 26 05:00:26 PM PDT 24
Peak memory 204764 kb
Host smart-2b87b4c2-6f15-4d3e-b137-0066f95a1cc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314645991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.2314645991
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.428241493
Short name T1465
Test name
Test status
Simulation time 161688170 ps
CPU time 1.31 seconds
Started Jun 26 05:00:23 PM PDT 24
Finished Jun 26 05:00:26 PM PDT 24
Peak memory 204592 kb
Host smart-158c4a47-a049-4f30-bede-338222f95b3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428241493 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.428241493
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.2719240354
Short name T1304
Test name
Test status
Simulation time 3630320746 ps
CPU time 5.54 seconds
Started Jun 26 05:00:16 PM PDT 24
Finished Jun 26 05:00:23 PM PDT 24
Peak memory 217168 kb
Host smart-0359e601-8694-4f53-92ac-04c079a954c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719240354 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.2719240354
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2791954472
Short name T393
Test name
Test status
Simulation time 22371038777 ps
CPU time 62.17 seconds
Started Jun 26 05:00:18 PM PDT 24
Finished Jun 26 05:01:21 PM PDT 24
Peak memory 1346876 kb
Host smart-64e642cd-ee4a-4621-9070-20c3350bdde8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791954472 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2791954472
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.1796816030
Short name T579
Test name
Test status
Simulation time 3086785427 ps
CPU time 24.78 seconds
Started Jun 26 05:00:20 PM PDT 24
Finished Jun 26 05:00:46 PM PDT 24
Peak memory 204992 kb
Host smart-48c93fe3-ec08-401a-a03b-4ec9a73a6f27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796816030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.1796816030
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.3655940490
Short name T292
Test name
Test status
Simulation time 1292378752 ps
CPU time 4.83 seconds
Started Jun 26 05:00:20 PM PDT 24
Finished Jun 26 05:00:25 PM PDT 24
Peak memory 204788 kb
Host smart-2b8f2f4c-2923-40c2-99be-72692f790bf3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655940490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.3655940490
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2484834577
Short name T391
Test name
Test status
Simulation time 60008960528 ps
CPU time 1663.71 seconds
Started Jun 26 05:00:18 PM PDT 24
Finished Jun 26 05:28:03 PM PDT 24
Peak memory 10173692 kb
Host smart-d2436f82-453b-4d96-a8ed-b188ad1f500c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484834577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2484834577
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.1896215415
Short name T644
Test name
Test status
Simulation time 5277668837 ps
CPU time 263.53 seconds
Started Jun 26 05:00:21 PM PDT 24
Finished Jun 26 05:04:46 PM PDT 24
Peak memory 1178152 kb
Host smart-a04d8a78-186d-4633-a202-2fcee9e664f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896215415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_
target_stretch.1896215415
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.1277633328
Short name T989
Test name
Test status
Simulation time 5926167887 ps
CPU time 7.31 seconds
Started Jun 26 05:00:20 PM PDT 24
Finished Jun 26 05:00:28 PM PDT 24
Peak memory 213268 kb
Host smart-9ef9043d-2dae-40c4-9047-40574098edd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277633328 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.1277633328
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2710175483
Short name T1437
Test name
Test status
Simulation time 26433146 ps
CPU time 0.64 seconds
Started Jun 26 05:00:35 PM PDT 24
Finished Jun 26 05:00:37 PM PDT 24
Peak memory 204500 kb
Host smart-db8acbae-1ca5-4dbc-8ae1-04ed3b200cde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710175483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2710175483
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.4274968291
Short name T1268
Test name
Test status
Simulation time 153003013 ps
CPU time 1.61 seconds
Started Jun 26 05:00:28 PM PDT 24
Finished Jun 26 05:00:31 PM PDT 24
Peak memory 213120 kb
Host smart-6ddf3e6a-63b3-48ee-8c9f-4dcd93613dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274968291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.4274968291
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1972554816
Short name T365
Test name
Test status
Simulation time 569458629 ps
CPU time 11.73 seconds
Started Jun 26 05:00:21 PM PDT 24
Finished Jun 26 05:00:34 PM PDT 24
Peak memory 287780 kb
Host smart-d7d2d84d-68af-4616-8ffd-6dd861edb607
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972554816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1972554816
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1942272370
Short name T985
Test name
Test status
Simulation time 5140257356 ps
CPU time 151.71 seconds
Started Jun 26 05:00:33 PM PDT 24
Finished Jun 26 05:03:05 PM PDT 24
Peak memory 730568 kb
Host smart-e766dc78-6969-444a-a179-9cd5f6c4f9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942272370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1942272370
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.4287541363
Short name T995
Test name
Test status
Simulation time 1399175421 ps
CPU time 89.87 seconds
Started Jun 26 05:00:22 PM PDT 24
Finished Jun 26 05:01:54 PM PDT 24
Peak memory 528020 kb
Host smart-2b5779eb-f9f1-4cce-a894-9fe8a0c8e367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287541363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.4287541363
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.2931539986
Short name T800
Test name
Test status
Simulation time 471002964 ps
CPU time 0.89 seconds
Started Jun 26 05:00:25 PM PDT 24
Finished Jun 26 05:00:28 PM PDT 24
Peak memory 204480 kb
Host smart-e7285f08-c419-4031-aa91-343300abb9b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931539986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.2931539986
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.4078121860
Short name T1472
Test name
Test status
Simulation time 264768530 ps
CPU time 8.19 seconds
Started Jun 26 05:00:22 PM PDT 24
Finished Jun 26 05:00:32 PM PDT 24
Peak memory 227284 kb
Host smart-e4aed6d3-d233-4be7-94ae-1a84a5837759
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078121860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.4078121860
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3025771401
Short name T660
Test name
Test status
Simulation time 14918236319 ps
CPU time 222.59 seconds
Started Jun 26 05:00:21 PM PDT 24
Finished Jun 26 05:04:06 PM PDT 24
Peak memory 967756 kb
Host smart-b9d3bff3-738d-4bab-a859-1f139fc890c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025771401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3025771401
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1217530932
Short name T245
Test name
Test status
Simulation time 1365875548 ps
CPU time 4.92 seconds
Started Jun 26 05:00:35 PM PDT 24
Finished Jun 26 05:00:41 PM PDT 24
Peak memory 204828 kb
Host smart-6c501453-31fb-4d07-92b2-12c1bbda7eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217530932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1217530932
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.441232741
Short name T336
Test name
Test status
Simulation time 3058637192 ps
CPU time 64.14 seconds
Started Jun 26 05:00:39 PM PDT 24
Finished Jun 26 05:01:44 PM PDT 24
Peak memory 342580 kb
Host smart-4fe3e575-b337-43ac-99d9-a7088d71f3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441232741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.441232741
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3970564417
Short name T1127
Test name
Test status
Simulation time 105755257 ps
CPU time 0.66 seconds
Started Jun 26 05:00:20 PM PDT 24
Finished Jun 26 05:00:22 PM PDT 24
Peak memory 204528 kb
Host smart-10402db9-b673-4b65-a662-a5ad80bc5548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970564417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3970564417
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.3665795274
Short name T962
Test name
Test status
Simulation time 27154025338 ps
CPU time 215.36 seconds
Started Jun 26 05:00:30 PM PDT 24
Finished Jun 26 05:04:06 PM PDT 24
Peak memory 1650032 kb
Host smart-44bd05b3-34c6-44d3-b1c0-97108bc59a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665795274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.3665795274
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.2713438605
Short name T938
Test name
Test status
Simulation time 627532375 ps
CPU time 5.09 seconds
Started Jun 26 05:00:30 PM PDT 24
Finished Jun 26 05:00:37 PM PDT 24
Peak memory 243092 kb
Host smart-f0338bb9-48fd-4e10-806e-abd2b2684690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713438605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2713438605
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.1497233324
Short name T699
Test name
Test status
Simulation time 1451428395 ps
CPU time 30.63 seconds
Started Jun 26 05:00:24 PM PDT 24
Finished Jun 26 05:00:56 PM PDT 24
Peak memory 364220 kb
Host smart-97866ccc-e20f-47b8-90da-df2a362f836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497233324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.1497233324
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.868851375
Short name T364
Test name
Test status
Simulation time 503713369 ps
CPU time 8.52 seconds
Started Jun 26 05:00:30 PM PDT 24
Finished Jun 26 05:00:39 PM PDT 24
Peak memory 213104 kb
Host smart-2c3cfdd9-17a4-4fb4-b200-5fe8be7f1972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868851375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.868851375
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.415749975
Short name T492
Test name
Test status
Simulation time 550050191 ps
CPU time 2.39 seconds
Started Jun 26 05:00:42 PM PDT 24
Finished Jun 26 05:00:45 PM PDT 24
Peak memory 204844 kb
Host smart-ebf21098-9449-4be3-984d-d531cd7f5318
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415749975 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.415749975
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2278251979
Short name T390
Test name
Test status
Simulation time 200322573 ps
CPU time 1.17 seconds
Started Jun 26 05:00:39 PM PDT 24
Finished Jun 26 05:00:41 PM PDT 24
Peak memory 204596 kb
Host smart-a5eeeb13-5dc9-429e-982e-1c39e3c98925
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278251979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2278251979
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.2340559572
Short name T545
Test name
Test status
Simulation time 154409392 ps
CPU time 1.17 seconds
Started Jun 26 05:00:38 PM PDT 24
Finished Jun 26 05:00:41 PM PDT 24
Peak memory 204824 kb
Host smart-e07605bf-9418-48a6-bc35-c553e107f32c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340559572 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.2340559572
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.3601585780
Short name T482
Test name
Test status
Simulation time 1858229895 ps
CPU time 2.5 seconds
Started Jun 26 05:00:39 PM PDT 24
Finished Jun 26 05:00:43 PM PDT 24
Peak memory 204736 kb
Host smart-39c41904-90c3-497b-acf6-a0e185243b5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601585780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.3601585780
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.2985632119
Short name T1078
Test name
Test status
Simulation time 227574724 ps
CPU time 1.17 seconds
Started Jun 26 05:00:38 PM PDT 24
Finished Jun 26 05:00:40 PM PDT 24
Peak memory 204552 kb
Host smart-49fe872f-4187-42f9-ab6d-9820f6ba37af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985632119 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.2985632119
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3023834274
Short name T775
Test name
Test status
Simulation time 1062239228 ps
CPU time 5.84 seconds
Started Jun 26 05:02:38 PM PDT 24
Finished Jun 26 05:02:45 PM PDT 24
Peak memory 218364 kb
Host smart-eae29bf4-38b1-4b27-ad4e-a88781090e96
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023834274 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3023834274
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.1460970114
Short name T432
Test name
Test status
Simulation time 9404573766 ps
CPU time 37.29 seconds
Started Jun 26 05:00:32 PM PDT 24
Finished Jun 26 05:01:10 PM PDT 24
Peak memory 765952 kb
Host smart-172dbddb-70d5-48da-9869-13ff2f34e621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460970114 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.1460970114
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3124553718
Short name T633
Test name
Test status
Simulation time 3910413877 ps
CPU time 16.38 seconds
Started Jun 26 05:00:31 PM PDT 24
Finished Jun 26 05:00:49 PM PDT 24
Peak memory 204984 kb
Host smart-8693fbc0-f712-4f95-8df6-283dad93c43a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124553718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3124553718
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.121222744
Short name T802
Test name
Test status
Simulation time 10645100487 ps
CPU time 45.68 seconds
Started Jun 26 05:00:30 PM PDT 24
Finished Jun 26 05:01:17 PM PDT 24
Peak memory 205432 kb
Host smart-d9009497-af5c-432a-96e6-331386c7959f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121222744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.121222744
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.1084130347
Short name T834
Test name
Test status
Simulation time 10112358804 ps
CPU time 19.3 seconds
Started Jun 26 05:00:31 PM PDT 24
Finished Jun 26 05:00:52 PM PDT 24
Peak memory 204980 kb
Host smart-caf83190-fb9f-4b95-ba01-0b224860da88
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084130347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.1084130347
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.246744012
Short name T280
Test name
Test status
Simulation time 38895696163 ps
CPU time 268.81 seconds
Started Jun 26 05:00:31 PM PDT 24
Finished Jun 26 05:05:01 PM PDT 24
Peak memory 2069368 kb
Host smart-1e131126-015b-4647-a784-c39820a8d565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246744012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.246744012
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.478367943
Short name T974
Test name
Test status
Simulation time 4744924294 ps
CPU time 6.16 seconds
Started Jun 26 05:00:31 PM PDT 24
Finished Jun 26 05:00:38 PM PDT 24
Peak memory 213144 kb
Host smart-ed60170a-ba78-4171-9331-58029acd0118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478367943 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.478367943
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2830610404
Short name T730
Test name
Test status
Simulation time 105054338 ps
CPU time 0.64 seconds
Started Jun 26 05:00:57 PM PDT 24
Finished Jun 26 05:00:59 PM PDT 24
Peak memory 204468 kb
Host smart-70c00f17-b691-4dcf-8ce8-1657b7235a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830610404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2830610404
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.2939293814
Short name T282
Test name
Test status
Simulation time 138142198 ps
CPU time 4.97 seconds
Started Jun 26 05:00:47 PM PDT 24
Finished Jun 26 05:00:53 PM PDT 24
Peak memory 230684 kb
Host smart-53c2ab57-d033-40dc-a182-b5734f2c2712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939293814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.2939293814
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.1911515585
Short name T1034
Test name
Test status
Simulation time 1615054844 ps
CPU time 21.84 seconds
Started Jun 26 05:00:45 PM PDT 24
Finished Jun 26 05:01:08 PM PDT 24
Peak memory 292984 kb
Host smart-df3cedcf-042c-4041-8e57-62baafbeae23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911515585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.1911515585
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.429690736
Short name T428
Test name
Test status
Simulation time 4039165829 ps
CPU time 60.02 seconds
Started Jun 26 05:00:46 PM PDT 24
Finished Jun 26 05:01:47 PM PDT 24
Peak memory 687824 kb
Host smart-78efb0a9-8903-44f9-b17b-0d7110d7cead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429690736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.429690736
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.1199355656
Short name T851
Test name
Test status
Simulation time 7590656545 ps
CPU time 51.4 seconds
Started Jun 26 05:00:44 PM PDT 24
Finished Jun 26 05:01:36 PM PDT 24
Peak memory 662368 kb
Host smart-9a1a7ede-3d96-4062-b3ae-f287f28b3a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199355656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.1199355656
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.2049872273
Short name T735
Test name
Test status
Simulation time 110184593 ps
CPU time 1.05 seconds
Started Jun 26 05:00:44 PM PDT 24
Finished Jun 26 05:00:46 PM PDT 24
Peak memory 204488 kb
Host smart-b02f4f64-c6ae-4e30-8623-61c63fc2417d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049872273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.2049872273
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.3793215240
Short name T1449
Test name
Test status
Simulation time 441981781 ps
CPU time 5.48 seconds
Started Jun 26 05:00:47 PM PDT 24
Finished Jun 26 05:00:54 PM PDT 24
Peak memory 204728 kb
Host smart-ef49c244-2fff-47f8-91fa-406fa05ce8c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793215240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.3793215240
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.738320848
Short name T109
Test name
Test status
Simulation time 3967784443 ps
CPU time 266.09 seconds
Started Jun 26 05:00:42 PM PDT 24
Finished Jun 26 05:05:09 PM PDT 24
Peak memory 1155656 kb
Host smart-8bd5da89-a42a-4864-990a-4ce5cdcb95bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738320848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.738320848
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1838189401
Short name T40
Test name
Test status
Simulation time 291776322 ps
CPU time 12.68 seconds
Started Jun 26 05:00:52 PM PDT 24
Finished Jun 26 05:01:06 PM PDT 24
Peak memory 204784 kb
Host smart-f88bde4c-c93e-49ca-aa2e-e0daa9d7a4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838189401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1838189401
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_override.3722174502
Short name T1422
Test name
Test status
Simulation time 53102490 ps
CPU time 0.65 seconds
Started Jun 26 05:00:45 PM PDT 24
Finished Jun 26 05:00:47 PM PDT 24
Peak memory 204504 kb
Host smart-ac0b2f6b-9f09-4f14-b868-97e1d44273fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722174502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3722174502
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3534988014
Short name T1251
Test name
Test status
Simulation time 9503431257 ps
CPU time 6.98 seconds
Started Jun 26 05:00:43 PM PDT 24
Finished Jun 26 05:00:52 PM PDT 24
Peak memory 213124 kb
Host smart-fb5f5005-bb7c-45d5-be68-087bab49cacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534988014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3534988014
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.3818072351
Short name T1185
Test name
Test status
Simulation time 6061948332 ps
CPU time 219.39 seconds
Started Jun 26 05:00:43 PM PDT 24
Finished Jun 26 05:04:24 PM PDT 24
Peak memory 204916 kb
Host smart-5106bc66-7861-4e66-a2dd-182381f46ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818072351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.3818072351
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2079888894
Short name T797
Test name
Test status
Simulation time 2063032848 ps
CPU time 36.29 seconds
Started Jun 26 05:00:36 PM PDT 24
Finished Jun 26 05:01:12 PM PDT 24
Peak memory 328740 kb
Host smart-afb68fdf-0182-4d35-8929-d44db945c84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079888894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2079888894
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.833095043
Short name T288
Test name
Test status
Simulation time 421470579 ps
CPU time 18.95 seconds
Started Jun 26 05:00:44 PM PDT 24
Finished Jun 26 05:01:04 PM PDT 24
Peak memory 212972 kb
Host smart-911929ca-9d40-4410-bff9-2378f5804b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833095043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.833095043
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1669984659
Short name T1051
Test name
Test status
Simulation time 2615790997 ps
CPU time 4.45 seconds
Started Jun 26 05:00:51 PM PDT 24
Finished Jun 26 05:00:57 PM PDT 24
Peak memory 213136 kb
Host smart-3a674291-84e5-4854-b7a1-a947c443556b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669984659 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1669984659
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3400582517
Short name T913
Test name
Test status
Simulation time 1401604888 ps
CPU time 1.18 seconds
Started Jun 26 05:00:59 PM PDT 24
Finished Jun 26 05:01:01 PM PDT 24
Peak memory 204640 kb
Host smart-054ef627-9441-410f-985d-fbfb85206036
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400582517 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3400582517
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.3926844585
Short name T1161
Test name
Test status
Simulation time 648568808 ps
CPU time 1.07 seconds
Started Jun 26 05:00:51 PM PDT 24
Finished Jun 26 05:00:54 PM PDT 24
Peak memory 204536 kb
Host smart-873912df-5c3c-43a8-b630-4486f2ff2061
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926844585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.3926844585
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.2597326199
Short name T562
Test name
Test status
Simulation time 1421418383 ps
CPU time 2.16 seconds
Started Jun 26 05:00:55 PM PDT 24
Finished Jun 26 05:00:58 PM PDT 24
Peak memory 204800 kb
Host smart-41239ae4-20e9-483b-ad4f-0bac22ddbd87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597326199 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.2597326199
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.869161042
Short name T751
Test name
Test status
Simulation time 138839200 ps
CPU time 1.15 seconds
Started Jun 26 05:00:51 PM PDT 24
Finished Jun 26 05:00:54 PM PDT 24
Peak memory 204628 kb
Host smart-c8ca6e7c-dc7a-4d50-abd6-2708d39fbe2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869161042 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.869161042
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.244731780
Short name T931
Test name
Test status
Simulation time 2494223236 ps
CPU time 6.58 seconds
Started Jun 26 05:00:50 PM PDT 24
Finished Jun 26 05:00:58 PM PDT 24
Peak memory 216324 kb
Host smart-e5c4fd65-f644-4d03-9b01-fe82a07e5732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244731780 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.244731780
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.4029882033
Short name T544
Test name
Test status
Simulation time 13296050609 ps
CPU time 221.9 seconds
Started Jun 26 05:00:56 PM PDT 24
Finished Jun 26 05:04:40 PM PDT 24
Peak memory 3185976 kb
Host smart-5923866c-6a02-4ab9-a28c-e6593addf140
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029882033 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.4029882033
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.476918160
Short name T594
Test name
Test status
Simulation time 5280291369 ps
CPU time 21.97 seconds
Started Jun 26 05:00:45 PM PDT 24
Finished Jun 26 05:01:08 PM PDT 24
Peak memory 204984 kb
Host smart-d849ee98-f1bc-47ef-916a-b6def0d3209e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476918160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_tar
get_smoke.476918160
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.813421983
Short name T1439
Test name
Test status
Simulation time 561627633 ps
CPU time 10.43 seconds
Started Jun 26 05:00:51 PM PDT 24
Finished Jun 26 05:01:02 PM PDT 24
Peak memory 206960 kb
Host smart-689f7489-c8c9-49e4-abb2-9f08b6a24a34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813421983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.813421983
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.77293858
Short name T744
Test name
Test status
Simulation time 52002058122 ps
CPU time 165.21 seconds
Started Jun 26 05:00:45 PM PDT 24
Finished Jun 26 05:03:31 PM PDT 24
Peak memory 2054080 kb
Host smart-5005d6fa-6149-4cb9-abde-d6c3ea595975
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77293858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stress_wr.77293858
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2068694483
Short name T1049
Test name
Test status
Simulation time 14181506532 ps
CPU time 195.32 seconds
Started Jun 26 05:00:59 PM PDT 24
Finished Jun 26 05:04:15 PM PDT 24
Peak memory 871384 kb
Host smart-d5f64d61-cecf-4b9c-ae64-00aea17d2310
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068694483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2068694483
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1644207826
Short name T1328
Test name
Test status
Simulation time 1126036818 ps
CPU time 6.12 seconds
Started Jun 26 05:00:52 PM PDT 24
Finished Jun 26 05:01:00 PM PDT 24
Peak memory 213008 kb
Host smart-d762477c-84e5-45c0-b6a3-cf5e1df04d06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644207826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1644207826
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2935382225
Short name T426
Test name
Test status
Simulation time 59029464 ps
CPU time 0.64 seconds
Started Jun 26 05:01:08 PM PDT 24
Finished Jun 26 05:01:10 PM PDT 24
Peak memory 204424 kb
Host smart-2f67d34c-be74-41d8-ba7c-a494efb1d8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935382225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2935382225
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2308161322
Short name T1238
Test name
Test status
Simulation time 639747290 ps
CPU time 5.41 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:01:13 PM PDT 24
Peak memory 233824 kb
Host smart-1ef7a02d-9412-4504-84d6-bbbe4c28fafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308161322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2308161322
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1770726009
Short name T603
Test name
Test status
Simulation time 1060900693 ps
CPU time 5.63 seconds
Started Jun 26 05:01:02 PM PDT 24
Finished Jun 26 05:01:09 PM PDT 24
Peak memory 255972 kb
Host smart-fe8371a7-3305-4c3d-a7f8-2f41651ca4d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770726009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1770726009
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.458600385
Short name T79
Test name
Test status
Simulation time 1623672722 ps
CPU time 54.88 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:02:03 PM PDT 24
Peak memory 605496 kb
Host smart-3c8669ab-c483-43d4-9191-0cd536df0b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458600385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.458600385
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.2277674629
Short name T1255
Test name
Test status
Simulation time 14856368936 ps
CPU time 50.08 seconds
Started Jun 26 05:01:01 PM PDT 24
Finished Jun 26 05:01:52 PM PDT 24
Peak memory 576736 kb
Host smart-a5df81fd-8136-4249-a47f-621eebb58278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277674629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.2277674629
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.3165779209
Short name T651
Test name
Test status
Simulation time 75646049 ps
CPU time 0.88 seconds
Started Jun 26 05:00:57 PM PDT 24
Finished Jun 26 05:00:59 PM PDT 24
Peak memory 204768 kb
Host smart-f347902b-49a1-4e52-8308-7227726cc68a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165779209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.3165779209
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.286146963
Short name T1167
Test name
Test status
Simulation time 174244693 ps
CPU time 8.2 seconds
Started Jun 26 05:01:02 PM PDT 24
Finished Jun 26 05:01:11 PM PDT 24
Peak memory 204772 kb
Host smart-ee172f40-d656-476d-95de-848c832ea240
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286146963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx.
286146963
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1757000245
Short name T401
Test name
Test status
Simulation time 19419959364 ps
CPU time 144.05 seconds
Started Jun 26 05:00:55 PM PDT 24
Finished Jun 26 05:03:20 PM PDT 24
Peak memory 1370408 kb
Host smart-8d27cd42-b3cb-4b3d-bdc1-d55bcd325c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757000245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1757000245
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.194521036
Short name T885
Test name
Test status
Simulation time 357324240 ps
CPU time 5.83 seconds
Started Jun 26 05:01:08 PM PDT 24
Finished Jun 26 05:01:15 PM PDT 24
Peak memory 204840 kb
Host smart-471bb06a-0a72-4a73-ab39-91a5fefaf12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194521036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.194521036
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2567573591
Short name T1447
Test name
Test status
Simulation time 35929023640 ps
CPU time 27.42 seconds
Started Jun 26 05:01:05 PM PDT 24
Finished Jun 26 05:01:33 PM PDT 24
Peak memory 318384 kb
Host smart-28c4aedd-dce9-45ae-bfd7-7fea69311540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567573591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2567573591
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2695571825
Short name T759
Test name
Test status
Simulation time 17207432 ps
CPU time 0.67 seconds
Started Jun 26 05:00:58 PM PDT 24
Finished Jun 26 05:01:00 PM PDT 24
Peak memory 204568 kb
Host smart-e8ef0925-6e1a-4584-94e5-78600e6523b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695571825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2695571825
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3179044002
Short name T685
Test name
Test status
Simulation time 2702456386 ps
CPU time 39.5 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:01:47 PM PDT 24
Peak memory 224120 kb
Host smart-d1a1b933-f42b-4b03-9a60-c09948b52883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179044002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3179044002
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.4002278682
Short name T524
Test name
Test status
Simulation time 2438591308 ps
CPU time 42.55 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:01:50 PM PDT 24
Peak memory 595472 kb
Host smart-19e75653-d7b8-47fb-8130-b65e4165a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002278682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.4002278682
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3125649731
Short name T646
Test name
Test status
Simulation time 8351093865 ps
CPU time 30.53 seconds
Started Jun 26 05:00:53 PM PDT 24
Finished Jun 26 05:01:26 PM PDT 24
Peak memory 385848 kb
Host smart-e151ceaf-103f-4515-8b2f-7451fd16a505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125649731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3125649731
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.1960714258
Short name T112
Test name
Test status
Simulation time 33149666660 ps
CPU time 244.29 seconds
Started Jun 26 05:01:02 PM PDT 24
Finished Jun 26 05:05:08 PM PDT 24
Peak memory 774296 kb
Host smart-e246404a-e700-4f14-ad0c-cc8b3bb4fdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960714258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.1960714258
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.913353396
Short name T666
Test name
Test status
Simulation time 923408705 ps
CPU time 43.67 seconds
Started Jun 26 05:01:03 PM PDT 24
Finished Jun 26 05:01:47 PM PDT 24
Peak memory 212964 kb
Host smart-2886780f-8526-40dd-b4d4-6e972ac488da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913353396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.913353396
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.987051694
Short name T25
Test name
Test status
Simulation time 1729508980 ps
CPU time 4.37 seconds
Started Jun 26 05:01:06 PM PDT 24
Finished Jun 26 05:01:11 PM PDT 24
Peak memory 213048 kb
Host smart-e58e00d3-36f7-4f4c-aa59-8d52195b58a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987051694 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.987051694
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1015587446
Short name T1381
Test name
Test status
Simulation time 1471517946 ps
CPU time 1.26 seconds
Started Jun 26 05:01:09 PM PDT 24
Finished Jun 26 05:01:11 PM PDT 24
Peak memory 204816 kb
Host smart-160fcb2a-c178-4381-85a1-0d33d1a73af7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015587446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1015587446
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.2595171816
Short name T1301
Test name
Test status
Simulation time 625272681 ps
CPU time 1.24 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:01:09 PM PDT 24
Peak memory 204828 kb
Host smart-ad0e42b1-dc3b-4965-978f-dcd491ee8e44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595171816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.2595171816
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.3019464426
Short name T247
Test name
Test status
Simulation time 2196229637 ps
CPU time 2.94 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:01:11 PM PDT 24
Peak memory 204940 kb
Host smart-e9a8d921-1617-452d-894b-f8a6440e9db3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019464426 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.3019464426
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.3906264634
Short name T316
Test name
Test status
Simulation time 901163205 ps
CPU time 1.27 seconds
Started Jun 26 05:01:13 PM PDT 24
Finished Jun 26 05:01:15 PM PDT 24
Peak memory 204552 kb
Host smart-8a9be4a6-7dd3-4c0d-87bb-7db02e48aa8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906264634 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.3906264634
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.2764700152
Short name T228
Test name
Test status
Simulation time 783703831 ps
CPU time 4.28 seconds
Started Jun 26 05:01:05 PM PDT 24
Finished Jun 26 05:01:10 PM PDT 24
Peak memory 204812 kb
Host smart-5614a10a-fe62-4266-a745-71324853364a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764700152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.2764700152
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2337679290
Short name T1427
Test name
Test status
Simulation time 1288048247 ps
CPU time 6.86 seconds
Started Jun 26 05:00:59 PM PDT 24
Finished Jun 26 05:01:07 PM PDT 24
Peak memory 218924 kb
Host smart-cfd7a2b4-b6d8-4efd-98c5-166ab405c5b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337679290 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2337679290
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.171763121
Short name T1473
Test name
Test status
Simulation time 11785231521 ps
CPU time 9.45 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:01:17 PM PDT 24
Peak memory 268892 kb
Host smart-3c4cd086-f7f9-47c1-944b-430f259d4c8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171763121 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.171763121
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.4161551054
Short name T798
Test name
Test status
Simulation time 2486518163 ps
CPU time 15.47 seconds
Started Jun 26 05:01:04 PM PDT 24
Finished Jun 26 05:01:20 PM PDT 24
Peak memory 204928 kb
Host smart-54f206f7-8d2e-4576-bac3-6b209a613bb8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161551054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.4161551054
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.696829611
Short name T1047
Test name
Test status
Simulation time 7348378696 ps
CPU time 28.5 seconds
Started Jun 26 05:01:00 PM PDT 24
Finished Jun 26 05:01:29 PM PDT 24
Peak memory 236200 kb
Host smart-be5aa0f3-6cea-411e-ac1c-0aacbfa795d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696829611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_rd.696829611
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.150736659
Short name T22
Test name
Test status
Simulation time 31093574229 ps
CPU time 39.17 seconds
Started Jun 26 05:01:01 PM PDT 24
Finished Jun 26 05:01:41 PM PDT 24
Peak memory 808348 kb
Host smart-d0f4d5cb-f0a6-43f4-898d-d7921befbf9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150736659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c
_target_stress_wr.150736659
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.3824281177
Short name T847
Test name
Test status
Simulation time 27120892549 ps
CPU time 223.76 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:04:52 PM PDT 24
Peak memory 1974008 kb
Host smart-398b95e3-003a-4446-8d2a-b7cac5a10136
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824281177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.3824281177
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.190607816
Short name T888
Test name
Test status
Simulation time 5661462267 ps
CPU time 7.6 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:01:16 PM PDT 24
Peak memory 212764 kb
Host smart-97fc3237-5a5e-4548-acfa-f745b6c7f7e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190607816 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.190607816
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.1937167972
Short name T1116
Test name
Test status
Simulation time 25111188 ps
CPU time 0.67 seconds
Started Jun 26 05:01:32 PM PDT 24
Finished Jun 26 05:01:35 PM PDT 24
Peak memory 204464 kb
Host smart-87f13960-9842-413b-b274-ec2c351ee007
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937167972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.1937167972
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.3078275894
Short name T281
Test name
Test status
Simulation time 1229438575 ps
CPU time 6.01 seconds
Started Jun 26 05:01:18 PM PDT 24
Finished Jun 26 05:01:25 PM PDT 24
Peak memory 251936 kb
Host smart-ca05bcd1-f139-479e-aeb3-30a840c7f9e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078275894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.3078275894
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.3157616046
Short name T1221
Test name
Test status
Simulation time 6829250962 ps
CPU time 122.34 seconds
Started Jun 26 05:01:15 PM PDT 24
Finished Jun 26 05:03:18 PM PDT 24
Peak memory 632104 kb
Host smart-bdfd77f3-1170-4e25-b35c-c5c5cf2d96ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157616046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.3157616046
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.99821433
Short name T983
Test name
Test status
Simulation time 5713940537 ps
CPU time 39.33 seconds
Started Jun 26 05:01:16 PM PDT 24
Finished Jun 26 05:01:56 PM PDT 24
Peak memory 548512 kb
Host smart-3026f92b-002e-408b-8f48-789bb44d884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99821433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.99821433
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.3403916744
Short name T1200
Test name
Test status
Simulation time 835866307 ps
CPU time 1.03 seconds
Started Jun 26 05:01:16 PM PDT 24
Finished Jun 26 05:01:19 PM PDT 24
Peak memory 204488 kb
Host smart-096a0ccf-8dad-4508-9593-a491e099f2ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403916744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.3403916744
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.2994543908
Short name T1197
Test name
Test status
Simulation time 133676666 ps
CPU time 3.03 seconds
Started Jun 26 05:01:16 PM PDT 24
Finished Jun 26 05:01:20 PM PDT 24
Peak memory 204844 kb
Host smart-84a74005-3579-4755-8d49-28ea0373b6e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994543908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.2994543908
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.3971264245
Short name T1413
Test name
Test status
Simulation time 6303929740 ps
CPU time 57.73 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:02:06 PM PDT 24
Peak memory 861680 kb
Host smart-948c5c05-b43e-4f8e-9a91-e39fdc68a823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971264245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.3971264245
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.4017104325
Short name T971
Test name
Test status
Simulation time 908982213 ps
CPU time 7.71 seconds
Started Jun 26 05:01:35 PM PDT 24
Finished Jun 26 05:01:44 PM PDT 24
Peak memory 204836 kb
Host smart-36d2b0f2-09e2-484e-a27b-13a8aec69bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017104325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.4017104325
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1367613961
Short name T1364
Test name
Test status
Simulation time 5961499838 ps
CPU time 67.42 seconds
Started Jun 26 05:01:27 PM PDT 24
Finished Jun 26 05:02:36 PM PDT 24
Peak memory 336076 kb
Host smart-7e60ed87-a646-4ee8-8484-358289f3b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367613961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1367613961
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.4180048716
Short name T273
Test name
Test status
Simulation time 16608984 ps
CPU time 0.67 seconds
Started Jun 26 05:01:06 PM PDT 24
Finished Jun 26 05:01:08 PM PDT 24
Peak memory 204440 kb
Host smart-c69e36de-a761-48fe-9a95-a1fc77b3b188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180048716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.4180048716
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.181287260
Short name T585
Test name
Test status
Simulation time 1666566871 ps
CPU time 21.01 seconds
Started Jun 26 05:01:17 PM PDT 24
Finished Jun 26 05:01:39 PM PDT 24
Peak memory 285308 kb
Host smart-a20aba04-ee3b-4470-be9c-f1c253078910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181287260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.181287260
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.2661591482
Short name T681
Test name
Test status
Simulation time 241077333 ps
CPU time 1.51 seconds
Started Jun 26 05:01:16 PM PDT 24
Finished Jun 26 05:01:18 PM PDT 24
Peak memory 204800 kb
Host smart-bb634ab1-8933-4459-82d6-1bacaef67be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661591482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2661591482
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.7164432
Short name T614
Test name
Test status
Simulation time 1773654184 ps
CPU time 85.44 seconds
Started Jun 26 05:01:07 PM PDT 24
Finished Jun 26 05:02:33 PM PDT 24
Peak memory 368852 kb
Host smart-cb0381c4-e727-4803-a90d-7c70c3b0fe3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7164432 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.7164432
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.2929348293
Short name T113
Test name
Test status
Simulation time 47769763823 ps
CPU time 342.09 seconds
Started Jun 26 05:01:17 PM PDT 24
Finished Jun 26 05:07:00 PM PDT 24
Peak memory 2035812 kb
Host smart-d7c8f2de-6052-4a25-8a7f-77611dbb6440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929348293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.2929348293
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.3275274748
Short name T262
Test name
Test status
Simulation time 2839446857 ps
CPU time 13.78 seconds
Started Jun 26 05:01:17 PM PDT 24
Finished Jun 26 05:01:33 PM PDT 24
Peak memory 220956 kb
Host smart-41a80408-1940-4014-8a92-9643d633ed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275274748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.3275274748
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.2574076387
Short name T828
Test name
Test status
Simulation time 2077265845 ps
CPU time 4.85 seconds
Started Jun 26 05:01:27 PM PDT 24
Finished Jun 26 05:01:34 PM PDT 24
Peak memory 213028 kb
Host smart-9dccecfa-8692-4c9b-a914-8aad6ee468ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574076387 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.2574076387
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2971210684
Short name T1039
Test name
Test status
Simulation time 227611751 ps
CPU time 1.38 seconds
Started Jun 26 05:01:24 PM PDT 24
Finished Jun 26 05:01:27 PM PDT 24
Peak memory 204816 kb
Host smart-a3fb4103-075a-4920-8455-0f73acd428bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971210684 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2971210684
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2343976669
Short name T506
Test name
Test status
Simulation time 248996966 ps
CPU time 1.48 seconds
Started Jun 26 05:01:25 PM PDT 24
Finished Jun 26 05:01:29 PM PDT 24
Peak memory 204808 kb
Host smart-d27e92ec-58a8-4bb4-988a-ad8843f751cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343976669 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2343976669
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.3082085310
Short name T1259
Test name
Test status
Simulation time 513438861 ps
CPU time 2.8 seconds
Started Jun 26 05:01:34 PM PDT 24
Finished Jun 26 05:01:38 PM PDT 24
Peak memory 205012 kb
Host smart-bfe1f035-0d52-4504-b6c6-10b53555d945
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082085310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.3082085310
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.694610426
Short name T1163
Test name
Test status
Simulation time 146279330 ps
CPU time 1.2 seconds
Started Jun 26 05:01:32 PM PDT 24
Finished Jun 26 05:01:35 PM PDT 24
Peak memory 204636 kb
Host smart-8aa42575-69bf-4026-9e18-83c2f4a3390b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694610426 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.694610426
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3882673550
Short name T481
Test name
Test status
Simulation time 439904510 ps
CPU time 3.42 seconds
Started Jun 26 05:01:27 PM PDT 24
Finished Jun 26 05:01:32 PM PDT 24
Peak memory 204796 kb
Host smart-38e3884f-f291-4676-9803-308790da0a51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882673550 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3882673550
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.4056052087
Short name T783
Test name
Test status
Simulation time 742973259 ps
CPU time 3.86 seconds
Started Jun 26 05:01:24 PM PDT 24
Finished Jun 26 05:01:29 PM PDT 24
Peak memory 204948 kb
Host smart-1c603f63-afa9-438f-9ad3-767e5e870f24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056052087 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.4056052087
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.3146242425
Short name T1463
Test name
Test status
Simulation time 4579545367 ps
CPU time 44.97 seconds
Started Jun 26 05:01:25 PM PDT 24
Finished Jun 26 05:02:12 PM PDT 24
Peak memory 1254492 kb
Host smart-948a6c20-4ad6-4890-b63d-a82936fd468a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146242425 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.3146242425
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.1908554658
Short name T151
Test name
Test status
Simulation time 1156357446 ps
CPU time 16.83 seconds
Started Jun 26 05:01:16 PM PDT 24
Finished Jun 26 05:01:34 PM PDT 24
Peak memory 204744 kb
Host smart-aff39db8-b54e-4131-96b7-cacf35655a39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908554658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.1908554658
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2753076769
Short name T595
Test name
Test status
Simulation time 4572670330 ps
CPU time 27.17 seconds
Started Jun 26 05:01:25 PM PDT 24
Finished Jun 26 05:01:54 PM PDT 24
Peak memory 231324 kb
Host smart-48d01d27-8c08-4761-a841-05d8a8aa2fef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753076769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2753076769
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.257322685
Short name T688
Test name
Test status
Simulation time 44106841348 ps
CPU time 99.39 seconds
Started Jun 26 05:01:17 PM PDT 24
Finished Jun 26 05:02:58 PM PDT 24
Peak memory 1629536 kb
Host smart-88b3bafc-5b4e-4296-b499-f762c4e839b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257322685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.257322685
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.3021751261
Short name T892
Test name
Test status
Simulation time 6462423986 ps
CPU time 65.56 seconds
Started Jun 26 05:01:26 PM PDT 24
Finished Jun 26 05:02:34 PM PDT 24
Peak memory 451496 kb
Host smart-2e750e31-4421-4c7e-b784-75502325abe1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021751261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.3021751261
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.1669365762
Short name T893
Test name
Test status
Simulation time 1213122122 ps
CPU time 6.27 seconds
Started Jun 26 05:01:26 PM PDT 24
Finished Jun 26 05:01:34 PM PDT 24
Peak memory 212980 kb
Host smart-5487afb6-7376-4a6f-8d72-3b7879846d2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669365762 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.1669365762
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.3157766196
Short name T756
Test name
Test status
Simulation time 22943995 ps
CPU time 0.65 seconds
Started Jun 26 05:01:50 PM PDT 24
Finished Jun 26 05:01:53 PM PDT 24
Peak memory 204424 kb
Host smart-ee84839e-215a-46b4-97f2-21586012f8a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157766196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.3157766196
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1146186655
Short name T51
Test name
Test status
Simulation time 339540849 ps
CPU time 4.8 seconds
Started Jun 26 05:01:38 PM PDT 24
Finished Jun 26 05:01:44 PM PDT 24
Peak memory 213036 kb
Host smart-3b6f4325-aa1d-4818-ba1c-cd16517a71cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146186655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1146186655
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.3115698506
Short name T65
Test name
Test status
Simulation time 869161718 ps
CPU time 5.1 seconds
Started Jun 26 05:01:34 PM PDT 24
Finished Jun 26 05:01:41 PM PDT 24
Peak memory 247540 kb
Host smart-dd0bc1e2-2fbb-43c9-a111-5a6de20c4077
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115698506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.3115698506
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2119682282
Short name T77
Test name
Test status
Simulation time 2860877662 ps
CPU time 194.66 seconds
Started Jun 26 05:01:32 PM PDT 24
Finished Jun 26 05:04:49 PM PDT 24
Peak memory 771904 kb
Host smart-03991855-a821-4149-8a67-5e58df405f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119682282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2119682282
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2598412424
Short name T809
Test name
Test status
Simulation time 9828962982 ps
CPU time 173.53 seconds
Started Jun 26 05:01:35 PM PDT 24
Finished Jun 26 05:04:30 PM PDT 24
Peak memory 706784 kb
Host smart-d731dfac-90b5-4dd7-834e-dceebf16bf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598412424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2598412424
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.562549619
Short name T581
Test name
Test status
Simulation time 143166902 ps
CPU time 1.04 seconds
Started Jun 26 05:01:34 PM PDT 24
Finished Jun 26 05:01:36 PM PDT 24
Peak memory 204464 kb
Host smart-3a5934b0-8b57-4c99-a736-37b9d086773a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562549619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.562549619
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2620322212
Short name T889
Test name
Test status
Simulation time 2459869395 ps
CPU time 4.46 seconds
Started Jun 26 05:01:35 PM PDT 24
Finished Jun 26 05:01:40 PM PDT 24
Peak memory 236644 kb
Host smart-e173520b-e9f0-4126-8eef-e90b0c05775c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620322212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2620322212
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1590419
Short name T1021
Test name
Test status
Simulation time 10933825149 ps
CPU time 158.68 seconds
Started Jun 26 05:01:34 PM PDT 24
Finished Jun 26 05:04:14 PM PDT 24
Peak memory 832992 kb
Host smart-9a1e6f6a-ad23-4db6-9929-1e86fff47d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1590419
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.3422474640
Short name T715
Test name
Test status
Simulation time 2024286251 ps
CPU time 7.12 seconds
Started Jun 26 05:01:51 PM PDT 24
Finished Jun 26 05:02:00 PM PDT 24
Peak memory 204884 kb
Host smart-0db316a1-6b14-4a8e-8bee-a616d8f698f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422474640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.3422474640
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.3365320676
Short name T33
Test name
Test status
Simulation time 1419684462 ps
CPU time 65.49 seconds
Started Jun 26 05:01:47 PM PDT 24
Finished Jun 26 05:02:53 PM PDT 24
Peak memory 318756 kb
Host smart-d3a93d4a-6b1d-4fa0-86d2-d812b2d84e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365320676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.3365320676
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2770432787
Short name T1330
Test name
Test status
Simulation time 46512130 ps
CPU time 0.67 seconds
Started Jun 26 05:01:34 PM PDT 24
Finished Jun 26 05:01:36 PM PDT 24
Peak memory 204464 kb
Host smart-d5af53f8-bd78-4ad1-9649-9c19edd46922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770432787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2770432787
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2709945751
Short name T621
Test name
Test status
Simulation time 54683236170 ps
CPU time 1081.31 seconds
Started Jun 26 05:01:40 PM PDT 24
Finished Jun 26 05:19:43 PM PDT 24
Peak memory 213104 kb
Host smart-63ea0c9f-7ae4-4904-a233-b899ac6c6add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709945751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2709945751
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.189402142
Short name T1002
Test name
Test status
Simulation time 64588702 ps
CPU time 1.56 seconds
Started Jun 26 05:01:37 PM PDT 24
Finished Jun 26 05:01:39 PM PDT 24
Peak memory 204800 kb
Host smart-1749cc87-8223-41ae-beaa-a6dea8961dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189402142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.189402142
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.2393728571
Short name T1372
Test name
Test status
Simulation time 1249806349 ps
CPU time 27.8 seconds
Started Jun 26 05:01:33 PM PDT 24
Finished Jun 26 05:02:03 PM PDT 24
Peak memory 375352 kb
Host smart-0bd93b48-b0f6-424d-9576-491531a85259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393728571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.2393728571
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.12175019
Short name T1157
Test name
Test status
Simulation time 1683683518 ps
CPU time 18.53 seconds
Started Jun 26 05:01:37 PM PDT 24
Finished Jun 26 05:01:57 PM PDT 24
Peak memory 213108 kb
Host smart-cd98c514-9dff-4127-ab96-8bfef2b5d397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12175019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.12175019
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1312697855
Short name T119
Test name
Test status
Simulation time 272756582 ps
CPU time 1.59 seconds
Started Jun 26 05:01:42 PM PDT 24
Finished Jun 26 05:01:45 PM PDT 24
Peak memory 204740 kb
Host smart-97b8bbcf-0464-4010-b86a-fcf51c178dd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312697855 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1312697855
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.798495649
Short name T253
Test name
Test status
Simulation time 664187767 ps
CPU time 1.48 seconds
Started Jun 26 05:01:45 PM PDT 24
Finished Jun 26 05:01:47 PM PDT 24
Peak memory 206720 kb
Host smart-d75ecad6-ba95-4746-818b-c6a97bf06c28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798495649 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.i2c_target_fifo_reset_tx.798495649
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.684026681
Short name T1363
Test name
Test status
Simulation time 1287955745 ps
CPU time 2.25 seconds
Started Jun 26 05:01:50 PM PDT 24
Finished Jun 26 05:01:54 PM PDT 24
Peak memory 204832 kb
Host smart-cb4c5ed9-3210-4f87-a549-035f71405284
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684026681 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.684026681
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.3888080608
Short name T1383
Test name
Test status
Simulation time 595455750 ps
CPU time 1.23 seconds
Started Jun 26 05:01:50 PM PDT 24
Finished Jun 26 05:01:53 PM PDT 24
Peak memory 204644 kb
Host smart-35c5211c-9f9a-40d4-a202-7c0d49d8ed11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888080608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.3888080608
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2638851608
Short name T886
Test name
Test status
Simulation time 1097341765 ps
CPU time 2.45 seconds
Started Jun 26 05:01:46 PM PDT 24
Finished Jun 26 05:01:49 PM PDT 24
Peak memory 204748 kb
Host smart-ebce3dca-1f3c-4f05-b8a6-3692a10aaa0c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638851608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2638851608
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.608081656
Short name T488
Test name
Test status
Simulation time 1347356226 ps
CPU time 2.53 seconds
Started Jun 26 05:01:38 PM PDT 24
Finished Jun 26 05:01:41 PM PDT 24
Peak memory 204772 kb
Host smart-fd28c102-c319-4c9c-9e7e-ebf1affe0d6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608081656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_intr_smoke.608081656
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.668115377
Short name T310
Test name
Test status
Simulation time 13057438079 ps
CPU time 223.84 seconds
Started Jun 26 05:01:40 PM PDT 24
Finished Jun 26 05:05:25 PM PDT 24
Peak memory 3296656 kb
Host smart-bb40d8f5-e795-4794-a5b3-1bdfa074d6ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668115377 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.668115377
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2278463710
Short name T149
Test name
Test status
Simulation time 1852319366 ps
CPU time 7.52 seconds
Started Jun 26 05:01:39 PM PDT 24
Finished Jun 26 05:01:48 PM PDT 24
Peak memory 204724 kb
Host smart-b9c8f43a-e3f0-4ee2-8cfb-9ecd2a641cc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278463710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2278463710
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.1502755557
Short name T1334
Test name
Test status
Simulation time 6191596125 ps
CPU time 18.31 seconds
Started Jun 26 05:01:38 PM PDT 24
Finished Jun 26 05:01:57 PM PDT 24
Peak memory 214356 kb
Host smart-99b88b06-0624-4b4b-9bc8-c26dd4074f02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502755557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.1502755557
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.1928764903
Short name T1118
Test name
Test status
Simulation time 31904222875 ps
CPU time 121.84 seconds
Started Jun 26 05:01:38 PM PDT 24
Finished Jun 26 05:03:40 PM PDT 24
Peak memory 1735848 kb
Host smart-1a2bb3fc-3851-4c03-9cd8-19af02fb82a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928764903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.1928764903
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3953208826
Short name T593
Test name
Test status
Simulation time 5172424649 ps
CPU time 6.84 seconds
Started Jun 26 05:01:43 PM PDT 24
Finished Jun 26 05:01:51 PM PDT 24
Peak memory 204952 kb
Host smart-423a9451-4ef3-4312-97d5-3cc231f6ad93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953208826 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3953208826
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.3569934427
Short name T880
Test name
Test status
Simulation time 29189201 ps
CPU time 0.64 seconds
Started Jun 26 04:56:05 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 204428 kb
Host smart-a6d5dfdb-adc6-4318-91a9-612ff5207a0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569934427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.3569934427
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.2407884252
Short name T118
Test name
Test status
Simulation time 612714984 ps
CPU time 2.29 seconds
Started Jun 26 04:55:55 PM PDT 24
Finished Jun 26 04:55:59 PM PDT 24
Peak memory 221296 kb
Host smart-a6e8ae46-5a68-4d15-b852-065a0739d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407884252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.2407884252
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.1482998938
Short name T1202
Test name
Test status
Simulation time 739959676 ps
CPU time 3.37 seconds
Started Jun 26 04:55:56 PM PDT 24
Finished Jun 26 04:56:02 PM PDT 24
Peak memory 226976 kb
Host smart-1e23204f-360f-4e3b-a308-401341f0db7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482998938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.1482998938
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3459536591
Short name T1184
Test name
Test status
Simulation time 6028031305 ps
CPU time 47.66 seconds
Started Jun 26 04:55:58 PM PDT 24
Finished Jun 26 04:56:48 PM PDT 24
Peak memory 582556 kb
Host smart-992e178a-1a99-4461-a621-4ff247036595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459536591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3459536591
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.2740997966
Short name T287
Test name
Test status
Simulation time 2448125886 ps
CPU time 167.97 seconds
Started Jun 26 04:55:58 PM PDT 24
Finished Jun 26 04:58:49 PM PDT 24
Peak memory 692960 kb
Host smart-37c4eefb-6998-4d2f-b24a-7c9bf15a484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740997966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.2740997966
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.2069190852
Short name T1321
Test name
Test status
Simulation time 120224031 ps
CPU time 0.95 seconds
Started Jun 26 04:56:00 PM PDT 24
Finished Jun 26 04:56:04 PM PDT 24
Peak memory 204560 kb
Host smart-2b3bac85-bc4d-4781-9978-f57205b644fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069190852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.2069190852
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1298257940
Short name T801
Test name
Test status
Simulation time 2356867579 ps
CPU time 4.16 seconds
Started Jun 26 04:56:03 PM PDT 24
Finished Jun 26 04:56:11 PM PDT 24
Peak memory 204932 kb
Host smart-abf24db4-d3d5-40cd-8189-7e3977504a3d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298257940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1298257940
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1059710408
Short name T334
Test name
Test status
Simulation time 5585251120 ps
CPU time 73.74 seconds
Started Jun 26 04:56:04 PM PDT 24
Finished Jun 26 04:57:21 PM PDT 24
Peak memory 886252 kb
Host smart-b3582445-d449-41aa-b341-db372406d013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059710408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1059710408
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.706624931
Short name T1195
Test name
Test status
Simulation time 2983749607 ps
CPU time 19.1 seconds
Started Jun 26 04:56:03 PM PDT 24
Finished Jun 26 04:56:26 PM PDT 24
Peak memory 204920 kb
Host smart-c883a2e4-448f-4c53-88eb-c402e1ea7ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706624931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.706624931
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_override.1557565996
Short name T127
Test name
Test status
Simulation time 47220329 ps
CPU time 0.64 seconds
Started Jun 26 04:56:00 PM PDT 24
Finished Jun 26 04:56:03 PM PDT 24
Peak memory 204552 kb
Host smart-ae50de90-59ef-4d37-a244-4fff7b0619ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557565996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.1557565996
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3706707205
Short name T1442
Test name
Test status
Simulation time 7288295845 ps
CPU time 569.64 seconds
Started Jun 26 04:56:01 PM PDT 24
Finished Jun 26 05:05:34 PM PDT 24
Peak memory 1352660 kb
Host smart-bb9ba5c1-122e-4b7c-b724-a68299b4354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706707205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3706707205
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.1020226400
Short name T1469
Test name
Test status
Simulation time 509870958 ps
CPU time 2.05 seconds
Started Jun 26 04:55:58 PM PDT 24
Finished Jun 26 04:56:03 PM PDT 24
Peak memory 204816 kb
Host smart-569b35a9-bfb0-4672-ab11-0a50a0ef0c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020226400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.1020226400
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2958284716
Short name T1378
Test name
Test status
Simulation time 1095957900 ps
CPU time 19.46 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:21 PM PDT 24
Peak memory 294304 kb
Host smart-440168ea-e316-4663-bce6-884b8312e9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958284716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2958284716
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.782395839
Short name T165
Test name
Test status
Simulation time 1972917077 ps
CPU time 33.41 seconds
Started Jun 26 04:55:56 PM PDT 24
Finished Jun 26 04:56:32 PM PDT 24
Peak memory 212964 kb
Host smart-5fd602a1-02e4-4e08-913e-2b324be5ecfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782395839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.782395839
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3765695440
Short name T163
Test name
Test status
Simulation time 63875020 ps
CPU time 0.9 seconds
Started Jun 26 04:56:21 PM PDT 24
Finished Jun 26 04:56:24 PM PDT 24
Peak memory 223292 kb
Host smart-3a8925e0-4235-4f91-9c1e-39108a3e6cf2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765695440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3765695440
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.3402118868
Short name T1362
Test name
Test status
Simulation time 1669490847 ps
CPU time 4.58 seconds
Started Jun 26 04:56:01 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 214128 kb
Host smart-2b013469-0cfc-4a8b-8810-9da1a05bd7ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402118868 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.3402118868
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.323425351
Short name T268
Test name
Test status
Simulation time 292799096 ps
CPU time 1.2 seconds
Started Jun 26 04:56:03 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 204884 kb
Host smart-03dc199a-d097-44a5-97ed-8fbce1147c7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323425351 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.323425351
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.1685167030
Short name T1139
Test name
Test status
Simulation time 504350548 ps
CPU time 2.4 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:09 PM PDT 24
Peak memory 204796 kb
Host smart-87de4f95-e2d1-40c1-b5b0-2b4381a1c1bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685167030 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.1685167030
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.1368555798
Short name T812
Test name
Test status
Simulation time 547371681 ps
CPU time 1.18 seconds
Started Jun 26 04:56:03 PM PDT 24
Finished Jun 26 04:56:07 PM PDT 24
Peak memory 204348 kb
Host smart-a6b0a9be-f07d-4bcc-ae13-178d1c29d9e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368555798 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.1368555798
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.3977835655
Short name T650
Test name
Test status
Simulation time 383774765 ps
CPU time 5.08 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 04:56:21 PM PDT 24
Peak memory 205052 kb
Host smart-e2cfde0a-a632-46df-8433-24044419253a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977835655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_hrst.3977835655
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.538961264
Short name T1445
Test name
Test status
Simulation time 972549422 ps
CPU time 5.02 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 04:56:21 PM PDT 24
Peak memory 212848 kb
Host smart-35d76025-5c9b-4330-b3b0-9487c8d74040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538961264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.538961264
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3324545799
Short name T19
Test name
Test status
Simulation time 16876050428 ps
CPU time 9.63 seconds
Started Jun 26 04:56:07 PM PDT 24
Finished Jun 26 04:56:18 PM PDT 24
Peak memory 279396 kb
Host smart-d15201b2-34b1-43e3-8624-29f35f9a77a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324545799 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3324545799
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.2175815732
Short name T84
Test name
Test status
Simulation time 920777185 ps
CPU time 13 seconds
Started Jun 26 04:56:03 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 204776 kb
Host smart-5d1f3893-0185-4f01-853f-6359b89bc1dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175815732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.2175815732
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1443166864
Short name T821
Test name
Test status
Simulation time 1716240490 ps
CPU time 73.92 seconds
Started Jun 26 04:56:11 PM PDT 24
Finished Jun 26 04:57:27 PM PDT 24
Peak memory 208196 kb
Host smart-e860c960-ccb8-4af0-8168-bc7cb172827f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443166864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1443166864
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1371014169
Short name T583
Test name
Test status
Simulation time 11916058721 ps
CPU time 7.16 seconds
Started Jun 26 04:56:07 PM PDT 24
Finished Jun 26 04:56:16 PM PDT 24
Peak memory 204972 kb
Host smart-36697ae5-6ef0-4040-a017-60c1cf5a85d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371014169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1371014169
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2767227839
Short name T1329
Test name
Test status
Simulation time 18024641222 ps
CPU time 719.45 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 05:08:05 PM PDT 24
Peak memory 3661776 kb
Host smart-c8d1a8bb-0ea1-48a1-8297-5952e9b6c0b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767227839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2767227839
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.2540120438
Short name T950
Test name
Test status
Simulation time 26981631893 ps
CPU time 6.8 seconds
Started Jun 26 04:56:11 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 213832 kb
Host smart-0c9b1a7f-4f64-41bb-b570-d3b46d531e8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540120438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.2540120438
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.1220617520
Short name T1071
Test name
Test status
Simulation time 51339845 ps
CPU time 0.63 seconds
Started Jun 26 05:02:13 PM PDT 24
Finished Jun 26 05:02:15 PM PDT 24
Peak memory 204420 kb
Host smart-35372bdb-f953-4a01-9c5c-05cf252ca2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220617520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.1220617520
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.98762409
Short name T1233
Test name
Test status
Simulation time 199798949 ps
CPU time 3.2 seconds
Started Jun 26 05:01:57 PM PDT 24
Finished Jun 26 05:02:03 PM PDT 24
Peak memory 219172 kb
Host smart-1642f802-8f4b-4ea9-ad84-bf0e166686da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98762409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.98762409
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.639497955
Short name T732
Test name
Test status
Simulation time 454141852 ps
CPU time 22.42 seconds
Started Jun 26 05:01:50 PM PDT 24
Finished Jun 26 05:02:14 PM PDT 24
Peak memory 285960 kb
Host smart-1eee3881-0c32-41fe-81f4-bd52cb570b43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639497955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_empt
y.639497955
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.925255972
Short name T994
Test name
Test status
Simulation time 5763240427 ps
CPU time 102.65 seconds
Started Jun 26 05:01:56 PM PDT 24
Finished Jun 26 05:03:40 PM PDT 24
Peak memory 770508 kb
Host smart-6534400c-15ab-4f4e-8f38-1a13ee53ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925255972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.925255972
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.2851225998
Short name T720
Test name
Test status
Simulation time 7999767281 ps
CPU time 144.28 seconds
Started Jun 26 05:01:49 PM PDT 24
Finished Jun 26 05:04:15 PM PDT 24
Peak memory 704996 kb
Host smart-496aba39-0a0e-4ed7-b32c-41bfb70c9017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851225998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.2851225998
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.978310725
Short name T874
Test name
Test status
Simulation time 678563002 ps
CPU time 1.26 seconds
Started Jun 26 05:01:50 PM PDT 24
Finished Jun 26 05:01:53 PM PDT 24
Peak memory 204752 kb
Host smart-24873f4a-37c8-443c-9c79-3c6b78078f5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978310725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_fm
t.978310725
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2201277131
Short name T665
Test name
Test status
Simulation time 153337176 ps
CPU time 3.64 seconds
Started Jun 26 05:01:55 PM PDT 24
Finished Jun 26 05:02:00 PM PDT 24
Peak memory 227440 kb
Host smart-d924da5b-a130-46dc-81f2-0138997dab35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201277131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2201277131
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.3393314302
Short name T1054
Test name
Test status
Simulation time 13310447390 ps
CPU time 140.44 seconds
Started Jun 26 05:01:51 PM PDT 24
Finished Jun 26 05:04:13 PM PDT 24
Peak memory 1302172 kb
Host smart-5fde0818-89e1-4d75-8c5d-06f4db52e269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393314302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.3393314302
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.3862449987
Short name T1222
Test name
Test status
Simulation time 1027303077 ps
CPU time 4.59 seconds
Started Jun 26 05:02:13 PM PDT 24
Finished Jun 26 05:02:18 PM PDT 24
Peak memory 204876 kb
Host smart-704dc4cc-f662-4326-b46a-4c78eaab7597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862449987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3862449987
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3652095058
Short name T1217
Test name
Test status
Simulation time 6355877683 ps
CPU time 22.85 seconds
Started Jun 26 05:02:08 PM PDT 24
Finished Jun 26 05:02:32 PM PDT 24
Peak memory 317156 kb
Host smart-a87c7d64-7ffc-499f-8d9a-a447ff996076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652095058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3652095058
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.3908654492
Short name T129
Test name
Test status
Simulation time 41066125 ps
CPU time 0.64 seconds
Started Jun 26 05:01:50 PM PDT 24
Finished Jun 26 05:01:52 PM PDT 24
Peak memory 204544 kb
Host smart-aef0fac8-eaba-41d7-9c33-b64f11a64604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908654492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.3908654492
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2913334224
Short name T987
Test name
Test status
Simulation time 28750920439 ps
CPU time 390.78 seconds
Started Jun 26 05:02:02 PM PDT 24
Finished Jun 26 05:08:34 PM PDT 24
Peak memory 767164 kb
Host smart-2b930b58-10b4-4507-9dac-6afd2785d622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913334224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2913334224
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.312981700
Short name T1219
Test name
Test status
Simulation time 482770069 ps
CPU time 2.65 seconds
Started Jun 26 05:01:56 PM PDT 24
Finished Jun 26 05:02:00 PM PDT 24
Peak memory 217712 kb
Host smart-21bafad7-b756-44d3-877f-0c36a2b03c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312981700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.312981700
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.1571834277
Short name T1188
Test name
Test status
Simulation time 2061576538 ps
CPU time 40.69 seconds
Started Jun 26 05:01:52 PM PDT 24
Finished Jun 26 05:02:34 PM PDT 24
Peak memory 418592 kb
Host smart-90e6b125-b253-42f4-97e7-632f3fc810d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571834277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.1571834277
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.2188001807
Short name T640
Test name
Test status
Simulation time 482616850 ps
CPU time 8.05 seconds
Started Jun 26 05:01:58 PM PDT 24
Finished Jun 26 05:02:08 PM PDT 24
Peak memory 212940 kb
Host smart-a339f337-0235-4da6-b30d-cba568108444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188001807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.2188001807
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.3968015659
Short name T1035
Test name
Test status
Simulation time 9009086419 ps
CPU time 5.62 seconds
Started Jun 26 05:02:08 PM PDT 24
Finished Jun 26 05:02:15 PM PDT 24
Peak memory 213088 kb
Host smart-62118cec-112d-43c7-8257-96e4f04624dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968015659 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.3968015659
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.523775306
Short name T630
Test name
Test status
Simulation time 300642272 ps
CPU time 1.09 seconds
Started Jun 26 05:02:08 PM PDT 24
Finished Jun 26 05:02:11 PM PDT 24
Peak memory 204628 kb
Host smart-0b287ef9-3d38-4b3f-b2b3-83114123414c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523775306 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.523775306
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.2330560000
Short name T154
Test name
Test status
Simulation time 416637970 ps
CPU time 1.03 seconds
Started Jun 26 05:02:07 PM PDT 24
Finished Jun 26 05:02:09 PM PDT 24
Peak memory 204604 kb
Host smart-42f7446e-c96b-41bb-9e91-3aa432057a58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330560000 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_tx.2330560000
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.2100757686
Short name T999
Test name
Test status
Simulation time 4834368397 ps
CPU time 2.53 seconds
Started Jun 26 05:02:14 PM PDT 24
Finished Jun 26 05:02:18 PM PDT 24
Peak memory 204896 kb
Host smart-ac8f2d46-81e3-4276-b3c9-1bde47ff02de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100757686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.2100757686
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.1357752576
Short name T917
Test name
Test status
Simulation time 423269311 ps
CPU time 1.07 seconds
Started Jun 26 05:02:12 PM PDT 24
Finished Jun 26 05:02:14 PM PDT 24
Peak memory 204528 kb
Host smart-dd5fe02a-6345-4ea8-a844-93e93b701a0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357752576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.1357752576
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1644244071
Short name T14
Test name
Test status
Simulation time 4829662779 ps
CPU time 2.97 seconds
Started Jun 26 05:02:02 PM PDT 24
Finished Jun 26 05:02:07 PM PDT 24
Peak memory 204912 kb
Host smart-cf474894-f086-479f-9fa5-f5800270df17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644244071 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1644244071
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.4006556980
Short name T191
Test name
Test status
Simulation time 3874546568 ps
CPU time 2.45 seconds
Started Jun 26 05:02:04 PM PDT 24
Finished Jun 26 05:02:07 PM PDT 24
Peak memory 204952 kb
Host smart-daeb3462-ab06-4de8-b4bb-fe2bd6f94a0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006556980 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.4006556980
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3792467829
Short name T928
Test name
Test status
Simulation time 2319586852 ps
CPU time 16.84 seconds
Started Jun 26 05:01:58 PM PDT 24
Finished Jun 26 05:02:17 PM PDT 24
Peak memory 204896 kb
Host smart-91ebf8c5-bc19-4235-b47d-4fa6939af0bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792467829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3792467829
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2743722896
Short name T568
Test name
Test status
Simulation time 817670333 ps
CPU time 14.06 seconds
Started Jun 26 05:02:03 PM PDT 24
Finished Jun 26 05:02:18 PM PDT 24
Peak memory 213328 kb
Host smart-a91b5b53-7d1c-4e4a-b8dc-c049171cac72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743722896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2743722896
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.2459292661
Short name T671
Test name
Test status
Simulation time 22403937423 ps
CPU time 11.32 seconds
Started Jun 26 05:01:56 PM PDT 24
Finished Jun 26 05:02:09 PM PDT 24
Peak memory 204916 kb
Host smart-9a3842e9-fbac-4e4b-94ca-5d787ec31eb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459292661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.2459292661
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1764831071
Short name T811
Test name
Test status
Simulation time 39245480809 ps
CPU time 2349.9 seconds
Started Jun 26 05:02:02 PM PDT 24
Finished Jun 26 05:41:14 PM PDT 24
Peak memory 9046480 kb
Host smart-d82cca7b-48a3-4f00-9196-0b1a81aebf02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764831071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1764831071
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.811722029
Short name T956
Test name
Test status
Simulation time 5256714756 ps
CPU time 7.14 seconds
Started Jun 26 05:02:03 PM PDT 24
Finished Jun 26 05:02:12 PM PDT 24
Peak memory 213168 kb
Host smart-06d3d1eb-ce3f-42bb-aa95-7062310d20f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811722029 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.811722029
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.2665479349
Short name T558
Test name
Test status
Simulation time 22334193 ps
CPU time 0.61 seconds
Started Jun 26 05:02:37 PM PDT 24
Finished Jun 26 05:02:39 PM PDT 24
Peak memory 204464 kb
Host smart-61041a34-a4d4-4ad8-9a61-00a7c6709dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665479349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.2665479349
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.1583692644
Short name T1290
Test name
Test status
Simulation time 532539232 ps
CPU time 1.97 seconds
Started Jun 26 05:02:26 PM PDT 24
Finished Jun 26 05:02:30 PM PDT 24
Peak memory 221072 kb
Host smart-00ac52b9-d3aa-4297-8685-adce71016680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583692644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.1583692644
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.887203788
Short name T3
Test name
Test status
Simulation time 1251207630 ps
CPU time 6.03 seconds
Started Jun 26 05:02:19 PM PDT 24
Finished Jun 26 05:02:26 PM PDT 24
Peak memory 267560 kb
Host smart-2261c17d-2e39-4187-b7ce-a28c3812e926
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887203788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.887203788
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.91649220
Short name T6
Test name
Test status
Simulation time 2086710939 ps
CPU time 142 seconds
Started Jun 26 05:02:22 PM PDT 24
Finished Jun 26 05:04:45 PM PDT 24
Peak memory 716796 kb
Host smart-30344132-bf64-4764-9b48-07694219d78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91649220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.91649220
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.365189102
Short name T396
Test name
Test status
Simulation time 1343355967 ps
CPU time 91.33 seconds
Started Jun 26 05:02:20 PM PDT 24
Finished Jun 26 05:03:53 PM PDT 24
Peak memory 538492 kb
Host smart-2ea1c264-2b17-43a5-99aa-1e138c92ac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365189102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.365189102
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2881779311
Short name T343
Test name
Test status
Simulation time 144510779 ps
CPU time 1.22 seconds
Started Jun 26 05:02:21 PM PDT 24
Finished Jun 26 05:02:23 PM PDT 24
Peak memory 204724 kb
Host smart-a2343c88-eded-47cb-8028-c478c4ed0620
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881779311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2881779311
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.3426150784
Short name T1340
Test name
Test status
Simulation time 180778421 ps
CPU time 4.33 seconds
Started Jun 26 05:02:20 PM PDT 24
Finished Jun 26 05:02:26 PM PDT 24
Peak memory 204760 kb
Host smart-fba1716b-6b56-48a1-a1d0-e65b16047d08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426150784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.3426150784
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.2523097629
Short name T368
Test name
Test status
Simulation time 14764246636 ps
CPU time 107.73 seconds
Started Jun 26 05:02:18 PM PDT 24
Finished Jun 26 05:04:06 PM PDT 24
Peak memory 1125528 kb
Host smart-bcfb0e83-9247-4d1c-b35c-ba9e0ff66a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523097629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.2523097629
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2682222268
Short name T246
Test name
Test status
Simulation time 495376008 ps
CPU time 5.86 seconds
Started Jun 26 05:02:31 PM PDT 24
Finished Jun 26 05:02:39 PM PDT 24
Peak memory 204876 kb
Host smart-844d428d-aeb7-47b1-bd08-d9f24924b5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682222268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2682222268
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1628992009
Short name T1316
Test name
Test status
Simulation time 7191201881 ps
CPU time 39.03 seconds
Started Jun 26 05:02:33 PM PDT 24
Finished Jun 26 05:03:13 PM PDT 24
Peak memory 422772 kb
Host smart-932f4302-985c-4234-bfe3-fa4fc1f40ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628992009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1628992009
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.2618176279
Short name T230
Test name
Test status
Simulation time 33233723 ps
CPU time 0.66 seconds
Started Jun 26 05:02:18 PM PDT 24
Finished Jun 26 05:02:20 PM PDT 24
Peak memory 204484 kb
Host smart-365768cc-9c96-4624-be1d-5a2cd61c5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618176279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.2618176279
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2476266791
Short name T1114
Test name
Test status
Simulation time 2599430045 ps
CPU time 45.93 seconds
Started Jun 26 05:02:19 PM PDT 24
Finished Jun 26 05:03:06 PM PDT 24
Peak memory 610068 kb
Host smart-cb13dea4-ab9c-4ba4-b139-0609fabbf212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476266791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2476266791
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.3779021517
Short name T954
Test name
Test status
Simulation time 233578135 ps
CPU time 1.74 seconds
Started Jun 26 05:02:25 PM PDT 24
Finished Jun 26 05:02:29 PM PDT 24
Peak memory 216688 kb
Host smart-22a0f1b3-1189-4ea8-bc99-1524008c8905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779021517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.3779021517
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.4104982961
Short name T549
Test name
Test status
Simulation time 2514148987 ps
CPU time 21.42 seconds
Started Jun 26 05:02:13 PM PDT 24
Finished Jun 26 05:02:36 PM PDT 24
Peak memory 316948 kb
Host smart-b52f32a7-b25a-4ee1-80e2-bf0c7034f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104982961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.4104982961
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1804047530
Short name T285
Test name
Test status
Simulation time 2245509732 ps
CPU time 10.6 seconds
Started Jun 26 05:02:27 PM PDT 24
Finished Jun 26 05:02:39 PM PDT 24
Peak memory 213136 kb
Host smart-9b3968b1-51fa-4317-b8a3-a5f6d65d5f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804047530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1804047530
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.3382874416
Short name T510
Test name
Test status
Simulation time 3834682749 ps
CPU time 4.18 seconds
Started Jun 26 05:02:36 PM PDT 24
Finished Jun 26 05:02:41 PM PDT 24
Peak memory 213176 kb
Host smart-484b00d1-545f-4c1c-a48d-e358e9ce65e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382874416 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.3382874416
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3123044878
Short name T700
Test name
Test status
Simulation time 148740821 ps
CPU time 1.11 seconds
Started Jun 26 05:02:33 PM PDT 24
Finished Jun 26 05:02:36 PM PDT 24
Peak memory 204788 kb
Host smart-35f3ab58-d230-4d65-92d3-f7315c2a94c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123044878 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3123044878
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2567603874
Short name T414
Test name
Test status
Simulation time 119963642 ps
CPU time 0.88 seconds
Started Jun 26 05:02:31 PM PDT 24
Finished Jun 26 05:02:33 PM PDT 24
Peak memory 204552 kb
Host smart-9a632eeb-1780-4964-bd3c-fb7dcd30df1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567603874 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2567603874
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.1141264547
Short name T891
Test name
Test status
Simulation time 1881073964 ps
CPU time 2.58 seconds
Started Jun 26 05:02:47 PM PDT 24
Finished Jun 26 05:02:50 PM PDT 24
Peak memory 204796 kb
Host smart-363fe08f-959a-453c-a7a7-fd52ff16be57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141264547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.1141264547
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.1458251017
Short name T1375
Test name
Test status
Simulation time 610082762 ps
CPU time 1.35 seconds
Started Jun 26 05:02:42 PM PDT 24
Finished Jun 26 05:02:45 PM PDT 24
Peak memory 204648 kb
Host smart-8f330293-2a1f-4e3b-9d67-b5a7dd295120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458251017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.1458251017
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.1456644862
Short name T141
Test name
Test status
Simulation time 5117186460 ps
CPU time 4.34 seconds
Started Jun 26 05:02:31 PM PDT 24
Finished Jun 26 05:02:36 PM PDT 24
Peak memory 204928 kb
Host smart-0766e755-230d-4af9-84b3-10e779204d0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456644862 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.1456644862
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.3846337385
Short name T565
Test name
Test status
Simulation time 6869833006 ps
CPU time 86.48 seconds
Started Jun 26 05:02:32 PM PDT 24
Finished Jun 26 05:04:00 PM PDT 24
Peak memory 1817476 kb
Host smart-003dae20-b185-4870-8b4c-8e53d83a912f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846337385 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.3846337385
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.2793935115
Short name T823
Test name
Test status
Simulation time 2916412102 ps
CPU time 27.24 seconds
Started Jun 26 05:02:26 PM PDT 24
Finished Jun 26 05:02:55 PM PDT 24
Peak memory 204864 kb
Host smart-a9f28817-62a5-49da-9001-a31cf37cf4dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793935115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.2793935115
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3747407726
Short name T505
Test name
Test status
Simulation time 318152748 ps
CPU time 13.31 seconds
Started Jun 26 05:02:23 PM PDT 24
Finished Jun 26 05:02:38 PM PDT 24
Peak memory 204816 kb
Host smart-7c71abda-7ea8-4ab0-af39-d2957630116b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747407726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3747407726
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.905875614
Short name T619
Test name
Test status
Simulation time 36834480009 ps
CPU time 433.81 seconds
Started Jun 26 05:02:31 PM PDT 24
Finished Jun 26 05:09:46 PM PDT 24
Peak memory 4297968 kb
Host smart-cdc63c30-35d6-4762-9f40-5b4643ad26c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905875614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.905875614
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2137284391
Short name T121
Test name
Test status
Simulation time 22039085251 ps
CPU time 929.59 seconds
Started Jun 26 05:02:25 PM PDT 24
Finished Jun 26 05:17:57 PM PDT 24
Peak memory 5266432 kb
Host smart-b3aad94b-44e4-444a-8c2a-3c4e18ac30aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137284391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2137284391
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1803637636
Short name T1038
Test name
Test status
Simulation time 2901038510 ps
CPU time 7.49 seconds
Started Jun 26 05:02:37 PM PDT 24
Finished Jun 26 05:02:46 PM PDT 24
Peak memory 213136 kb
Host smart-7e2ddb4b-dd83-4ba2-b1e7-0c9ce0d5667d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803637636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1803637636
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.4024081985
Short name T942
Test name
Test status
Simulation time 125238605 ps
CPU time 0.65 seconds
Started Jun 26 05:03:03 PM PDT 24
Finished Jun 26 05:03:05 PM PDT 24
Peak memory 204716 kb
Host smart-2b75565c-b31f-4375-b9bc-b43ab0a0d627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024081985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.4024081985
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.59270026
Short name T1
Test name
Test status
Simulation time 1192603388 ps
CPU time 2.34 seconds
Started Jun 26 05:02:44 PM PDT 24
Finished Jun 26 05:02:48 PM PDT 24
Peak memory 214212 kb
Host smart-aabc5257-de6d-44b0-a593-a11c7ef3e6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59270026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.59270026
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.3181690095
Short name T1408
Test name
Test status
Simulation time 374272707 ps
CPU time 8 seconds
Started Jun 26 05:02:43 PM PDT 24
Finished Jun 26 05:02:52 PM PDT 24
Peak memory 283136 kb
Host smart-cee3eadb-b2c4-4fd6-8c25-1297cb0b0d5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181690095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.3181690095
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2588719044
Short name T1347
Test name
Test status
Simulation time 9574952750 ps
CPU time 183.54 seconds
Started Jun 26 05:02:58 PM PDT 24
Finished Jun 26 05:06:03 PM PDT 24
Peak memory 826776 kb
Host smart-8f216f75-5574-4081-bca8-7b81cf53b0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588719044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2588719044
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.3763037113
Short name T850
Test name
Test status
Simulation time 2275500855 ps
CPU time 164.56 seconds
Started Jun 26 05:02:41 PM PDT 24
Finished Jun 26 05:05:27 PM PDT 24
Peak memory 769112 kb
Host smart-debd02b3-dac0-4a79-b89f-3e6093f5c7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763037113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.3763037113
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.3359347702
Short name T1153
Test name
Test status
Simulation time 106013332 ps
CPU time 0.91 seconds
Started Jun 26 05:02:39 PM PDT 24
Finished Jun 26 05:02:41 PM PDT 24
Peak memory 204460 kb
Host smart-4c54b2ac-91aa-4f70-8c11-f7c69df4ff97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359347702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.3359347702
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.4260425714
Short name T521
Test name
Test status
Simulation time 500918823 ps
CPU time 3.87 seconds
Started Jun 26 05:02:44 PM PDT 24
Finished Jun 26 05:02:49 PM PDT 24
Peak memory 224388 kb
Host smart-bcec2be6-7bac-472f-b8d6-9e568fb0d396
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260425714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.4260425714
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.610576423
Short name T1065
Test name
Test status
Simulation time 2878242825 ps
CPU time 77.6 seconds
Started Jun 26 05:02:48 PM PDT 24
Finished Jun 26 05:04:07 PM PDT 24
Peak memory 922860 kb
Host smart-b3fb3368-cdad-4bc9-9510-f2c642657fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610576423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.610576423
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.2787687148
Short name T659
Test name
Test status
Simulation time 490553832 ps
CPU time 6.18 seconds
Started Jun 26 05:03:02 PM PDT 24
Finished Jun 26 05:03:10 PM PDT 24
Peak memory 204788 kb
Host smart-172b19bc-b743-45f3-9ce6-a27137d7cb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787687148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.2787687148
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.990313386
Short name T359
Test name
Test status
Simulation time 2615647455 ps
CPU time 20.4 seconds
Started Jun 26 05:02:58 PM PDT 24
Finished Jun 26 05:03:20 PM PDT 24
Peak memory 298000 kb
Host smart-be1c2e2a-a7ee-46a5-83d1-942897a03c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990313386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.990313386
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3591366229
Short name T442
Test name
Test status
Simulation time 26944844703 ps
CPU time 1405.65 seconds
Started Jun 26 05:02:43 PM PDT 24
Finished Jun 26 05:26:10 PM PDT 24
Peak memory 4044644 kb
Host smart-5b0b1c4d-bef5-4d23-8cb7-761eb0165c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591366229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3591366229
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.3742725936
Short name T837
Test name
Test status
Simulation time 522924108 ps
CPU time 3.25 seconds
Started Jun 26 05:02:43 PM PDT 24
Finished Jun 26 05:02:47 PM PDT 24
Peak memory 204752 kb
Host smart-d1fb935a-0522-46f5-a36a-c48e09b13346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742725936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.3742725936
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.2678216944
Short name T844
Test name
Test status
Simulation time 5027705127 ps
CPU time 17.41 seconds
Started Jun 26 05:02:37 PM PDT 24
Finished Jun 26 05:02:56 PM PDT 24
Peak memory 244840 kb
Host smart-2baeff42-c253-48e7-bfb5-84a71669148b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678216944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.2678216944
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.1222235916
Short name T563
Test name
Test status
Simulation time 155529198293 ps
CPU time 2913.71 seconds
Started Jun 26 05:02:44 PM PDT 24
Finished Jun 26 05:51:20 PM PDT 24
Peak memory 4902420 kb
Host smart-f0fd83b2-5a84-459e-9e42-2b157f04764c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222235916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.1222235916
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.4169483941
Short name T384
Test name
Test status
Simulation time 1627018516 ps
CPU time 13.86 seconds
Started Jun 26 05:02:45 PM PDT 24
Finished Jun 26 05:03:00 PM PDT 24
Peak memory 220532 kb
Host smart-a6b7d084-41df-4f94-b95e-048042f4f730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169483941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.4169483941
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1230111581
Short name T147
Test name
Test status
Simulation time 593520996 ps
CPU time 3.68 seconds
Started Jun 26 05:02:58 PM PDT 24
Finished Jun 26 05:03:03 PM PDT 24
Peak memory 204756 kb
Host smart-65c1713f-19b4-4277-bcf6-56889dad57de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230111581 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1230111581
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.408107942
Short name T1100
Test name
Test status
Simulation time 226823354 ps
CPU time 1.39 seconds
Started Jun 26 05:02:48 PM PDT 24
Finished Jun 26 05:02:51 PM PDT 24
Peak memory 213036 kb
Host smart-efc475d4-c99c-44f5-a9d0-02ebc33d19bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408107942 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_acq.408107942
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.4196993951
Short name T948
Test name
Test status
Simulation time 251040392 ps
CPU time 1.77 seconds
Started Jun 26 05:02:58 PM PDT 24
Finished Jun 26 05:03:01 PM PDT 24
Peak memory 208796 kb
Host smart-ef08736b-7c90-4e7e-a59d-d759a318f96c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196993951 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.4196993951
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.1657636585
Short name T255
Test name
Test status
Simulation time 926413437 ps
CPU time 2.46 seconds
Started Jun 26 05:03:02 PM PDT 24
Finished Jun 26 05:03:06 PM PDT 24
Peak memory 204840 kb
Host smart-f71e5a59-7d2b-4bff-9122-b0c4f5dec843
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657636585 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.1657636585
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.3439882095
Short name T1122
Test name
Test status
Simulation time 128502577 ps
CPU time 1.21 seconds
Started Jun 26 05:03:05 PM PDT 24
Finished Jun 26 05:03:07 PM PDT 24
Peak memory 204596 kb
Host smart-f156ac42-b7e6-433c-a074-0892e89406b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439882095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.3439882095
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3765867153
Short name T1110
Test name
Test status
Simulation time 427171815 ps
CPU time 3.36 seconds
Started Jun 26 05:02:59 PM PDT 24
Finished Jun 26 05:03:03 PM PDT 24
Peak memory 204856 kb
Host smart-2f96405f-5b97-405f-84c9-d93820637149
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765867153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3765867153
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.223186700
Short name T1013
Test name
Test status
Simulation time 3689281982 ps
CPU time 3.99 seconds
Started Jun 26 05:02:51 PM PDT 24
Finished Jun 26 05:02:56 PM PDT 24
Peak memory 213144 kb
Host smart-15b52e27-f2ce-4673-b776-58337c79ab82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223186700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_intr_smoke.223186700
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.3642969533
Short name T1459
Test name
Test status
Simulation time 25238923309 ps
CPU time 169.55 seconds
Started Jun 26 05:02:53 PM PDT 24
Finished Jun 26 05:05:44 PM PDT 24
Peak memory 2874452 kb
Host smart-c82f1bc6-2221-4afa-b5e7-5fef101ae99c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642969533 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.3642969533
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.2917402855
Short name T760
Test name
Test status
Simulation time 3368994679 ps
CPU time 15.09 seconds
Started Jun 26 05:02:58 PM PDT 24
Finished Jun 26 05:03:15 PM PDT 24
Peak memory 204944 kb
Host smart-91280a49-e6e6-41a8-a973-118f9f46e37f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917402855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.2917402855
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.388962861
Short name T972
Test name
Test status
Simulation time 5215659503 ps
CPU time 24.73 seconds
Started Jun 26 05:02:50 PM PDT 24
Finished Jun 26 05:03:16 PM PDT 24
Peak memory 227480 kb
Host smart-b0f5cb17-f3f6-4033-b725-c1f9f26af0f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388962861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.388962861
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.1987787916
Short name T664
Test name
Test status
Simulation time 71283070164 ps
CPU time 3201.85 seconds
Started Jun 26 05:02:43 PM PDT 24
Finished Jun 26 05:56:07 PM PDT 24
Peak memory 13099224 kb
Host smart-a322fc9c-b002-4fe6-9b8a-862559c7c0aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987787916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_wr.1987787916
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1854033362
Short name T949
Test name
Test status
Simulation time 38566180103 ps
CPU time 817.72 seconds
Started Jun 26 05:02:50 PM PDT 24
Finished Jun 26 05:16:29 PM PDT 24
Peak memory 4474516 kb
Host smart-5fa5a2c0-c669-4be5-b67e-eb5184ce64ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854033362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1854033362
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.3620605484
Short name T315
Test name
Test status
Simulation time 2302410377 ps
CPU time 7.3 seconds
Started Jun 26 05:02:50 PM PDT 24
Finished Jun 26 05:02:58 PM PDT 24
Peak memory 213144 kb
Host smart-70924fb5-3317-4b96-924a-6aea39e8c0b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620605484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.3620605484
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.3788848148
Short name T1267
Test name
Test status
Simulation time 36087049 ps
CPU time 0.62 seconds
Started Jun 26 05:03:35 PM PDT 24
Finished Jun 26 05:03:37 PM PDT 24
Peak memory 204464 kb
Host smart-6a7175fe-51ff-40ed-ae67-fe0a7e4db442
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788848148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.3788848148
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1377869082
Short name T600
Test name
Test status
Simulation time 1449954496 ps
CPU time 3.36 seconds
Started Jun 26 05:03:09 PM PDT 24
Finished Jun 26 05:03:13 PM PDT 24
Peak memory 213060 kb
Host smart-166182e7-c92c-448d-ac64-247325b8833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377869082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1377869082
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.2893474754
Short name T314
Test name
Test status
Simulation time 537160476 ps
CPU time 11.87 seconds
Started Jun 26 05:03:10 PM PDT 24
Finished Jun 26 05:03:22 PM PDT 24
Peak memory 312728 kb
Host smart-851f808d-3476-4f3a-acfc-a47733501325
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893474754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.2893474754
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.1776123995
Short name T820
Test name
Test status
Simulation time 9330648826 ps
CPU time 160.16 seconds
Started Jun 26 05:03:07 PM PDT 24
Finished Jun 26 05:05:48 PM PDT 24
Peak memory 763372 kb
Host smart-3cc1a4f4-ba7d-404f-9141-a7be01e494ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776123995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.1776123995
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.2903641706
Short name T337
Test name
Test status
Simulation time 3545004742 ps
CPU time 55.02 seconds
Started Jun 26 05:03:07 PM PDT 24
Finished Jun 26 05:04:03 PM PDT 24
Peak memory 599724 kb
Host smart-7852c8ed-2038-4eb5-84ab-0e783ed6e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903641706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.2903641706
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2141533166
Short name T222
Test name
Test status
Simulation time 83147057 ps
CPU time 0.89 seconds
Started Jun 26 05:03:08 PM PDT 24
Finished Jun 26 05:03:09 PM PDT 24
Peak memory 204560 kb
Host smart-955e8116-847c-484b-a4b4-0cacf124dcd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141533166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2141533166
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.2464937656
Short name T674
Test name
Test status
Simulation time 488982270 ps
CPU time 2.82 seconds
Started Jun 26 05:03:08 PM PDT 24
Finished Jun 26 05:03:11 PM PDT 24
Peak memory 204860 kb
Host smart-392226cb-ec49-46a2-94a4-b02336fbd4a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464937656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.2464937656
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3617222576
Short name T1208
Test name
Test status
Simulation time 4626623794 ps
CPU time 324.17 seconds
Started Jun 26 05:03:02 PM PDT 24
Finished Jun 26 05:08:28 PM PDT 24
Peak memory 1314020 kb
Host smart-8b82d16b-8016-4bfe-bd86-b0df56895c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617222576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3617222576
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3099723168
Short name T1209
Test name
Test status
Simulation time 929111432 ps
CPU time 17.41 seconds
Started Jun 26 05:03:36 PM PDT 24
Finished Jun 26 05:03:54 PM PDT 24
Peak memory 204840 kb
Host smart-01ae1d1e-183e-4d71-95f6-56ebfe7763f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099723168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3099723168
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.4237310352
Short name T1048
Test name
Test status
Simulation time 1749425004 ps
CPU time 24.91 seconds
Started Jun 26 05:03:34 PM PDT 24
Finished Jun 26 05:04:00 PM PDT 24
Peak memory 302224 kb
Host smart-5fa0f2b4-56ad-457c-8685-30a21a64fdd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237310352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.4237310352
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.1279023434
Short name T1112
Test name
Test status
Simulation time 14943567 ps
CPU time 0.68 seconds
Started Jun 26 05:03:02 PM PDT 24
Finished Jun 26 05:03:03 PM PDT 24
Peak memory 204480 kb
Host smart-db381208-17cb-40d0-a865-882f4aa891f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279023434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.1279023434
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.1470543663
Short name T878
Test name
Test status
Simulation time 13179356883 ps
CPU time 106.91 seconds
Started Jun 26 05:03:09 PM PDT 24
Finished Jun 26 05:04:56 PM PDT 24
Peak memory 725624 kb
Host smart-7890049b-9312-4a91-b705-3b82a4b60410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470543663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.1470543663
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.3394928861
Short name T1234
Test name
Test status
Simulation time 121530081 ps
CPU time 1.19 seconds
Started Jun 26 05:03:08 PM PDT 24
Finished Jun 26 05:03:10 PM PDT 24
Peak memory 222008 kb
Host smart-000a5f67-7b6b-4f02-b749-b26f19169d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394928861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.3394928861
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.368831396
Short name T736
Test name
Test status
Simulation time 2339658014 ps
CPU time 58.69 seconds
Started Jun 26 05:03:03 PM PDT 24
Finished Jun 26 05:04:03 PM PDT 24
Peak memory 328652 kb
Host smart-85f0c314-9466-4891-9f99-9d11c45d0d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368831396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.368831396
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1249408259
Short name T667
Test name
Test status
Simulation time 393318420 ps
CPU time 18.44 seconds
Started Jun 26 05:03:10 PM PDT 24
Finished Jun 26 05:03:29 PM PDT 24
Peak memory 213080 kb
Host smart-213ac54d-b699-45b1-af0f-5fb80bb266f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249408259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1249408259
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2632071478
Short name T323
Test name
Test status
Simulation time 477195650 ps
CPU time 2.53 seconds
Started Jun 26 05:03:29 PM PDT 24
Finished Jun 26 05:03:32 PM PDT 24
Peak memory 204836 kb
Host smart-601b651b-b018-45b5-b5d2-797ce3f705c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632071478 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2632071478
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.930597498
Short name T1305
Test name
Test status
Simulation time 146442016 ps
CPU time 0.86 seconds
Started Jun 26 05:03:23 PM PDT 24
Finished Jun 26 05:03:24 PM PDT 24
Peak memory 204548 kb
Host smart-6bdc92bb-aec5-4f4e-802f-a561c593af62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930597498 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.930597498
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.58893054
Short name T1066
Test name
Test status
Simulation time 196433374 ps
CPU time 1.13 seconds
Started Jun 26 05:03:22 PM PDT 24
Finished Jun 26 05:03:24 PM PDT 24
Peak memory 204560 kb
Host smart-509bfff2-a04d-493b-9887-c9df9151f38d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58893054 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.i2c_target_fifo_reset_tx.58893054
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.4017352390
Short name T911
Test name
Test status
Simulation time 1563446441 ps
CPU time 2.15 seconds
Started Jun 26 05:03:38 PM PDT 24
Finished Jun 26 05:03:41 PM PDT 24
Peak memory 204828 kb
Host smart-41318642-c3a0-43e2-8dae-d2dbc3854542
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017352390 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.4017352390
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.686251062
Short name T1327
Test name
Test status
Simulation time 251895332 ps
CPU time 1.16 seconds
Started Jun 26 05:03:34 PM PDT 24
Finished Jun 26 05:03:36 PM PDT 24
Peak memory 204628 kb
Host smart-82123059-7a8c-40c9-ac86-508d0fb7e301
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686251062 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.686251062
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.2066857407
Short name T389
Test name
Test status
Simulation time 1383080961 ps
CPU time 2.52 seconds
Started Jun 26 05:03:30 PM PDT 24
Finished Jun 26 05:03:33 PM PDT 24
Peak memory 204828 kb
Host smart-1ff32fee-57af-4b0f-95ce-ecd08f8cf895
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066857407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.2066857407
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3052608854
Short name T512
Test name
Test status
Simulation time 4032561932 ps
CPU time 6 seconds
Started Jun 26 05:03:16 PM PDT 24
Finished Jun 26 05:03:23 PM PDT 24
Peak memory 213220 kb
Host smart-fb82a1d7-ae33-4cae-85cc-5efd3506536c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052608854 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3052608854
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.3822342439
Short name T901
Test name
Test status
Simulation time 7981125818 ps
CPU time 96.38 seconds
Started Jun 26 05:03:15 PM PDT 24
Finished Jun 26 05:04:52 PM PDT 24
Peak memory 2041408 kb
Host smart-f036d94a-f15c-49b6-ac5d-a7f74d8fc9b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822342439 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.3822342439
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.3043560272
Short name T632
Test name
Test status
Simulation time 700182979 ps
CPU time 9.12 seconds
Started Jun 26 05:03:16 PM PDT 24
Finished Jun 26 05:03:27 PM PDT 24
Peak memory 204736 kb
Host smart-8840fa5f-bb79-4e6f-9f7c-1112da0576ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043560272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.3043560272
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3454242944
Short name T1354
Test name
Test status
Simulation time 449742824 ps
CPU time 8.48 seconds
Started Jun 26 05:03:15 PM PDT 24
Finished Jun 26 05:03:25 PM PDT 24
Peak memory 204816 kb
Host smart-3d746a83-b4c3-4c29-bf70-c5ca315f7e0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454242944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3454242944
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.2556542706
Short name T858
Test name
Test status
Simulation time 55378325120 ps
CPU time 189.4 seconds
Started Jun 26 05:03:17 PM PDT 24
Finished Jun 26 05:06:27 PM PDT 24
Peak memory 2379572 kb
Host smart-261aca20-b771-42ac-b59a-a04f17b887a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556542706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.2556542706
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1681346467
Short name T641
Test name
Test status
Simulation time 8480807936 ps
CPU time 31.4 seconds
Started Jun 26 05:03:15 PM PDT 24
Finished Jun 26 05:03:48 PM PDT 24
Peak memory 483796 kb
Host smart-a0d8c153-d37e-43bf-b017-fa9db8fc4163
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681346467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1681346467
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2732842446
Short name T1324
Test name
Test status
Simulation time 1903299390 ps
CPU time 6.83 seconds
Started Jun 26 05:03:22 PM PDT 24
Finished Jun 26 05:03:29 PM PDT 24
Peak memory 204820 kb
Host smart-d6375887-3acd-4ea9-8028-770822df489a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732842446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2732842446
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.537941598
Short name T1179
Test name
Test status
Simulation time 24059513 ps
CPU time 0.66 seconds
Started Jun 26 05:04:16 PM PDT 24
Finished Jun 26 05:04:18 PM PDT 24
Peak memory 204456 kb
Host smart-ddd8bbbb-0839-484b-b119-80b4143e8668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537941598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.537941598
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.1941778811
Short name T1198
Test name
Test status
Simulation time 391416406 ps
CPU time 2.55 seconds
Started Jun 26 05:03:46 PM PDT 24
Finished Jun 26 05:03:50 PM PDT 24
Peak memory 213068 kb
Host smart-fd1b08d7-e91e-4f99-b685-cf60c4bda9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941778811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.1941778811
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.714910319
Short name T295
Test name
Test status
Simulation time 578166597 ps
CPU time 15.44 seconds
Started Jun 26 05:03:44 PM PDT 24
Finished Jun 26 05:04:01 PM PDT 24
Peak memory 265596 kb
Host smart-cf9da55c-444e-4cc2-a4e1-e02c3fd11068
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714910319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_empt
y.714910319
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.1235691800
Short name T78
Test name
Test status
Simulation time 9451251020 ps
CPU time 188.59 seconds
Started Jun 26 05:03:43 PM PDT 24
Finished Jun 26 05:06:52 PM PDT 24
Peak memory 863932 kb
Host smart-f1b1af70-7051-492a-a257-c5030659878b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235691800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.1235691800
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.4168443514
Short name T466
Test name
Test status
Simulation time 14176129947 ps
CPU time 94.39 seconds
Started Jun 26 05:03:43 PM PDT 24
Finished Jun 26 05:05:19 PM PDT 24
Peak memory 872972 kb
Host smart-144d2f0e-7728-4cd0-8f80-71aef57f6fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168443514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.4168443514
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2008815071
Short name T1214
Test name
Test status
Simulation time 237306106 ps
CPU time 1.07 seconds
Started Jun 26 05:03:42 PM PDT 24
Finished Jun 26 05:03:44 PM PDT 24
Peak memory 204440 kb
Host smart-0a7c0270-872a-430f-afe1-5c7a3872cb35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008815071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2008815071
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.1554959982
Short name T397
Test name
Test status
Simulation time 199390803 ps
CPU time 4.18 seconds
Started Jun 26 05:03:41 PM PDT 24
Finished Jun 26 05:03:46 PM PDT 24
Peak memory 204744 kb
Host smart-ce864f0d-a7f9-4438-8a83-e39ebd0d0b2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554959982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.1554959982
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2967030877
Short name T415
Test name
Test status
Simulation time 4718578998 ps
CPU time 143.32 seconds
Started Jun 26 05:03:43 PM PDT 24
Finished Jun 26 05:06:07 PM PDT 24
Peak memory 1380272 kb
Host smart-3da31020-9f74-4e25-9ec4-69f49eba9b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967030877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2967030877
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2901112057
Short name T1119
Test name
Test status
Simulation time 427850678 ps
CPU time 5.99 seconds
Started Jun 26 05:04:11 PM PDT 24
Finished Jun 26 05:04:18 PM PDT 24
Peak memory 204792 kb
Host smart-6b700c83-efda-49ef-9881-247c2b4f8cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901112057 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2901112057
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.3336922699
Short name T1279
Test name
Test status
Simulation time 4467643844 ps
CPU time 16.54 seconds
Started Jun 26 05:04:13 PM PDT 24
Finished Jun 26 05:04:31 PM PDT 24
Peak memory 311284 kb
Host smart-a5528ca9-66e6-46a4-a67f-f9fcace7008d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336922699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.3336922699
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.858139709
Short name T869
Test name
Test status
Simulation time 56004085 ps
CPU time 0.66 seconds
Started Jun 26 05:03:36 PM PDT 24
Finished Jun 26 05:03:37 PM PDT 24
Peak memory 204560 kb
Host smart-30718af5-9049-4788-a778-b14cc722519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858139709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.858139709
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.2423249069
Short name T372
Test name
Test status
Simulation time 369126995 ps
CPU time 15.15 seconds
Started Jun 26 05:03:49 PM PDT 24
Finished Jun 26 05:04:05 PM PDT 24
Peak memory 229316 kb
Host smart-439e1fb0-37d8-400e-8522-49705b376557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423249069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.2423249069
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.864695733
Short name T1124
Test name
Test status
Simulation time 2388998587 ps
CPU time 62.45 seconds
Started Jun 26 05:03:47 PM PDT 24
Finished Jun 26 05:04:51 PM PDT 24
Peak memory 204924 kb
Host smart-9a101dac-abc5-4a0a-a731-32aaa9a96b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864695733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.864695733
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1979855811
Short name T1166
Test name
Test status
Simulation time 5156434952 ps
CPU time 56.64 seconds
Started Jun 26 05:03:37 PM PDT 24
Finished Jun 26 05:04:35 PM PDT 24
Peak memory 279572 kb
Host smart-8e9dfa3b-c4ee-4d07-abb1-de8a8075ba43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979855811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1979855811
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.1088156479
Short name T104
Test name
Test status
Simulation time 22673991191 ps
CPU time 400.89 seconds
Started Jun 26 05:03:53 PM PDT 24
Finished Jun 26 05:10:35 PM PDT 24
Peak memory 2416132 kb
Host smart-3c142c71-2ea6-4eec-8035-2ff0bee40c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088156479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.1088156479
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.759806590
Short name T884
Test name
Test status
Simulation time 1046470310 ps
CPU time 20.31 seconds
Started Jun 26 05:03:48 PM PDT 24
Finished Jun 26 05:04:09 PM PDT 24
Peak memory 221272 kb
Host smart-634eed4c-f413-4556-93a2-67fce6652ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759806590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.759806590
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.1264312969
Short name T1417
Test name
Test status
Simulation time 1057995982 ps
CPU time 3.08 seconds
Started Jun 26 05:04:11 PM PDT 24
Finished Jun 26 05:04:15 PM PDT 24
Peak memory 205024 kb
Host smart-2be54c2e-ea25-47fd-a6fc-2817ffafdf68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264312969 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.1264312969
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.684139014
Short name T766
Test name
Test status
Simulation time 608644770 ps
CPU time 1.36 seconds
Started Jun 26 05:04:12 PM PDT 24
Finished Jun 26 05:04:14 PM PDT 24
Peak memory 204716 kb
Host smart-28517585-8088-42dd-ba23-c91443a4c62d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684139014 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_acq.684139014
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1600161797
Short name T813
Test name
Test status
Simulation time 297024372 ps
CPU time 1.86 seconds
Started Jun 26 05:04:12 PM PDT 24
Finished Jun 26 05:04:14 PM PDT 24
Peak memory 210576 kb
Host smart-8fc1d76e-e582-449f-80e6-2999189998fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600161797 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1600161797
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.2961010607
Short name T1356
Test name
Test status
Simulation time 411742130 ps
CPU time 1.44 seconds
Started Jun 26 05:04:10 PM PDT 24
Finished Jun 26 05:04:13 PM PDT 24
Peak memory 204544 kb
Host smart-42c0de58-5013-468a-aaf0-94fb67162a51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961010607 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.2961010607
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.637824912
Short name T567
Test name
Test status
Simulation time 135217706 ps
CPU time 1.22 seconds
Started Jun 26 05:04:16 PM PDT 24
Finished Jun 26 05:04:19 PM PDT 24
Peak memory 204632 kb
Host smart-f4b6d88a-a0e4-4a6c-9cf1-7eb7ec7311ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637824912 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.637824912
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.3542711785
Short name T297
Test name
Test status
Simulation time 1030721011 ps
CPU time 5.49 seconds
Started Jun 26 05:03:59 PM PDT 24
Finished Jun 26 05:04:06 PM PDT 24
Peak memory 215040 kb
Host smart-7530720f-aad9-4f89-a774-59c584fdf644
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542711785 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.3542711785
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.3294206789
Short name T330
Test name
Test status
Simulation time 5620769681 ps
CPU time 15.1 seconds
Started Jun 26 05:03:58 PM PDT 24
Finished Jun 26 05:04:14 PM PDT 24
Peak memory 625192 kb
Host smart-668a3667-5e91-493d-a3b2-e4dce30a6b40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294206789 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.3294206789
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3812866384
Short name T1250
Test name
Test status
Simulation time 734872431 ps
CPU time 10.05 seconds
Started Jun 26 05:03:54 PM PDT 24
Finished Jun 26 05:04:05 PM PDT 24
Peak memory 204800 kb
Host smart-72956966-7af8-400b-8ad0-96c4b09e874a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812866384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3812866384
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.641100412
Short name T380
Test name
Test status
Simulation time 4464169223 ps
CPU time 50.73 seconds
Started Jun 26 05:04:00 PM PDT 24
Finished Jun 26 05:04:52 PM PDT 24
Peak memory 206304 kb
Host smart-ad09cb20-e3b6-4c82-ba65-faf65f6fbd3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641100412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.641100412
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.1149253484
Short name T1199
Test name
Test status
Simulation time 15165566052 ps
CPU time 15.78 seconds
Started Jun 26 05:03:55 PM PDT 24
Finished Jun 26 05:04:12 PM PDT 24
Peak memory 204960 kb
Host smart-d942e71a-0c4d-4437-91af-3bf5b709a75e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149253484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.1149253484
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1598183496
Short name T476
Test name
Test status
Simulation time 43654904526 ps
CPU time 2228.59 seconds
Started Jun 26 05:03:59 PM PDT 24
Finished Jun 26 05:41:09 PM PDT 24
Peak memory 4571960 kb
Host smart-d024881f-3ece-40dc-ae3e-b4121043401f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598183496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1598183496
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1088872065
Short name T982
Test name
Test status
Simulation time 1134239168 ps
CPU time 5.88 seconds
Started Jun 26 05:04:09 PM PDT 24
Finished Jun 26 05:04:16 PM PDT 24
Peak memory 212976 kb
Host smart-3536d08d-2e00-4014-8f00-c2aff6d4b557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088872065 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1088872065
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.730706725
Short name T340
Test name
Test status
Simulation time 29747546 ps
CPU time 0.65 seconds
Started Jun 26 05:05:01 PM PDT 24
Finished Jun 26 05:05:03 PM PDT 24
Peak memory 204428 kb
Host smart-cee8466e-afaa-451d-91e5-d8284f415f3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730706725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.730706725
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.997202191
Short name T598
Test name
Test status
Simulation time 369866331 ps
CPU time 7.08 seconds
Started Jun 26 05:04:34 PM PDT 24
Finished Jun 26 05:04:42 PM PDT 24
Peak memory 258148 kb
Host smart-81f023f2-e5aa-442e-8e45-c2b89b24f50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997202191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.997202191
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2916960285
Short name T1254
Test name
Test status
Simulation time 1411348019 ps
CPU time 6.68 seconds
Started Jun 26 05:04:23 PM PDT 24
Finished Jun 26 05:04:30 PM PDT 24
Peak memory 280252 kb
Host smart-5ae3f408-5730-4049-b1b7-69c56d825e21
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916960285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2916960285
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.2881643894
Short name T855
Test name
Test status
Simulation time 15626897968 ps
CPU time 69.52 seconds
Started Jun 26 05:04:30 PM PDT 24
Finished Jun 26 05:05:41 PM PDT 24
Peak memory 714764 kb
Host smart-ecdc5a10-4bcd-47c9-bc1f-5a230f04c817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881643894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.2881643894
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.2671342223
Short name T1018
Test name
Test status
Simulation time 1694210044 ps
CPU time 56.18 seconds
Started Jun 26 05:04:23 PM PDT 24
Finished Jun 26 05:05:20 PM PDT 24
Peak memory 623888 kb
Host smart-9a087bcd-6948-41e5-9a54-2e8f019db54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671342223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.2671342223
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3645702513
Short name T412
Test name
Test status
Simulation time 91425024 ps
CPU time 0.89 seconds
Started Jun 26 05:04:24 PM PDT 24
Finished Jun 26 05:04:26 PM PDT 24
Peak memory 204524 kb
Host smart-547ad450-8bb2-4137-b920-76f231828170
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645702513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3645702513
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3231892400
Short name T803
Test name
Test status
Simulation time 848353366 ps
CPU time 6.5 seconds
Started Jun 26 05:04:28 PM PDT 24
Finished Jun 26 05:04:36 PM PDT 24
Peak memory 254048 kb
Host smart-688cbff3-857e-42ae-969b-873da7dffb2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231892400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3231892400
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.453318624
Short name T275
Test name
Test status
Simulation time 6786763702 ps
CPU time 83.19 seconds
Started Jun 26 05:04:18 PM PDT 24
Finished Jun 26 05:05:42 PM PDT 24
Peak memory 959052 kb
Host smart-756b270a-dd7d-497e-bab6-1081fefac032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453318624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.453318624
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.187946526
Short name T957
Test name
Test status
Simulation time 2054719525 ps
CPU time 6.72 seconds
Started Jun 26 05:04:54 PM PDT 24
Finished Jun 26 05:05:02 PM PDT 24
Peak memory 204836 kb
Host smart-d77a5afd-d5b9-4c59-85bc-77485cc2ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187946526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.187946526
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2136552749
Short name T1341
Test name
Test status
Simulation time 7088355138 ps
CPU time 51.51 seconds
Started Jun 26 05:04:55 PM PDT 24
Finished Jun 26 05:05:48 PM PDT 24
Peak memory 269928 kb
Host smart-58e8ea58-9adf-47bd-b695-3587d3f4cd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136552749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2136552749
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.3797806884
Short name T2
Test name
Test status
Simulation time 48581939 ps
CPU time 0.66 seconds
Started Jun 26 05:04:17 PM PDT 24
Finished Jun 26 05:04:19 PM PDT 24
Peak memory 204560 kb
Host smart-80a82a7e-fe06-4492-9f0f-517662f8b59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797806884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.3797806884
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.1855672603
Short name T611
Test name
Test status
Simulation time 965719036 ps
CPU time 11.62 seconds
Started Jun 26 05:04:30 PM PDT 24
Finished Jun 26 05:04:42 PM PDT 24
Peak memory 254984 kb
Host smart-634795cb-96d3-4037-a0a6-739993838235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855672603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.1855672603
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.3069003594
Short name T817
Test name
Test status
Simulation time 5742699367 ps
CPU time 57.44 seconds
Started Jun 26 05:04:32 PM PDT 24
Finished Jun 26 05:05:30 PM PDT 24
Peak memory 213048 kb
Host smart-6a87e6e4-c620-4936-a624-f7d9ce793a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069003594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.3069003594
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.380187944
Short name T1365
Test name
Test status
Simulation time 3289821911 ps
CPU time 79.27 seconds
Started Jun 26 05:04:16 PM PDT 24
Finished Jun 26 05:05:37 PM PDT 24
Peak memory 343552 kb
Host smart-2e2a3c94-a274-4fa9-835b-d42df8bfbc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380187944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.380187944
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.3213061372
Short name T1397
Test name
Test status
Simulation time 26138639441 ps
CPU time 187.25 seconds
Started Jun 26 05:04:39 PM PDT 24
Finished Jun 26 05:07:47 PM PDT 24
Peak memory 1297788 kb
Host smart-7f14efe3-ee64-463e-a8db-35ecfacdf48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213061372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3213061372
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.1972887070
Short name T925
Test name
Test status
Simulation time 1389144613 ps
CPU time 16.18 seconds
Started Jun 26 05:04:39 PM PDT 24
Finished Jun 26 05:04:56 PM PDT 24
Peak memory 213032 kb
Host smart-f2816796-2832-4394-b428-13bfbca3bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972887070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1972887070
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1073258617
Short name T1421
Test name
Test status
Simulation time 746812670 ps
CPU time 3.74 seconds
Started Jun 26 05:04:59 PM PDT 24
Finished Jun 26 05:05:03 PM PDT 24
Peak memory 204740 kb
Host smart-1399d666-9007-4ace-8891-09909e170f5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073258617 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1073258617
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2168400433
Short name T1252
Test name
Test status
Simulation time 1007000984 ps
CPU time 1.25 seconds
Started Jun 26 05:04:53 PM PDT 24
Finished Jun 26 05:04:55 PM PDT 24
Peak memory 204804 kb
Host smart-ecc0a454-8480-4673-b447-9d6d77f6e68f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168400433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2168400433
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2254748150
Short name T959
Test name
Test status
Simulation time 141807074 ps
CPU time 0.83 seconds
Started Jun 26 05:04:51 PM PDT 24
Finished Jun 26 05:04:53 PM PDT 24
Peak memory 204624 kb
Host smart-a794bbc8-d413-4d87-bcc1-dd05be52be91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254748150 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2254748150
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.3461289008
Short name T946
Test name
Test status
Simulation time 577014129 ps
CPU time 2.87 seconds
Started Jun 26 05:04:58 PM PDT 24
Finished Jun 26 05:05:02 PM PDT 24
Peak memory 204764 kb
Host smart-96f49293-b158-445f-88ff-6110253d4a32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461289008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.3461289008
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.2173609722
Short name T912
Test name
Test status
Simulation time 180882090 ps
CPU time 1.01 seconds
Started Jun 26 05:04:55 PM PDT 24
Finished Jun 26 05:04:57 PM PDT 24
Peak memory 204592 kb
Host smart-31060694-ce86-4a66-a4b6-7ddb70f41ae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173609722 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.2173609722
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1504633341
Short name T652
Test name
Test status
Simulation time 595018192 ps
CPU time 2.39 seconds
Started Jun 26 05:04:53 PM PDT 24
Finished Jun 26 05:04:56 PM PDT 24
Peak memory 204832 kb
Host smart-a59b47fb-a363-41d9-b663-7f5b0def5463
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504633341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1504633341
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2124071149
Short name T1358
Test name
Test status
Simulation time 670857527 ps
CPU time 3.96 seconds
Started Jun 26 05:04:42 PM PDT 24
Finished Jun 26 05:04:47 PM PDT 24
Peak memory 204824 kb
Host smart-87bc0d9f-50a6-4588-b408-7262f32d58b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124071149 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2124071149
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2175766693
Short name T1024
Test name
Test status
Simulation time 14262433063 ps
CPU time 31.52 seconds
Started Jun 26 05:04:42 PM PDT 24
Finished Jun 26 05:05:15 PM PDT 24
Peak memory 835732 kb
Host smart-1687795d-02db-45d2-956f-99ebe15079e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175766693 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2175766693
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.1652323586
Short name T1019
Test name
Test status
Simulation time 4162293052 ps
CPU time 16.43 seconds
Started Jun 26 05:04:37 PM PDT 24
Finished Jun 26 05:04:54 PM PDT 24
Peak memory 204904 kb
Host smart-a0d641df-755d-41ac-bde3-8a6b86caa76f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652323586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.1652323586
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.933586507
Short name T1237
Test name
Test status
Simulation time 5087856779 ps
CPU time 50.64 seconds
Started Jun 26 05:04:40 PM PDT 24
Finished Jun 26 05:05:31 PM PDT 24
Peak memory 206096 kb
Host smart-abba60ea-1698-442d-897b-c5450c29e21b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933586507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c
_target_stress_rd.933586507
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2314568296
Short name T192
Test name
Test status
Simulation time 39434565768 ps
CPU time 208 seconds
Started Jun 26 05:04:35 PM PDT 24
Finished Jun 26 05:08:04 PM PDT 24
Peak memory 2554368 kb
Host smart-7565355f-654b-4fa5-b653-0eaeda9ccb1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314568296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2314568296
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1528249247
Short name T361
Test name
Test status
Simulation time 13275610934 ps
CPU time 62.06 seconds
Started Jun 26 05:04:43 PM PDT 24
Finished Jun 26 05:05:46 PM PDT 24
Peak memory 757484 kb
Host smart-07a34240-b330-43d7-8d18-7bdab68a1ea5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528249247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1528249247
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.2534331364
Short name T1300
Test name
Test status
Simulation time 1345774645 ps
CPU time 7.15 seconds
Started Jun 26 05:04:42 PM PDT 24
Finished Jun 26 05:04:50 PM PDT 24
Peak memory 204836 kb
Host smart-c717c568-cfbb-4af2-91ef-3fd1d721f952
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534331364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.2534331364
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.3991708451
Short name T483
Test name
Test status
Simulation time 18474794 ps
CPU time 0.64 seconds
Started Jun 26 05:05:47 PM PDT 24
Finished Jun 26 05:05:49 PM PDT 24
Peak memory 204424 kb
Host smart-f0a58228-a1be-4b3d-ae64-3921d2d9da2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991708451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.3991708451
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1494522356
Short name T726
Test name
Test status
Simulation time 283183460 ps
CPU time 4.68 seconds
Started Jun 26 05:05:21 PM PDT 24
Finished Jun 26 05:05:27 PM PDT 24
Peak memory 213120 kb
Host smart-134e816c-3727-431e-b5aa-c1e8834a2357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494522356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1494522356
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.1149531613
Short name T657
Test name
Test status
Simulation time 713889340 ps
CPU time 8.06 seconds
Started Jun 26 05:05:09 PM PDT 24
Finished Jun 26 05:05:18 PM PDT 24
Peak memory 277264 kb
Host smart-2dde583b-0ce3-4a8f-8676-3914530b538d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149531613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.1149531613
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.1281697146
Short name T1059
Test name
Test status
Simulation time 1686479369 ps
CPU time 48.16 seconds
Started Jun 26 05:05:15 PM PDT 24
Finished Jun 26 05:06:04 PM PDT 24
Peak memory 606108 kb
Host smart-30da1be4-b7be-4ba5-a3c9-0322aa3b9d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281697146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.1281697146
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.4167426887
Short name T773
Test name
Test status
Simulation time 1604983834 ps
CPU time 53.52 seconds
Started Jun 26 05:05:11 PM PDT 24
Finished Jun 26 05:06:06 PM PDT 24
Peak memory 602392 kb
Host smart-3dacb6fd-84d5-4a88-9eb1-fa98b5a411d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167426887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.4167426887
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.2730821127
Short name T1296
Test name
Test status
Simulation time 272197564 ps
CPU time 0.84 seconds
Started Jun 26 05:05:09 PM PDT 24
Finished Jun 26 05:05:11 PM PDT 24
Peak memory 204524 kb
Host smart-39a0d71f-dc02-4f57-8ea4-8a03629623ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730821127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.2730821127
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1794439334
Short name T748
Test name
Test status
Simulation time 1684763191 ps
CPU time 9.17 seconds
Started Jun 26 05:05:14 PM PDT 24
Finished Jun 26 05:05:24 PM PDT 24
Peak memory 232076 kb
Host smart-4d20909d-a544-424e-8fe1-08417108462e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794439334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1794439334
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.3748930660
Short name T447
Test name
Test status
Simulation time 22230028353 ps
CPU time 114.62 seconds
Started Jun 26 05:05:10 PM PDT 24
Finished Jun 26 05:07:06 PM PDT 24
Peak memory 1205704 kb
Host smart-cbec4504-9571-4698-a5d4-4a185d946ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748930660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3748930660
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2569283226
Short name T470
Test name
Test status
Simulation time 661059819 ps
CPU time 9.06 seconds
Started Jun 26 05:05:40 PM PDT 24
Finished Jun 26 05:05:51 PM PDT 24
Peak memory 204772 kb
Host smart-08152a31-56af-45eb-819c-fd67e040256a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569283226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2569283226
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_override.1042108200
Short name T680
Test name
Test status
Simulation time 40275857 ps
CPU time 0.65 seconds
Started Jun 26 05:05:05 PM PDT 24
Finished Jun 26 05:05:07 PM PDT 24
Peak memory 204544 kb
Host smart-bb630ae3-8fdc-4d35-9b42-7f4ea821d768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042108200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1042108200
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3830924548
Short name T533
Test name
Test status
Simulation time 302368752 ps
CPU time 12.96 seconds
Started Jun 26 05:05:14 PM PDT 24
Finished Jun 26 05:05:28 PM PDT 24
Peak memory 238660 kb
Host smart-b60db833-e872-4e78-939d-fc6b95ee306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830924548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3830924548
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.3123968927
Short name T1368
Test name
Test status
Simulation time 2716785822 ps
CPU time 12.66 seconds
Started Jun 26 05:05:15 PM PDT 24
Finished Jun 26 05:05:28 PM PDT 24
Peak memory 357064 kb
Host smart-df3e4c83-1bb5-4440-814b-8295d049941b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123968927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.3123968927
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3533177682
Short name T1191
Test name
Test status
Simulation time 3199420972 ps
CPU time 23.67 seconds
Started Jun 26 05:04:58 PM PDT 24
Finished Jun 26 05:05:23 PM PDT 24
Peak memory 323744 kb
Host smart-b6658fdf-71ee-4590-b368-0bc51f09116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533177682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3533177682
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3686668711
Short name T214
Test name
Test status
Simulation time 54419793269 ps
CPU time 2588.06 seconds
Started Jun 26 05:05:22 PM PDT 24
Finished Jun 26 05:48:32 PM PDT 24
Peak memory 4346224 kb
Host smart-5e450e4d-b030-4c09-912c-4ba6323e54d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686668711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3686668711
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.2430881399
Short name T304
Test name
Test status
Simulation time 9787840340 ps
CPU time 12.73 seconds
Started Jun 26 05:05:22 PM PDT 24
Finished Jun 26 05:05:37 PM PDT 24
Peak memory 219016 kb
Host smart-2f28490d-1879-423c-abe7-372c4db3f1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430881399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.2430881399
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.2574317482
Short name T472
Test name
Test status
Simulation time 7191037775 ps
CPU time 4 seconds
Started Jun 26 05:05:41 PM PDT 24
Finished Jun 26 05:05:47 PM PDT 24
Peak memory 213136 kb
Host smart-7ccfda92-a46e-4985-bf28-25a9e5c427da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574317482 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.2574317482
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.648148172
Short name T535
Test name
Test status
Simulation time 613420100 ps
CPU time 0.94 seconds
Started Jun 26 05:05:30 PM PDT 24
Finished Jun 26 05:05:32 PM PDT 24
Peak memory 204544 kb
Host smart-21ebd761-440b-4952-913f-9623cceefeff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648148172 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_acq.648148172
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2287295489
Short name T921
Test name
Test status
Simulation time 377936800 ps
CPU time 1.07 seconds
Started Jun 26 05:05:39 PM PDT 24
Finished Jun 26 05:05:42 PM PDT 24
Peak memory 215432 kb
Host smart-c5e43ba1-9615-4091-b4fc-b54e1094f4d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287295489 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2287295489
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.816040971
Short name T170
Test name
Test status
Simulation time 302970433 ps
CPU time 1.77 seconds
Started Jun 26 05:05:49 PM PDT 24
Finished Jun 26 05:05:52 PM PDT 24
Peak memory 204796 kb
Host smart-a9b7d6f0-269f-4ac6-9887-e69e99be4cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816040971 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.816040971
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.654281483
Short name T404
Test name
Test status
Simulation time 145701399 ps
CPU time 1.22 seconds
Started Jun 26 05:05:47 PM PDT 24
Finished Jun 26 05:05:50 PM PDT 24
Peak memory 204592 kb
Host smart-6bea37e4-8f00-45c1-b5e9-cf5cf8678065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654281483 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.654281483
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.475972380
Short name T1076
Test name
Test status
Simulation time 748371468 ps
CPU time 3.96 seconds
Started Jun 26 05:05:40 PM PDT 24
Finished Jun 26 05:05:45 PM PDT 24
Peak memory 204848 kb
Host smart-984f14fd-c1e4-4790-ad6f-5451f9bb2741
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475972380 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 46.i2c_target_hrst.475972380
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2556026542
Short name T1220
Test name
Test status
Simulation time 4231586256 ps
CPU time 5.9 seconds
Started Jun 26 05:05:31 PM PDT 24
Finished Jun 26 05:05:38 PM PDT 24
Peak memory 210896 kb
Host smart-ce3b20e9-9771-4690-8fef-1795d3a448f8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556026542 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2556026542
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2077231650
Short name T571
Test name
Test status
Simulation time 8727872870 ps
CPU time 11.26 seconds
Started Jun 26 05:05:30 PM PDT 24
Finished Jun 26 05:05:42 PM PDT 24
Peak memory 264360 kb
Host smart-823a2d86-5732-4a81-960a-6cd44e8d3b59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077231650 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2077231650
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1941765469
Short name T272
Test name
Test status
Simulation time 947547795 ps
CPU time 13.02 seconds
Started Jun 26 05:05:22 PM PDT 24
Finished Jun 26 05:05:37 PM PDT 24
Peak memory 204800 kb
Host smart-998a3243-bdf0-4741-ac28-936ff1ffc6e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941765469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1941765469
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.3906990855
Short name T195
Test name
Test status
Simulation time 945508189 ps
CPU time 15.8 seconds
Started Jun 26 05:05:32 PM PDT 24
Finished Jun 26 05:05:49 PM PDT 24
Peak memory 220160 kb
Host smart-77c3f45a-72b3-4fcf-bb62-ac5dd46de82c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906990855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.3906990855
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3511217571
Short name T796
Test name
Test status
Simulation time 40875865811 ps
CPU time 595.66 seconds
Started Jun 26 05:05:21 PM PDT 24
Finished Jun 26 05:15:18 PM PDT 24
Peak memory 5396680 kb
Host smart-58f83516-7fbd-4ff1-a329-5718e711d2a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511217571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3511217571
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.3450240271
Short name T501
Test name
Test status
Simulation time 5693865052 ps
CPU time 112.3 seconds
Started Jun 26 05:05:30 PM PDT 24
Finished Jun 26 05:07:24 PM PDT 24
Peak memory 1245536 kb
Host smart-967523f8-1c88-46c1-9a80-8fd3e068106c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450240271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_
target_stretch.3450240271
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3252529816
Short name T309
Test name
Test status
Simulation time 1369083514 ps
CPU time 7.48 seconds
Started Jun 26 05:05:32 PM PDT 24
Finished Jun 26 05:05:40 PM PDT 24
Peak memory 219720 kb
Host smart-0fb23c26-87e0-4471-9a0c-0d0c1281280e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252529816 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3252529816
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.4263472144
Short name T856
Test name
Test status
Simulation time 19909825 ps
CPU time 0.63 seconds
Started Jun 26 05:06:34 PM PDT 24
Finished Jun 26 05:06:35 PM PDT 24
Peak memory 204500 kb
Host smart-ced8297f-6fd6-44fc-bceb-581279422237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263472144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.4263472144
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.14142788
Short name T1280
Test name
Test status
Simulation time 186295614 ps
CPU time 3.52 seconds
Started Jun 26 05:06:13 PM PDT 24
Finished Jun 26 05:06:17 PM PDT 24
Peak memory 218656 kb
Host smart-1003435f-1b2d-4964-b1a5-e28298d0880c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14142788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.14142788
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.929052422
Short name T785
Test name
Test status
Simulation time 6007863505 ps
CPU time 21.97 seconds
Started Jun 26 05:06:05 PM PDT 24
Finished Jun 26 05:06:28 PM PDT 24
Peak memory 299916 kb
Host smart-d3c236ca-e604-4b24-a8ad-65f269e5ca7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929052422 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.929052422
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.100641919
Short name T73
Test name
Test status
Simulation time 25856170557 ps
CPU time 180.12 seconds
Started Jun 26 05:06:06 PM PDT 24
Finished Jun 26 05:09:07 PM PDT 24
Peak memory 765832 kb
Host smart-9c6a3de1-5376-41c8-a5e7-e090d2555b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100641919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.100641919
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2227567511
Short name T876
Test name
Test status
Simulation time 9476658295 ps
CPU time 71.37 seconds
Started Jun 26 05:05:56 PM PDT 24
Finished Jun 26 05:07:09 PM PDT 24
Peak memory 772580 kb
Host smart-9e62cdd7-8441-474c-95a8-1c4d04bd5d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227567511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2227567511
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.422103805
Short name T1150
Test name
Test status
Simulation time 211145405 ps
CPU time 1.02 seconds
Started Jun 26 05:05:54 PM PDT 24
Finished Jun 26 05:05:56 PM PDT 24
Peak memory 204664 kb
Host smart-6024b2dc-92b0-4173-95af-d2801108167d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422103805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_fm
t.422103805
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1446359266
Short name T451
Test name
Test status
Simulation time 343962725 ps
CPU time 4.42 seconds
Started Jun 26 05:06:04 PM PDT 24
Finished Jun 26 05:06:09 PM PDT 24
Peak memory 204780 kb
Host smart-f90590f1-6e46-4da9-8ca4-639ea9f96f1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446359266 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1446359266
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.3764836042
Short name T1298
Test name
Test status
Simulation time 2632927316 ps
CPU time 164.85 seconds
Started Jun 26 05:05:55 PM PDT 24
Finished Jun 26 05:08:41 PM PDT 24
Peak memory 832464 kb
Host smart-041f015c-e400-463f-a288-3e99da3ae011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764836042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.3764836042
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.3797655875
Short name T231
Test name
Test status
Simulation time 818302892 ps
CPU time 16.54 seconds
Started Jun 26 05:06:30 PM PDT 24
Finished Jun 26 05:06:47 PM PDT 24
Peak memory 204876 kb
Host smart-05318c53-eb16-40a3-b97a-a62dce2fcab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797655875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.3797655875
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.1934784837
Short name T68
Test name
Test status
Simulation time 23171981437 ps
CPU time 103.72 seconds
Started Jun 26 05:06:26 PM PDT 24
Finished Jun 26 05:08:10 PM PDT 24
Peak memory 363068 kb
Host smart-8f39e186-cca8-40e2-9e32-2463fee0715d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934784837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.1934784837
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.4175101427
Short name T124
Test name
Test status
Simulation time 18347786 ps
CPU time 0.64 seconds
Started Jun 26 05:05:48 PM PDT 24
Finished Jun 26 05:05:50 PM PDT 24
Peak memory 204472 kb
Host smart-7cae3251-ea60-47fc-813b-3fdf6f013882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175101427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.4175101427
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2027002881
Short name T493
Test name
Test status
Simulation time 7223577365 ps
CPU time 28.39 seconds
Started Jun 26 05:06:05 PM PDT 24
Finished Jun 26 05:06:34 PM PDT 24
Peak memory 362036 kb
Host smart-b6b61eb5-1372-49d9-8d94-48098196bfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027002881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2027002881
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.3366663412
Short name T1348
Test name
Test status
Simulation time 97488910 ps
CPU time 1.25 seconds
Started Jun 26 05:06:03 PM PDT 24
Finished Jun 26 05:06:06 PM PDT 24
Peak memory 222468 kb
Host smart-d684eef9-f22a-442b-95f2-ae68cabe38eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366663412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.3366663412
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1887729954
Short name T978
Test name
Test status
Simulation time 2630933900 ps
CPU time 63.4 seconds
Started Jun 26 05:05:49 PM PDT 24
Finished Jun 26 05:06:54 PM PDT 24
Peak memory 299228 kb
Host smart-34f22268-ff83-4bc6-b662-cd80e72d9094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887729954 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1887729954
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.1106129757
Short name T110
Test name
Test status
Simulation time 17479896284 ps
CPU time 914.32 seconds
Started Jun 26 05:06:10 PM PDT 24
Finished Jun 26 05:21:25 PM PDT 24
Peak memory 2842188 kb
Host smart-ec494bac-bd58-4256-b22f-d79325db40bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106129757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.1106129757
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3323672069
Short name T408
Test name
Test status
Simulation time 729699196 ps
CPU time 13.66 seconds
Started Jun 26 05:06:11 PM PDT 24
Finished Jun 26 05:06:26 PM PDT 24
Peak memory 221036 kb
Host smart-9003d46a-d65e-4890-8cad-687a90b26b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323672069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3323672069
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.3272708924
Short name T494
Test name
Test status
Simulation time 1165843749 ps
CPU time 5.02 seconds
Started Jun 26 05:06:26 PM PDT 24
Finished Jun 26 05:06:32 PM PDT 24
Peak memory 213076 kb
Host smart-ea1ddeed-bf19-4b87-afbc-a13db4fd4600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272708924 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.3272708924
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.1354573731
Short name T668
Test name
Test status
Simulation time 489057783 ps
CPU time 1.06 seconds
Started Jun 26 05:06:22 PM PDT 24
Finished Jun 26 05:06:23 PM PDT 24
Peak memory 204628 kb
Host smart-067948d6-99cf-4a27-8d6d-0156520e777d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354573731 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.1354573731
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2134760687
Short name T358
Test name
Test status
Simulation time 216192576 ps
CPU time 0.99 seconds
Started Jun 26 05:06:21 PM PDT 24
Finished Jun 26 05:06:23 PM PDT 24
Peak memory 204564 kb
Host smart-74a88aa8-402b-412c-8a0f-69b16015e980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134760687 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2134760687
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.4106912277
Short name T541
Test name
Test status
Simulation time 345926710 ps
CPU time 2.07 seconds
Started Jun 26 05:06:27 PM PDT 24
Finished Jun 26 05:06:30 PM PDT 24
Peak memory 204836 kb
Host smart-8fe897f4-b745-4cc9-b936-b1c692900631
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106912277 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.4106912277
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.2688242529
Short name T507
Test name
Test status
Simulation time 111429138 ps
CPU time 1.09 seconds
Started Jun 26 05:06:29 PM PDT 24
Finished Jun 26 05:06:31 PM PDT 24
Peak memory 204552 kb
Host smart-edf2d80b-20ed-4c60-b492-6556fb5a9f1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688242529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.2688242529
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2873304681
Short name T1235
Test name
Test status
Simulation time 2083683677 ps
CPU time 5.82 seconds
Started Jun 26 05:06:19 PM PDT 24
Finished Jun 26 05:06:26 PM PDT 24
Peak memory 213068 kb
Host smart-b3875b31-c74d-41dc-8924-cfe193c155b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873304681 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2873304681
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.3452887847
Short name T322
Test name
Test status
Simulation time 5900394808 ps
CPU time 62.9 seconds
Started Jun 26 05:06:19 PM PDT 24
Finished Jun 26 05:07:23 PM PDT 24
Peak memory 1579748 kb
Host smart-429d57e2-6535-46a5-bb25-bcf3ea7fa110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452887847 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3452887847
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.506724029
Short name T152
Test name
Test status
Simulation time 941221391 ps
CPU time 16.24 seconds
Started Jun 26 05:06:12 PM PDT 24
Finished Jun 26 05:06:29 PM PDT 24
Peak memory 204796 kb
Host smart-24c3c742-88de-4ff1-9b53-00b1217ce28f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506724029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.506724029
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2418210299
Short name T345
Test name
Test status
Simulation time 1097316353 ps
CPU time 24.74 seconds
Started Jun 26 05:06:20 PM PDT 24
Finished Jun 26 05:06:45 PM PDT 24
Peak memory 204780 kb
Host smart-ee922b12-5ee3-4c56-91e1-21bb69bbee2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418210299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2418210299
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2315058649
Short name T1338
Test name
Test status
Simulation time 68136961008 ps
CPU time 270.93 seconds
Started Jun 26 05:06:11 PM PDT 24
Finished Jun 26 05:10:42 PM PDT 24
Peak memory 2961416 kb
Host smart-95d0595d-9bdc-4ba9-8dbc-dac32de71c67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315058649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2315058649
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3960570790
Short name T605
Test name
Test status
Simulation time 15385180852 ps
CPU time 159.03 seconds
Started Jun 26 05:06:21 PM PDT 24
Finished Jun 26 05:09:00 PM PDT 24
Peak memory 777084 kb
Host smart-7ff27019-1604-4e0f-8bf4-f19fe0c5dcef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960570790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3960570790
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.3937086167
Short name T370
Test name
Test status
Simulation time 1248937936 ps
CPU time 6.83 seconds
Started Jun 26 05:06:18 PM PDT 24
Finished Jun 26 05:06:26 PM PDT 24
Peak memory 220952 kb
Host smart-d53789de-e09b-470b-9228-036966a2d4a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937086167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.3937086167
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1054847800
Short name T774
Test name
Test status
Simulation time 17045454 ps
CPU time 0.64 seconds
Started Jun 26 05:07:27 PM PDT 24
Finished Jun 26 05:07:29 PM PDT 24
Peak memory 204500 kb
Host smart-faf33dae-98c8-4f70-a415-342aaafdf431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054847800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1054847800
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3202921017
Short name T990
Test name
Test status
Simulation time 118024261 ps
CPU time 1.75 seconds
Started Jun 26 05:06:53 PM PDT 24
Finished Jun 26 05:06:55 PM PDT 24
Peak memory 213116 kb
Host smart-4a033ebd-0dae-4f2c-9610-b4f84f50f188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202921017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3202921017
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2610200204
Short name T278
Test name
Test status
Simulation time 782186344 ps
CPU time 7.88 seconds
Started Jun 26 05:06:43 PM PDT 24
Finished Jun 26 05:06:52 PM PDT 24
Peak memory 257088 kb
Host smart-4ef8e75a-f21f-46ff-8273-c46b3f8994b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610200204 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2610200204
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.522490115
Short name T1022
Test name
Test status
Simulation time 32327893686 ps
CPU time 171.28 seconds
Started Jun 26 05:06:43 PM PDT 24
Finished Jun 26 05:09:35 PM PDT 24
Peak memory 769312 kb
Host smart-c32411d3-385a-41b5-a576-5c712ac1a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522490115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.522490115
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.3066213310
Short name T1311
Test name
Test status
Simulation time 2858825574 ps
CPU time 36.23 seconds
Started Jun 26 05:06:44 PM PDT 24
Finished Jun 26 05:07:21 PM PDT 24
Peak memory 506880 kb
Host smart-97f46f07-3c95-407c-89ea-dd879ddbbc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066213310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.3066213310
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.801897755
Short name T939
Test name
Test status
Simulation time 374295023 ps
CPU time 0.87 seconds
Started Jun 26 05:06:44 PM PDT 24
Finished Jun 26 05:06:45 PM PDT 24
Peak memory 204548 kb
Host smart-1ce8c4fe-f097-4149-a577-3b60a575d268
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801897755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.801897755
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.3508278117
Short name T218
Test name
Test status
Simulation time 608329862 ps
CPU time 3.75 seconds
Started Jun 26 05:06:43 PM PDT 24
Finished Jun 26 05:06:48 PM PDT 24
Peak memory 204796 kb
Host smart-2601892e-4fba-429b-a69b-33e605c4866b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508278117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.3508278117
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.740509656
Short name T405
Test name
Test status
Simulation time 2712465163 ps
CPU time 69.43 seconds
Started Jun 26 05:06:36 PM PDT 24
Finished Jun 26 05:07:46 PM PDT 24
Peak memory 861092 kb
Host smart-6469711b-a983-460f-9138-57e27e2f3606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740509656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.740509656
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.1649837630
Short name T1240
Test name
Test status
Simulation time 2489834678 ps
CPU time 26.44 seconds
Started Jun 26 05:07:22 PM PDT 24
Finished Jun 26 05:07:50 PM PDT 24
Peak memory 204932 kb
Host smart-6e470967-b110-4f82-a704-942a6d933297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649837630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.1649837630
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3215372757
Short name T1423
Test name
Test status
Simulation time 30346168973 ps
CPU time 69.66 seconds
Started Jun 26 05:07:15 PM PDT 24
Finished Jun 26 05:08:26 PM PDT 24
Peak memory 351008 kb
Host smart-ac6fdf76-de50-4065-a8bb-5165a2c95b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215372757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3215372757
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3358397643
Short name T388
Test name
Test status
Simulation time 35468379 ps
CPU time 0.67 seconds
Started Jun 26 05:06:35 PM PDT 24
Finished Jun 26 05:06:37 PM PDT 24
Peak memory 204552 kb
Host smart-12c9ea3b-85a4-4f7a-a402-443c1cbc5d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358397643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3358397643
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.4236319340
Short name T215
Test name
Test status
Simulation time 72078687569 ps
CPU time 906.51 seconds
Started Jun 26 05:06:53 PM PDT 24
Finished Jun 26 05:22:01 PM PDT 24
Peak memory 204956 kb
Host smart-d1abe219-0ae1-4c6d-b2ec-3df456aa7454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236319340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.4236319340
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.365073567
Short name T1401
Test name
Test status
Simulation time 81726722 ps
CPU time 1.19 seconds
Started Jun 26 05:06:54 PM PDT 24
Finished Jun 26 05:06:55 PM PDT 24
Peak memory 224768 kb
Host smart-c1c891b4-be47-40a6-b1da-cb2324d35e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365073567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.365073567
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.1385703161
Short name T1315
Test name
Test status
Simulation time 5002889562 ps
CPU time 36.31 seconds
Started Jun 26 05:06:35 PM PDT 24
Finished Jun 26 05:07:12 PM PDT 24
Peak memory 387876 kb
Host smart-db86c345-40f1-4289-ac08-44c49aea3856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385703161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.1385703161
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.3426275956
Short name T256
Test name
Test status
Simulation time 5075935733 ps
CPU time 116.83 seconds
Started Jun 26 05:06:56 PM PDT 24
Finished Jun 26 05:08:53 PM PDT 24
Peak memory 236500 kb
Host smart-83ba16ba-6f62-412b-a1c1-41f5884623c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426275956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.3426275956
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.728929039
Short name T1243
Test name
Test status
Simulation time 1166822894 ps
CPU time 9.02 seconds
Started Jun 26 05:06:56 PM PDT 24
Finished Jun 26 05:07:06 PM PDT 24
Peak memory 221044 kb
Host smart-78205fb8-4f49-4046-85c6-9d8bd095f652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728929039 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.728929039
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.743650039
Short name T683
Test name
Test status
Simulation time 1991047886 ps
CPU time 5.4 seconds
Started Jun 26 05:07:13 PM PDT 24
Finished Jun 26 05:07:20 PM PDT 24
Peak memory 214456 kb
Host smart-45c31069-8834-41ac-b906-5448403b1c53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743650039 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.743650039
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.849143979
Short name T429
Test name
Test status
Simulation time 621501317 ps
CPU time 0.92 seconds
Started Jun 26 05:07:10 PM PDT 24
Finished Jun 26 05:07:11 PM PDT 24
Peak memory 204548 kb
Host smart-664c4f73-21bc-4ba8-85a3-74003f380648
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849143979 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.849143979
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3171037166
Short name T284
Test name
Test status
Simulation time 284820526 ps
CPU time 1.1 seconds
Started Jun 26 05:07:06 PM PDT 24
Finished Jun 26 05:07:08 PM PDT 24
Peak memory 204616 kb
Host smart-bd184a0b-44d6-48a4-9b64-ed5c89242ac0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171037166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3171037166
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.279178871
Short name T381
Test name
Test status
Simulation time 1362034157 ps
CPU time 1.98 seconds
Started Jun 26 05:07:21 PM PDT 24
Finished Jun 26 05:07:23 PM PDT 24
Peak memory 204800 kb
Host smart-0b05298a-3533-46fc-8fbd-eb4cf3b42900
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279178871 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.279178871
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.1587014717
Short name T252
Test name
Test status
Simulation time 147534726 ps
CPU time 1.29 seconds
Started Jun 26 05:07:20 PM PDT 24
Finished Jun 26 05:07:22 PM PDT 24
Peak memory 204612 kb
Host smart-41e96044-c003-41c1-b789-8d9931c9fcbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587014717 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.1587014717
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.594750282
Short name T881
Test name
Test status
Simulation time 255089923 ps
CPU time 2.44 seconds
Started Jun 26 05:07:16 PM PDT 24
Finished Jun 26 05:07:19 PM PDT 24
Peak memory 204756 kb
Host smart-8c9594d8-858a-466e-8b15-a4c37eb23965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594750282 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.594750282
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.1003311517
Short name T686
Test name
Test status
Simulation time 5736593079 ps
CPU time 3.73 seconds
Started Jun 26 05:07:07 PM PDT 24
Finished Jun 26 05:07:12 PM PDT 24
Peak memory 205628 kb
Host smart-5f2ae85c-f3fb-4910-a92f-5aea1f7e3965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003311517 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.1003311517
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.1806860686
Short name T392
Test name
Test status
Simulation time 15388268315 ps
CPU time 34.38 seconds
Started Jun 26 05:07:07 PM PDT 24
Finished Jun 26 05:07:42 PM PDT 24
Peak memory 967312 kb
Host smart-ec172a5a-7454-4a8a-b5aa-0d01a466b20b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806860686 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.1806860686
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2257301456
Short name T1115
Test name
Test status
Simulation time 1187827362 ps
CPU time 19.16 seconds
Started Jun 26 05:06:58 PM PDT 24
Finished Jun 26 05:07:18 PM PDT 24
Peak memory 204772 kb
Host smart-6190880e-dc78-4291-8d5d-371838044655
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257301456 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2257301456
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3000020602
Short name T233
Test name
Test status
Simulation time 7226160636 ps
CPU time 22.28 seconds
Started Jun 26 05:07:00 PM PDT 24
Finished Jun 26 05:07:23 PM PDT 24
Peak memory 230512 kb
Host smart-4aa15db9-c123-4ad4-ae79-6d6d102f96ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000020602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3000020602
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3274140805
Short name T1436
Test name
Test status
Simulation time 14863413243 ps
CPU time 7.39 seconds
Started Jun 26 05:07:02 PM PDT 24
Finished Jun 26 05:07:10 PM PDT 24
Peak memory 204896 kb
Host smart-f536fcde-86ee-400a-a3f5-8f98b5654d0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274140805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3274140805
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2147266423
Short name T1317
Test name
Test status
Simulation time 22929827280 ps
CPU time 362.92 seconds
Started Jun 26 05:06:58 PM PDT 24
Finished Jun 26 05:13:02 PM PDT 24
Peak memory 1336236 kb
Host smart-6759766b-2932-464a-bf54-41e220b219e0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147266423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2147266423
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.479704479
Short name T312
Test name
Test status
Simulation time 1208021842 ps
CPU time 6.83 seconds
Started Jun 26 05:07:12 PM PDT 24
Finished Jun 26 05:07:19 PM PDT 24
Peak memory 213004 kb
Host smart-ce52e487-a51f-4c10-9fec-24fde2d2be4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479704479 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.479704479
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.3803422756
Short name T859
Test name
Test status
Simulation time 18528310 ps
CPU time 0.61 seconds
Started Jun 26 05:08:23 PM PDT 24
Finished Jun 26 05:08:25 PM PDT 24
Peak memory 204516 kb
Host smart-1a1384e7-c15c-4244-aae3-ee98e494d09a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803422756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.3803422756
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.1610156707
Short name T47
Test name
Test status
Simulation time 524122386 ps
CPU time 3.04 seconds
Started Jun 26 05:07:48 PM PDT 24
Finished Jun 26 05:07:52 PM PDT 24
Peak memory 230128 kb
Host smart-d3e6fcbf-a9e5-43c8-8cf8-ad15fb02d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610156707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.1610156707
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.2981399055
Short name T569
Test name
Test status
Simulation time 383463507 ps
CPU time 8.91 seconds
Started Jun 26 05:07:34 PM PDT 24
Finished Jun 26 05:07:44 PM PDT 24
Peak memory 290072 kb
Host smart-39628d42-f28a-4981-a601-fc7fa973008b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981399055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.2981399055
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.1889075679
Short name T76
Test name
Test status
Simulation time 15438286758 ps
CPU time 106.27 seconds
Started Jun 26 05:07:41 PM PDT 24
Finished Jun 26 05:09:28 PM PDT 24
Peak memory 1016104 kb
Host smart-73ed1fa8-9b36-45bb-b5b6-b16d00e0de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889075679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.1889075679
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.2132090046
Short name T914
Test name
Test status
Simulation time 2730352555 ps
CPU time 213.84 seconds
Started Jun 26 05:07:33 PM PDT 24
Finished Jun 26 05:11:08 PM PDT 24
Peak memory 871756 kb
Host smart-6978206d-982a-4387-a74f-6aabaec8fbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132090046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.2132090046
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.3397811818
Short name T1448
Test name
Test status
Simulation time 344741480 ps
CPU time 0.87 seconds
Started Jun 26 05:07:35 PM PDT 24
Finished Jun 26 05:07:36 PM PDT 24
Peak memory 204512 kb
Host smart-96e9e0c6-dcc0-4f52-98a7-80b4c2d65bb2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397811818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.3397811818
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1862257970
Short name T676
Test name
Test status
Simulation time 626516244 ps
CPU time 3.09 seconds
Started Jun 26 05:07:35 PM PDT 24
Finished Jun 26 05:07:39 PM PDT 24
Peak memory 204816 kb
Host smart-e41c75cf-0609-4b38-abc2-076491bcc973
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862257970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1862257970
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.549705075
Short name T1175
Test name
Test status
Simulation time 19320433271 ps
CPU time 333.98 seconds
Started Jun 26 05:07:35 PM PDT 24
Finished Jun 26 05:13:10 PM PDT 24
Peak memory 1295020 kb
Host smart-4510a8b5-287c-4782-a49a-6273520b22c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549705075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.549705075
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3681380326
Short name T525
Test name
Test status
Simulation time 298970348 ps
CPU time 3.87 seconds
Started Jun 26 05:08:16 PM PDT 24
Finished Jun 26 05:08:20 PM PDT 24
Peak memory 204852 kb
Host smart-b4145d84-2234-4b36-90cb-bdcf322c22e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681380326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3681380326
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1839764129
Short name T1007
Test name
Test status
Simulation time 1360845735 ps
CPU time 63.76 seconds
Started Jun 26 05:08:17 PM PDT 24
Finished Jun 26 05:09:21 PM PDT 24
Peak memory 318148 kb
Host smart-f597eb26-d783-40a8-82df-2ed76c0bc82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839764129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1839764129
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.1447640461
Short name T1246
Test name
Test status
Simulation time 126525454 ps
CPU time 0.75 seconds
Started Jun 26 05:07:28 PM PDT 24
Finished Jun 26 05:07:30 PM PDT 24
Peak memory 204504 kb
Host smart-ef3f554f-eba3-4bc3-9ff3-dcdb046605a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447640461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.1447640461
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1968912699
Short name T1206
Test name
Test status
Simulation time 24008345067 ps
CPU time 2826.77 seconds
Started Jun 26 05:07:45 PM PDT 24
Finished Jun 26 05:54:53 PM PDT 24
Peak memory 3663776 kb
Host smart-5a64165d-32aa-4843-ae3e-959f3154d94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968912699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1968912699
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.4021400318
Short name T548
Test name
Test status
Simulation time 141364880 ps
CPU time 1.54 seconds
Started Jun 26 05:07:42 PM PDT 24
Finished Jun 26 05:07:44 PM PDT 24
Peak memory 204724 kb
Host smart-7d61a49b-ae64-4ff4-908b-43e51b72aff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021400318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.4021400318
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.936953320
Short name T831
Test name
Test status
Simulation time 3439159018 ps
CPU time 84.66 seconds
Started Jun 26 05:07:27 PM PDT 24
Finished Jun 26 05:08:53 PM PDT 24
Peak memory 347412 kb
Host smart-a54c0f0d-deaf-4828-84d5-5c2363c5d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936953320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.936953320
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.4005674713
Short name T997
Test name
Test status
Simulation time 2197987149 ps
CPU time 11.54 seconds
Started Jun 26 05:07:48 PM PDT 24
Finished Jun 26 05:08:01 PM PDT 24
Peak memory 213164 kb
Host smart-817cb183-d0e3-416c-b68b-ffc4ca91e337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005674713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.4005674713
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.688877391
Short name T23
Test name
Test status
Simulation time 2072188899 ps
CPU time 3.85 seconds
Started Jun 26 05:08:09 PM PDT 24
Finished Jun 26 05:08:13 PM PDT 24
Peak memory 213080 kb
Host smart-4ed533d2-cb8e-43ee-8bc1-5d31111f6313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688877391 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.688877391
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2383908193
Short name T520
Test name
Test status
Simulation time 482391018 ps
CPU time 0.89 seconds
Started Jun 26 05:08:03 PM PDT 24
Finished Jun 26 05:08:07 PM PDT 24
Peak memory 204536 kb
Host smart-eada6f7f-3001-462f-b119-e03e3b3326d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383908193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2383908193
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.1951570724
Short name T1385
Test name
Test status
Simulation time 168236814 ps
CPU time 1.13 seconds
Started Jun 26 05:08:02 PM PDT 24
Finished Jun 26 05:08:06 PM PDT 24
Peak memory 204564 kb
Host smart-b0349789-5297-4ec2-8723-f0270fede80d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951570724 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.1951570724
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.2034613368
Short name T248
Test name
Test status
Simulation time 1041262293 ps
CPU time 2.91 seconds
Started Jun 26 05:08:24 PM PDT 24
Finished Jun 26 05:08:28 PM PDT 24
Peak memory 204820 kb
Host smart-44a331fa-aea5-4020-aa71-e0ce0cfd1e59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034613368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.2034613368
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.3737298123
Short name T459
Test name
Test status
Simulation time 221158665 ps
CPU time 0.91 seconds
Started Jun 26 05:08:22 PM PDT 24
Finished Jun 26 05:08:24 PM PDT 24
Peak memory 204556 kb
Host smart-aa27e6de-5f0f-463c-81c2-3dd1525ae5d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737298123 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.3737298123
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.4009197909
Short name T419
Test name
Test status
Simulation time 2461724962 ps
CPU time 2.62 seconds
Started Jun 26 05:08:17 PM PDT 24
Finished Jun 26 05:08:20 PM PDT 24
Peak memory 204908 kb
Host smart-bfd02967-303e-49f5-8229-12f0bb4ba78e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009197909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.4009197909
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1915542298
Short name T576
Test name
Test status
Simulation time 1142896502 ps
CPU time 6.23 seconds
Started Jun 26 05:07:56 PM PDT 24
Finished Jun 26 05:08:03 PM PDT 24
Peak memory 217336 kb
Host smart-9cef9c48-f5d8-4dd5-8dfe-ec488a6b1d41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915542298 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1915542298
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1316870652
Short name T1016
Test name
Test status
Simulation time 29338293475 ps
CPU time 13.51 seconds
Started Jun 26 05:08:03 PM PDT 24
Finished Jun 26 05:08:19 PM PDT 24
Peak memory 463120 kb
Host smart-24ad3764-034c-4693-b173-5238c803e01f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316870652 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1316870652
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2212343237
Short name T895
Test name
Test status
Simulation time 4792174673 ps
CPU time 16 seconds
Started Jun 26 05:07:47 PM PDT 24
Finished Jun 26 05:08:04 PM PDT 24
Peak memory 204936 kb
Host smart-415bbcd4-c8e4-4af2-b99a-0df022e5ee98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212343237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2212343237
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3337017873
Short name T1084
Test name
Test status
Simulation time 24493581393 ps
CPU time 22.15 seconds
Started Jun 26 05:07:56 PM PDT 24
Finished Jun 26 05:08:19 PM PDT 24
Peak memory 228776 kb
Host smart-71286a79-699d-4c9c-80a8-381adbdfa7aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337017873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3337017873
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.725682259
Short name T909
Test name
Test status
Simulation time 28076039261 ps
CPU time 28.76 seconds
Started Jun 26 05:07:54 PM PDT 24
Finished Jun 26 05:08:24 PM PDT 24
Peak memory 686276 kb
Host smart-ce899f0a-e93c-4da2-945c-49e292abebac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725682259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.725682259
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.418385190
Short name T899
Test name
Test status
Simulation time 36983940883 ps
CPU time 739.8 seconds
Started Jun 26 05:07:55 PM PDT 24
Finished Jun 26 05:20:16 PM PDT 24
Peak memory 4157636 kb
Host smart-a485b3ef-2a54-48af-ac62-950e46846a7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418385190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.418385190
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.2172576969
Short name T1361
Test name
Test status
Simulation time 1321385103 ps
CPU time 6.74 seconds
Started Jun 26 05:08:04 PM PDT 24
Finished Jun 26 05:08:13 PM PDT 24
Peak memory 209740 kb
Host smart-2c3edcd7-926e-4f61-8881-3d32a4a64e5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172576969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.2172576969
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.3271814242
Short name T853
Test name
Test status
Simulation time 43028583 ps
CPU time 0.64 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 04:56:17 PM PDT 24
Peak memory 204416 kb
Host smart-0fa8938d-d1ba-4cf1-a946-25e56b8d1dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271814242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.3271814242
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3677331069
Short name T1353
Test name
Test status
Simulation time 76981413 ps
CPU time 1.49 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:56:24 PM PDT 24
Peak memory 213340 kb
Host smart-16f8e547-8777-4803-b7e6-895dd66830cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677331069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3677331069
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2509473273
Short name T502
Test name
Test status
Simulation time 679751572 ps
CPU time 7.76 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:18 PM PDT 24
Peak memory 269300 kb
Host smart-2cf3a43f-5793-4707-9d04-778619cc7075
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509473273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2509473273
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.3056279000
Short name T349
Test name
Test status
Simulation time 6829332518 ps
CPU time 58.93 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:57:05 PM PDT 24
Peak memory 632680 kb
Host smart-c9dc3627-378c-41ae-8069-85a369b3c5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056279000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.3056279000
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.4134805209
Short name T1154
Test name
Test status
Simulation time 2916676392 ps
CPU time 100.64 seconds
Started Jun 26 04:56:03 PM PDT 24
Finished Jun 26 04:57:47 PM PDT 24
Peak memory 561436 kb
Host smart-4ca8364d-4fb1-4d0f-a62d-6e53801d7081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134805209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.4134805209
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.1974837666
Short name T1147
Test name
Test status
Simulation time 950417154 ps
CPU time 0.96 seconds
Started Jun 26 04:55:59 PM PDT 24
Finished Jun 26 04:56:03 PM PDT 24
Peak memory 204472 kb
Host smart-cb7ec9e5-9ed7-425b-a89b-25c324e81cdf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974837666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.1974837666
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2509438731
Short name T784
Test name
Test status
Simulation time 746900133 ps
CPU time 9.28 seconds
Started Jun 26 04:56:01 PM PDT 24
Finished Jun 26 04:56:14 PM PDT 24
Peak memory 204828 kb
Host smart-0585abac-93c2-4945-8c48-67ae5dfddfe0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509438731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2509438731
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.4007977628
Short name T1149
Test name
Test status
Simulation time 13580418247 ps
CPU time 225.02 seconds
Started Jun 26 04:56:06 PM PDT 24
Finished Jun 26 04:59:53 PM PDT 24
Peak memory 1054084 kb
Host smart-f15e2bdf-2141-489d-94fd-bbcb54100286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007977628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.4007977628
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.371647526
Short name T1226
Test name
Test status
Simulation time 892154863 ps
CPU time 3.2 seconds
Started Jun 26 04:56:08 PM PDT 24
Finished Jun 26 04:56:13 PM PDT 24
Peak memory 204804 kb
Host smart-330a0c43-a121-4b9e-a87e-83113d2b58ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371647526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.371647526
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.2106707724
Short name T1416
Test name
Test status
Simulation time 1260265287 ps
CPU time 27.19 seconds
Started Jun 26 04:56:09 PM PDT 24
Finished Jun 26 04:56:38 PM PDT 24
Peak memory 383608 kb
Host smart-5f6850fd-a1fa-43e0-ab9c-fd90a6aac3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106707724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.2106707724
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.706767044
Short name T81
Test name
Test status
Simulation time 27835989 ps
CPU time 0.7 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:06 PM PDT 24
Peak memory 204532 kb
Host smart-ae678565-0dcf-47e2-b00a-837c5fadf776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706767044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.706767044
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.3595211602
Short name T725
Test name
Test status
Simulation time 7646205131 ps
CPU time 262.12 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 05:00:37 PM PDT 24
Peak memory 1131884 kb
Host smart-f1ffa304-f4be-4853-a696-2122636558e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595211602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.3595211602
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.4231399504
Short name T465
Test name
Test status
Simulation time 235159105 ps
CPU time 6.15 seconds
Started Jun 26 04:56:11 PM PDT 24
Finished Jun 26 04:56:19 PM PDT 24
Peak memory 226500 kb
Host smart-7416e91e-4546-4f4d-9edb-4f3c932a29d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231399504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.4231399504
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.2131807634
Short name T1292
Test name
Test status
Simulation time 5026482086 ps
CPU time 65.72 seconds
Started Jun 26 04:56:21 PM PDT 24
Finished Jun 26 04:57:29 PM PDT 24
Peak memory 358988 kb
Host smart-a2b6217d-77a3-4abc-adaa-58ffb9357cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131807634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.2131807634
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.392727509
Short name T328
Test name
Test status
Simulation time 1869744378 ps
CPU time 14.18 seconds
Started Jun 26 04:56:06 PM PDT 24
Finished Jun 26 04:56:22 PM PDT 24
Peak memory 229428 kb
Host smart-eb19d62c-e478-417d-a371-ef85014b4751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392727509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.392727509
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.1203220011
Short name T703
Test name
Test status
Simulation time 904679110 ps
CPU time 4.14 seconds
Started Jun 26 04:56:08 PM PDT 24
Finished Jun 26 04:56:14 PM PDT 24
Peak memory 213036 kb
Host smart-e8aba6b9-adf2-42f4-8897-31badc9ca1ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203220011 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.1203220011
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.76588475
Short name T597
Test name
Test status
Simulation time 357642757 ps
CPU time 1.33 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 04:56:16 PM PDT 24
Peak memory 204508 kb
Host smart-f8f7604e-7f69-4163-bae7-82d9d66af6ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76588475 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.i2c_target_fifo_reset_acq.76588475
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2699946091
Short name T1106
Test name
Test status
Simulation time 108637710 ps
CPU time 0.88 seconds
Started Jun 26 04:56:13 PM PDT 24
Finished Jun 26 04:56:16 PM PDT 24
Peak memory 204500 kb
Host smart-a3b52ce9-d97a-4430-8718-1367a8e5256b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699946091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2699946091
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.3405675364
Short name T1008
Test name
Test status
Simulation time 418092629 ps
CPU time 2.35 seconds
Started Jun 26 04:56:09 PM PDT 24
Finished Jun 26 04:56:13 PM PDT 24
Peak memory 204856 kb
Host smart-8c47595b-0632-4b86-aea8-add35497a871
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405675364 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.3405675364
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.4263946995
Short name T1020
Test name
Test status
Simulation time 114426344 ps
CPU time 1.21 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 04:56:17 PM PDT 24
Peak memory 204820 kb
Host smart-86ed7893-1137-4e41-9da6-1ee49fda136d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263946995 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.4263946995
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.940678964
Short name T1216
Test name
Test status
Simulation time 1055274788 ps
CPU time 2.3 seconds
Started Jun 26 04:56:18 PM PDT 24
Finished Jun 26 04:56:23 PM PDT 24
Peak memory 204808 kb
Host smart-d703152b-641a-492a-b6e8-36ba1665533b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940678964 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.940678964
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.567438492
Short name T254
Test name
Test status
Simulation time 3438298845 ps
CPU time 4.63 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 204632 kb
Host smart-90e38dfc-5fec-49a3-aff4-2e9c6fdead11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567438492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_intr_smoke.567438492
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3191988779
Short name T338
Test name
Test status
Simulation time 6426397464 ps
CPU time 2 seconds
Started Jun 26 04:56:06 PM PDT 24
Finished Jun 26 04:56:10 PM PDT 24
Peak memory 204960 kb
Host smart-799af6e7-2f8c-424a-ad6f-18532f56a59a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191988779 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3191988779
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.926187572
Short name T559
Test name
Test status
Simulation time 4774639993 ps
CPU time 44.77 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:57:07 PM PDT 24
Peak memory 204924 kb
Host smart-d5e8c97d-a0b9-4e5e-bc79-7f1f7b537342
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926187572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_targ
et_smoke.926187572
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.916931833
Short name T1276
Test name
Test status
Simulation time 4391022596 ps
CPU time 17.6 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:24 PM PDT 24
Peak memory 216936 kb
Host smart-113dfc7c-2879-4e56-bddf-45f02b75544e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916931833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.916931833
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.343765321
Short name T444
Test name
Test status
Simulation time 24233023392 ps
CPU time 23.95 seconds
Started Jun 26 04:56:03 PM PDT 24
Finished Jun 26 04:56:31 PM PDT 24
Peak memory 469008 kb
Host smart-483318e4-e570-4d03-a8d7-d72434c3b8df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343765321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_wr.343765321
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.4247557106
Short name T721
Test name
Test status
Simulation time 29468621014 ps
CPU time 142.95 seconds
Started Jun 26 04:56:03 PM PDT 24
Finished Jun 26 04:58:30 PM PDT 24
Peak memory 602352 kb
Host smart-2b6c9a04-a7bf-426b-b22f-8e2b15da9b6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247557106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.4247557106
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.3528834819
Short name T781
Test name
Test status
Simulation time 10400436846 ps
CPU time 7.89 seconds
Started Jun 26 04:56:02 PM PDT 24
Finished Jun 26 04:56:14 PM PDT 24
Peak memory 221264 kb
Host smart-b41b45df-0bdf-42a6-9356-79699cd71841
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528834819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.3528834819
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.3278254562
Short name T321
Test name
Test status
Simulation time 76175259 ps
CPU time 0.62 seconds
Started Jun 26 04:56:27 PM PDT 24
Finished Jun 26 04:56:29 PM PDT 24
Peak memory 204488 kb
Host smart-3a6b7e47-db55-4b3c-a19d-f1ae2c1bc923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278254562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.3278254562
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.574391004
Short name T350
Test name
Test status
Simulation time 322717113 ps
CPU time 13.6 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 04:56:29 PM PDT 24
Peak memory 239332 kb
Host smart-c4f313d0-5922-4d16-975b-7d1429a9bc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574391004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.574391004
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.2690437165
Short name T378
Test name
Test status
Simulation time 751540587 ps
CPU time 4.91 seconds
Started Jun 26 04:56:10 PM PDT 24
Finished Jun 26 04:56:17 PM PDT 24
Peak memory 246168 kb
Host smart-f82bdb0e-f87e-45b9-8700-8106e7253b8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690437165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.2690437165
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2838339941
Short name T329
Test name
Test status
Simulation time 8490567144 ps
CPU time 62.26 seconds
Started Jun 26 04:56:09 PM PDT 24
Finished Jun 26 04:57:13 PM PDT 24
Peak memory 656848 kb
Host smart-1cb31943-174d-4be7-b7e3-2cfdeabfcf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838339941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2838339941
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.1419438857
Short name T420
Test name
Test status
Simulation time 1923084723 ps
CPU time 132.72 seconds
Started Jun 26 04:56:09 PM PDT 24
Finished Jun 26 04:58:25 PM PDT 24
Peak memory 638316 kb
Host smart-58868bd1-cd2c-4e1f-8903-18985ff570b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419438857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.1419438857
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.128176270
Short name T1032
Test name
Test status
Simulation time 290828452 ps
CPU time 1.03 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:56:23 PM PDT 24
Peak memory 204460 kb
Host smart-9ae118b3-47f9-42e0-a3b0-aaef58101d64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128176270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.128176270
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.3355240144
Short name T770
Test name
Test status
Simulation time 275525279 ps
CPU time 3.87 seconds
Started Jun 26 04:56:08 PM PDT 24
Finished Jun 26 04:56:14 PM PDT 24
Peak memory 226312 kb
Host smart-df5b0317-1d44-4baf-be83-304d593897b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355240144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
3355240144
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.473485847
Short name T1087
Test name
Test status
Simulation time 31183233282 ps
CPU time 220.99 seconds
Started Jun 26 04:56:09 PM PDT 24
Finished Jun 26 04:59:52 PM PDT 24
Peak memory 984368 kb
Host smart-3941ff05-2977-4b73-afa7-843a239011bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473485847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.473485847
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.2869589803
Short name T625
Test name
Test status
Simulation time 833866647 ps
CPU time 3.42 seconds
Started Jun 26 04:56:14 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 204828 kb
Host smart-f7ea16aa-488e-43b0-80e9-cae5bba2c476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869589803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.2869589803
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.50097390
Short name T286
Test name
Test status
Simulation time 2335363389 ps
CPU time 20.1 seconds
Started Jun 26 04:56:17 PM PDT 24
Finished Jun 26 04:56:39 PM PDT 24
Peak memory 298880 kb
Host smart-cc1c9089-9429-4f62-8ff3-265999aa5cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50097390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.50097390
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.3202568074
Short name T82
Test name
Test status
Simulation time 28390189 ps
CPU time 0.7 seconds
Started Jun 26 04:56:08 PM PDT 24
Finished Jun 26 04:56:10 PM PDT 24
Peak memory 204524 kb
Host smart-8ea00ec0-a6ce-4985-b787-be48b94da899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202568074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.3202568074
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1865751169
Short name T410
Test name
Test status
Simulation time 47467372931 ps
CPU time 1103.13 seconds
Started Jun 26 04:56:21 PM PDT 24
Finished Jun 26 05:14:46 PM PDT 24
Peak memory 2183204 kb
Host smart-ea7e81c4-6a29-40e5-9d5f-362b4900aa69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865751169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1865751169
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.1633330489
Short name T1069
Test name
Test status
Simulation time 24260950656 ps
CPU time 373.14 seconds
Started Jun 26 04:56:22 PM PDT 24
Finished Jun 26 05:02:38 PM PDT 24
Peak memory 853140 kb
Host smart-d4f3a68d-5556-479f-a899-16ee40aab3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633330489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.1633330489
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.630900295
Short name T351
Test name
Test status
Simulation time 5785787888 ps
CPU time 64.63 seconds
Started Jun 26 04:56:17 PM PDT 24
Finished Jun 26 04:57:24 PM PDT 24
Peak memory 292904 kb
Host smart-a9a46c68-d4df-47cc-9723-8f4c1057bef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630900295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.630900295
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1337255231
Short name T1060
Test name
Test status
Simulation time 448147155 ps
CPU time 20.2 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:56:42 PM PDT 24
Peak memory 212992 kb
Host smart-cb41956a-17e9-4f77-a444-225190a1bd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337255231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1337255231
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.3818735149
Short name T320
Test name
Test status
Simulation time 3288452582 ps
CPU time 3.13 seconds
Started Jun 26 04:56:24 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 213160 kb
Host smart-78c4f60d-3e26-47a1-bc2c-e7c70ee79c9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818735149 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.3818735149
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2758376411
Short name T806
Test name
Test status
Simulation time 189481587 ps
CPU time 1.2 seconds
Started Jun 26 04:56:10 PM PDT 24
Finished Jun 26 04:56:13 PM PDT 24
Peak memory 204760 kb
Host smart-7add52cc-4655-40cd-96a8-7fa4e3089118
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758376411 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2758376411
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.3246957092
Short name T354
Test name
Test status
Simulation time 554864221 ps
CPU time 0.78 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:56:23 PM PDT 24
Peak memory 204552 kb
Host smart-b7498d36-bbe8-40c8-a798-0060b0ceaee7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246957092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.3246957092
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.3194177529
Short name T692
Test name
Test status
Simulation time 618308341 ps
CPU time 2.84 seconds
Started Jun 26 04:56:15 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 204896 kb
Host smart-133dd75a-d60c-431a-8a76-353e5538d267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194177529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.3194177529
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.1767702897
Short name T1104
Test name
Test status
Simulation time 768994399 ps
CPU time 1.33 seconds
Started Jun 26 04:56:18 PM PDT 24
Finished Jun 26 04:56:21 PM PDT 24
Peak memory 204552 kb
Host smart-c08be2a8-c03f-4e63-99ff-aa0691504557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767702897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.1767702897
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.364181503
Short name T1041
Test name
Test status
Simulation time 1293499736 ps
CPU time 2.86 seconds
Started Jun 26 04:56:21 PM PDT 24
Finished Jun 26 04:56:27 PM PDT 24
Peak memory 204740 kb
Host smart-fe766fac-c65d-41fc-950e-f1a3441c3fca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364181503 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 6.i2c_target_hrst.364181503
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.1360601190
Short name T1294
Test name
Test status
Simulation time 3175239380 ps
CPU time 4.14 seconds
Started Jun 26 04:56:08 PM PDT 24
Finished Jun 26 04:56:14 PM PDT 24
Peak memory 205348 kb
Host smart-9d113320-0059-4a5d-9f91-500d7a29f4b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360601190 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.1360601190
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2116504109
Short name T969
Test name
Test status
Simulation time 6906998903 ps
CPU time 13.26 seconds
Started Jun 26 04:56:18 PM PDT 24
Finished Jun 26 04:56:34 PM PDT 24
Peak memory 204956 kb
Host smart-36f6ea0c-1d56-406b-bc54-54bad45d179d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116504109 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2116504109
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.1270619505
Short name T839
Test name
Test status
Simulation time 8276183998 ps
CPU time 21.25 seconds
Started Jun 26 04:56:19 PM PDT 24
Finished Jun 26 04:56:42 PM PDT 24
Peak memory 204832 kb
Host smart-2942fa6a-ec94-4254-8b87-2b105dc27fd7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270619505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.1270619505
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.3838659349
Short name T11
Test name
Test status
Simulation time 1553877699 ps
CPU time 31 seconds
Started Jun 26 04:56:10 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 204852 kb
Host smart-805a16bc-5237-4521-88d6-9d7c2412ba53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838659349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.3838659349
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.2296468654
Short name T935
Test name
Test status
Simulation time 8395633411 ps
CPU time 5.03 seconds
Started Jun 26 04:56:10 PM PDT 24
Finished Jun 26 04:56:17 PM PDT 24
Peak memory 204860 kb
Host smart-a734bb3f-d77b-4b7d-9661-1a909a82642e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296468654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.2296468654
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.51240675
Short name T543
Test name
Test status
Simulation time 8414393067 ps
CPU time 247.79 seconds
Started Jun 26 04:56:08 PM PDT 24
Finished Jun 26 05:00:18 PM PDT 24
Peak memory 2231308 kb
Host smart-b1cb3589-be75-4d97-bbc6-28ca012f44a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51240675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_stretch.51240675
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2211258268
Short name T9
Test name
Test status
Simulation time 2617519502 ps
CPU time 7.31 seconds
Started Jun 26 04:56:10 PM PDT 24
Finished Jun 26 04:56:19 PM PDT 24
Peak memory 221144 kb
Host smart-b86e184f-930e-4c03-9d3d-ff7c618f99a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211258268 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2211258268
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_alert_test.3573780838
Short name T564
Test name
Test status
Simulation time 47287795 ps
CPU time 0.61 seconds
Started Jun 26 04:56:27 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 204468 kb
Host smart-f4a9af24-7736-48fe-934c-06bf79fff62f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573780838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3573780838
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2478874593
Short name T694
Test name
Test status
Simulation time 257795800 ps
CPU time 3.35 seconds
Started Jun 26 04:56:15 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 213084 kb
Host smart-2d109085-8295-414f-8dfa-fc4b3af285b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478874593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2478874593
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.516633594
Short name T333
Test name
Test status
Simulation time 174661859 ps
CPU time 8.19 seconds
Started Jun 26 04:56:17 PM PDT 24
Finished Jun 26 04:56:27 PM PDT 24
Peak memory 229948 kb
Host smart-245920a2-1657-4732-93a4-55e78591b338
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516633594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.516633594
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2989689449
Short name T910
Test name
Test status
Simulation time 3009565001 ps
CPU time 107.78 seconds
Started Jun 26 04:56:16 PM PDT 24
Finished Jun 26 04:58:06 PM PDT 24
Peak memory 871548 kb
Host smart-15df2563-44c6-4cd0-ad90-06176f86b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989689449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2989689449
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2024710668
Short name T467
Test name
Test status
Simulation time 3650891033 ps
CPU time 53.42 seconds
Started Jun 26 04:56:26 PM PDT 24
Finished Jun 26 04:57:22 PM PDT 24
Peak memory 641288 kb
Host smart-335e276a-304b-4f21-bc07-4cd832e7675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024710668 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2024710668
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.715125780
Short name T342
Test name
Test status
Simulation time 283416827 ps
CPU time 0.8 seconds
Started Jun 26 04:56:16 PM PDT 24
Finished Jun 26 04:56:19 PM PDT 24
Peak memory 204516 kb
Host smart-2dc025f6-cd68-4f27-b910-b8d84a2653dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715125780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.715125780
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1787013478
Short name T1318
Test name
Test status
Simulation time 499251937 ps
CPU time 3.33 seconds
Started Jun 26 04:56:26 PM PDT 24
Finished Jun 26 04:56:32 PM PDT 24
Peak memory 204856 kb
Host smart-1d6c5a00-8a91-4586-9328-0930f1a69505
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787013478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1787013478
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.4005743675
Short name T55
Test name
Test status
Simulation time 15750067542 ps
CPU time 86.49 seconds
Started Jun 26 04:56:17 PM PDT 24
Finished Jun 26 04:57:46 PM PDT 24
Peak memory 1119808 kb
Host smart-bcdf1390-0495-4b0a-b771-2e87e75c93a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005743675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.4005743675
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.787884604
Short name T232
Test name
Test status
Simulation time 540828943 ps
CPU time 21.71 seconds
Started Jun 26 04:56:30 PM PDT 24
Finished Jun 26 04:56:53 PM PDT 24
Peak memory 204788 kb
Host smart-d3eb1799-1cbf-44a2-9746-eb3434e60a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787884604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.787884604
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.3494199914
Short name T241
Test name
Test status
Simulation time 35112627995 ps
CPU time 41.13 seconds
Started Jun 26 04:56:29 PM PDT 24
Finished Jun 26 04:57:13 PM PDT 24
Peak memory 365064 kb
Host smart-71c14c8b-ee25-483f-8418-84bd0fc77eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494199914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.3494199914
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.3037277414
Short name T1359
Test name
Test status
Simulation time 36643838 ps
CPU time 0.67 seconds
Started Jun 26 04:56:17 PM PDT 24
Finished Jun 26 04:56:20 PM PDT 24
Peak memory 204504 kb
Host smart-195635f1-03ef-49bf-9b9c-9ff5fe37bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037277414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.3037277414
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.4129186109
Short name T120
Test name
Test status
Simulation time 2080079577 ps
CPU time 26.87 seconds
Started Jun 26 04:56:19 PM PDT 24
Finished Jun 26 04:56:49 PM PDT 24
Peak memory 213052 kb
Host smart-332ecb99-62b4-4a27-89c6-b18e64649191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129186109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.4129186109
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.1139414991
Short name T1109
Test name
Test status
Simulation time 97898789 ps
CPU time 1.78 seconds
Started Jun 26 04:56:15 PM PDT 24
Finished Jun 26 04:56:19 PM PDT 24
Peak memory 212940 kb
Host smart-08c2061b-27dc-4735-9324-acf2e85e0cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139414991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.1139414991
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.4082346765
Short name T843
Test name
Test status
Simulation time 20525053715 ps
CPU time 112.09 seconds
Started Jun 26 04:56:18 PM PDT 24
Finished Jun 26 04:58:12 PM PDT 24
Peak memory 410100 kb
Host smart-bdc9f4da-3753-4bd3-9fe7-5b64060eef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082346765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.4082346765
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.1065229828
Short name T749
Test name
Test status
Simulation time 87034554920 ps
CPU time 2660.58 seconds
Started Jun 26 04:56:22 PM PDT 24
Finished Jun 26 05:40:45 PM PDT 24
Peak memory 743344 kb
Host smart-543a49d0-3e78-4298-9a29-9a9148ba49c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065229828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.1065229828
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2297683995
Short name T546
Test name
Test status
Simulation time 1571120806 ps
CPU time 17.37 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:56:40 PM PDT 24
Peak memory 213020 kb
Host smart-00bcde52-ff15-4992-a09c-aed4ba4d0d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297683995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2297683995
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.2547618491
Short name T1367
Test name
Test status
Simulation time 2764034439 ps
CPU time 3.99 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:56:26 PM PDT 24
Peak memory 213120 kb
Host smart-40b56304-525a-4220-aa1c-0df35f655a71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547618491 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.2547618491
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.2534737227
Short name T836
Test name
Test status
Simulation time 383568106 ps
CPU time 0.65 seconds
Started Jun 26 04:56:22 PM PDT 24
Finished Jun 26 04:56:25 PM PDT 24
Peak memory 204520 kb
Host smart-50475769-a838-4b59-a59a-d4d406a78ce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534737227 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.2534737227
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.4209428211
Short name T1395
Test name
Test status
Simulation time 251886975 ps
CPU time 1.55 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:56:23 PM PDT 24
Peak memory 205012 kb
Host smart-58983ebf-1b1f-4fcc-a4ef-b7851a4aa441
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209428211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.4209428211
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.3578756461
Short name T789
Test name
Test status
Simulation time 1982144456 ps
CPU time 2.09 seconds
Started Jun 26 04:56:25 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 204720 kb
Host smart-4e3ea15f-0c02-49d0-aa36-bd9d93001995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578756461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.3578756461
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.990741988
Short name T511
Test name
Test status
Simulation time 179631780 ps
CPU time 1.3 seconds
Started Jun 26 04:56:23 PM PDT 24
Finished Jun 26 04:56:27 PM PDT 24
Peak memory 204636 kb
Host smart-3e31e1a0-81ca-4b14-a3b7-30d642425e06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990741988 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.990741988
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.1363221533
Short name T148
Test name
Test status
Simulation time 312235686 ps
CPU time 2.51 seconds
Started Jun 26 04:56:26 PM PDT 24
Finished Jun 26 04:56:31 PM PDT 24
Peak memory 204728 kb
Host smart-aff7bfdd-6908-4d14-9bca-bc88c83d1fcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363221533 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.1363221533
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2717169435
Short name T908
Test name
Test status
Simulation time 680635857 ps
CPU time 3.92 seconds
Started Jun 26 04:56:15 PM PDT 24
Finished Jun 26 04:56:21 PM PDT 24
Peak memory 205128 kb
Host smart-c5e15d3a-4108-4154-980f-5c40541fdb72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717169435 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2717169435
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2579254431
Short name T1173
Test name
Test status
Simulation time 13181870897 ps
CPU time 15.64 seconds
Started Jun 26 04:56:19 PM PDT 24
Finished Jun 26 04:56:37 PM PDT 24
Peak memory 416388 kb
Host smart-30c591bd-7534-411f-8c84-260c20a4f7b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579254431 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2579254431
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3736767501
Short name T1249
Test name
Test status
Simulation time 2757698709 ps
CPU time 9.49 seconds
Started Jun 26 04:56:18 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 204892 kb
Host smart-156b8861-fe74-48fe-8b28-6a1967226694
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736767501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3736767501
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.418747229
Short name T445
Test name
Test status
Simulation time 4925947135 ps
CPU time 53.85 seconds
Started Jun 26 04:56:19 PM PDT 24
Finished Jun 26 04:57:15 PM PDT 24
Peak memory 207492 kb
Host smart-ae10f39a-30ac-406f-9f08-f4e6eafcea29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418747229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.418747229
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.4049571506
Short name T1253
Test name
Test status
Simulation time 27506175399 ps
CPU time 59.23 seconds
Started Jun 26 04:56:15 PM PDT 24
Finished Jun 26 04:57:17 PM PDT 24
Peak memory 1041536 kb
Host smart-29cf6855-77f2-4f21-8505-4e9210f355de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049571506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.4049571506
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.3362410497
Short name T842
Test name
Test status
Simulation time 34917575210 ps
CPU time 2656.34 seconds
Started Jun 26 04:56:22 PM PDT 24
Finished Jun 26 05:40:40 PM PDT 24
Peak memory 8739136 kb
Host smart-7c5396e9-a2e4-4fbd-826e-5454f78c1341
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362410497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.3362410497
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.180476036
Short name T394
Test name
Test status
Simulation time 6546300856 ps
CPU time 7.24 seconds
Started Jun 26 04:56:26 PM PDT 24
Finished Jun 26 04:56:36 PM PDT 24
Peak memory 213072 kb
Host smart-7abd9b71-3bdf-45ae-8432-1551bc47134b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180476036 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.180476036
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.1340288631
Short name T943
Test name
Test status
Simulation time 35608283 ps
CPU time 0.62 seconds
Started Jun 26 04:56:31 PM PDT 24
Finished Jun 26 04:56:33 PM PDT 24
Peak memory 204468 kb
Host smart-f2954b9d-1e19-46d2-a9e0-2d16e964e9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340288631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.1340288631
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.70527344
Short name T547
Test name
Test status
Simulation time 138031736 ps
CPU time 1.79 seconds
Started Jun 26 04:56:23 PM PDT 24
Finished Jun 26 04:56:27 PM PDT 24
Peak memory 213048 kb
Host smart-1fd88a71-7173-4917-9be2-981f77b6d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70527344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.70527344
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.4095614883
Short name T757
Test name
Test status
Simulation time 1426570431 ps
CPU time 6.51 seconds
Started Jun 26 04:56:25 PM PDT 24
Finished Jun 26 04:56:34 PM PDT 24
Peak memory 280580 kb
Host smart-25002d59-39eb-46c8-a844-29cac5bad41b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095614883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.4095614883
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.4284894127
Short name T758
Test name
Test status
Simulation time 6356713450 ps
CPU time 48.45 seconds
Started Jun 26 04:56:31 PM PDT 24
Finished Jun 26 04:57:21 PM PDT 24
Peak memory 424616 kb
Host smart-d53ee427-bd8f-45f7-b02f-c885fdb7035b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284894127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.4284894127
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2543791689
Short name T829
Test name
Test status
Simulation time 2551089753 ps
CPU time 195.78 seconds
Started Jun 26 04:56:26 PM PDT 24
Finished Jun 26 04:59:44 PM PDT 24
Peak memory 835200 kb
Host smart-d8a7d3f4-d081-4bb3-bb30-47687a57ffad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543791689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2543791689
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.18295974
Short name T386
Test name
Test status
Simulation time 370995601 ps
CPU time 0.88 seconds
Started Jun 26 04:56:29 PM PDT 24
Finished Jun 26 04:56:32 PM PDT 24
Peak memory 204476 kb
Host smart-5382b88c-5f95-49df-9e26-a59dc55336e9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18295974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fm
t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt.18295974
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.1226252232
Short name T1105
Test name
Test status
Simulation time 189745142 ps
CPU time 4.1 seconds
Started Jun 26 04:56:29 PM PDT 24
Finished Jun 26 04:56:35 PM PDT 24
Peak memory 204744 kb
Host smart-d1745109-49f6-4455-a1a1-2d4c831bfb6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226252232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
1226252232
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.3177148914
Short name T743
Test name
Test status
Simulation time 3507016263 ps
CPU time 232.37 seconds
Started Jun 26 04:56:27 PM PDT 24
Finished Jun 26 05:00:22 PM PDT 24
Peak memory 1044756 kb
Host smart-db40f3a0-8efd-466a-b651-f38ec2ff4a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177148914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.3177148914
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1697794488
Short name T1010
Test name
Test status
Simulation time 755630740 ps
CPU time 15.79 seconds
Started Jun 26 04:56:34 PM PDT 24
Finished Jun 26 04:56:52 PM PDT 24
Peak memory 204836 kb
Host smart-7cba9b69-07e3-492a-9801-cee8b663b037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697794488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1697794488
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1196802943
Short name T294
Test name
Test status
Simulation time 1892822483 ps
CPU time 30.8 seconds
Started Jun 26 04:56:28 PM PDT 24
Finished Jun 26 04:57:01 PM PDT 24
Peak memory 294936 kb
Host smart-ba66b9cb-416c-4bd6-add5-1ec032e275bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196802943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1196802943
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.2718473205
Short name T1207
Test name
Test status
Simulation time 54093609 ps
CPU time 0.69 seconds
Started Jun 26 04:56:27 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 204528 kb
Host smart-02ae00f4-85a6-48ad-a57d-0ef5755a6c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718473205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.2718473205
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.3293075719
Short name T1431
Test name
Test status
Simulation time 754299627 ps
CPU time 35.18 seconds
Started Jun 26 04:56:30 PM PDT 24
Finished Jun 26 04:57:07 PM PDT 24
Peak memory 312920 kb
Host smart-58a56dfe-9275-4897-94b0-e5ab1f163464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293075719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.3293075719
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.884953447
Short name T212
Test name
Test status
Simulation time 950013059 ps
CPU time 4.07 seconds
Started Jun 26 04:56:23 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 220948 kb
Host smart-7c32b904-3797-4cf4-8219-3db7d0c58ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884953447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.884953447
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.2888249033
Short name T497
Test name
Test status
Simulation time 6147715822 ps
CPU time 18.35 seconds
Started Jun 26 04:56:34 PM PDT 24
Finished Jun 26 04:56:54 PM PDT 24
Peak memory 279104 kb
Host smart-c1212afd-f9c1-428b-8351-4aa9d99336ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888249033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.2888249033
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2869434394
Short name T873
Test name
Test status
Simulation time 2526990193 ps
CPU time 10.02 seconds
Started Jun 26 04:56:24 PM PDT 24
Finished Jun 26 04:56:36 PM PDT 24
Peak memory 221276 kb
Host smart-60425e4d-1a4c-4d91-9fcd-2264155d595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869434394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2869434394
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.4037838354
Short name T729
Test name
Test status
Simulation time 2287987481 ps
CPU time 4.46 seconds
Started Jun 26 04:56:23 PM PDT 24
Finished Jun 26 04:56:29 PM PDT 24
Peak memory 213160 kb
Host smart-170282ca-2a51-4089-b3a9-f70d14f3b1d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037838354 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.4037838354
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3275062723
Short name T984
Test name
Test status
Simulation time 462636464 ps
CPU time 1.49 seconds
Started Jun 26 04:56:27 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 204936 kb
Host smart-22149b5b-a0ed-429f-94bf-61ee47638111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275062723 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3275062723
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2463276746
Short name T1143
Test name
Test status
Simulation time 335844655 ps
CPU time 0.95 seconds
Started Jun 26 04:56:24 PM PDT 24
Finished Jun 26 04:56:28 PM PDT 24
Peak memory 204552 kb
Host smart-93059a72-a6f0-4109-ae50-3cbf19199b59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463276746 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2463276746
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.3562937864
Short name T673
Test name
Test status
Simulation time 1409746398 ps
CPU time 2.11 seconds
Started Jun 26 04:56:32 PM PDT 24
Finished Jun 26 04:56:35 PM PDT 24
Peak memory 204700 kb
Host smart-ba3f30a7-9d2e-4603-b2c7-85fb371a0ae1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562937864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.3562937864
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.4079897086
Short name T649
Test name
Test status
Simulation time 418876986 ps
CPU time 1.07 seconds
Started Jun 26 04:56:35 PM PDT 24
Finished Jun 26 04:56:38 PM PDT 24
Peak memory 204592 kb
Host smart-bedf60db-e6fa-4480-b883-57eeeb7fb393
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079897086 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.4079897086
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.507285373
Short name T1229
Test name
Test status
Simulation time 1128580307 ps
CPU time 4.1 seconds
Started Jun 26 04:56:24 PM PDT 24
Finished Jun 26 04:56:30 PM PDT 24
Peak memory 204744 kb
Host smart-a2075157-d045-4196-a24a-a21c561c5526
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507285373 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.i2c_target_hrst.507285373
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3589314636
Short name T875
Test name
Test status
Simulation time 1284224808 ps
CPU time 6.47 seconds
Started Jun 26 04:56:24 PM PDT 24
Finished Jun 26 04:56:33 PM PDT 24
Peak memory 221048 kb
Host smart-f83c7bb3-b2a4-4739-a509-3f00054a0ca9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589314636 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3589314636
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1530629308
Short name T1331
Test name
Test status
Simulation time 4560329053 ps
CPU time 5.46 seconds
Started Jun 26 04:56:20 PM PDT 24
Finished Jun 26 04:56:28 PM PDT 24
Peak memory 204972 kb
Host smart-667f729a-549a-4f65-b839-964441c3e390
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530629308 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1530629308
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2842415190
Short name T662
Test name
Test status
Simulation time 5117686781 ps
CPU time 17.6 seconds
Started Jun 26 04:56:28 PM PDT 24
Finished Jun 26 04:56:48 PM PDT 24
Peak memory 204860 kb
Host smart-2022ec53-d1bb-4b8b-930f-84df06f80c76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842415190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2842415190
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.567166619
Short name T519
Test name
Test status
Simulation time 1081699176 ps
CPU time 17.12 seconds
Started Jun 26 04:56:28 PM PDT 24
Finished Jun 26 04:56:47 PM PDT 24
Peak memory 217448 kb
Host smart-08ac5f76-46bd-4760-ae93-aa25e21b5f8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567166619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_rd.567166619
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.698520324
Short name T1336
Test name
Test status
Simulation time 36362616806 ps
CPU time 159.17 seconds
Started Jun 26 04:56:23 PM PDT 24
Finished Jun 26 04:59:04 PM PDT 24
Peak memory 2215840 kb
Host smart-e36e23a4-c34f-4ca0-b9fe-84b8e37e4550
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698520324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.698520324
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.3893125338
Short name T739
Test name
Test status
Simulation time 17782966216 ps
CPU time 125.24 seconds
Started Jun 26 04:56:23 PM PDT 24
Finished Jun 26 04:58:31 PM PDT 24
Peak memory 1164692 kb
Host smart-ad44b3a9-65fe-45ce-9717-a9720f41b519
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893125338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.3893125338
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3799707099
Short name T1391
Test name
Test status
Simulation time 5328359727 ps
CPU time 7.85 seconds
Started Jun 26 04:56:28 PM PDT 24
Finished Jun 26 04:56:38 PM PDT 24
Peak memory 213608 kb
Host smart-a859cf79-75c7-4a44-b4a1-615b0ab609c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799707099 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3799707099
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.4164517690
Short name T1187
Test name
Test status
Simulation time 19450676 ps
CPU time 0.62 seconds
Started Jun 26 04:56:37 PM PDT 24
Finished Jun 26 04:56:39 PM PDT 24
Peak memory 204504 kb
Host smart-efe1fb16-cf2a-4df2-b478-98e7f2ebaa6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164517690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.4164517690
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3954225496
Short name T961
Test name
Test status
Simulation time 893741709 ps
CPU time 3.82 seconds
Started Jun 26 04:56:58 PM PDT 24
Finished Jun 26 04:57:03 PM PDT 24
Peak memory 235816 kb
Host smart-a9502935-6d01-483e-8cf5-c5a5f4473b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954225496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3954225496
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.954247579
Short name T1082
Test name
Test status
Simulation time 234426741 ps
CPU time 10.81 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 04:56:46 PM PDT 24
Peak memory 241512 kb
Host smart-d685e967-80fe-4a4d-bd30-7762d06baffb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954247579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.954247579
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2236965023
Short name T80
Test name
Test status
Simulation time 9739317634 ps
CPU time 127.74 seconds
Started Jun 26 04:56:34 PM PDT 24
Finished Jun 26 04:58:44 PM PDT 24
Peak memory 405732 kb
Host smart-2049116d-2905-4fb6-8b5e-10fa83bdf7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236965023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2236965023
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1258513450
Short name T693
Test name
Test status
Simulation time 2408594660 ps
CPU time 71.67 seconds
Started Jun 26 04:56:32 PM PDT 24
Finished Jun 26 04:57:45 PM PDT 24
Peak memory 764672 kb
Host smart-ba0546e4-fc2b-4bf5-8538-2aa891edd42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258513450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1258513450
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.4011013308
Short name T572
Test name
Test status
Simulation time 463204129 ps
CPU time 1.07 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 04:56:35 PM PDT 24
Peak memory 204484 kb
Host smart-f71c3bce-1c50-4654-8103-a319fdcd05a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011013308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.4011013308
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1207436934
Short name T986
Test name
Test status
Simulation time 750124419 ps
CPU time 4.02 seconds
Started Jun 26 04:56:38 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 204832 kb
Host smart-674f1f4f-0e32-481d-9e82-4737ccc7a7fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207436934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1207436934
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2060919928
Short name T509
Test name
Test status
Simulation time 29593368839 ps
CPU time 241.17 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 05:00:36 PM PDT 24
Peak memory 1093068 kb
Host smart-424bc222-c14f-445e-a0a6-2fbba3e64f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060919928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2060919928
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.2045301005
Short name T1419
Test name
Test status
Simulation time 544509782 ps
CPU time 11.09 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 04:56:45 PM PDT 24
Peak memory 204756 kb
Host smart-3aaa0e51-c328-480e-b6a1-2f0b0257dac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045301005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.2045301005
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.3651505097
Short name T1474
Test name
Test status
Simulation time 11730290316 ps
CPU time 39.23 seconds
Started Jun 26 04:56:32 PM PDT 24
Finished Jun 26 04:57:13 PM PDT 24
Peak memory 357992 kb
Host smart-f8b00f61-4c82-4d03-80fc-896ac0fb5d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651505097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.3651505097
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.2486853328
Short name T1092
Test name
Test status
Simulation time 28173037 ps
CPU time 0.69 seconds
Started Jun 26 04:56:32 PM PDT 24
Finished Jun 26 04:56:34 PM PDT 24
Peak memory 204484 kb
Host smart-e7438e33-89b3-45a9-b7a0-856786061a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486853328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.2486853328
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.1924595176
Short name T1033
Test name
Test status
Simulation time 7722565367 ps
CPU time 543.96 seconds
Started Jun 26 04:56:35 PM PDT 24
Finished Jun 26 05:05:41 PM PDT 24
Peak memory 1154948 kb
Host smart-f4e43bc9-84a3-4b19-adff-eb9095c953b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924595176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.1924595176
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.4146635302
Short name T1262
Test name
Test status
Simulation time 677034346 ps
CPU time 5.44 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 04:56:40 PM PDT 24
Peak memory 204812 kb
Host smart-3aa5f3b5-9940-48d8-8d52-09c922131d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146635302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.4146635302
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1195090132
Short name T1282
Test name
Test status
Simulation time 1642458921 ps
CPU time 73.58 seconds
Started Jun 26 04:56:37 PM PDT 24
Finished Jun 26 04:57:52 PM PDT 24
Peak memory 358120 kb
Host smart-91319599-3bec-490b-8f0e-ea54cd3e19fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195090132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1195090132
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2539072040
Short name T947
Test name
Test status
Simulation time 31407073526 ps
CPU time 264.74 seconds
Started Jun 26 04:56:34 PM PDT 24
Finished Jun 26 05:01:01 PM PDT 24
Peak memory 1306244 kb
Host smart-cf0f2cde-9749-4f79-99b1-050008f9130d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539072040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2539072040
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2131878687
Short name T672
Test name
Test status
Simulation time 2954710245 ps
CPU time 12.24 seconds
Started Jun 26 04:56:36 PM PDT 24
Finished Jun 26 04:56:50 PM PDT 24
Peak memory 221304 kb
Host smart-6c905790-78f4-4565-b8d7-10c8cd5f5d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131878687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2131878687
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.2835565395
Short name T1086
Test name
Test status
Simulation time 1899162975 ps
CPU time 4.72 seconds
Started Jun 26 04:56:35 PM PDT 24
Finished Jun 26 04:56:42 PM PDT 24
Peak memory 204892 kb
Host smart-56af4827-1d4e-4ae9-8223-6956db187617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835565395 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.2835565395
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2869829408
Short name T696
Test name
Test status
Simulation time 211876149 ps
CPU time 1.32 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 04:56:36 PM PDT 24
Peak memory 204632 kb
Host smart-8eb4ee41-eff4-4c9a-a28d-fa136ab11290
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869829408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2869829408
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.2367433907
Short name T768
Test name
Test status
Simulation time 191744980 ps
CPU time 1.22 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 04:56:36 PM PDT 24
Peak memory 204592 kb
Host smart-b01c8f88-941c-4825-950e-87f7e639cee7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367433907 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.2367433907
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.2555251359
Short name T556
Test name
Test status
Simulation time 1438054757 ps
CPU time 2.02 seconds
Started Jun 26 04:56:35 PM PDT 24
Finished Jun 26 04:56:39 PM PDT 24
Peak memory 204696 kb
Host smart-f149a059-22fb-451e-aebd-454a52276961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555251359 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.2555251359
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.4239102081
Short name T1374
Test name
Test status
Simulation time 112242144 ps
CPU time 1.13 seconds
Started Jun 26 04:56:32 PM PDT 24
Finished Jun 26 04:56:35 PM PDT 24
Peak memory 204592 kb
Host smart-66866676-edb8-41f7-a167-b147255e4954
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239102081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.4239102081
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.2007037568
Short name T407
Test name
Test status
Simulation time 408167408 ps
CPU time 3.5 seconds
Started Jun 26 04:56:32 PM PDT 24
Finished Jun 26 04:56:36 PM PDT 24
Peak memory 204744 kb
Host smart-f1f54517-9bf2-4e24-917a-dd7381766761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007037568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.2007037568
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.1346582847
Short name T406
Test name
Test status
Simulation time 3828809837 ps
CPU time 4.8 seconds
Started Jun 26 04:56:37 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 218132 kb
Host smart-9d7e4873-6b4d-4c28-a464-36179ca7d4f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346582847 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.1346582847
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2243200096
Short name T689
Test name
Test status
Simulation time 9028651158 ps
CPU time 17.17 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 04:56:52 PM PDT 24
Peak memory 616980 kb
Host smart-ac108997-5260-4378-bfe2-44b2e0e2bc37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243200096 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2243200096
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.1882398295
Short name T1387
Test name
Test status
Simulation time 6300494687 ps
CPU time 8.48 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 04:56:44 PM PDT 24
Peak memory 204992 kb
Host smart-70e13311-bbee-4910-893e-9c14c02781d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882398295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.1882398295
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.294454536
Short name T702
Test name
Test status
Simulation time 935582380 ps
CPU time 40.05 seconds
Started Jun 26 04:56:32 PM PDT 24
Finished Jun 26 04:57:13 PM PDT 24
Peak memory 204768 kb
Host smart-b03d860b-5e36-4fe6-818a-864d4438873d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294454536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_rd.294454536
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.3849564596
Short name T1266
Test name
Test status
Simulation time 49504737697 ps
CPU time 1147.24 seconds
Started Jun 26 04:56:33 PM PDT 24
Finished Jun 26 05:15:42 PM PDT 24
Peak memory 7262160 kb
Host smart-01934cc1-f2e6-4e81-ae84-045da1dc2313
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849564596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.3849564596
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.1267273379
Short name T367
Test name
Test status
Simulation time 35687508331 ps
CPU time 900.62 seconds
Started Jun 26 04:56:32 PM PDT 24
Finished Jun 26 05:11:34 PM PDT 24
Peak memory 2546492 kb
Host smart-6457596f-1f4b-4a59-aca0-073f8e4e4e94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267273379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.1267273379
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.851024119
Short name T307
Test name
Test status
Simulation time 2615992401 ps
CPU time 6.57 seconds
Started Jun 26 04:56:35 PM PDT 24
Finished Jun 26 04:56:43 PM PDT 24
Peak memory 204956 kb
Host smart-93aabbd9-eafe-43be-bb11-dc2b70793cd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851024119 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.851024119
Directory /workspace/9.i2c_target_timeout/latest
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