Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1031986	1			T1	3		T2	87		T3	2
all_values[1]	1031986	1			T1	3		T2	87		T3	2
all_values[2]	1031986	1			T1	3		T2	87		T3	2
all_values[3]	1031986	1			T1	3		T2	87		T3	2
all_values[4]	1031986	1			T1	3		T2	87		T3	2
all_values[5]	1031986	1			T1	3		T2	87		T3	2
all_values[6]	1031986	1			T1	3		T2	87		T3	2
all_values[7]	1031986	1			T1	3		T2	87		T3	2
all_values[8]	1031986	1			T1	3		T2	87		T3	2
all_values[9]	1031986	1			T1	3		T2	87		T3	2
all_values[10]	1031986	1			T1	3		T2	87		T3	2
all_values[11]	1031986	1			T1	3		T2	87		T3	2
all_values[12]	1031986	1			T1	3		T2	87		T3	2
all_values[13]	1031986	1			T1	3		T2	87		T3	2
all_values[14]	1031986	1			T1	3		T2	87		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12662002

1

T1

39

T2

1137

T3

30

auto[1]

2817788

1

T1

6

T2

168

T4

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13380668

1

T1

45

T2

1305

T3

30

auto[1]

2099122

1

T38

248013

T37

50288

T39

2733

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103101	1			T1	1		T2	3		T3	2
all_values[0]	auto[0]	auto[1]	12562	1			T38	2534		T37	291		T39	13
all_values[0]	auto[1]	auto[0]	783210	1			T1	2		T2	84		T4	4
all_values[0]	auto[1]	auto[1]	133113	1			T38	14001		T37	3301		T39	170
all_values[1]	auto[0]	auto[0]	885859	1			T1	3		T2	87		T3	2
all_values[1]	auto[0]	auto[1]	145409	1			T38	16530		T37	3576		T39	179
all_values[1]	auto[1]	auto[0]	421	1			T8	3		T9	33		T81	1
all_values[1]	auto[1]	auto[1]	297	1			T38	3		T37	14		T39	3
all_values[2]	auto[0]	auto[0]	892450	1			T1	3		T2	87		T3	2
all_values[2]	auto[0]	auto[1]	139282	1			T38	16530		T37	3587		T39	178
all_values[2]	auto[1]	auto[0]	51	1			T4	1		T21	1		T258	1
all_values[2]	auto[1]	auto[1]	203	1			T38	5		T37	5		T39	1
all_values[3]	auto[0]	auto[0]	886333	1			T1	3		T2	87		T3	2
all_values[3]	auto[0]	auto[1]	145423	1			T38	16523		T37	3586		T39	177
all_values[3]	auto[1]	auto[1]	230	1			T38	12		T37	5		T39	3
all_values[4]	auto[0]	auto[0]	888605	1			T1	3		T2	87		T3	2
all_values[4]	auto[0]	auto[1]	143159	1			T38	16526		T37	3585		T39	180
all_values[4]	auto[1]	auto[0]	13	1			T45	1		T259	2		T260	1
all_values[4]	auto[1]	auto[1]	209	1			T38	9		T37	6		T39	3
all_values[5]	auto[0]	auto[0]	886317	1			T1	3		T2	87		T3	2
all_values[5]	auto[0]	auto[1]	145441	1			T38	16526		T37	3585		T39	179
all_values[5]	auto[1]	auto[1]	228	1			T38	9		T37	6		T39	5
all_values[6]	auto[0]	auto[0]	894643	1			T1	3		T2	87		T3	2
all_values[6]	auto[0]	auto[1]	137089	1			T38	16527		T37	3588		T39	181
all_values[6]	auto[1]	auto[1]	254	1			T38	7		T37	3		T39	2
all_values[7]	auto[0]	auto[0]	866834	1			T1	2		T2	87		T3	2
all_values[7]	auto[0]	auto[1]	134557	1			T38	16252		T37	8		T39	151
all_values[7]	auto[1]	auto[0]	27398	1			T1	1		T7	39		T8	84
all_values[7]	auto[1]	auto[1]	3197	1			T38	283		T37	1		T39	29
all_values[8]	auto[0]	auto[0]	929035	1			T1	3		T2	87		T3	2
all_values[8]	auto[0]	auto[1]	102720	1			T38	16529		T37	3584		T39	180
all_values[8]	auto[1]	auto[1]	231	1			T38	4		T37	8		T39	1
all_values[9]	auto[0]	auto[0]	180897	1			T1	2		T2	87		T3	2
all_values[9]	auto[0]	auto[1]	11960	1			T38	1386		T37	79		T39	169
all_values[9]	auto[1]	auto[0]	711411	1			T1	1		T4	1		T5	1
all_values[9]	auto[1]	auto[1]	127718	1			T38	15146		T37	3512		T39	14
all_values[10]	auto[0]	auto[0]	886311	1			T1	3		T2	87		T3	2
all_values[10]	auto[0]	auto[1]	145443	1			T38	16525		T37	3585		T39	181
all_values[10]	auto[1]	auto[1]	232	1			T38	9		T37	7		T39	3
all_values[11]	auto[0]	auto[0]	2818	1			T1	1		T2	3		T3	2
all_values[11]	auto[0]	auto[1]	488	1			T38	26		T37	15		T39	5
all_values[11]	auto[1]	auto[0]	883827	1			T1	2		T2	84		T4	4
all_values[11]	auto[1]	auto[1]	144853	1			T38	16509		T37	3577		T39	176
all_values[12]	auto[0]	auto[0]	886291	1			T1	3		T2	87		T3	2
all_values[12]	auto[0]	auto[1]	145485	1			T38	16531		T37	3587		T39	180
all_values[12]	auto[1]	auto[0]	13	1			T261	1		T262	1		T263	1
all_values[12]	auto[1]	auto[1]	197	1			T38	3		T37	4		T39	3
all_values[13]	auto[0]	auto[0]	892486	1			T1	3		T2	87		T3	2
all_values[13]	auto[0]	auto[1]	139251	1			T38	16525		T37	3586		T39	181
all_values[13]	auto[1]	auto[1]	249	1			T38	10		T37	5		T39	3
all_values[14]	auto[0]	auto[0]	892344	1			T1	3		T2	87		T3	2
all_values[14]	auto[0]	auto[1]	139409	1			T38	16526		T37	3587		T39	177
all_values[14]	auto[1]	auto[1]	233	1			T38	7		T37	5		T39	6