Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1031986	1			T1	3		T2	87		T3	2
all_pins[1]	1031986	1			T1	3		T2	87		T3	2
all_pins[2]	1031986	1			T1	3		T2	87		T3	2
all_pins[3]	1031986	1			T1	3		T2	87		T3	2
all_pins[4]	1031986	1			T1	3		T2	87		T3	2
all_pins[5]	1031986	1			T1	3		T2	87		T3	2
all_pins[6]	1031986	1			T1	3		T2	87		T3	2
all_pins[7]	1031986	1			T1	3		T2	87		T3	2
all_pins[8]	1031986	1			T1	3		T2	87		T3	2
all_pins[9]	1031986	1			T1	3		T2	87		T3	2
all_pins[10]	1031986	1			T1	3		T2	87		T3	2
all_pins[11]	1031986	1			T1	3		T2	87		T3	2
all_pins[12]	1031986	1			T1	3		T2	87		T3	2
all_pins[13]	1031986	1			T1	3		T2	87		T3	2
all_pins[14]	1031986	1			T1	3		T2	87		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	12666719	1			T1	39		T2	1137		T3	30
values[0x1]	2813071	1			T1	6		T2	168		T4	10
transitions[0x0=>0x1]	2812004	1			T1	6		T2	168		T4	10
transitions[0x1=>0x0]	2810853	1			T1	5		T2	167		T4	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	118912	1			T1	1		T2	3		T3	2
all_pins[0]	values[0x1]	913074	1			T1	2		T2	84		T4	4
all_pins[0]	transitions[0x0=>0x1]	912435	1			T1	2		T2	84		T4	4
all_pins[0]	transitions[0x1=>0x0]	79	1			T38	2		T37	2		T39	2
all_pins[1]	values[0x0]	1031268	1			T1	3		T2	87		T3	2
all_pins[1]	values[0x1]	718	1			T8	3		T9	36		T38	2
all_pins[1]	transitions[0x0=>0x1]	693	1			T8	3		T9	36		T38	2
all_pins[1]	transitions[0x1=>0x0]	137	1			T4	1		T21	1		T38	3
all_pins[2]	values[0x0]	1031824	1			T1	3		T2	87		T3	2
all_pins[2]	values[0x1]	162	1			T4	1		T21	1		T38	3
all_pins[2]	transitions[0x0=>0x1]	130	1			T4	1		T21	1		T38	1
all_pins[2]	transitions[0x1=>0x0]	79	1			T38	5		T37	1		T39	1
all_pins[3]	values[0x0]	1031875	1			T1	3		T2	87		T3	2
all_pins[3]	values[0x1]	111	1			T38	7		T37	2		T39	1
all_pins[3]	transitions[0x0=>0x1]	87	1			T38	5		T37	2		T39	1
all_pins[3]	transitions[0x1=>0x0]	101	1			T38	1		T37	3		T39	2
all_pins[4]	values[0x0]	1031861	1			T1	3		T2	87		T3	2
all_pins[4]	values[0x1]	125	1			T38	3		T37	3		T39	2
all_pins[4]	transitions[0x0=>0x1]	101	1			T38	1		T37	3		T39	1
all_pins[4]	transitions[0x1=>0x0]	84	1			T38	1		T37	1		T39	3
all_pins[5]	values[0x0]	1031878	1			T1	3		T2	87		T3	2
all_pins[5]	values[0x1]	108	1			T38	3		T37	1		T39	4
all_pins[5]	transitions[0x0=>0x1]	86	1			T38	3		T37	1		T39	2
all_pins[5]	transitions[0x1=>0x0]	98	1			T52	3		T55	4		T281	2
all_pins[6]	values[0x0]	1031866	1			T1	3		T2	87		T3	2
all_pins[6]	values[0x1]	120	1			T39	2		T52	3		T55	4
all_pins[6]	transitions[0x0=>0x1]	89	1			T39	2		T52	3		T55	4
all_pins[6]	transitions[0x1=>0x0]	33832	1			T1	1		T7	41		T8	88
all_pins[7]	values[0x0]	998123	1			T1	2		T2	87		T3	2
all_pins[7]	values[0x1]	33863	1			T1	1		T7	41		T8	88
all_pins[7]	transitions[0x0=>0x1]	33836	1			T1	1		T7	41		T8	88
all_pins[7]	transitions[0x1=>0x0]	81	1			T38	1		T37	5		T52	2
all_pins[8]	values[0x0]	1031878	1			T1	3		T2	87		T3	2
all_pins[8]	values[0x1]	108	1			T38	1		T37	5		T52	2
all_pins[8]	transitions[0x0=>0x1]	70	1			T38	1		T37	4		T282	1
all_pins[8]	transitions[0x1=>0x0]	839010	1			T1	1		T4	1		T5	1
all_pins[9]	values[0x0]	192938	1			T1	2		T2	87		T3	2
all_pins[9]	values[0x1]	839048	1			T1	1		T4	1		T5	1
all_pins[9]	transitions[0x0=>0x1]	839015	1			T1	1		T4	1		T5	1
all_pins[9]	transitions[0x1=>0x0]	86	1			T38	4		T37	4		T39	1
all_pins[10]	values[0x0]	1031867	1			T1	3		T2	87		T3	2
all_pins[10]	values[0x1]	119	1			T38	4		T37	5		T39	1
all_pins[10]	transitions[0x0=>0x1]	83	1			T38	3		T37	2		T39	1
all_pins[10]	transitions[0x1=>0x0]	1025125	1			T1	2		T2	84		T4	4
all_pins[11]	values[0x0]	6825	1			T1	1		T2	3		T3	2
all_pins[11]	values[0x1]	1025161	1			T1	2		T2	84		T4	4
all_pins[11]	transitions[0x0=>0x1]	1025111	1			T1	2		T2	84		T4	4
all_pins[11]	transitions[0x1=>0x0]	67	1			T38	1		T37	1		T39	3
all_pins[12]	values[0x0]	1031869	1			T1	3		T2	87		T3	2
all_pins[12]	values[0x1]	117	1			T21	1		T38	1		T37	2
all_pins[12]	transitions[0x0=>0x1]	95	1			T21	1		T38	1		T37	2
all_pins[12]	transitions[0x1=>0x0]	104	1			T38	6		T37	3		T39	1
all_pins[13]	values[0x0]	1031860	1			T1	3		T2	87		T3	2
all_pins[13]	values[0x1]	126	1			T38	6		T37	3		T39	2
all_pins[13]	transitions[0x0=>0x1]	103	1			T38	6		T37	1		T39	2
all_pins[13]	transitions[0x1=>0x0]	88	1			T38	2		T37	3		T39	1
all_pins[14]	values[0x0]	1031875	1			T1	3		T2	87		T3	2
all_pins[14]	values[0x1]	111	1			T38	2		T37	5		T39	1
all_pins[14]	transitions[0x0=>0x1]	70	1			T38	2		T37	3		T39	1
all_pins[14]	transitions[0x1=>0x0]	911882	1			T1	1		T2	83		T4	3