Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	516	1			T38	14		T37	11		T39	7
all_values[1]	516	1			T38	14		T37	11		T39	7
all_values[2]	516	1			T38	14		T37	11		T39	7
all_values[3]	516	1			T38	14		T37	11		T39	7
all_values[4]	516	1			T38	14		T37	11		T39	7
all_values[5]	516	1			T38	14		T37	11		T39	7
all_values[6]	516	1			T38	14		T37	11		T39	7
all_values[7]	516	1			T38	14		T37	11		T39	7
all_values[8]	516	1			T38	14		T37	11		T39	7
all_values[9]	516	1			T38	14		T37	11		T39	7
all_values[10]	516	1			T38	14		T37	11		T39	7
all_values[11]	516	1			T38	14		T37	11		T39	7
all_values[12]	516	1			T38	14		T37	11		T39	7
all_values[13]	516	1			T38	14		T37	11		T39	7
all_values[14]	516	1			T38	14		T37	11		T39	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3976

1

T38

115

T37

67

T39

50

auto[1]

3764

1

T38

95

T37

98

T39

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1330

1

T38

12

T37

13

T39

27

auto[1]

6410

1

T38

198

T37

152

T39

78

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4596

1

T38

124

T37

89

T39

67

auto[1]

3144

1

T38

86

T37

76

T39

38

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	55	1			T39	1		T55	7		T159	2
all_values[0]	auto[0]	auto[0]	auto[1]	97	1			T38	9		T37	1		T39	1
all_values[0]	auto[0]	auto[1]	auto[0]	36	1			T282	1		T55	4		T283	1
all_values[0]	auto[0]	auto[1]	auto[1]	108	1			T37	6		T39	4		T52	2
all_values[0]	auto[1]	auto[0]	auto[1]	105	1			T38	4		T37	1		T52	2
all_values[0]	auto[1]	auto[1]	auto[1]	115	1			T38	1		T37	3		T39	1
all_values[1]	auto[0]	auto[0]	auto[0]	38	1			T38	1		T39	1		T52	2
all_values[1]	auto[0]	auto[0]	auto[1]	114	1			T38	5		T37	3		T282	1
all_values[1]	auto[0]	auto[1]	auto[0]	25	1			T38	1		T37	2		T39	1
all_values[1]	auto[0]	auto[1]	auto[1]	114	1			T38	4		T37	2		T39	2
all_values[1]	auto[1]	auto[0]	auto[1]	111	1			T38	1		T37	3		T39	2
all_values[1]	auto[1]	auto[1]	auto[1]	114	1			T38	2		T37	1		T39	1
all_values[2]	auto[0]	auto[0]	auto[0]	42	1			T39	4		T52	1		T281	6
all_values[2]	auto[0]	auto[0]	auto[1]	111	1			T38	4		T37	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	44	1			T39	1		T52	2		T282	1
all_values[2]	auto[0]	auto[1]	auto[1]	116	1			T38	5		T37	5		T52	2
all_values[2]	auto[1]	auto[0]	auto[1]	105	1			T38	2		T39	1		T52	1
all_values[2]	auto[1]	auto[1]	auto[1]	98	1			T38	3		T37	5		T282	2
all_values[3]	auto[0]	auto[0]	auto[0]	67	1			T39	1		T52	1		T281	3
all_values[3]	auto[0]	auto[0]	auto[1]	110	1			T38	3		T37	1		T39	1
all_values[3]	auto[0]	auto[1]	auto[0]	39	1			T37	1		T39	3		T52	1
all_values[3]	auto[0]	auto[1]	auto[1]	99	1			T38	4		T37	3		T39	1
all_values[3]	auto[1]	auto[0]	auto[1]	110	1			T38	4		T37	3		T39	1
all_values[3]	auto[1]	auto[1]	auto[1]	91	1			T38	3		T37	3		T52	1
all_values[4]	auto[0]	auto[0]	auto[0]	37	1			T55	2		T159	1		T284	4
all_values[4]	auto[0]	auto[0]	auto[1]	110	1			T38	5		T37	2		T39	1
all_values[4]	auto[0]	auto[1]	auto[0]	42	1			T37	1		T39	1		T244	1
all_values[4]	auto[0]	auto[1]	auto[1]	118	1			T37	2		T39	2		T52	1
all_values[4]	auto[1]	auto[0]	auto[1]	100	1			T38	6		T37	1		T39	3
all_values[4]	auto[1]	auto[1]	auto[1]	109	1			T38	3		T37	5		T52	3
all_values[5]	auto[0]	auto[0]	auto[0]	51	1			T282	1		T244	3		T55	1
all_values[5]	auto[0]	auto[0]	auto[1]	111	1			T38	6		T37	4		T52	3
all_values[5]	auto[0]	auto[1]	auto[0]	40	1			T37	1		T282	3		T244	1
all_values[5]	auto[0]	auto[1]	auto[1]	114	1			T38	1		T37	3		T39	4
all_values[5]	auto[1]	auto[0]	auto[1]	104	1			T38	2		T37	1		T39	1
all_values[5]	auto[1]	auto[1]	auto[1]	96	1			T38	5		T37	2		T39	2
all_values[6]	auto[0]	auto[0]	auto[0]	48	1			T39	1		T282	1		T244	1
all_values[6]	auto[0]	auto[0]	auto[1]	99	1			T38	4		T37	1		T39	1
all_values[6]	auto[0]	auto[1]	auto[0]	52	1			T38	1		T37	1		T52	1
all_values[6]	auto[0]	auto[1]	auto[1]	110	1			T38	3		T37	4		T39	2
all_values[6]	auto[1]	auto[0]	auto[1]	121	1			T38	5		T37	3		T52	2
all_values[6]	auto[1]	auto[1]	auto[1]	86	1			T38	1		T37	2		T39	3
all_values[7]	auto[0]	auto[0]	auto[0]	68	1			T37	1		T39	2		T52	2
all_values[7]	auto[0]	auto[0]	auto[1]	97	1			T38	3		T37	2		T39	1
all_values[7]	auto[0]	auto[1]	auto[0]	53	1			T37	3		T39	2		T244	5
all_values[7]	auto[0]	auto[1]	auto[1]	101	1			T38	5		T37	2		T282	1
all_values[7]	auto[1]	auto[0]	auto[1]	109	1			T38	2		T37	2		T39	1
all_values[7]	auto[1]	auto[1]	auto[1]	88	1			T38	4		T37	1		T39	1
all_values[8]	auto[0]	auto[0]	auto[0]	52	1			T52	3		T281	1		T284	1
all_values[8]	auto[0]	auto[0]	auto[1]	121	1			T38	5		T37	2		T39	1
all_values[8]	auto[0]	auto[1]	auto[0]	46	1			T38	2		T39	3		T282	1
all_values[8]	auto[0]	auto[1]	auto[1]	97	1			T38	3		T37	3		T39	1
all_values[8]	auto[1]	auto[0]	auto[1]	108	1			T38	4		T39	1		T52	1
all_values[8]	auto[1]	auto[1]	auto[1]	92	1			T37	6		T39	1		T52	2
all_values[9]	auto[0]	auto[0]	auto[0]	43	1			T38	1		T55	3		T281	2
all_values[9]	auto[0]	auto[0]	auto[1]	109	1			T38	8		T37	2		T39	1
all_values[9]	auto[0]	auto[1]	auto[0]	42	1			T38	2		T37	1		T39	1
all_values[9]	auto[0]	auto[1]	auto[1]	98	1			T39	1		T52	1		T244	2
all_values[9]	auto[1]	auto[0]	auto[1]	107	1			T38	2		T37	6		T39	2
all_values[9]	auto[1]	auto[1]	auto[1]	117	1			T38	1		T37	2		T39	2
all_values[10]	auto[0]	auto[0]	auto[0]	38	1			T284	1		T279	4		T285	3
all_values[10]	auto[0]	auto[0]	auto[1]	114	1			T38	1		T39	1		T52	2
all_values[10]	auto[0]	auto[1]	auto[0]	31	1			T38	1		T52	2		T282	2
all_values[10]	auto[0]	auto[1]	auto[1]	101	1			T38	3		T37	4		T39	3
all_values[10]	auto[1]	auto[0]	auto[1]	115	1			T38	3		T37	3		T39	1
all_values[10]	auto[1]	auto[1]	auto[1]	117	1			T38	6		T37	4		T39	2
all_values[11]	auto[0]	auto[0]	auto[0]	43	1			T39	1		T52	1		T55	2
all_values[11]	auto[0]	auto[0]	auto[1]	115	1			T38	3		T37	3		T39	2
all_values[11]	auto[0]	auto[1]	auto[0]	36	1			T39	2		T282	1		T281	2
all_values[11]	auto[0]	auto[1]	auto[1]	109	1			T38	5		T37	2		T52	2
all_values[11]	auto[1]	auto[0]	auto[1]	105	1			T38	1		T37	3		T39	2
all_values[11]	auto[1]	auto[1]	auto[1]	108	1			T38	5		T37	3		T52	1
all_values[12]	auto[0]	auto[0]	auto[0]	36	1			T39	1		T55	1		T159	2
all_values[12]	auto[0]	auto[0]	auto[1]	125	1			T38	4		T37	4		T39	1
all_values[12]	auto[0]	auto[1]	auto[0]	49	1			T38	1		T37	1		T100	1
all_values[12]	auto[0]	auto[1]	auto[1]	109	1			T38	6		T37	2		T39	2
all_values[12]	auto[1]	auto[0]	auto[1]	103	1			T38	3		T37	4		T282	1
all_values[12]	auto[1]	auto[1]	auto[1]	94	1			T39	3		T52	2		T282	1
all_values[13]	auto[0]	auto[0]	auto[0]	37	1			T159	2		T284	3		T121	1
all_values[13]	auto[0]	auto[0]	auto[1]	106	1			T38	1		T37	5		T39	3
all_values[13]	auto[0]	auto[1]	auto[0]	40	1			T37	1		T284	1		T216	2
all_values[13]	auto[0]	auto[1]	auto[1]	125	1			T38	3		T37	1		T39	1
all_values[13]	auto[1]	auto[0]	auto[1]	111	1			T38	4		T37	2		T39	2
all_values[13]	auto[1]	auto[1]	auto[1]	97	1			T38	6		T37	2		T39	1
all_values[14]	auto[0]	auto[0]	auto[0]	49	1			T39	1		T52	1		T282	1
all_values[14]	auto[0]	auto[0]	auto[1]	100	1			T38	8		T37	2		T39	1
all_values[14]	auto[0]	auto[1]	auto[0]	51	1			T38	2		T244	3		T284	1
all_values[14]	auto[0]	auto[1]	auto[1]	108	1			T38	1		T37	4		T39	1
all_values[14]	auto[1]	auto[0]	auto[1]	119	1			T38	1		T37	1		T39	4
all_values[14]	auto[1]	auto[1]	auto[1]	89	1			T38	2		T37	4		T52	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal