Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.75 96.57 89.50 97.22 69.05 93.55 98.44 90.95


Total test records in report: 1594
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html
T1516 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1801022027 Jun 27 04:44:35 PM PDT 24 Jun 27 04:44:37 PM PDT 24 24153851 ps
T1517 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2814673519 Jun 27 04:44:17 PM PDT 24 Jun 27 04:44:24 PM PDT 24 168917910 ps
T1518 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4213094241 Jun 27 04:44:09 PM PDT 24 Jun 27 04:44:18 PM PDT 24 26229190 ps
T1519 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1037554281 Jun 27 04:44:25 PM PDT 24 Jun 27 04:44:30 PM PDT 24 97074666 ps
T1520 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1138713890 Jun 27 04:44:33 PM PDT 24 Jun 27 04:44:35 PM PDT 24 85363945 ps
T223 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3951441964 Jun 27 04:44:06 PM PDT 24 Jun 27 04:44:14 PM PDT 24 19845547 ps
T1521 /workspace/coverage/cover_reg_top/3.i2c_intr_test.3593699597 Jun 27 04:44:08 PM PDT 24 Jun 27 04:44:15 PM PDT 24 25436777 ps
T1522 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2681185771 Jun 27 04:44:40 PM PDT 24 Jun 27 04:44:43 PM PDT 24 136104242 ps
T1523 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1475915895 Jun 27 04:44:19 PM PDT 24 Jun 27 04:44:25 PM PDT 24 191636709 ps
T1524 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2403146363 Jun 27 04:44:17 PM PDT 24 Jun 27 04:44:23 PM PDT 24 22605949 ps
T1525 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4224468692 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:19 PM PDT 24 218988633 ps
T1526 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2118481042 Jun 27 04:44:18 PM PDT 24 Jun 27 04:44:24 PM PDT 24 84592398 ps
T1527 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3972915213 Jun 27 04:44:08 PM PDT 24 Jun 27 04:44:16 PM PDT 24 56922505 ps
T153 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3346594992 Jun 27 04:44:35 PM PDT 24 Jun 27 04:44:38 PM PDT 24 130866487 ps
T1528 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4124531500 Jun 27 04:44:07 PM PDT 24 Jun 27 04:44:15 PM PDT 24 39831170 ps
T1529 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1923500019 Jun 27 04:44:28 PM PDT 24 Jun 27 04:44:33 PM PDT 24 22515102 ps
T1530 /workspace/coverage/cover_reg_top/45.i2c_intr_test.1693254395 Jun 27 04:44:27 PM PDT 24 Jun 27 04:44:31 PM PDT 24 51888108 ps
T1531 /workspace/coverage/cover_reg_top/22.i2c_intr_test.2284607923 Jun 27 04:44:25 PM PDT 24 Jun 27 04:44:30 PM PDT 24 50167884 ps
T207 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3645928345 Jun 27 04:44:07 PM PDT 24 Jun 27 04:44:15 PM PDT 24 187457702 ps
T1532 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.4105472313 Jun 27 04:44:11 PM PDT 24 Jun 27 04:44:19 PM PDT 24 43256176 ps
T1533 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.798700271 Jun 27 04:44:36 PM PDT 24 Jun 27 04:44:40 PM PDT 24 50934628 ps
T1534 /workspace/coverage/cover_reg_top/36.i2c_intr_test.3415880399 Jun 27 04:44:23 PM PDT 24 Jun 27 04:44:28 PM PDT 24 19414604 ps
T206 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.512355830 Jun 27 04:44:16 PM PDT 24 Jun 27 04:44:25 PM PDT 24 87648391 ps
T1535 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2049531080 Jun 27 04:44:36 PM PDT 24 Jun 27 04:44:38 PM PDT 24 34533361 ps
T1536 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.911118624 Jun 27 04:44:07 PM PDT 24 Jun 27 04:44:15 PM PDT 24 189742619 ps
T154 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2105586618 Jun 27 04:44:33 PM PDT 24 Jun 27 04:44:37 PM PDT 24 284003074 ps
T1537 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.571481877 Jun 27 04:44:08 PM PDT 24 Jun 27 04:44:16 PM PDT 24 53691122 ps
T1538 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4072576965 Jun 27 04:44:19 PM PDT 24 Jun 27 04:44:25 PM PDT 24 73621507 ps
T1539 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.87684714 Jun 27 04:44:25 PM PDT 24 Jun 27 04:44:32 PM PDT 24 154301602 ps
T1540 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4253667438 Jun 27 04:44:05 PM PDT 24 Jun 27 04:44:14 PM PDT 24 286470125 ps
T1541 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3871816681 Jun 27 04:44:39 PM PDT 24 Jun 27 04:44:42 PM PDT 24 174540081 ps
T1542 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3433779813 Jun 27 04:44:11 PM PDT 24 Jun 27 04:44:19 PM PDT 24 27691517 ps
T1543 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2033273638 Jun 27 04:44:35 PM PDT 24 Jun 27 04:44:38 PM PDT 24 46441310 ps
T1544 /workspace/coverage/cover_reg_top/2.i2c_intr_test.4127124053 Jun 27 04:44:08 PM PDT 24 Jun 27 04:44:15 PM PDT 24 41298092 ps
T1545 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2049631007 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:18 PM PDT 24 108920272 ps
T1546 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.59923275 Jun 27 04:44:12 PM PDT 24 Jun 27 04:44:21 PM PDT 24 178236852 ps
T1547 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2401684523 Jun 27 04:44:08 PM PDT 24 Jun 27 04:44:16 PM PDT 24 52890356 ps
T1548 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1821059542 Jun 27 04:44:12 PM PDT 24 Jun 27 04:44:24 PM PDT 24 262808879 ps
T1549 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2522879367 Jun 27 04:44:05 PM PDT 24 Jun 27 04:44:18 PM PDT 24 530648708 ps
T1550 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.716479536 Jun 27 04:44:04 PM PDT 24 Jun 27 04:44:13 PM PDT 24 71103848 ps
T1551 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3544665606 Jun 27 04:44:06 PM PDT 24 Jun 27 04:44:14 PM PDT 24 114443364 ps
T1552 /workspace/coverage/cover_reg_top/10.i2c_intr_test.3943159696 Jun 27 04:44:18 PM PDT 24 Jun 27 04:44:24 PM PDT 24 32438943 ps
T1553 /workspace/coverage/cover_reg_top/34.i2c_intr_test.3643562130 Jun 27 04:44:28 PM PDT 24 Jun 27 04:44:31 PM PDT 24 18056620 ps
T1554 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1723288906 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:18 PM PDT 24 21505043 ps
T1555 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4227813077 Jun 27 04:44:12 PM PDT 24 Jun 27 04:44:21 PM PDT 24 29981842 ps
T1556 /workspace/coverage/cover_reg_top/11.i2c_intr_test.3296662166 Jun 27 04:44:16 PM PDT 24 Jun 27 04:44:23 PM PDT 24 58399860 ps
T1557 /workspace/coverage/cover_reg_top/20.i2c_intr_test.2070672261 Jun 27 04:44:28 PM PDT 24 Jun 27 04:44:32 PM PDT 24 55172585 ps
T212 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.293255619 Jun 27 04:44:33 PM PDT 24 Jun 27 04:44:36 PM PDT 24 292078693 ps
T1558 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3655829202 Jun 27 04:44:42 PM PDT 24 Jun 27 04:44:44 PM PDT 24 17361567 ps
T213 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1941081589 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:19 PM PDT 24 51970362 ps
T1559 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1639186560 Jun 27 04:44:09 PM PDT 24 Jun 27 04:44:17 PM PDT 24 52969543 ps
T1560 /workspace/coverage/cover_reg_top/39.i2c_intr_test.342193773 Jun 27 04:44:29 PM PDT 24 Jun 27 04:44:33 PM PDT 24 43462787 ps
T1561 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.849988535 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:20 PM PDT 24 463852373 ps
T1562 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.893915598 Jun 27 04:44:07 PM PDT 24 Jun 27 04:44:16 PM PDT 24 64450795 ps
T1563 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.527321784 Jun 27 04:44:05 PM PDT 24 Jun 27 04:44:13 PM PDT 24 136186378 ps
T1564 /workspace/coverage/cover_reg_top/25.i2c_intr_test.2656282450 Jun 27 04:44:25 PM PDT 24 Jun 27 04:44:30 PM PDT 24 22667194 ps
T224 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3974618045 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:18 PM PDT 24 26853100 ps
T1565 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1047025752 Jun 27 04:44:07 PM PDT 24 Jun 27 04:44:21 PM PDT 24 94966430 ps
T1566 /workspace/coverage/cover_reg_top/49.i2c_intr_test.3015902320 Jun 27 04:44:35 PM PDT 24 Jun 27 04:44:37 PM PDT 24 66792714 ps
T1567 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1039761239 Jun 27 04:44:37 PM PDT 24 Jun 27 04:44:40 PM PDT 24 123495588 ps
T1568 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3976847393 Jun 27 04:44:24 PM PDT 24 Jun 27 04:44:29 PM PDT 24 59974906 ps
T1569 /workspace/coverage/cover_reg_top/9.i2c_intr_test.3210493759 Jun 27 04:44:39 PM PDT 24 Jun 27 04:44:41 PM PDT 24 49095488 ps
T1570 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2165612343 Jun 27 04:44:07 PM PDT 24 Jun 27 04:44:15 PM PDT 24 23908813 ps
T1571 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2478148969 Jun 27 04:44:07 PM PDT 24 Jun 27 04:44:16 PM PDT 24 528936428 ps
T1572 /workspace/coverage/cover_reg_top/35.i2c_intr_test.35171200 Jun 27 04:44:37 PM PDT 24 Jun 27 04:44:40 PM PDT 24 18018703 ps
T225 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3249710551 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:18 PM PDT 24 49374582 ps
T1573 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1604250065 Jun 27 04:44:37 PM PDT 24 Jun 27 04:44:40 PM PDT 24 21649520 ps
T1574 /workspace/coverage/cover_reg_top/24.i2c_intr_test.1197585617 Jun 27 04:44:28 PM PDT 24 Jun 27 04:44:32 PM PDT 24 15045511 ps
T264 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2299017627 Jun 27 04:44:25 PM PDT 24 Jun 27 04:44:30 PM PDT 24 51632226 ps
T1575 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.582987592 Jun 27 04:44:17 PM PDT 24 Jun 27 04:44:24 PM PDT 24 41189672 ps
T1576 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2058978621 Jun 27 04:44:09 PM PDT 24 Jun 27 04:44:19 PM PDT 24 2140660131 ps
T1577 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3039791566 Jun 27 04:44:37 PM PDT 24 Jun 27 04:44:40 PM PDT 24 18178036 ps
T1578 /workspace/coverage/cover_reg_top/12.i2c_intr_test.1408113867 Jun 27 04:44:17 PM PDT 24 Jun 27 04:44:23 PM PDT 24 50257247 ps
T1579 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.397709956 Jun 27 04:44:25 PM PDT 24 Jun 27 04:44:30 PM PDT 24 38238204 ps
T1580 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3489083254 Jun 27 04:44:09 PM PDT 24 Jun 27 04:44:22 PM PDT 24 37867901 ps
T228 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3621195120 Jun 27 04:44:25 PM PDT 24 Jun 27 04:44:30 PM PDT 24 23926510 ps
T1581 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3872091805 Jun 27 04:44:17 PM PDT 24 Jun 27 04:44:24 PM PDT 24 47019235 ps
T1582 /workspace/coverage/cover_reg_top/8.i2c_intr_test.1043875203 Jun 27 04:44:25 PM PDT 24 Jun 27 04:44:30 PM PDT 24 20410027 ps
T1583 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2073625080 Jun 27 04:44:38 PM PDT 24 Jun 27 04:44:41 PM PDT 24 39439592 ps
T208 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2455072907 Jun 27 04:44:09 PM PDT 24 Jun 27 04:44:18 PM PDT 24 353190753 ps
T1584 /workspace/coverage/cover_reg_top/15.i2c_intr_test.3293297745 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:18 PM PDT 24 48074409 ps
T1585 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.443776543 Jun 27 04:44:05 PM PDT 24 Jun 27 04:44:13 PM PDT 24 122684508 ps
T210 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2807195509 Jun 27 04:44:06 PM PDT 24 Jun 27 04:44:15 PM PDT 24 54253773 ps
T1586 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1331481249 Jun 27 04:44:23 PM PDT 24 Jun 27 04:44:28 PM PDT 24 34528014 ps
T1587 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3658337253 Jun 27 04:44:38 PM PDT 24 Jun 27 04:44:41 PM PDT 24 78078169 ps
T1588 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.189346282 Jun 27 04:44:06 PM PDT 24 Jun 27 04:44:14 PM PDT 24 63130391 ps
T1589 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1202118417 Jun 27 04:44:08 PM PDT 24 Jun 27 04:44:16 PM PDT 24 56946877 ps
T1590 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1658709892 Jun 27 04:44:35 PM PDT 24 Jun 27 04:44:37 PM PDT 24 27156133 ps
T1591 /workspace/coverage/cover_reg_top/5.i2c_intr_test.2299842370 Jun 27 04:44:09 PM PDT 24 Jun 27 04:44:16 PM PDT 24 42634770 ps
T226 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2184058569 Jun 27 04:44:18 PM PDT 24 Jun 27 04:44:24 PM PDT 24 62188587 ps
T1592 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3242622888 Jun 27 04:44:19 PM PDT 24 Jun 27 04:44:27 PM PDT 24 248673866 ps
T1593 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.4199769616 Jun 27 04:44:38 PM PDT 24 Jun 27 04:44:40 PM PDT 24 295745202 ps
T227 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3654736069 Jun 27 04:44:13 PM PDT 24 Jun 27 04:44:21 PM PDT 24 149023563 ps
T1594 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2817885542 Jun 27 04:44:10 PM PDT 24 Jun 27 04:44:20 PM PDT 24 99736146 ps

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.780332706
Short name T1
Test name
Test status
Simulation time 438117695 ps
CPU time 9.17 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:22 PM PDT 24
Peak memory 235792 kb
Host smart-f6d323b3-2cdf-44dd-b598-157876e23055
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780332706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.780332706
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1697281453
Short name T18
Test name
Test status
Simulation time 908905467 ps
CPU time 1.09 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:48:57 PM PDT 24
Peak memory 212804 kb
Host smart-b0e9a088-0c3a-47ec-bf5f-38393964d4b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697281453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1697281453
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.1541067735
Short name T38
Test name
Test status
Simulation time 6469226947 ps
CPU time 457.62 seconds
Started Jun 27 04:49:35 PM PDT 24
Finished Jun 27 04:57:18 PM PDT 24
Peak memory 1321828 kb
Host smart-74e43a60-2f66-4131-8fdc-1c7a98108523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541067735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.1541067735
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.3695244199
Short name T15
Test name
Test status
Simulation time 2318721820 ps
CPU time 11.44 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:49:07 PM PDT 24
Peak memory 213732 kb
Host smart-80858771-2ebb-4e2f-a6a5-562c9513741c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695244199 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.3695244199
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.1246179076
Short name T6
Test name
Test status
Simulation time 13789516238 ps
CPU time 110.05 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 1725692 kb
Host smart-6dc03a2d-2312-4c2c-ba4a-a05b97aa18a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246179076 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.1246179076
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.1710064825
Short name T88
Test name
Test status
Simulation time 615339626 ps
CPU time 2.43 seconds
Started Jun 27 04:44:36 PM PDT 24
Finished Jun 27 04:44:40 PM PDT 24
Peak memory 204348 kb
Host smart-78a9643e-2bec-407f-a32f-c67a31315267
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710064825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.1710064825
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3588362462
Short name T201
Test name
Test status
Simulation time 27988700 ps
CPU time 1.31 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204428 kb
Host smart-94a91a3a-2edc-417f-98f7-01d405182047
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588362462 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3588362462
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.i2c_host_perf.3085483395
Short name T30
Test name
Test status
Simulation time 28099690177 ps
CPU time 241.73 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:54:32 PM PDT 24
Peak memory 235936 kb
Host smart-b030c5eb-0334-4774-947a-7dbc0d4d6714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085483395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.3085483395
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_override.4152413070
Short name T70
Test name
Test status
Simulation time 139466177 ps
CPU time 0.67 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:08 PM PDT 24
Peak memory 204544 kb
Host smart-54644b78-6793-4157-8bb1-2bb1370917b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152413070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.4152413070
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3625518665
Short name T11
Test name
Test status
Simulation time 6393390176 ps
CPU time 7.27 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:23 PM PDT 24
Peak memory 213140 kb
Host smart-9cf7ea61-b24d-426a-a7ec-5ee30a87ce65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625518665 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3625518665
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.475301312
Short name T37
Test name
Test status
Simulation time 14316218988 ps
CPU time 634.01 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 05:00:40 PM PDT 24
Peak memory 1718252 kb
Host smart-21b7ff7f-06de-4146-9685-432ebedc271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475301312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.475301312
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.378116709
Short name T45
Test name
Test status
Simulation time 1547291370 ps
CPU time 6.03 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:52:37 PM PDT 24
Peak memory 204832 kb
Host smart-7357ef7d-8573-4af0-bbfc-f45b3a8123c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378116709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.378116709
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.3587392478
Short name T191
Test name
Test status
Simulation time 66047811 ps
CPU time 0.83 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 222036 kb
Host smart-9dd3b895-ef8e-4d7b-8b4c-8dd16da8c1d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587392478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.3587392478
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.577072613
Short name T55
Test name
Test status
Simulation time 48283626476 ps
CPU time 292.32 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:56:38 PM PDT 24
Peak memory 836544 kb
Host smart-55cdb5c3-6f85-4df2-a13a-c1982b4934c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577072613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.577072613
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.3951441964
Short name T223
Test name
Test status
Simulation time 19845547 ps
CPU time 0.75 seconds
Started Jun 27 04:44:06 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 204300 kb
Host smart-5a690dfc-203a-4308-bede-566257171fc2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951441964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.3951441964
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.222489058
Short name T383
Test name
Test status
Simulation time 6435164433 ps
CPU time 5.09 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:53:11 PM PDT 24
Peak memory 206300 kb
Host smart-ace0a29a-5c7c-4310-bb70-284d3c0ea695
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222489058 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.222489058
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1843826354
Short name T59
Test name
Test status
Simulation time 10209923994 ps
CPU time 306.68 seconds
Started Jun 27 04:51:09 PM PDT 24
Finished Jun 27 04:56:17 PM PDT 24
Peak memory 823668 kb
Host smart-f2edfbcb-d657-418a-9276-3925c5b01978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843826354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1843826354
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.199336242
Short name T17
Test name
Test status
Simulation time 4649068814 ps
CPU time 6.93 seconds
Started Jun 27 04:52:55 PM PDT 24
Finished Jun 27 04:53:02 PM PDT 24
Peak memory 204908 kb
Host smart-bcd0d93e-8fc2-423f-876c-5654a41a3aaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199336242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_tar
get_smoke.199336242
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.1338354795
Short name T100
Test name
Test status
Simulation time 11442168974 ps
CPU time 124.97 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 1276668 kb
Host smart-45fc885b-db07-468f-b598-ca3844cb0a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338354795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.1338354795
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.2597830202
Short name T239
Test name
Test status
Simulation time 117805388 ps
CPU time 0.9 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 204420 kb
Host smart-2afba35b-8c48-48f9-bf9b-50317abb93a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597830202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.2597830202
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.265557379
Short name T285
Test name
Test status
Simulation time 18556721028 ps
CPU time 1270.29 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 05:13:41 PM PDT 24
Peak memory 3612488 kb
Host smart-9e300e3d-e063-4df2-8e5b-a136f1b641b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265557379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.265557379
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_alert_test.4178893550
Short name T348
Test name
Test status
Simulation time 23264436 ps
CPU time 0.66 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:48:55 PM PDT 24
Peak memory 204372 kb
Host smart-2580948f-023c-4a6f-9441-4b1e81486b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178893550 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.4178893550
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.3953669993
Short name T238
Test name
Test status
Simulation time 19984880213 ps
CPU time 3192.26 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 05:42:30 PM PDT 24
Peak memory 4476712 kb
Host smart-ae46c3c8-200d-466c-a8c8-28c3d52f3e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953669993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.3953669993
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.1027154342
Short name T8
Test name
Test status
Simulation time 1787224340 ps
CPU time 87.97 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:51:33 PM PDT 24
Peak memory 474524 kb
Host smart-3d526e30-a92a-42f3-b080-b6958111039e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027154342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.1027154342
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1110165029
Short name T204
Test name
Test status
Simulation time 430258718 ps
CPU time 2.73 seconds
Started Jun 27 04:44:18 PM PDT 24
Finished Jun 27 04:44:26 PM PDT 24
Peak memory 212588 kb
Host smart-b3f43d9c-f181-4565-9a70-891b83998b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110165029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1110165029
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.1559552819
Short name T217
Test name
Test status
Simulation time 586958135 ps
CPU time 1.17 seconds
Started Jun 27 04:49:44 PM PDT 24
Finished Jun 27 04:49:51 PM PDT 24
Peak memory 204708 kb
Host smart-4f639f42-5a72-4498-9f01-7c625aeea1b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559552819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.1559552819
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1606253349
Short name T9
Test name
Test status
Simulation time 1806747295 ps
CPU time 16.51 seconds
Started Jun 27 04:51:46 PM PDT 24
Finished Jun 27 04:52:05 PM PDT 24
Peak memory 221120 kb
Host smart-bdc4a0b9-48f9-474b-a689-ee6536ed50ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606253349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1606253349
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.421997765
Short name T200
Test name
Test status
Simulation time 84070759 ps
CPU time 2.14 seconds
Started Jun 27 04:44:22 PM PDT 24
Finished Jun 27 04:44:28 PM PDT 24
Peak memory 204524 kb
Host smart-a712ee00-ea43-427e-8905-a71f74b42a65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421997765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.421997765
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2184314769
Short name T232
Test name
Test status
Simulation time 50474333 ps
CPU time 1.02 seconds
Started Jun 27 04:44:17 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204520 kb
Host smart-2a038e76-3e16-4005-913e-3fd5016cd71f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184314769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.2184314769
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.718297225
Short name T243
Test name
Test status
Simulation time 138972640 ps
CPU time 1.07 seconds
Started Jun 27 04:48:49 PM PDT 24
Finished Jun 27 04:48:51 PM PDT 24
Peak memory 204444 kb
Host smart-dd58ffed-061d-4cc0-9197-b40af9bf7fa8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718297225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fmt
.718297225
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.326933243
Short name T262
Test name
Test status
Simulation time 2613379530 ps
CPU time 2.98 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:49:35 PM PDT 24
Peak memory 204888 kb
Host smart-7d66b85c-242b-490e-8e1a-2079ab8b1437
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326933243 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.326933243
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.344563115
Short name T279
Test name
Test status
Simulation time 49872006685 ps
CPU time 1169.21 seconds
Started Jun 27 04:49:32 PM PDT 24
Finished Jun 27 05:09:07 PM PDT 24
Peak memory 2268168 kb
Host smart-36d8916a-26c9-476d-b912-4ea29283be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344563115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.344563115
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.907137086
Short name T248
Test name
Test status
Simulation time 1210018167 ps
CPU time 8.61 seconds
Started Jun 27 04:49:54 PM PDT 24
Finished Jun 27 04:50:05 PM PDT 24
Peak memory 209956 kb
Host smart-9d57fbc9-44e3-425e-9489-b221c119f74f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907137086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.907137086
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3895365840
Short name T287
Test name
Test status
Simulation time 209650640 ps
CPU time 1.31 seconds
Started Jun 27 04:50:19 PM PDT 24
Finished Jun 27 04:50:26 PM PDT 24
Peak memory 204756 kb
Host smart-4ee746bb-3a13-4a15-96db-177e4a172a80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895365840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3895365840
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1909144755
Short name T235
Test name
Test status
Simulation time 198207135 ps
CPU time 1.32 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:36 PM PDT 24
Peak memory 204784 kb
Host smart-e6f034bf-7b92-4547-89b3-de3b795038bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909144755 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1909144755
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.1744559772
Short name T237
Test name
Test status
Simulation time 91715990314 ps
CPU time 1341.99 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 05:11:40 PM PDT 24
Peak memory 4662028 kb
Host smart-0f54ba2b-dcce-4118-87b6-16a4326bec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744559772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.1744559772
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3951209654
Short name T57
Test name
Test status
Simulation time 3377836616 ps
CPU time 7.56 seconds
Started Jun 27 04:49:15 PM PDT 24
Finished Jun 27 04:49:33 PM PDT 24
Peak memory 219400 kb
Host smart-5c843ee7-55a0-4e48-9971-7f406d43512e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951209654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3951209654
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.923478240
Short name T54
Test name
Test status
Simulation time 989171377 ps
CPU time 4.72 seconds
Started Jun 27 04:50:16 PM PDT 24
Finished Jun 27 04:50:22 PM PDT 24
Peak memory 224232 kb
Host smart-49f6288e-369e-4691-bb04-a0e2b72e0fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923478240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.923478240
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.1916889228
Short name T68
Test name
Test status
Simulation time 6114101946 ps
CPU time 62.57 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:50:49 PM PDT 24
Peak memory 311684 kb
Host smart-fe0436f4-934c-4088-acf1-004820160d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916889228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.1916889228
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2455072907
Short name T208
Test name
Test status
Simulation time 353190753 ps
CPU time 2.25 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204364 kb
Host smart-d8cff553-75f2-4735-9175-cc5b4fb880ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455072907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2455072907
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3044456134
Short name T184
Test name
Test status
Simulation time 632459796 ps
CPU time 0.83 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 204612 kb
Host smart-12031607-777f-4d73-bbc7-0047de8419f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044456134 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3044456134
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.480089040
Short name T124
Test name
Test status
Simulation time 19124091 ps
CPU time 0.65 seconds
Started Jun 27 04:44:23 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 204272 kb
Host smart-42b2eb7e-9d6c-4d7a-827a-2a107b4bef96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480089040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.480089040
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.859210864
Short name T993
Test name
Test status
Simulation time 421871360 ps
CPU time 1.63 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:48:53 PM PDT 24
Peak memory 204452 kb
Host smart-c88c1e88-90c6-4bf4-8930-2375e431930d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859210864 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.859210864
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.3521648731
Short name T146
Test name
Test status
Simulation time 1228883389 ps
CPU time 6.47 seconds
Started Jun 27 04:49:02 PM PDT 24
Finished Jun 27 04:49:10 PM PDT 24
Peak memory 213836 kb
Host smart-23ce6dc2-d7ac-4bac-8180-3ebf79108c1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521648731 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.3521648731
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.1195703292
Short name T295
Test name
Test status
Simulation time 19192448342 ps
CPU time 88.16 seconds
Started Jun 27 04:49:18 PM PDT 24
Finished Jun 27 04:50:56 PM PDT 24
Peak memory 491704 kb
Host smart-3988ea8d-55db-4c15-b5ec-f917f74ab626
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195703292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.1195703292
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1522143099
Short name T273
Test name
Test status
Simulation time 879420802 ps
CPU time 8.8 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:49:58 PM PDT 24
Peak memory 204848 kb
Host smart-60711e36-b8c9-4e3c-97e4-e2c97a95fa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522143099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1522143099
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.1287056566
Short name T171
Test name
Test status
Simulation time 4030635762 ps
CPU time 4.31 seconds
Started Jun 27 04:49:38 PM PDT 24
Finished Jun 27 04:49:47 PM PDT 24
Peak memory 204992 kb
Host smart-131648b4-bd23-478f-acc8-89ab1fa01ddf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287056566 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.1287056566
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.3445329047
Short name T257
Test name
Test status
Simulation time 1530489238 ps
CPU time 25.08 seconds
Started Jun 27 04:50:06 PM PDT 24
Finished Jun 27 04:50:36 PM PDT 24
Peak memory 364812 kb
Host smart-d5146a9d-4d5c-4d99-9f08-1b7c7b570a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445329047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.3445329047
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.1881344176
Short name T275
Test name
Test status
Simulation time 5556033190 ps
CPU time 337.53 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:57:06 PM PDT 24
Peak memory 1381848 kb
Host smart-5b33a407-0393-4f6a-ab04-1c5d5696d4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881344176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.1881344176
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1804091047
Short name T203
Test name
Test status
Simulation time 128993964 ps
CPU time 1.44 seconds
Started Jun 27 04:45:21 PM PDT 24
Finished Jun 27 04:45:24 PM PDT 24
Peak memory 204500 kb
Host smart-703f4d99-84d7-4fae-bd43-d6a3df34534a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804091047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1804091047
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.2807195509
Short name T210
Test name
Test status
Simulation time 54253773 ps
CPU time 1.41 seconds
Started Jun 27 04:44:06 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204364 kb
Host smart-3ae1c1f1-9155-4272-8676-3483e71cfee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807195509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.2807195509
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.512355830
Short name T206
Test name
Test status
Simulation time 87648391 ps
CPU time 2.12 seconds
Started Jun 27 04:44:16 PM PDT 24
Finished Jun 27 04:44:25 PM PDT 24
Peak memory 204412 kb
Host smart-55348951-044a-4f7c-a09e-97539627437d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512355830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.512355830
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.1485236227
Short name T165
Test name
Test status
Simulation time 245748336 ps
CPU time 1.26 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:17 PM PDT 24
Peak memory 204496 kb
Host smart-b0267edf-0a92-49b6-bf69-8d88967984dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485236227 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_fifo_reset_acq.1485236227
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.1571830037
Short name T87
Test name
Test status
Simulation time 241493198 ps
CPU time 1.4 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:20 PM PDT 24
Peak memory 204336 kb
Host smart-3a8a97a4-244d-4d11-aee0-e461b2ecdcdd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571830037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.1571830037
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.4105472313
Short name T1532
Test name
Test status
Simulation time 43256176 ps
CPU time 0.75 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204252 kb
Host smart-181bebac-bd31-4595-9c63-d1e6a982343b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105472313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.4105472313
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.4213094241
Short name T1518
Test name
Test status
Simulation time 26229190 ps
CPU time 1.22 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204500 kb
Host smart-28e786f7-b37a-4d24-bcf4-9647d1c0bb1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213094241 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.4213094241
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.3974618045
Short name T224
Test name
Test status
Simulation time 26853100 ps
CPU time 0.8 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204356 kb
Host smart-484ae22d-c78f-4917-81e9-bf70c75fe51c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974618045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.3974618045
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.2227039383
Short name T1496
Test name
Test status
Simulation time 86689210 ps
CPU time 0.66 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204300 kb
Host smart-729595ba-6ee3-402c-ab7c-2bb8da2417ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227039383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.2227039383
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.4253667438
Short name T1540
Test name
Test status
Simulation time 286470125 ps
CPU time 1.87 seconds
Started Jun 27 04:44:05 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 204504 kb
Host smart-c5afd93a-e192-4d3a-9bcc-d27eb1a9871c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253667438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.4253667438
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2522879367
Short name T1549
Test name
Test status
Simulation time 530648708 ps
CPU time 5.38 seconds
Started Jun 27 04:44:05 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204468 kb
Host smart-70f4191f-fb61-4ffe-82b8-535afc4155b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522879367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2522879367
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2932682190
Short name T288
Test name
Test status
Simulation time 234170881 ps
CPU time 0.7 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204296 kb
Host smart-0b2a2cea-ef33-48ad-a472-b9ce299799f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932682190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2932682190
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.527321784
Short name T1563
Test name
Test status
Simulation time 136186378 ps
CPU time 0.92 seconds
Started Jun 27 04:44:05 PM PDT 24
Finished Jun 27 04:44:13 PM PDT 24
Peak memory 204452 kb
Host smart-bcdc322e-9b65-4c6f-949e-3aea4362af25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527321784 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.527321784
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.4124531500
Short name T1528
Test name
Test status
Simulation time 39831170 ps
CPU time 0.7 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204424 kb
Host smart-cf088617-67e3-48c5-a789-f253278616e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124531500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.4124531500
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1802016467
Short name T1488
Test name
Test status
Simulation time 45015187 ps
CPU time 0.6 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204128 kb
Host smart-b9b171f3-74fe-491c-a2d5-78a1e3586256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802016467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1802016467
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.189346282
Short name T1588
Test name
Test status
Simulation time 63130391 ps
CPU time 0.83 seconds
Started Jun 27 04:44:06 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 204396 kb
Host smart-faac77c4-939c-4fd7-b8c4-89d908c59564
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189346282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_out
standing.189346282
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.911118624
Short name T1536
Test name
Test status
Simulation time 189742619 ps
CPU time 1.3 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204576 kb
Host smart-ce90a850-cc69-44ac-bfdd-701b7e62017a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911118624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.911118624
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4072576965
Short name T1538
Test name
Test status
Simulation time 73621507 ps
CPU time 0.9 seconds
Started Jun 27 04:44:19 PM PDT 24
Finished Jun 27 04:44:25 PM PDT 24
Peak memory 204340 kb
Host smart-6942b56c-9239-4ae3-9eec-544abbcc01d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072576965 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.4072576965
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.3522336334
Short name T157
Test name
Test status
Simulation time 73060423 ps
CPU time 0.79 seconds
Started Jun 27 04:44:18 PM PDT 24
Finished Jun 27 04:44:25 PM PDT 24
Peak memory 204276 kb
Host smart-146508c4-f768-47dd-bed0-3a14b89da259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522336334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.3522336334
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.3943159696
Short name T1552
Test name
Test status
Simulation time 32438943 ps
CPU time 0.68 seconds
Started Jun 27 04:44:18 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204156 kb
Host smart-f68175d3-0a42-4943-8748-9cc658a3c539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943159696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.3943159696
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.582987592
Short name T1575
Test name
Test status
Simulation time 41189672 ps
CPU time 0.87 seconds
Started Jun 27 04:44:17 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204240 kb
Host smart-64dcb2cf-e3f5-46e3-884a-bf3161c2a6c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582987592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.582987592
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.798700271
Short name T1533
Test name
Test status
Simulation time 50934628 ps
CPU time 2.35 seconds
Started Jun 27 04:44:36 PM PDT 24
Finished Jun 27 04:44:40 PM PDT 24
Peak memory 204408 kb
Host smart-d74538f3-cb4a-406e-8871-1637675d9982
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798700271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.798700271
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.1110600502
Short name T199
Test name
Test status
Simulation time 154441409 ps
CPU time 1.42 seconds
Started Jun 27 04:44:41 PM PDT 24
Finished Jun 27 04:44:43 PM PDT 24
Peak memory 204340 kb
Host smart-517b59dc-8960-448f-8cdf-3241f508d17b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110600502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.1110600502
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.2995694949
Short name T198
Test name
Test status
Simulation time 62490806 ps
CPU time 1.04 seconds
Started Jun 27 04:44:41 PM PDT 24
Finished Jun 27 04:44:43 PM PDT 24
Peak memory 204288 kb
Host smart-6718b1d0-05c3-4a75-ab09-1ead4a9b1485
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995694949 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.2995694949
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2118481042
Short name T1526
Test name
Test status
Simulation time 84592398 ps
CPU time 0.79 seconds
Started Jun 27 04:44:18 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204280 kb
Host smart-1c45e6e7-c906-43c9-9cf0-567611944734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118481042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2118481042
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.3296662166
Short name T1556
Test name
Test status
Simulation time 58399860 ps
CPU time 0.66 seconds
Started Jun 27 04:44:16 PM PDT 24
Finished Jun 27 04:44:23 PM PDT 24
Peak memory 204176 kb
Host smart-cd30fc9e-f691-414d-b264-85be264f047b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296662166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.3296662166
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.1037554281
Short name T1519
Test name
Test status
Simulation time 97074666 ps
CPU time 1.13 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 204336 kb
Host smart-e917e4d1-99ce-49cc-97f1-013853ca0e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037554281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.1037554281
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.2814673519
Short name T1517
Test name
Test status
Simulation time 168917910 ps
CPU time 1.39 seconds
Started Jun 27 04:44:17 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204420 kb
Host smart-85ec7ea5-0331-45c2-b533-47fac8ddc808
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814673519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.2814673519
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.2073625080
Short name T1583
Test name
Test status
Simulation time 39439592 ps
CPU time 1.07 seconds
Started Jun 27 04:44:38 PM PDT 24
Finished Jun 27 04:44:41 PM PDT 24
Peak memory 204380 kb
Host smart-df177a4d-d485-48d9-8bc9-3b2d3cec905e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073625080 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.2073625080
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.4199769616
Short name T1593
Test name
Test status
Simulation time 295745202 ps
CPU time 0.76 seconds
Started Jun 27 04:44:38 PM PDT 24
Finished Jun 27 04:44:40 PM PDT 24
Peak memory 204228 kb
Host smart-eb5bc70a-728e-4eec-a110-6175063c52d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199769616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.4199769616
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1408113867
Short name T1578
Test name
Test status
Simulation time 50257247 ps
CPU time 0.69 seconds
Started Jun 27 04:44:17 PM PDT 24
Finished Jun 27 04:44:23 PM PDT 24
Peak memory 204176 kb
Host smart-e290d60c-fed5-4897-9f70-38db5dca6acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408113867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1408113867
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3976847393
Short name T1568
Test name
Test status
Simulation time 59974906 ps
CPU time 1.08 seconds
Started Jun 27 04:44:24 PM PDT 24
Finished Jun 27 04:44:29 PM PDT 24
Peak memory 204280 kb
Host smart-21fcffa4-6d83-405e-8604-19666e1b25cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976847393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3976847393
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.3242622888
Short name T1592
Test name
Test status
Simulation time 248673866 ps
CPU time 2.63 seconds
Started Jun 27 04:44:19 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 204384 kb
Host smart-775a4849-09cf-44c6-8d51-ca9430407500
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242622888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.3242622888
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.87684714
Short name T1539
Test name
Test status
Simulation time 154301602 ps
CPU time 2.39 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:32 PM PDT 24
Peak memory 204284 kb
Host smart-0b6c3df0-cd1c-427c-92f4-b13ff128fcb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87684714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.87684714
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.2707993777
Short name T211
Test name
Test status
Simulation time 156080655 ps
CPU time 1.52 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 220364 kb
Host smart-5bf8be3a-c0bc-41cb-8590-c731bd9d5015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707993777 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.2707993777
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.2184058569
Short name T226
Test name
Test status
Simulation time 62188587 ps
CPU time 0.68 seconds
Started Jun 27 04:44:18 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204276 kb
Host smart-95e704de-5bb1-4856-9c37-8f45757bd2cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184058569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.2184058569
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3489083254
Short name T1580
Test name
Test status
Simulation time 37867901 ps
CPU time 0.65 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:44:22 PM PDT 24
Peak memory 204168 kb
Host smart-a52ced9a-0f79-450a-81fc-b92965c77e72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489083254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3489083254
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.3972915213
Short name T1527
Test name
Test status
Simulation time 56922505 ps
CPU time 0.81 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204244 kb
Host smart-ce9b3535-66c1-4563-a84e-bbd469eef809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972915213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.3972915213
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3872091805
Short name T1581
Test name
Test status
Simulation time 47019235 ps
CPU time 1.25 seconds
Started Jun 27 04:44:17 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204480 kb
Host smart-eddf0eb8-f20d-48c2-ae58-a9641bfddbef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872091805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3872091805
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.4224468692
Short name T1525
Test name
Test status
Simulation time 218988633 ps
CPU time 1.44 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 220056 kb
Host smart-e472d587-5694-4d2b-b63a-13800d72c528
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224468692 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.4224468692
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.3214833488
Short name T222
Test name
Test status
Simulation time 44620670 ps
CPU time 0.78 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204272 kb
Host smart-a8bea9ca-0757-446d-bc23-4dc5692ef317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214833488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.3214833488
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.2710759568
Short name T1512
Test name
Test status
Simulation time 42541312 ps
CPU time 0.63 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204168 kb
Host smart-2166d847-e3e8-444b-b50c-a2a36817611b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710759568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.2710759568
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.1723288906
Short name T1554
Test name
Test status
Simulation time 21505043 ps
CPU time 0.76 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204268 kb
Host smart-5e5da747-c7f7-45e2-89bf-6eddd25b9cf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723288906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.1723288906
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3420591272
Short name T1514
Test name
Test status
Simulation time 47442004 ps
CPU time 2.17 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204372 kb
Host smart-e6d30bef-cfb2-42ff-b74b-1f11a120219c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420591272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3420591272
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.870489890
Short name T188
Test name
Test status
Simulation time 43944692 ps
CPU time 0.81 seconds
Started Jun 27 04:44:28 PM PDT 24
Finished Jun 27 04:44:32 PM PDT 24
Peak memory 204256 kb
Host smart-7c707098-d5f0-4407-a1c4-24ad7cea0fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870489890 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.870489890
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.915430750
Short name T155
Test name
Test status
Simulation time 47753463 ps
CPU time 0.69 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204220 kb
Host smart-e6ad9bc0-ce2e-43fc-ae84-d16156417cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915430750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.915430750
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.3293297745
Short name T1584
Test name
Test status
Simulation time 48074409 ps
CPU time 0.66 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204104 kb
Host smart-d3895ba1-7ac5-47b6-bab0-a1579023355e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293297745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.3293297745
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.3835346265
Short name T229
Test name
Test status
Simulation time 61325836 ps
CPU time 0.87 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204328 kb
Host smart-820b41e7-d8c9-43ae-81b7-a0b35be9e231
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835346265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_o
utstanding.3835346265
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.594962908
Short name T96
Test name
Test status
Simulation time 1132523403 ps
CPU time 1.65 seconds
Started Jun 27 04:44:26 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204376 kb
Host smart-c8935bcd-6f54-43d5-bf35-134161b70606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594962908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.594962908
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.2935029341
Short name T209
Test name
Test status
Simulation time 150781225 ps
CPU time 1.49 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204476 kb
Host smart-0beb4615-344a-44d5-863f-1c205f1d9576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935029341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.2935029341
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3346594992
Short name T153
Test name
Test status
Simulation time 130866487 ps
CPU time 0.98 seconds
Started Jun 27 04:44:35 PM PDT 24
Finished Jun 27 04:44:38 PM PDT 24
Peak memory 204428 kb
Host smart-be635ceb-9606-4a20-b398-5a1d31456816
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346594992 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3346594992
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1801022027
Short name T1516
Test name
Test status
Simulation time 24153851 ps
CPU time 0.73 seconds
Started Jun 27 04:44:35 PM PDT 24
Finished Jun 27 04:44:37 PM PDT 24
Peak memory 204284 kb
Host smart-28d973c7-aee8-420c-91c1-dcafb65bb334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801022027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1801022027
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1324945120
Short name T1495
Test name
Test status
Simulation time 25374695 ps
CPU time 0.67 seconds
Started Jun 27 04:44:23 PM PDT 24
Finished Jun 27 04:44:28 PM PDT 24
Peak memory 204232 kb
Host smart-0cf64fb3-5e32-400b-adf8-361d68bf79ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324945120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1324945120
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1331481249
Short name T1586
Test name
Test status
Simulation time 34528014 ps
CPU time 0.9 seconds
Started Jun 27 04:44:23 PM PDT 24
Finished Jun 27 04:44:28 PM PDT 24
Peak memory 204340 kb
Host smart-628e4ca4-ac51-4b47-8e75-9efe406f25e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331481249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1331481249
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1486169047
Short name T95
Test name
Test status
Simulation time 1465728724 ps
CPU time 2.5 seconds
Started Jun 27 04:44:40 PM PDT 24
Finished Jun 27 04:44:44 PM PDT 24
Peak memory 204404 kb
Host smart-cbc9d595-de23-432d-94b6-667a45057c90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486169047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1486169047
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.942957181
Short name T219
Test name
Test status
Simulation time 342659991 ps
CPU time 1.03 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 204448 kb
Host smart-f2f25391-4033-4682-8b2e-dc75501c6db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942957181 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.942957181
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3594477059
Short name T90
Test name
Test status
Simulation time 53428791 ps
CPU time 0.67 seconds
Started Jun 27 04:44:22 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 204240 kb
Host smart-479f1743-a0f0-458c-b1d9-3118727e7ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594477059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3594477059
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2337408168
Short name T1498
Test name
Test status
Simulation time 21386198 ps
CPU time 0.62 seconds
Started Jun 27 04:44:22 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 204288 kb
Host smart-307937f6-5877-4961-a25e-b80239dc5914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337408168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2337408168
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.4280183294
Short name T231
Test name
Test status
Simulation time 21493154 ps
CPU time 0.89 seconds
Started Jun 27 04:44:22 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 204248 kb
Host smart-0f564511-d55a-4b53-9a47-d692decb2f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280183294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.4280183294
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2201959227
Short name T205
Test name
Test status
Simulation time 215888069 ps
CPU time 1.57 seconds
Started Jun 27 04:44:27 PM PDT 24
Finished Jun 27 04:44:32 PM PDT 24
Peak memory 204552 kb
Host smart-66ca3038-fc4c-4a25-9ade-b9e85d7a9493
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201959227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2201959227
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.1834192520
Short name T189
Test name
Test status
Simulation time 73710166 ps
CPU time 1.5 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204528 kb
Host smart-29814bc2-c53c-4e04-b9a2-73152e6e0b00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834192520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.1834192520
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1039761239
Short name T1567
Test name
Test status
Simulation time 123495588 ps
CPU time 0.83 seconds
Started Jun 27 04:44:37 PM PDT 24
Finished Jun 27 04:44:40 PM PDT 24
Peak memory 204424 kb
Host smart-ad7cdfb1-219c-4cdc-b4fe-cf5535c8128a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039761239 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1039761239
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.3621195120
Short name T228
Test name
Test status
Simulation time 23926510 ps
CPU time 0.8 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 204368 kb
Host smart-7bbf35e0-abad-47d7-9afa-b9483c35d9d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621195120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.3621195120
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1138713890
Short name T1520
Test name
Test status
Simulation time 85363945 ps
CPU time 0.67 seconds
Started Jun 27 04:44:33 PM PDT 24
Finished Jun 27 04:44:35 PM PDT 24
Peak memory 204148 kb
Host smart-7b9ae2ab-80a1-4e15-b8b9-1bfe84531333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138713890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1138713890
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3930726486
Short name T94
Test name
Test status
Simulation time 44574785 ps
CPU time 0.96 seconds
Started Jun 27 04:44:26 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204360 kb
Host smart-51de160b-d9dd-4daf-ba48-a8659b447b96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930726486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3930726486
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.1796167479
Short name T117
Test name
Test status
Simulation time 173490018 ps
CPU time 1.34 seconds
Started Jun 27 04:44:26 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204344 kb
Host smart-352a955a-598e-4ddc-82b2-c787d08b0f59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796167479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.1796167479
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2105586618
Short name T154
Test name
Test status
Simulation time 284003074 ps
CPU time 2.6 seconds
Started Jun 27 04:44:33 PM PDT 24
Finished Jun 27 04:44:37 PM PDT 24
Peak memory 204448 kb
Host smart-0186118d-b00f-4d49-b154-9efeaf5060f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105586618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2105586618
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2787041931
Short name T1506
Test name
Test status
Simulation time 63636183 ps
CPU time 1 seconds
Started Jun 27 04:44:34 PM PDT 24
Finished Jun 27 04:44:36 PM PDT 24
Peak memory 204456 kb
Host smart-6fd186fc-d980-4e83-92b7-dc245a0d534c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787041931 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2787041931
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2272617028
Short name T220
Test name
Test status
Simulation time 18823772 ps
CPU time 0.75 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:29 PM PDT 24
Peak memory 204376 kb
Host smart-4f01e2cb-2a51-4ee6-bf57-e2c03544426d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272617028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2272617028
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.4004438562
Short name T1510
Test name
Test status
Simulation time 61531706 ps
CPU time 0.73 seconds
Started Jun 27 04:44:26 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204132 kb
Host smart-d829f6d4-a7c4-43a3-a1a3-4ec582a5ad73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004438562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.4004438562
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1923500019
Short name T1529
Test name
Test status
Simulation time 22515102 ps
CPU time 0.86 seconds
Started Jun 27 04:44:28 PM PDT 24
Finished Jun 27 04:44:33 PM PDT 24
Peak memory 204312 kb
Host smart-37ffb152-8976-4b31-9160-d56dd751302a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923500019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1923500019
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3028634708
Short name T202
Test name
Test status
Simulation time 248454418 ps
CPU time 1.75 seconds
Started Jun 27 04:44:36 PM PDT 24
Finished Jun 27 04:44:39 PM PDT 24
Peak memory 204456 kb
Host smart-6db15a22-43ec-44c7-a533-4721f46362de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028634708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3028634708
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.293255619
Short name T212
Test name
Test status
Simulation time 292078693 ps
CPU time 1.61 seconds
Started Jun 27 04:44:33 PM PDT 24
Finished Jun 27 04:44:36 PM PDT 24
Peak memory 204392 kb
Host smart-32ff8282-1f27-419f-8d06-668dd4dec57f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293255619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.293255619
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.3466096608
Short name T92
Test name
Test status
Simulation time 278253871 ps
CPU time 1.4 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204348 kb
Host smart-dbd4d0b5-567c-419a-afb4-45b6949d3f23
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466096608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.3466096608
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.571481877
Short name T1537
Test name
Test status
Simulation time 53691122 ps
CPU time 1.06 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204348 kb
Host smart-22f6f19e-a073-40f1-a3bb-a07d0cff51f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571481877 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.571481877
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.897247584
Short name T230
Test name
Test status
Simulation time 17745958 ps
CPU time 0.69 seconds
Started Jun 27 04:44:06 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 204264 kb
Host smart-c6b3c126-1e77-43d8-9fe4-d7a2e06acb23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897247584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.897247584
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.4127124053
Short name T1544
Test name
Test status
Simulation time 41298092 ps
CPU time 0.68 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204256 kb
Host smart-10bc3db2-cc40-4b6d-837b-b9c655fa1fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127124053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.4127124053
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1202118417
Short name T1589
Test name
Test status
Simulation time 56946877 ps
CPU time 1.17 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204376 kb
Host smart-f92752d8-ad38-4dee-8631-227c92b8c65a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202118417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1202118417
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.1017679322
Short name T190
Test name
Test status
Simulation time 34323021 ps
CPU time 1.65 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204568 kb
Host smart-8b76784b-daca-420d-ae7f-78606f60a797
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017679322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.1017679322
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.2401684523
Short name T1547
Test name
Test status
Simulation time 52890356 ps
CPU time 1.5 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204556 kb
Host smart-9df58fa1-8387-4100-bf6f-59a009111f95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401684523 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.2401684523
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.2070672261
Short name T1557
Test name
Test status
Simulation time 55172585 ps
CPU time 0.66 seconds
Started Jun 27 04:44:28 PM PDT 24
Finished Jun 27 04:44:32 PM PDT 24
Peak memory 204288 kb
Host smart-72156504-862c-4368-9063-e26ee11b7dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070672261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.2070672261
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.2284607923
Short name T1531
Test name
Test status
Simulation time 50167884 ps
CPU time 0.72 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 204268 kb
Host smart-585e0901-5200-43ac-9357-8644aeb5bf69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284607923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.2284607923
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.4107728219
Short name T1489
Test name
Test status
Simulation time 16552560 ps
CPU time 0.63 seconds
Started Jun 27 04:44:30 PM PDT 24
Finished Jun 27 04:44:33 PM PDT 24
Peak memory 204132 kb
Host smart-1d29b228-33c5-4181-9caa-bb25cba7b159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107728219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.4107728219
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.1197585617
Short name T1574
Test name
Test status
Simulation time 15045511 ps
CPU time 0.66 seconds
Started Jun 27 04:44:28 PM PDT 24
Finished Jun 27 04:44:32 PM PDT 24
Peak memory 204176 kb
Host smart-ec88ce6c-73a5-4531-928b-06b0d0837613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197585617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.1197585617
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.2656282450
Short name T1564
Test name
Test status
Simulation time 22667194 ps
CPU time 0.65 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 204260 kb
Host smart-88aba7aa-8583-4275-a2d1-237bf82f9875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656282450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.2656282450
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.1190268460
Short name T1492
Test name
Test status
Simulation time 19598930 ps
CPU time 0.66 seconds
Started Jun 27 04:44:24 PM PDT 24
Finished Jun 27 04:44:29 PM PDT 24
Peak memory 204156 kb
Host smart-2d40b7fe-49d9-4b03-84e0-aa03a4df268f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190268460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.1190268460
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.703130343
Short name T1493
Test name
Test status
Simulation time 17692736 ps
CPU time 0.69 seconds
Started Jun 27 04:44:43 PM PDT 24
Finished Jun 27 04:44:45 PM PDT 24
Peak memory 204152 kb
Host smart-8428eb88-dd63-4669-9510-15d718b6787d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703130343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.703130343
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.980056609
Short name T1505
Test name
Test status
Simulation time 16157341 ps
CPU time 0.7 seconds
Started Jun 27 04:44:36 PM PDT 24
Finished Jun 27 04:44:39 PM PDT 24
Peak memory 204196 kb
Host smart-1fb43e1d-2db4-4285-942d-5988131f2844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980056609 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.980056609
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.2721956192
Short name T1504
Test name
Test status
Simulation time 43893823 ps
CPU time 0.68 seconds
Started Jun 27 04:44:26 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204296 kb
Host smart-3677d2d4-bfd9-4d13-a5b8-d1922f3b405d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721956192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.2721956192
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.1180296183
Short name T89
Test name
Test status
Simulation time 132608301 ps
CPU time 1.37 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204484 kb
Host smart-f3522d06-1e9f-44b5-8d7d-f5446de4108e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180296183 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.1180296183
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.1821059542
Short name T1548
Test name
Test status
Simulation time 262808879 ps
CPU time 5.09 seconds
Started Jun 27 04:44:12 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204364 kb
Host smart-fc09c529-b335-488d-86bd-f2466bb91857
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821059542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.1821059542
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.1047025752
Short name T1565
Test name
Test status
Simulation time 94966430 ps
CPU time 0.69 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:44:21 PM PDT 24
Peak memory 204300 kb
Host smart-5850a70c-72f7-4d54-82f3-01192713b8f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047025752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.1047025752
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.3544665606
Short name T1551
Test name
Test status
Simulation time 114443364 ps
CPU time 0.97 seconds
Started Jun 27 04:44:06 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 204452 kb
Host smart-c49da8b4-84ce-422b-ae3a-6b2c7f137ffa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544665606 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.3544665606
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3433779813
Short name T1542
Test name
Test status
Simulation time 27691517 ps
CPU time 0.71 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204396 kb
Host smart-efcce686-d25a-41e5-af3d-a2143f12fee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433779813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3433779813
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.3593699597
Short name T1521
Test name
Test status
Simulation time 25436777 ps
CPU time 0.66 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204144 kb
Host smart-8c89f349-11b4-429d-aae9-984e19335479
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593699597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3593699597
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.1238014397
Short name T1515
Test name
Test status
Simulation time 37801923 ps
CPU time 0.96 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204284 kb
Host smart-6635c246-66b8-4782-be00-cb08b02ea47a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238014397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.1238014397
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.716479536
Short name T1550
Test name
Test status
Simulation time 71103848 ps
CPU time 1.49 seconds
Started Jun 27 04:44:04 PM PDT 24
Finished Jun 27 04:44:13 PM PDT 24
Peak memory 204440 kb
Host smart-c3349490-55c9-4a89-81d1-7e9de7fd38e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716479536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.716479536
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1941081589
Short name T213
Test name
Test status
Simulation time 51970362 ps
CPU time 1.38 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204480 kb
Host smart-43b3e1d9-3ce0-4b73-b5eb-a2d228253d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941081589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1941081589
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.4238056852
Short name T1490
Test name
Test status
Simulation time 29533869 ps
CPU time 0.66 seconds
Started Jun 27 04:44:29 PM PDT 24
Finished Jun 27 04:44:33 PM PDT 24
Peak memory 204176 kb
Host smart-7e6b9c43-ff97-4fd3-9231-f3a1fbd652ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238056852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.4238056852
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2049531080
Short name T1535
Test name
Test status
Simulation time 34533361 ps
CPU time 0.65 seconds
Started Jun 27 04:44:36 PM PDT 24
Finished Jun 27 04:44:38 PM PDT 24
Peak memory 204192 kb
Host smart-2fd56938-39e3-4c84-99e0-827086e0ed28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049531080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2049531080
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.2064182549
Short name T126
Test name
Test status
Simulation time 19010211 ps
CPU time 0.69 seconds
Started Jun 27 04:44:34 PM PDT 24
Finished Jun 27 04:44:36 PM PDT 24
Peak memory 204336 kb
Host smart-4360a172-2cee-4a31-b4e0-a6d05edbdd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064182549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.2064182549
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1658709892
Short name T1590
Test name
Test status
Simulation time 27156133 ps
CPU time 0.66 seconds
Started Jun 27 04:44:35 PM PDT 24
Finished Jun 27 04:44:37 PM PDT 24
Peak memory 204148 kb
Host smart-1bce27ea-a72a-4ec9-b9fe-7c35ac622af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658709892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1658709892
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.3643562130
Short name T1553
Test name
Test status
Simulation time 18056620 ps
CPU time 0.66 seconds
Started Jun 27 04:44:28 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204280 kb
Host smart-7407194d-dd7b-4d72-8bcf-51db4420d6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643562130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.3643562130
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.35171200
Short name T1572
Test name
Test status
Simulation time 18018703 ps
CPU time 0.69 seconds
Started Jun 27 04:44:37 PM PDT 24
Finished Jun 27 04:44:40 PM PDT 24
Peak memory 204272 kb
Host smart-664893e1-24cd-4d54-87b6-3a52fc132c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35171200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.35171200
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3415880399
Short name T1534
Test name
Test status
Simulation time 19414604 ps
CPU time 0.67 seconds
Started Jun 27 04:44:23 PM PDT 24
Finished Jun 27 04:44:28 PM PDT 24
Peak memory 204164 kb
Host smart-6a9ed8d4-60ed-47df-8b00-b90e2f5414b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415880399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3415880399
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.3895854157
Short name T125
Test name
Test status
Simulation time 26042500 ps
CPU time 0.76 seconds
Started Jun 27 04:44:40 PM PDT 24
Finished Jun 27 04:44:42 PM PDT 24
Peak memory 204192 kb
Host smart-bdc813a0-99b1-4202-8ad0-6f35ca665ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895854157 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.3895854157
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2033273638
Short name T1543
Test name
Test status
Simulation time 46441310 ps
CPU time 0.67 seconds
Started Jun 27 04:44:35 PM PDT 24
Finished Jun 27 04:44:38 PM PDT 24
Peak memory 204336 kb
Host smart-d3fe1e9b-1b14-4a21-81b2-0da2553a2118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033273638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2033273638
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.342193773
Short name T1560
Test name
Test status
Simulation time 43462787 ps
CPU time 0.66 seconds
Started Jun 27 04:44:29 PM PDT 24
Finished Jun 27 04:44:33 PM PDT 24
Peak memory 204196 kb
Host smart-76d61e70-5f4a-438b-8cd3-9fa0dfb0a2de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342193773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.342193773
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.1045142793
Short name T221
Test name
Test status
Simulation time 33287548 ps
CPU time 1.25 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204496 kb
Host smart-e549d114-b955-48bc-bf8c-966a69fcd653
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045142793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.1045142793
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2058978621
Short name T1576
Test name
Test status
Simulation time 2140660131 ps
CPU time 3.22 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204360 kb
Host smart-381dc334-da29-4e53-b104-d02ccca00d5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058978621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2058978621
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.1639186560
Short name T1559
Test name
Test status
Simulation time 52969543 ps
CPU time 0.7 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:44:17 PM PDT 24
Peak memory 204264 kb
Host smart-830b6558-e6c3-4729-a748-7c137987b2c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639186560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.1639186560
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.4142602674
Short name T116
Test name
Test status
Simulation time 25025134 ps
CPU time 0.78 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204436 kb
Host smart-6e673dba-cf86-4d9c-9692-329a0ce78697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142602674 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.4142602674
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3654736069
Short name T227
Test name
Test status
Simulation time 149023563 ps
CPU time 0.66 seconds
Started Jun 27 04:44:13 PM PDT 24
Finished Jun 27 04:44:21 PM PDT 24
Peak memory 204352 kb
Host smart-a315f37c-9315-4524-b8c2-84ef40bb4428
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654736069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3654736069
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.188087421
Short name T1494
Test name
Test status
Simulation time 26306110 ps
CPU time 0.67 seconds
Started Jun 27 04:44:13 PM PDT 24
Finished Jun 27 04:44:21 PM PDT 24
Peak memory 204296 kb
Host smart-eb290bfe-cae0-4dd5-b90a-24db0b0c4f05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188087421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.188087421
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.443776543
Short name T1585
Test name
Test status
Simulation time 122684508 ps
CPU time 0.9 seconds
Started Jun 27 04:44:05 PM PDT 24
Finished Jun 27 04:44:13 PM PDT 24
Peak memory 204260 kb
Host smart-6cefc2dc-d4c4-4bd1-bf37-2d425015205c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443776543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_out
standing.443776543
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2478148969
Short name T1571
Test name
Test status
Simulation time 528936428 ps
CPU time 2.85 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204548 kb
Host smart-bb4afdc4-5883-41ad-9eb5-544b35d88701
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478148969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2478148969
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.59923275
Short name T1546
Test name
Test status
Simulation time 178236852 ps
CPU time 1.44 seconds
Started Jun 27 04:44:12 PM PDT 24
Finished Jun 27 04:44:21 PM PDT 24
Peak memory 204424 kb
Host smart-fd9cdf41-ac49-43db-b9bb-445d5818f22d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59923275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.59923275
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3039791566
Short name T1577
Test name
Test status
Simulation time 18178036 ps
CPU time 0.68 seconds
Started Jun 27 04:44:37 PM PDT 24
Finished Jun 27 04:44:40 PM PDT 24
Peak memory 204280 kb
Host smart-869ce0ac-5646-4291-a7c7-0079cec315dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039791566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3039791566
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.3840177741
Short name T1503
Test name
Test status
Simulation time 44425491 ps
CPU time 0.71 seconds
Started Jun 27 04:44:35 PM PDT 24
Finished Jun 27 04:44:38 PM PDT 24
Peak memory 204292 kb
Host smart-f1148523-2d72-46ed-b8d5-0c2f63cc871d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840177741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.3840177741
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2918039028
Short name T1500
Test name
Test status
Simulation time 27606031 ps
CPU time 0.68 seconds
Started Jun 27 04:44:36 PM PDT 24
Finished Jun 27 04:44:38 PM PDT 24
Peak memory 204132 kb
Host smart-75f88afc-13fb-4039-b4c5-b44df64e8382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918039028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2918039028
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.2008402398
Short name T1497
Test name
Test status
Simulation time 41652775 ps
CPU time 0.72 seconds
Started Jun 27 04:44:27 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204296 kb
Host smart-3b7a7add-9202-4452-8a54-482abe1a3df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008402398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.2008402398
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3655829202
Short name T1558
Test name
Test status
Simulation time 17361567 ps
CPU time 0.66 seconds
Started Jun 27 04:44:42 PM PDT 24
Finished Jun 27 04:44:44 PM PDT 24
Peak memory 204200 kb
Host smart-82f50ef9-0c81-40fd-8974-a1cfb1bf0386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655829202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3655829202
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.1693254395
Short name T1530
Test name
Test status
Simulation time 51888108 ps
CPU time 0.72 seconds
Started Jun 27 04:44:27 PM PDT 24
Finished Jun 27 04:44:31 PM PDT 24
Peak memory 204292 kb
Host smart-0f92d5dc-cf41-4510-ba5f-94281bb52fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693254395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.1693254395
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.2677953496
Short name T1511
Test name
Test status
Simulation time 20223299 ps
CPU time 0.66 seconds
Started Jun 27 04:44:36 PM PDT 24
Finished Jun 27 04:44:39 PM PDT 24
Peak memory 204292 kb
Host smart-6ad55fec-6af9-4ef0-a521-01988dfe20d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677953496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.2677953496
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1604250065
Short name T1573
Test name
Test status
Simulation time 21649520 ps
CPU time 0.7 seconds
Started Jun 27 04:44:37 PM PDT 24
Finished Jun 27 04:44:40 PM PDT 24
Peak memory 204264 kb
Host smart-b5c3a763-a883-40e7-9685-1a7b558d1b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604250065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1604250065
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2147878529
Short name T1509
Test name
Test status
Simulation time 44288295 ps
CPU time 0.75 seconds
Started Jun 27 04:44:41 PM PDT 24
Finished Jun 27 04:44:43 PM PDT 24
Peak memory 204296 kb
Host smart-d905d299-1e9c-4461-a2f0-6923990885a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147878529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2147878529
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.3015902320
Short name T1566
Test name
Test status
Simulation time 66792714 ps
CPU time 0.68 seconds
Started Jun 27 04:44:35 PM PDT 24
Finished Jun 27 04:44:37 PM PDT 24
Peak memory 204296 kb
Host smart-44390630-a3b1-482b-ada2-6f5f9790dd1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015902320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.3015902320
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.2165612343
Short name T1570
Test name
Test status
Simulation time 23908813 ps
CPU time 0.99 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204404 kb
Host smart-66213dc1-f416-4201-97f9-ca438143e1f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165612343 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.2165612343
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4227813077
Short name T1555
Test name
Test status
Simulation time 29981842 ps
CPU time 0.72 seconds
Started Jun 27 04:44:12 PM PDT 24
Finished Jun 27 04:44:21 PM PDT 24
Peak memory 204252 kb
Host smart-e4e71fb0-b1e2-4230-8194-84971dc29795
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227813077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.4227813077
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.2299842370
Short name T1591
Test name
Test status
Simulation time 42634770 ps
CPU time 0.64 seconds
Started Jun 27 04:44:09 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204156 kb
Host smart-188e6ca3-3a0c-42cc-9748-2a4099095c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299842370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.2299842370
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.953392171
Short name T1499
Test name
Test status
Simulation time 20414705 ps
CPU time 0.85 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204364 kb
Host smart-e5b33e1d-3d6a-463b-8b8a-5a178edb9504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953392171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_out
standing.953392171
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.893915598
Short name T1562
Test name
Test status
Simulation time 64450795 ps
CPU time 1.57 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:44:16 PM PDT 24
Peak memory 204428 kb
Host smart-2ef46fc9-3f4f-4baf-917f-302b2bb47674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893915598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.893915598
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3645928345
Short name T207
Test name
Test status
Simulation time 187457702 ps
CPU time 1.34 seconds
Started Jun 27 04:44:07 PM PDT 24
Finished Jun 27 04:44:15 PM PDT 24
Peak memory 204340 kb
Host smart-529bc06b-fa87-42ea-a233-1307b57ff4ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645928345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3645928345
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.166959721
Short name T93
Test name
Test status
Simulation time 84712633 ps
CPU time 0.81 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204276 kb
Host smart-3807b41c-2cc8-49d7-a2cd-55cff6b70379
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166959721 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.166959721
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2784526578
Short name T1513
Test name
Test status
Simulation time 55467313 ps
CPU time 0.76 seconds
Started Jun 27 04:44:06 PM PDT 24
Finished Jun 27 04:44:14 PM PDT 24
Peak memory 204276 kb
Host smart-2e0f910d-2708-4468-b634-b5f1b77a6ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784526578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2784526578
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.3125999038
Short name T1501
Test name
Test status
Simulation time 32238322 ps
CPU time 0.68 seconds
Started Jun 27 04:44:11 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204288 kb
Host smart-9684ff62-6562-4adc-8218-c85d695a8f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125999038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.3125999038
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.397709956
Short name T1579
Test name
Test status
Simulation time 38238204 ps
CPU time 0.94 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 203844 kb
Host smart-573a539b-7037-4e7c-8b8f-b0a71218dfae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397709956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_out
standing.397709956
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2161398811
Short name T1508
Test name
Test status
Simulation time 288058069 ps
CPU time 3.06 seconds
Started Jun 27 04:44:08 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204432 kb
Host smart-a0f51eb3-cc3f-49fa-92db-e05995a1351a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161398811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2161398811
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2529649511
Short name T1502
Test name
Test status
Simulation time 39129780 ps
CPU time 1.1 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:19 PM PDT 24
Peak memory 204316 kb
Host smart-55f30fca-2c04-4030-b1ee-a6a325c2d8c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529649511 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2529649511
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.3249710551
Short name T225
Test name
Test status
Simulation time 49374582 ps
CPU time 0.82 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204324 kb
Host smart-6dadcf3e-55ff-406d-82aa-a8133dde891b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249710551 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.3249710551
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.3981359808
Short name T1491
Test name
Test status
Simulation time 18544809 ps
CPU time 0.66 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204300 kb
Host smart-851b2449-db6d-4547-8558-ca26c7df1ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981359808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.3981359808
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.580681951
Short name T1507
Test name
Test status
Simulation time 64860959 ps
CPU time 0.92 seconds
Started Jun 27 04:44:12 PM PDT 24
Finished Jun 27 04:44:27 PM PDT 24
Peak memory 204248 kb
Host smart-2e082f14-c13a-4f2a-b590-09f3256c7570
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580681951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_out
standing.580681951
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.849988535
Short name T1561
Test name
Test status
Simulation time 463852373 ps
CPU time 2.86 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:20 PM PDT 24
Peak memory 204592 kb
Host smart-a995719c-b73d-4c34-a421-aa355a7d41d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849988535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.849988535
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.2817885542
Short name T1594
Test name
Test status
Simulation time 99736146 ps
CPU time 2.28 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:20 PM PDT 24
Peak memory 204384 kb
Host smart-e79be4f6-2d23-4825-894f-ad8f024caa12
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817885542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.2817885542
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.3670319928
Short name T91
Test name
Test status
Simulation time 35025535 ps
CPU time 0.71 seconds
Started Jun 27 04:44:18 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204240 kb
Host smart-5eca904d-dd29-4c2b-a23b-8950af17eb47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670319928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.3670319928
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.1043875203
Short name T1582
Test name
Test status
Simulation time 20410027 ps
CPU time 0.74 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 203536 kb
Host smart-ba513bf0-2e8e-426e-9d29-f2cbb763cd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043875203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.1043875203
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4011051474
Short name T156
Test name
Test status
Simulation time 22556702 ps
CPU time 0.84 seconds
Started Jun 27 04:44:17 PM PDT 24
Finished Jun 27 04:44:24 PM PDT 24
Peak memory 204240 kb
Host smart-3fdb1d78-73c5-4422-ad5a-d613d8a13cdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011051474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.4011051474
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2049631007
Short name T1545
Test name
Test status
Simulation time 108920272 ps
CPU time 1.56 seconds
Started Jun 27 04:44:10 PM PDT 24
Finished Jun 27 04:44:18 PM PDT 24
Peak memory 204548 kb
Host smart-8c81131f-29cb-4f66-b4f1-407fdef9e8b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049631007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2049631007
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3871816681
Short name T1541
Test name
Test status
Simulation time 174540081 ps
CPU time 1.53 seconds
Started Jun 27 04:44:39 PM PDT 24
Finished Jun 27 04:44:42 PM PDT 24
Peak memory 203868 kb
Host smart-9cef3081-4934-4c98-9eb5-6473d2f7837e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871816681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3871816681
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.1475915895
Short name T1523
Test name
Test status
Simulation time 191636709 ps
CPU time 1.36 seconds
Started Jun 27 04:44:19 PM PDT 24
Finished Jun 27 04:44:25 PM PDT 24
Peak memory 204428 kb
Host smart-f3866916-1b28-4a34-b27b-a339fd1ef9c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475915895 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.1475915895
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.2403146363
Short name T1524
Test name
Test status
Simulation time 22605949 ps
CPU time 0.7 seconds
Started Jun 27 04:44:17 PM PDT 24
Finished Jun 27 04:44:23 PM PDT 24
Peak memory 204268 kb
Host smart-4e6f1da7-8b8a-4155-ab94-8218558e91b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403146363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.2403146363
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3210493759
Short name T1569
Test name
Test status
Simulation time 49095488 ps
CPU time 0.65 seconds
Started Jun 27 04:44:39 PM PDT 24
Finished Jun 27 04:44:41 PM PDT 24
Peak memory 203708 kb
Host smart-950aaff2-cc3e-49ed-a654-0ec1f9752043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210493759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3210493759
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.2681185771
Short name T1522
Test name
Test status
Simulation time 136104242 ps
CPU time 0.88 seconds
Started Jun 27 04:44:40 PM PDT 24
Finished Jun 27 04:44:43 PM PDT 24
Peak memory 204216 kb
Host smart-56db7ca9-beaa-40bc-85d2-21cdd418d97c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681185771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.2681185771
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.3658337253
Short name T1587
Test name
Test status
Simulation time 78078169 ps
CPU time 2.1 seconds
Started Jun 27 04:44:38 PM PDT 24
Finished Jun 27 04:44:41 PM PDT 24
Peak memory 204368 kb
Host smart-2287fc2b-cac3-4e0f-8fe6-0c66bd432ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658337253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.3658337253
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.2299017627
Short name T264
Test name
Test status
Simulation time 51632226 ps
CPU time 1.47 seconds
Started Jun 27 04:44:25 PM PDT 24
Finished Jun 27 04:44:30 PM PDT 24
Peak memory 204356 kb
Host smart-23cf34f6-9619-46da-8312-b0acd8e25f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299017627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.2299017627
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.2601996655
Short name T816
Test name
Test status
Simulation time 137115372 ps
CPU time 2.93 seconds
Started Jun 27 04:48:49 PM PDT 24
Finished Jun 27 04:48:53 PM PDT 24
Peak memory 221040 kb
Host smart-2b37d12c-45ae-4718-a727-34b6ad9a38aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601996655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.2601996655
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.3020458293
Short name T786
Test name
Test status
Simulation time 389094649 ps
CPU time 6.47 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:48:56 PM PDT 24
Peak memory 267884 kb
Host smart-b38ad715-6791-4f48-911b-2c3dbcf176b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020458293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empt
y.3020458293
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3034939277
Short name T1089
Test name
Test status
Simulation time 5529886697 ps
CPU time 93.13 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 896184 kb
Host smart-2d0c1bd3-badc-46cf-8d56-f3e33770030c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034939277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3034939277
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3063424515
Short name T390
Test name
Test status
Simulation time 2774802020 ps
CPU time 102.19 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:50:35 PM PDT 24
Peak memory 877944 kb
Host smart-86430c49-2320-4b75-92b3-a5d57ee4d072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063424515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3063424515
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.2369266141
Short name T1400
Test name
Test status
Simulation time 126122027 ps
CPU time 0.95 seconds
Started Jun 27 04:49:02 PM PDT 24
Finished Jun 27 04:49:04 PM PDT 24
Peak memory 204548 kb
Host smart-5f4590b0-68da-4d63-9b91-d27a919c6046
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369266141 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.2369266141
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.2379667753
Short name T602
Test name
Test status
Simulation time 981273523 ps
CPU time 4.48 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:48:56 PM PDT 24
Peak memory 239460 kb
Host smart-9729a7e0-df38-4261-8e49-e3674cdbff74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379667753 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
2379667753
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3518044188
Short name T1201
Test name
Test status
Simulation time 3139664215 ps
CPU time 182.73 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:51:56 PM PDT 24
Peak memory 870300 kb
Host smart-c76b7c18-70ba-484d-afbf-f7e963f9b293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518044188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3518044188
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.89072770
Short name T594
Test name
Test status
Simulation time 532785176 ps
CPU time 8.06 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 204864 kb
Host smart-d8da8d61-4ee4-4c47-a5e8-4330c36fbcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89072770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.89072770
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.2181344012
Short name T1020
Test name
Test status
Simulation time 1486712404 ps
CPU time 25.81 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 295688 kb
Host smart-14b78c4e-9bd0-430b-9679-0601b70a511e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181344012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.2181344012
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3197354476
Short name T408
Test name
Test status
Simulation time 55510043 ps
CPU time 0.65 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:48:54 PM PDT 24
Peak memory 204560 kb
Host smart-3eba147a-1f32-4189-9f0a-a88be1cadefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197354476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3197354476
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.3950189908
Short name T1202
Test name
Test status
Simulation time 2042228134 ps
CPU time 21.61 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:49:17 PM PDT 24
Peak memory 229144 kb
Host smart-0e814d08-b8cc-4153-aa00-8435dfe9af68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950189908 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.3950189908
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.3127717679
Short name T1123
Test name
Test status
Simulation time 355848509 ps
CPU time 2.04 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:48:57 PM PDT 24
Peak memory 212944 kb
Host smart-a7681f8d-5be0-4e47-ab4a-fa73bb6e7436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127717679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.3127717679
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.2792630071
Short name T1401
Test name
Test status
Simulation time 5081166051 ps
CPU time 22.72 seconds
Started Jun 27 04:48:49 PM PDT 24
Finished Jun 27 04:49:12 PM PDT 24
Peak memory 353736 kb
Host smart-af420f94-0dd0-4964-95cc-cbea3c9d0aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792630071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.2792630071
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.25892733
Short name T103
Test name
Test status
Simulation time 55771960770 ps
CPU time 434.44 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:56:07 PM PDT 24
Peak memory 1856148 kb
Host smart-7f685184-d75e-40f8-bcba-6d49e84cdbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25892733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.25892733
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1917470
Short name T334
Test name
Test status
Simulation time 497794629 ps
CPU time 7.84 seconds
Started Jun 27 04:48:45 PM PDT 24
Finished Jun 27 04:48:53 PM PDT 24
Peak memory 221168 kb
Host smart-4c2df00c-7ac0-4fa1-a9d2-8a4ad372279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1917470
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.2710286329
Short name T195
Test name
Test status
Simulation time 212600376 ps
CPU time 0.89 seconds
Started Jun 27 04:48:47 PM PDT 24
Finished Jun 27 04:48:49 PM PDT 24
Peak memory 223240 kb
Host smart-775638e4-a070-499e-affc-e9a578764245
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710286329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.2710286329
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.124491989
Short name T809
Test name
Test status
Simulation time 743029168 ps
CPU time 3.82 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:22 PM PDT 24
Peak memory 212992 kb
Host smart-53d4435a-5ab5-498e-bb65-a3d0fc6c4a1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124491989 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.124491989
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2295161588
Short name T299
Test name
Test status
Simulation time 154776430 ps
CPU time 1.01 seconds
Started Jun 27 04:48:47 PM PDT 24
Finished Jun 27 04:48:49 PM PDT 24
Peak memory 204516 kb
Host smart-8b95482a-9c47-4532-9208-558f13ea1c4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295161588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2295161588
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.2058058519
Short name T481
Test name
Test status
Simulation time 264969022 ps
CPU time 1.41 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:48:51 PM PDT 24
Peak memory 204748 kb
Host smart-5e6bfeb5-ecd8-45d4-98e5-3224f0bfe5e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058058519 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.i2c_target_fifo_reset_tx.2058058519
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.4210447429
Short name T501
Test name
Test status
Simulation time 256047998 ps
CPU time 0.94 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:15 PM PDT 24
Peak memory 204540 kb
Host smart-d4dc70da-8659-48c1-9a8f-1536aa25db48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210447429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.4210447429
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.376952653
Short name T16
Test name
Test status
Simulation time 2516644090 ps
CPU time 11.95 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:49:05 PM PDT 24
Peak memory 212772 kb
Host smart-36b965fc-d702-41e3-bfce-768555f48f8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376952653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.376952653
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1345491096
Short name T1358
Test name
Test status
Simulation time 1321143524 ps
CPU time 2.64 seconds
Started Jun 27 04:48:47 PM PDT 24
Finished Jun 27 04:48:50 PM PDT 24
Peak memory 204812 kb
Host smart-ef4b4d1f-2ec6-4211-8005-0632cf41b241
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345491096 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1345491096
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.793092321
Short name T1173
Test name
Test status
Simulation time 16652432158 ps
CPU time 293.65 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:53:43 PM PDT 24
Peak memory 4054684 kb
Host smart-40be810e-4b66-4fda-8a2f-ce5b36e2453c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793092321 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.793092321
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.43930974
Short name T1281
Test name
Test status
Simulation time 1455024792 ps
CPU time 26.45 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:49:23 PM PDT 24
Peak memory 204804 kb
Host smart-896cba6f-7518-45e6-825f-782535412b15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43930974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_targe
t_smoke.43930974
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.3005932561
Short name T617
Test name
Test status
Simulation time 6269131990 ps
CPU time 20.31 seconds
Started Jun 27 04:48:45 PM PDT 24
Finished Jun 27 04:49:06 PM PDT 24
Peak memory 223100 kb
Host smart-5caf2e1c-9de1-4a28-9b6a-dd8c1fa06072
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005932561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.3005932561
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.1051490595
Short name T875
Test name
Test status
Simulation time 12801611985 ps
CPU time 11.91 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:49:01 PM PDT 24
Peak memory 204960 kb
Host smart-40352b3c-c916-4a61-8dc2-f818ecdd80f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051490595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.1051490595
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.1120812251
Short name T831
Test name
Test status
Simulation time 37158365964 ps
CPU time 278.09 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:53:27 PM PDT 24
Peak memory 1041656 kb
Host smart-1a2151a9-691d-4abd-91a0-1433199b33a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120812251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_t
arget_stretch.1120812251
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.10505644
Short name T1031
Test name
Test status
Simulation time 1653262696 ps
CPU time 6.77 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:48:59 PM PDT 24
Peak memory 218172 kb
Host smart-648cb641-dfcb-422b-886e-588b297b011e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10505644 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_timeout.10505644
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_alert_test.3311751085
Short name T930
Test name
Test status
Simulation time 15313538 ps
CPU time 0.61 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:11 PM PDT 24
Peak memory 204392 kb
Host smart-d711dd3e-82eb-4b27-a1e2-06910a768ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311751085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.3311751085
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2981872548
Short name T1343
Test name
Test status
Simulation time 276514976 ps
CPU time 1.63 seconds
Started Jun 27 04:49:02 PM PDT 24
Finished Jun 27 04:49:05 PM PDT 24
Peak memory 213084 kb
Host smart-f6488baa-3771-45c0-be7b-bb78be9c1602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981872548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2981872548
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.3616534138
Short name T913
Test name
Test status
Simulation time 425103776 ps
CPU time 8.88 seconds
Started Jun 27 04:48:49 PM PDT 24
Finished Jun 27 04:48:59 PM PDT 24
Peak memory 291500 kb
Host smart-260a0143-1b95-421e-9b5a-4bc6be4430b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616534138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empt
y.3616534138
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.4189905330
Short name T784
Test name
Test status
Simulation time 2481838091 ps
CPU time 183.54 seconds
Started Jun 27 04:48:55 PM PDT 24
Finished Jun 27 04:52:02 PM PDT 24
Peak memory 824300 kb
Host smart-c024a13f-dd0e-4f53-ad81-0b72fcee222f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189905330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.4189905330
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.2702353101
Short name T485
Test name
Test status
Simulation time 2269070992 ps
CPU time 67.76 seconds
Started Jun 27 04:48:49 PM PDT 24
Finished Jun 27 04:49:59 PM PDT 24
Peak memory 684248 kb
Host smart-859416ab-e8ac-417f-8128-a038301ec86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702353101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.2702353101
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.2980738453
Short name T351
Test name
Test status
Simulation time 1003432640 ps
CPU time 6.77 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:48:56 PM PDT 24
Peak memory 204824 kb
Host smart-02c709d5-5968-43c1-93c6-88e73b50d21c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980738453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.
2980738453
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.3573735166
Short name T574
Test name
Test status
Simulation time 3921477975 ps
CPU time 98.99 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:50:38 PM PDT 24
Peak memory 1044496 kb
Host smart-5b19a57e-4aeb-447d-8b35-5d86af6e41c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573735166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.3573735166
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.4184255161
Short name T497
Test name
Test status
Simulation time 523097027 ps
CPU time 21.73 seconds
Started Jun 27 04:49:18 PM PDT 24
Finished Jun 27 04:49:50 PM PDT 24
Peak memory 204876 kb
Host smart-29b0ccf1-ac71-422c-95df-3b3a337ce79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184255161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.4184255161
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.316101214
Short name T1205
Test name
Test status
Simulation time 4289259162 ps
CPU time 26.31 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:39 PM PDT 24
Peak memory 299080 kb
Host smart-58ac8f82-fb44-4717-916d-fefd87a30dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316101214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.316101214
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.2952094575
Short name T686
Test name
Test status
Simulation time 55387151 ps
CPU time 0.64 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:48:50 PM PDT 24
Peak memory 204492 kb
Host smart-c3f08550-e2cd-4d72-b672-a96f351f00e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952094575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2952094575
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1427579667
Short name T233
Test name
Test status
Simulation time 50583085682 ps
CPU time 2599.88 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 05:32:15 PM PDT 24
Peak memory 3736976 kb
Host smart-2dce4ebd-20d9-4643-a817-cf453ed4968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427579667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1427579667
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.1792271983
Short name T899
Test name
Test status
Simulation time 361091671 ps
CPU time 13.75 seconds
Started Jun 27 04:48:55 PM PDT 24
Finished Jun 27 04:49:12 PM PDT 24
Peak memory 204700 kb
Host smart-1f64d20e-589e-445d-85f5-3a73307cd504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792271983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.1792271983
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.3767592552
Short name T1247
Test name
Test status
Simulation time 3545853336 ps
CPU time 35.42 seconds
Started Jun 27 04:48:48 PM PDT 24
Finished Jun 27 04:49:25 PM PDT 24
Peak memory 343600 kb
Host smart-6773984b-f2b3-4f1d-bff4-bf1b29eef322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767592552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.3767592552
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2899731279
Short name T1320
Test name
Test status
Simulation time 1726429176 ps
CPU time 38.36 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:49:35 PM PDT 24
Peak memory 213008 kb
Host smart-9bd788d8-976e-436b-903c-85586f164d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899731279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2899731279
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.2324413027
Short name T193
Test name
Test status
Simulation time 113691444 ps
CPU time 0.92 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 223184 kb
Host smart-dc5cd441-eb5c-4401-892d-ab62c7a23c87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324413027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.2324413027
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.2664314378
Short name T719
Test name
Test status
Simulation time 634533360 ps
CPU time 3.3 seconds
Started Jun 27 04:49:01 PM PDT 24
Finished Jun 27 04:49:06 PM PDT 24
Peak memory 213012 kb
Host smart-6463778a-8427-4145-86f1-303cfe7486de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664314378 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.2664314378
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3387698353
Short name T1395
Test name
Test status
Simulation time 720312476 ps
CPU time 1.36 seconds
Started Jun 27 04:48:57 PM PDT 24
Finished Jun 27 04:49:00 PM PDT 24
Peak memory 212952 kb
Host smart-d5f3cc7c-a2e4-4f71-a0bd-a4a9f6e352eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387698353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3387698353
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.2362590492
Short name T1365
Test name
Test status
Simulation time 280445271 ps
CPU time 0.94 seconds
Started Jun 27 04:49:02 PM PDT 24
Finished Jun 27 04:49:05 PM PDT 24
Peak memory 204592 kb
Host smart-8513d406-b1a1-44a8-909a-c84753629001
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362590492 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.2362590492
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.65251280
Short name T1254
Test name
Test status
Simulation time 2987420107 ps
CPU time 2.69 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:23 PM PDT 24
Peak memory 204916 kb
Host smart-cd305805-b0f3-4994-9169-3b2f6b957616
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65251280 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.65251280
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.3799875513
Short name T420
Test name
Test status
Simulation time 986499691 ps
CPU time 1.25 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 204608 kb
Host smart-5c713096-47d6-4c65-a98f-83637ecff1ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799875513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.3799875513
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2400400630
Short name T1047
Test name
Test status
Simulation time 4504677678 ps
CPU time 5.35 seconds
Started Jun 27 04:48:59 PM PDT 24
Finished Jun 27 04:49:06 PM PDT 24
Peak memory 213144 kb
Host smart-0021f740-6831-4ce5-8e81-d69a8cd2f580
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400400630 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2400400630
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.1551538363
Short name T512
Test name
Test status
Simulation time 23213272595 ps
CPU time 62.62 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:49:59 PM PDT 24
Peak memory 1367004 kb
Host smart-a4509003-5cd5-4e7c-b85c-c4a8e6f1acf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551538363 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.1551538363
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.3067339492
Short name T735
Test name
Test status
Simulation time 6559955464 ps
CPU time 11.91 seconds
Started Jun 27 04:49:02 PM PDT 24
Finished Jun 27 04:49:16 PM PDT 24
Peak memory 204956 kb
Host smart-76106cb2-81ce-442c-9e06-8b746061e1a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067339492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.3067339492
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.4095714125
Short name T1216
Test name
Test status
Simulation time 6700602572 ps
CPU time 70.05 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:50:17 PM PDT 24
Peak memory 209788 kb
Host smart-92307a96-bc3c-448d-ab12-b2f3dc9c9216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095714125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.4095714125
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2449270168
Short name T790
Test name
Test status
Simulation time 30007274149 ps
CPU time 16.19 seconds
Started Jun 27 04:48:55 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 420544 kb
Host smart-5163a92f-46ac-4344-84d2-957e3bd8e719
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449270168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2449270168
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1147085411
Short name T134
Test name
Test status
Simulation time 20213483535 ps
CPU time 902.47 seconds
Started Jun 27 04:48:55 PM PDT 24
Finished Jun 27 05:04:01 PM PDT 24
Peak memory 4854712 kb
Host smart-8ed1e752-ef24-4c93-a25c-145ea81dcfb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147085411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1147085411
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.1667150287
Short name T358
Test name
Test status
Simulation time 1421664711 ps
CPU time 7.43 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:28 PM PDT 24
Peak memory 219044 kb
Host smart-88abeb6d-d637-4e3e-88c4-2c8798eac55a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667150287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.1667150287
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_alert_test.4185803641
Short name T354
Test name
Test status
Simulation time 70685292 ps
CPU time 0.63 seconds
Started Jun 27 04:49:29 PM PDT 24
Finished Jun 27 04:49:36 PM PDT 24
Peak memory 204472 kb
Host smart-907e66b1-ea49-4422-b0dd-713c105df85a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185803641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.4185803641
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.3434595088
Short name T779
Test name
Test status
Simulation time 606219971 ps
CPU time 2.4 seconds
Started Jun 27 04:49:14 PM PDT 24
Finished Jun 27 04:49:28 PM PDT 24
Peak memory 213108 kb
Host smart-5686def2-dd6e-44ff-935e-e421f8839154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434595088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.3434595088
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1377194590
Short name T130
Test name
Test status
Simulation time 860483781 ps
CPU time 19.94 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 279996 kb
Host smart-4d8c7199-11a2-4fc7-af84-a6f823e05918
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377194590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1377194590
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.3647654162
Short name T1054
Test name
Test status
Simulation time 2444657062 ps
CPU time 161.4 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:52:16 PM PDT 24
Peak memory 733064 kb
Host smart-d4f61b02-85e6-4ee4-946a-73c6b6f31937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647654162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.3647654162
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.1738426322
Short name T1206
Test name
Test status
Simulation time 23145367190 ps
CPU time 61.93 seconds
Started Jun 27 04:49:11 PM PDT 24
Finished Jun 27 04:50:24 PM PDT 24
Peak memory 669788 kb
Host smart-3ab885ec-c81d-4fb2-b8d0-df80e05afc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738426322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.1738426322
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.3224897224
Short name T743
Test name
Test status
Simulation time 108163290 ps
CPU time 0.98 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:32 PM PDT 24
Peak memory 204476 kb
Host smart-ef81eddb-97ef-46ec-bf24-01eb773af163
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224897224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.3224897224
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1325550941
Short name T439
Test name
Test status
Simulation time 376239167 ps
CPU time 9.53 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:49:39 PM PDT 24
Peak memory 235976 kb
Host smart-6b461ab4-0279-4106-a835-aed114cd8fea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325550941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1325550941
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2865042022
Short name T596
Test name
Test status
Simulation time 9544314026 ps
CPU time 336.68 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:54:56 PM PDT 24
Peak memory 1342508 kb
Host smart-53d5105a-fe22-4583-a155-7f0264671ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865042022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2865042022
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1054143519
Short name T419
Test name
Test status
Simulation time 2629752678 ps
CPU time 24.45 seconds
Started Jun 27 04:49:40 PM PDT 24
Finished Jun 27 04:50:10 PM PDT 24
Peak memory 204892 kb
Host smart-34a0f7ba-599a-4492-ad8d-702adee3cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054143519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1054143519
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.171911890
Short name T374
Test name
Test status
Simulation time 4182049111 ps
CPU time 23.2 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:50:12 PM PDT 24
Peak memory 328204 kb
Host smart-efedb98d-175e-4cf1-8932-bc3d190dc72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171911890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.171911890
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.418633997
Short name T878
Test name
Test status
Simulation time 19056527 ps
CPU time 0.65 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 204560 kb
Host smart-5ec411f4-dec9-46c8-ba4b-cfaa17dec124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418633997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.418633997
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.1632504840
Short name T1228
Test name
Test status
Simulation time 27157963549 ps
CPU time 47.04 seconds
Started Jun 27 04:49:36 PM PDT 24
Finished Jun 27 04:50:29 PM PDT 24
Peak memory 218176 kb
Host smart-6b59f2b8-d24b-4997-8275-3429efcacccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632504840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.1632504840
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.2772918010
Short name T638
Test name
Test status
Simulation time 408395994 ps
CPU time 1.01 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:49:32 PM PDT 24
Peak memory 204544 kb
Host smart-b69b7774-8eff-43d7-abf3-732dcb434598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772918010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.2772918010
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2416046467
Short name T1330
Test name
Test status
Simulation time 2116495875 ps
CPU time 45.32 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 462348 kb
Host smart-ea7dbda6-2271-4d4d-906a-e2425bf33c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416046467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2416046467
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.2036802679
Short name T502
Test name
Test status
Simulation time 1325140984 ps
CPU time 29.1 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:50:02 PM PDT 24
Peak memory 212880 kb
Host smart-1834914d-e105-4b8b-b8da-21289d6d0614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036802679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.2036802679
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.1179313819
Short name T451
Test name
Test status
Simulation time 1205416785 ps
CPU time 3.39 seconds
Started Jun 27 04:49:37 PM PDT 24
Finished Jun 27 04:49:46 PM PDT 24
Peak memory 204876 kb
Host smart-f14e863c-c80c-44b7-9ec2-5936040412c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179313819 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.1179313819
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.1477111392
Short name T920
Test name
Test status
Simulation time 235374208 ps
CPU time 0.83 seconds
Started Jun 27 04:49:39 PM PDT 24
Finished Jun 27 04:49:44 PM PDT 24
Peak memory 204528 kb
Host smart-b82c1a83-e85e-4f36-9209-f74e08e307cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477111392 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.1477111392
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.1816444335
Short name T422
Test name
Test status
Simulation time 176529369 ps
CPU time 1.15 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:32 PM PDT 24
Peak memory 204600 kb
Host smart-a7116e2f-888c-4766-bacd-cf6d65c24e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816444335 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.1816444335
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.3867023297
Short name T361
Test name
Test status
Simulation time 139195154 ps
CPU time 0.9 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:32 PM PDT 24
Peak memory 204540 kb
Host smart-1b19f1f1-992d-4438-96ec-c50f6f19abaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867023297 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.3867023297
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.473914297
Short name T739
Test name
Test status
Simulation time 2503745081 ps
CPU time 3.04 seconds
Started Jun 27 04:49:31 PM PDT 24
Finished Jun 27 04:49:41 PM PDT 24
Peak memory 204856 kb
Host smart-27242dd8-b8ca-469f-a95a-d4e0100e1c42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473914297 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 10.i2c_target_hrst.473914297
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2685877579
Short name T660
Test name
Test status
Simulation time 1583723363 ps
CPU time 4.52 seconds
Started Jun 27 04:49:21 PM PDT 24
Finished Jun 27 04:49:34 PM PDT 24
Peak memory 204784 kb
Host smart-e523a8ee-a627-4d0f-992b-ef46cee915cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685877579 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2685877579
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.4136201859
Short name T1233
Test name
Test status
Simulation time 16291041057 ps
CPU time 294.3 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:54:27 PM PDT 24
Peak memory 3885648 kb
Host smart-7e92ee8d-bb3a-4b53-a021-189bb24a9f0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136201859 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.4136201859
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.2286403982
Short name T632
Test name
Test status
Simulation time 1050307381 ps
CPU time 14.65 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:34 PM PDT 24
Peak memory 204744 kb
Host smart-13704418-e782-42b9-adc3-6d81c1fa54b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286403982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.2286403982
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.3004755095
Short name T450
Test name
Test status
Simulation time 1091613311 ps
CPU time 16.24 seconds
Started Jun 27 04:49:49 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 220784 kb
Host smart-96198434-7b9c-491e-9280-ccc20369d8b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004755095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.3004755095
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.993877435
Short name T290
Test name
Test status
Simulation time 13907108590 ps
CPU time 27.35 seconds
Started Jun 27 04:49:32 PM PDT 24
Finished Jun 27 04:50:05 PM PDT 24
Peak memory 204904 kb
Host smart-0a14302f-0ba4-4a46-89da-1c2a91a824dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993877435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_wr.993877435
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.3310211914
Short name T1251
Test name
Test status
Simulation time 15062139897 ps
CPU time 323.17 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:54:56 PM PDT 24
Peak memory 2493384 kb
Host smart-2e02e5c0-89f8-4f24-a25b-d6de43258539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310211914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.3310211914
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.1935607710
Short name T573
Test name
Test status
Simulation time 4827411779 ps
CPU time 6.78 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:28 PM PDT 24
Peak memory 219712 kb
Host smart-66b291f9-f753-4753-a41f-2779e9f9bd59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935607710 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.1935607710
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_alert_test.4259395860
Short name T988
Test name
Test status
Simulation time 39135393 ps
CPU time 0.64 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:49:36 PM PDT 24
Peak memory 204472 kb
Host smart-6cbcada1-8f0e-4dbe-b70f-4f3bd842e7ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259395860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.4259395860
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.406795359
Short name T723
Test name
Test status
Simulation time 105413884 ps
CPU time 2.19 seconds
Started Jun 27 04:49:18 PM PDT 24
Finished Jun 27 04:49:30 PM PDT 24
Peak memory 213032 kb
Host smart-8c1da8be-a568-483a-9a7c-c1096adf2a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406795359 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.406795359
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.242554276
Short name T703
Test name
Test status
Simulation time 506712677 ps
CPU time 12.46 seconds
Started Jun 27 04:49:26 PM PDT 24
Finished Jun 27 04:49:45 PM PDT 24
Peak memory 248100 kb
Host smart-5d90f47c-f961-48e1-9af8-ab7358115466
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242554276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.242554276
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.239690102
Short name T587
Test name
Test status
Simulation time 2321199568 ps
CPU time 68.34 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 681472 kb
Host smart-4f6c0ddb-93b7-4b76-bcfd-ab961cb6b588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239690102 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.239690102
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.2309908320
Short name T1230
Test name
Test status
Simulation time 1333257811 ps
CPU time 32.38 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 496500 kb
Host smart-c28a46f5-29ac-46e2-aff7-f9a63d94b50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309908320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.2309908320
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1807941015
Short name T1090
Test name
Test status
Simulation time 220453930 ps
CPU time 0.98 seconds
Started Jun 27 04:49:39 PM PDT 24
Finished Jun 27 04:49:44 PM PDT 24
Peak memory 204512 kb
Host smart-a661e8b1-86fa-4f1e-a420-3d42d2b4b00a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807941015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1807941015
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.2091181371
Short name T637
Test name
Test status
Simulation time 136684714 ps
CPU time 3.2 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:34 PM PDT 24
Peak memory 224300 kb
Host smart-e018f1ce-320f-47fb-a494-a5042dcfb2ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091181371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.2091181371
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.2333434885
Short name T555
Test name
Test status
Simulation time 4897397665 ps
CPU time 324.07 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 04:55:01 PM PDT 24
Peak memory 1267592 kb
Host smart-3c82f834-57ee-4982-a786-28e9073a643d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333434885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.2333434885
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.549107274
Short name T1094
Test name
Test status
Simulation time 377121100 ps
CPU time 4.85 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 204764 kb
Host smart-cb473bd8-af6a-49cb-bd7a-dfd2a4fc5c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549107274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.549107274
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3749738922
Short name T1160
Test name
Test status
Simulation time 18794022145 ps
CPU time 28.27 seconds
Started Jun 27 04:49:38 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 332576 kb
Host smart-f250a2ad-fe0b-4d14-a4fa-7fb4fef8557e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749738922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3749738922
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.1066208777
Short name T438
Test name
Test status
Simulation time 116732371 ps
CPU time 0.65 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:49:32 PM PDT 24
Peak memory 204512 kb
Host smart-bbbc8a3b-650d-43b9-a4b1-44cbf18ae27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066208777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.1066208777
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1802493029
Short name T1363
Test name
Test status
Simulation time 3356730186 ps
CPU time 209.27 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:52:59 PM PDT 24
Peak memory 948972 kb
Host smart-73ee4595-73a5-4a0d-9d90-69b6d043952a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802493029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1802493029
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.2988538737
Short name T1275
Test name
Test status
Simulation time 2294286303 ps
CPU time 28.39 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:50:00 PM PDT 24
Peak memory 489312 kb
Host smart-0d819412-5ac8-4018-8daa-f491d0df3194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988538737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.2988538737
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.2243513214
Short name T1121
Test name
Test status
Simulation time 18490852254 ps
CPU time 77 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:50:30 PM PDT 24
Peak memory 350720 kb
Host smart-d361da9e-8bb0-4209-be10-d88109c69238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243513214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.2243513214
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.805370993
Short name T119
Test name
Test status
Simulation time 5987615715 ps
CPU time 135.78 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 742196 kb
Host smart-1bcfbe88-e1da-4865-87b7-b9ce9bada014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805370993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.805370993
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.1896677639
Short name T464
Test name
Test status
Simulation time 2521949644 ps
CPU time 35.65 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 212852 kb
Host smart-595d3241-69ea-43ac-9e5d-a7f55de0b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896677639 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.1896677639
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.787581423
Short name T1154
Test name
Test status
Simulation time 1038276727 ps
CPU time 5.34 seconds
Started Jun 27 04:49:45 PM PDT 24
Finished Jun 27 04:49:55 PM PDT 24
Peak memory 214936 kb
Host smart-93c62f4d-d657-466b-8ad2-32b9403c08ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787581423 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.787581423
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.370200543
Short name T532
Test name
Test status
Simulation time 738543136 ps
CPU time 1.31 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:49:37 PM PDT 24
Peak memory 214616 kb
Host smart-ccbb692d-54bc-4685-b993-c55ccb58ccb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370200543 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_acq.370200543
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.2649629375
Short name T728
Test name
Test status
Simulation time 153396134 ps
CPU time 1.07 seconds
Started Jun 27 04:49:36 PM PDT 24
Finished Jun 27 04:49:43 PM PDT 24
Peak memory 204716 kb
Host smart-d165d4a7-66fb-4228-ad20-0b76921c6afc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649629375 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.2649629375
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.3904904484
Short name T1404
Test name
Test status
Simulation time 428594914 ps
CPU time 2.34 seconds
Started Jun 27 04:49:39 PM PDT 24
Finished Jun 27 04:49:47 PM PDT 24
Peak memory 204804 kb
Host smart-ee6f7698-835b-4012-ab37-0112ba6e58df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904904484 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.3904904484
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.2855848202
Short name T1426
Test name
Test status
Simulation time 324133110 ps
CPU time 1.12 seconds
Started Jun 27 04:49:38 PM PDT 24
Finished Jun 27 04:49:44 PM PDT 24
Peak memory 204520 kb
Host smart-6eb8d8d2-0da4-4024-8743-7ac9de25b043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855848202 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.2855848202
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.1926874353
Short name T755
Test name
Test status
Simulation time 2392900869 ps
CPU time 6.46 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:49:55 PM PDT 24
Peak memory 221100 kb
Host smart-25d2819a-6326-496e-9a37-a962c8be3e7c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926874353 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.1926874353
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.3840068745
Short name T1313
Test name
Test status
Simulation time 20313958241 ps
CPU time 142.66 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 2430556 kb
Host smart-e964bc19-5dd2-4469-8f8c-20dcba5e3201
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840068745 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.3840068745
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.175601963
Short name T381
Test name
Test status
Simulation time 1196182378 ps
CPU time 18.23 seconds
Started Jun 27 04:49:14 PM PDT 24
Finished Jun 27 04:49:43 PM PDT 24
Peak memory 204816 kb
Host smart-f9627a69-c0ff-4ad5-b6ae-4a15b945a069
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175601963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_tar
get_smoke.175601963
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.1238595303
Short name T446
Test name
Test status
Simulation time 1390912842 ps
CPU time 5.09 seconds
Started Jun 27 04:49:18 PM PDT 24
Finished Jun 27 04:49:36 PM PDT 24
Peak memory 204772 kb
Host smart-ccf09007-a1e0-42dc-81ad-5e83f78a6ce7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238595303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.1238595303
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.415648848
Short name T607
Test name
Test status
Simulation time 21239123590 ps
CPU time 11.61 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:49:44 PM PDT 24
Peak memory 204936 kb
Host smart-95529140-401e-4b63-88f4-09ecebfb445f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415648848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.415648848
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.703883638
Short name T1299
Test name
Test status
Simulation time 7960491830 ps
CPU time 6.99 seconds
Started Jun 27 04:49:21 PM PDT 24
Finished Jun 27 04:49:36 PM PDT 24
Peak memory 221092 kb
Host smart-7816c82e-9006-4cb1-832a-d0f4fe711ec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703883638 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_timeout.703883638
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.3361986319
Short name T317
Test name
Test status
Simulation time 77378493 ps
CPU time 0.63 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 04:49:37 PM PDT 24
Peak memory 204460 kb
Host smart-cf26d442-84dc-483e-91b3-2ba358db1cf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361986319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.3361986319
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.1447333015
Short name T1024
Test name
Test status
Simulation time 1002978177 ps
CPU time 2.2 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:49:38 PM PDT 24
Peak memory 221108 kb
Host smart-78f29d8a-453f-4361-bee0-1aa75ea5924e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447333015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.1447333015
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2786431019
Short name T581
Test name
Test status
Simulation time 419823114 ps
CPU time 5.4 seconds
Started Jun 27 04:49:46 PM PDT 24
Finished Jun 27 04:49:56 PM PDT 24
Peak memory 263156 kb
Host smart-2bb287d5-dfef-4af3-9098-3b315b7a73bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786431019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2786431019
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3677270165
Short name T517
Test name
Test status
Simulation time 1357714190 ps
CPU time 78.5 seconds
Started Jun 27 04:49:27 PM PDT 24
Finished Jun 27 04:50:53 PM PDT 24
Peak memory 515756 kb
Host smart-7fcbe4f2-3e76-4d6a-a632-84cb9ecaf912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677270165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3677270165
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.2960283902
Short name T658
Test name
Test status
Simulation time 17338169506 ps
CPU time 82.85 seconds
Started Jun 27 04:49:47 PM PDT 24
Finished Jun 27 04:51:14 PM PDT 24
Peak memory 829332 kb
Host smart-eb4ebee8-a50a-4088-baf9-66837580c536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960283902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.2960283902
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.1660135360
Short name T1026
Test name
Test status
Simulation time 104391265 ps
CPU time 0.96 seconds
Started Jun 27 04:49:38 PM PDT 24
Finished Jun 27 04:49:44 PM PDT 24
Peak memory 204476 kb
Host smart-8797e5e9-7e31-44cc-a3bf-a48c490c6306
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660135360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.1660135360
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.3885209444
Short name T1394
Test name
Test status
Simulation time 934672177 ps
CPU time 5.75 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 04:49:43 PM PDT 24
Peak memory 243780 kb
Host smart-bc6e809a-b4a5-462e-987c-53cc2221ae39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885209444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.3885209444
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1338927775
Short name T1351
Test name
Test status
Simulation time 88570307863 ps
CPU time 110.85 seconds
Started Jun 27 04:49:31 PM PDT 24
Finished Jun 27 04:51:29 PM PDT 24
Peak memory 1271228 kb
Host smart-617c83d3-8bb9-49b3-9b1d-936221f80e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338927775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1338927775
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_override.2314006607
Short name T773
Test name
Test status
Simulation time 87035792 ps
CPU time 0.69 seconds
Started Jun 27 04:49:34 PM PDT 24
Finished Jun 27 04:49:40 PM PDT 24
Peak memory 204564 kb
Host smart-736807ed-1a11-491e-b9df-b8ce0ea11a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314006607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2314006607
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.690674600
Short name T416
Test name
Test status
Simulation time 7642658940 ps
CPU time 10.96 seconds
Started Jun 27 04:49:40 PM PDT 24
Finished Jun 27 04:50:02 PM PDT 24
Peak memory 213420 kb
Host smart-b720c3c5-6f68-49ee-8ec5-7c43f49eeae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690674600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.690674600
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.2698771927
Short name T537
Test name
Test status
Simulation time 63098523 ps
CPU time 3.22 seconds
Started Jun 27 04:49:27 PM PDT 24
Finished Jun 27 04:49:37 PM PDT 24
Peak memory 216244 kb
Host smart-07301a30-d3fd-4aad-bd60-1066066bd5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698771927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.2698771927
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.2610447622
Short name T1342
Test name
Test status
Simulation time 10570526939 ps
CPU time 89.18 seconds
Started Jun 27 04:49:33 PM PDT 24
Finished Jun 27 04:51:08 PM PDT 24
Peak memory 362236 kb
Host smart-c20b3bbb-eb2d-4ebf-bea0-fe2c57006058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610447622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.2610447622
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.163722955
Short name T276
Test name
Test status
Simulation time 31300165167 ps
CPU time 722.9 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 05:01:40 PM PDT 24
Peak memory 1639420 kb
Host smart-b045da46-6d34-4a96-87c1-cab68d746c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163722955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.163722955
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2724400497
Short name T981
Test name
Test status
Simulation time 4665382737 ps
CPU time 10.06 seconds
Started Jun 27 04:49:44 PM PDT 24
Finished Jun 27 04:50:00 PM PDT 24
Peak memory 220184 kb
Host smart-f00c8dbc-aa3d-4664-9d45-ae09dc7f3f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724400497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2724400497
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.2497420281
Short name T310
Test name
Test status
Simulation time 4665912747 ps
CPU time 3.97 seconds
Started Jun 27 04:49:27 PM PDT 24
Finished Jun 27 04:49:38 PM PDT 24
Peak memory 213044 kb
Host smart-45870c13-666d-4076-91ad-23118e258e13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497420281 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.2497420281
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.3216016472
Short name T1159
Test name
Test status
Simulation time 547565769 ps
CPU time 1.06 seconds
Started Jun 27 04:49:27 PM PDT 24
Finished Jun 27 04:49:35 PM PDT 24
Peak memory 204540 kb
Host smart-357ce508-a31e-4a6d-a704-e60b1f13765f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216016472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_fifo_reset_acq.3216016472
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.2041178896
Short name T1408
Test name
Test status
Simulation time 228327409 ps
CPU time 0.82 seconds
Started Jun 27 04:49:44 PM PDT 24
Finished Jun 27 04:49:50 PM PDT 24
Peak memory 204632 kb
Host smart-edc432d0-9ac7-44ce-8e83-718b9593ad73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041178896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.2041178896
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.1740763764
Short name T253
Test name
Test status
Simulation time 5058559744 ps
CPU time 2.25 seconds
Started Jun 27 04:49:36 PM PDT 24
Finished Jun 27 04:49:43 PM PDT 24
Peak memory 204896 kb
Host smart-c64a6ab9-1cc0-45e6-b5c3-86dbceae5e58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740763764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.1740763764
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.3602502803
Short name T294
Test name
Test status
Simulation time 178064670 ps
CPU time 1.36 seconds
Started Jun 27 04:49:29 PM PDT 24
Finished Jun 27 04:49:37 PM PDT 24
Peak memory 204544 kb
Host smart-000479c8-9322-4198-8381-40d995367dff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602502803 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.3602502803
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.973968102
Short name T759
Test name
Test status
Simulation time 1236131081 ps
CPU time 4.15 seconds
Started Jun 27 04:49:44 PM PDT 24
Finished Jun 27 04:49:54 PM PDT 24
Peak memory 204828 kb
Host smart-ec4f8c8d-038e-4bb4-8a4c-2fe10d8dac17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973968102 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_hrst.973968102
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.1356820757
Short name T825
Test name
Test status
Simulation time 2638665117 ps
CPU time 6.61 seconds
Started Jun 27 04:49:33 PM PDT 24
Finished Jun 27 04:49:45 PM PDT 24
Peak memory 213072 kb
Host smart-a968e590-225e-40bb-b355-0eda66ddf386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356820757 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 12.i2c_target_intr_smoke.1356820757
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.735143723
Short name T538
Test name
Test status
Simulation time 9031853843 ps
CPU time 23.74 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 04:50:01 PM PDT 24
Peak memory 743468 kb
Host smart-7177cbaf-4902-4637-a511-759c808e3a6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735143723 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.735143723
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3361860776
Short name T736
Test name
Test status
Simulation time 2487896583 ps
CPU time 13.2 seconds
Started Jun 27 04:49:33 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 204936 kb
Host smart-2528d854-dedf-4dbb-96d2-61c90137b163
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361860776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3361860776
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.491313710
Short name T1172
Test name
Test status
Simulation time 18002973029 ps
CPU time 25.71 seconds
Started Jun 27 04:49:39 PM PDT 24
Finished Jun 27 04:50:10 PM PDT 24
Peak memory 236660 kb
Host smart-24c33504-7a29-4f7f-96cb-57838e92ae2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491313710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_rd.491313710
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.481336820
Short name T661
Test name
Test status
Simulation time 32186674272 ps
CPU time 37.92 seconds
Started Jun 27 04:49:31 PM PDT 24
Finished Jun 27 04:50:15 PM PDT 24
Peak memory 852796 kb
Host smart-b2d84722-a1bb-4cd6-a73a-613fdd4ce4c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481336820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_wr.481336820
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.3365652448
Short name T1103
Test name
Test status
Simulation time 6994446334 ps
CPU time 163.98 seconds
Started Jun 27 04:49:31 PM PDT 24
Finished Jun 27 04:52:22 PM PDT 24
Peak memory 1879028 kb
Host smart-2ac3f8cd-4c8c-4c52-8583-d0972b025133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365652448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.3365652448
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2178365969
Short name T455
Test name
Test status
Simulation time 11608433111 ps
CPU time 6.39 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:49:53 PM PDT 24
Peak memory 210636 kb
Host smart-28a57b4d-9de5-4dc8-9898-b0655bc7c51e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178365969 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2178365969
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_alert_test.2373534310
Short name T409
Test name
Test status
Simulation time 15089869 ps
CPU time 0.6 seconds
Started Jun 27 04:49:35 PM PDT 24
Finished Jun 27 04:49:41 PM PDT 24
Peak memory 204336 kb
Host smart-d8481d9a-7f79-4ae4-ade2-49906bac4f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373534310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.2373534310
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.4169694833
Short name T417
Test name
Test status
Simulation time 2107092028 ps
CPU time 8.12 seconds
Started Jun 27 04:49:35 PM PDT 24
Finished Jun 27 04:49:48 PM PDT 24
Peak memory 288296 kb
Host smart-f8ca42a6-dff1-4337-b8cc-b4e6eb2e7c2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169694833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.4169694833
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.2122026700
Short name T1290
Test name
Test status
Simulation time 4887478608 ps
CPU time 37.28 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:50:26 PM PDT 24
Peak memory 521036 kb
Host smart-5e4381ee-f2c2-45dd-9c31-81c8d8c26420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122026700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.2122026700
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.871036008
Short name T690
Test name
Test status
Simulation time 1703278209 ps
CPU time 106.75 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:51:34 PM PDT 24
Peak memory 538444 kb
Host smart-4c3a2fed-1a8c-41f5-88c5-8ee2f5ff19d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871036008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.871036008
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.548865115
Short name T1296
Test name
Test status
Simulation time 469895571 ps
CPU time 0.87 seconds
Started Jun 27 04:49:35 PM PDT 24
Finished Jun 27 04:49:41 PM PDT 24
Peak memory 204476 kb
Host smart-a62b36a5-2581-4c0b-9536-3f22a81ab0f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548865115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_fm
t.548865115
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.4152703117
Short name T386
Test name
Test status
Simulation time 3025546447 ps
CPU time 9.85 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:49:57 PM PDT 24
Peak memory 204892 kb
Host smart-b9688aef-13ca-439a-a3e7-8fddc29388d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152703117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.4152703117
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.4052169803
Short name T1317
Test name
Test status
Simulation time 3727928275 ps
CPU time 101.89 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:51:30 PM PDT 24
Peak memory 1056332 kb
Host smart-0d01b5ce-d439-4eaf-943a-11bfc6c4cd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052169803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.4052169803
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1747978852
Short name T539
Test name
Test status
Simulation time 528795787 ps
CPU time 21.76 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:50:10 PM PDT 24
Peak memory 204792 kb
Host smart-948ddbac-2227-4c83-a5e6-bdf9be5962b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747978852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1747978852
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.1897655812
Short name T35
Test name
Test status
Simulation time 5167391033 ps
CPU time 39.16 seconds
Started Jun 27 04:49:55 PM PDT 24
Finished Jun 27 04:50:36 PM PDT 24
Peak memory 367100 kb
Host smart-b4decb78-7dce-4f9b-911b-79997ba204c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897655812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.1897655812
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.1637880977
Short name T914
Test name
Test status
Simulation time 49694881 ps
CPU time 0.64 seconds
Started Jun 27 04:49:38 PM PDT 24
Finished Jun 27 04:49:44 PM PDT 24
Peak memory 204492 kb
Host smart-96640b91-86f9-4527-b2ec-79f643b9f229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637880977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1637880977
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.3036369871
Short name T949
Test name
Test status
Simulation time 17728163643 ps
CPU time 564.83 seconds
Started Jun 27 04:49:38 PM PDT 24
Finished Jun 27 04:59:07 PM PDT 24
Peak memory 213124 kb
Host smart-a0c2bc1e-47c0-4b69-8f17-5d3adf8254d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036369871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.3036369871
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.4261581267
Short name T234
Test name
Test status
Simulation time 428037407 ps
CPU time 3.96 seconds
Started Jun 27 04:49:47 PM PDT 24
Finished Jun 27 04:49:55 PM PDT 24
Peak memory 204784 kb
Host smart-633b3c9e-8b70-475e-97d2-72d9a4ccd5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261581267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.4261581267
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1401342578
Short name T1013
Test name
Test status
Simulation time 7206696142 ps
CPU time 29.5 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 376920 kb
Host smart-431aed82-d65e-4fdd-aecd-e1b019ffcf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401342578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1401342578
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3701504205
Short name T1142
Test name
Test status
Simulation time 1360016341 ps
CPU time 29.06 seconds
Started Jun 27 04:49:27 PM PDT 24
Finished Jun 27 04:50:03 PM PDT 24
Peak memory 213088 kb
Host smart-317af3c8-477b-4e35-99e2-88901691778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701504205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3701504205
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1426127211
Short name T909
Test name
Test status
Simulation time 622982046 ps
CPU time 1.22 seconds
Started Jun 27 04:49:39 PM PDT 24
Finished Jun 27 04:49:46 PM PDT 24
Peak memory 204712 kb
Host smart-e15c5a54-e374-41e7-b466-a5edf3ad17fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426127211 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1426127211
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3370985557
Short name T794
Test name
Test status
Simulation time 381519122 ps
CPU time 1.01 seconds
Started Jun 27 04:49:34 PM PDT 24
Finished Jun 27 04:49:40 PM PDT 24
Peak memory 204760 kb
Host smart-40f811f3-da61-4a4f-8bf9-aa45e55a4bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370985557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3370985557
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.3485732842
Short name T1190
Test name
Test status
Simulation time 1208207632 ps
CPU time 1.81 seconds
Started Jun 27 04:49:40 PM PDT 24
Finished Jun 27 04:49:48 PM PDT 24
Peak memory 204644 kb
Host smart-3fc9ff59-2961-452c-a893-7b5d44ffbf99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485732842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.3485732842
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.3521888982
Short name T341
Test name
Test status
Simulation time 551200891 ps
CPU time 1.32 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:04 PM PDT 24
Peak memory 204644 kb
Host smart-88295acc-864f-42cf-a6b6-e50a202c2df4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521888982 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.3521888982
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.482362979
Short name T1180
Test name
Test status
Simulation time 2771694416 ps
CPU time 3.8 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 04:49:41 PM PDT 24
Peak memory 204936 kb
Host smart-af7ca0d2-6d5d-4483-9b24-89b1c32fc097
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482362979 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.482362979
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.4050053528
Short name T505
Test name
Test status
Simulation time 10675623403 ps
CPU time 28.73 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:50:18 PM PDT 24
Peak memory 810048 kb
Host smart-f4cf39eb-2a7d-4f10-9c2c-139949d82d3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050053528 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.4050053528
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.778770056
Short name T554
Test name
Test status
Simulation time 8781744673 ps
CPU time 13.97 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:50:02 PM PDT 24
Peak memory 205168 kb
Host smart-7d9b7b1a-fa1d-47fb-a512-4fd16bc3dd33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778770056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_tar
get_smoke.778770056
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.1439126508
Short name T1161
Test name
Test status
Simulation time 7824664436 ps
CPU time 26.77 seconds
Started Jun 27 04:49:31 PM PDT 24
Finished Jun 27 04:50:04 PM PDT 24
Peak memory 222900 kb
Host smart-0cb9d85d-8d1f-415d-b50c-7ae6cd8bdc0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439126508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.1439126508
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.100070355
Short name T343
Test name
Test status
Simulation time 31832002564 ps
CPU time 34.14 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:50:21 PM PDT 24
Peak memory 721288 kb
Host smart-10a583e3-9c32-4050-800a-d288eeaeea64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100070355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_wr.100070355
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.2264527458
Short name T493
Test name
Test status
Simulation time 18515094107 ps
CPU time 834.35 seconds
Started Jun 27 04:49:44 PM PDT 24
Finished Jun 27 05:03:44 PM PDT 24
Peak memory 2299996 kb
Host smart-d5e8ea94-5767-467e-ab91-8b85006a2872
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264527458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.2264527458
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.466185327
Short name T987
Test name
Test status
Simulation time 1449503350 ps
CPU time 7.28 seconds
Started Jun 27 04:49:38 PM PDT 24
Finished Jun 27 04:49:50 PM PDT 24
Peak memory 212996 kb
Host smart-1dbf5974-9896-4653-a908-ff22fd51b090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466185327 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_timeout.466185327
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3333902920
Short name T606
Test name
Test status
Simulation time 53580213 ps
CPU time 0.62 seconds
Started Jun 27 04:49:57 PM PDT 24
Finished Jun 27 04:50:01 PM PDT 24
Peak memory 204488 kb
Host smart-7ef22730-86b9-43e4-ad36-a2535272fb06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333902920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3333902920
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.3704147124
Short name T1017
Test name
Test status
Simulation time 3467675301 ps
CPU time 5.66 seconds
Started Jun 27 04:49:55 PM PDT 24
Finished Jun 27 04:50:03 PM PDT 24
Peak memory 231304 kb
Host smart-1a367185-4a2b-4054-843e-f6237054396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704147124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.3704147124
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.944613214
Short name T1402
Test name
Test status
Simulation time 271660939 ps
CPU time 5.32 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 04:49:42 PM PDT 24
Peak memory 249916 kb
Host smart-f1e01701-e896-43f1-97b8-dd827f50413e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944613214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_empt
y.944613214
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.1363678286
Short name T912
Test name
Test status
Simulation time 7832101328 ps
CPU time 128.11 seconds
Started Jun 27 04:49:55 PM PDT 24
Finished Jun 27 04:52:05 PM PDT 24
Peak memory 675784 kb
Host smart-96c0d691-f02b-444d-b1bf-da3053e67dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363678286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.1363678286
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.2899605235
Short name T1001
Test name
Test status
Simulation time 3418662987 ps
CPU time 56.04 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:50:59 PM PDT 24
Peak memory 615672 kb
Host smart-d0f735f8-8373-4780-82dc-97b4a82ba2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899605235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.2899605235
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.4265036942
Short name T240
Test name
Test status
Simulation time 185443530 ps
CPU time 1.02 seconds
Started Jun 27 04:49:50 PM PDT 24
Finished Jun 27 04:49:54 PM PDT 24
Peak memory 204580 kb
Host smart-ffbc9f99-dc0c-4974-a7da-dc3312066a3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265036942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.4265036942
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2685910003
Short name T583
Test name
Test status
Simulation time 202888312 ps
CPU time 4.03 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:07 PM PDT 24
Peak memory 204872 kb
Host smart-63f9341a-cb67-421a-842d-b7511371cad8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685910003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2685910003
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.908689053
Short name T80
Test name
Test status
Simulation time 19612256279 ps
CPU time 342.86 seconds
Started Jun 27 04:49:50 PM PDT 24
Finished Jun 27 04:55:36 PM PDT 24
Peak memory 1341604 kb
Host smart-56bc4272-9582-42a4-8413-2b64d7563659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908689053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.908689053
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.3005078186
Short name T651
Test name
Test status
Simulation time 421121397 ps
CPU time 5.86 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 204864 kb
Host smart-e952589a-35bf-4020-bbc9-ea1163c9e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005078186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.3005078186
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.660835617
Short name T845
Test name
Test status
Simulation time 1062952393 ps
CPU time 42.42 seconds
Started Jun 27 04:49:57 PM PDT 24
Finished Jun 27 04:50:42 PM PDT 24
Peak memory 245780 kb
Host smart-6f5cf1d6-6559-45c7-ba5f-cfdff516e998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660835617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.660835617
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3898973087
Short name T560
Test name
Test status
Simulation time 34824345 ps
CPU time 0.69 seconds
Started Jun 27 04:49:47 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 204464 kb
Host smart-6a2defc1-a231-4298-a596-e101c88eb3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898973087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3898973087
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.3389564565
Short name T980
Test name
Test status
Simulation time 4416617531 ps
CPU time 89.35 seconds
Started Jun 27 04:49:29 PM PDT 24
Finished Jun 27 04:51:05 PM PDT 24
Peak memory 250400 kb
Host smart-552db29e-540c-49ee-a881-69e35ff4fc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389564565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.3389564565
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.19335270
Short name T147
Test name
Test status
Simulation time 243727429 ps
CPU time 4.65 seconds
Started Jun 27 04:49:37 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 214636 kb
Host smart-911d6ec8-61f8-4700-8e66-084014fe657f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19335270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.19335270
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.854110694
Short name T715
Test name
Test status
Simulation time 7472809183 ps
CPU time 37.74 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:50:27 PM PDT 24
Peak memory 361736 kb
Host smart-ee44af04-f36e-4826-9b45-b0fdc2e9f652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854110694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.854110694
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.2952756172
Short name T1006
Test name
Test status
Simulation time 68651243937 ps
CPU time 1815.13 seconds
Started Jun 27 04:49:55 PM PDT 24
Finished Jun 27 05:20:13 PM PDT 24
Peak memory 3326492 kb
Host smart-2e7c2b61-9402-4bd5-9d4f-99555033c2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952756172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.2952756172
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1509281821
Short name T708
Test name
Test status
Simulation time 673656847 ps
CPU time 27.27 seconds
Started Jun 27 04:49:45 PM PDT 24
Finished Jun 27 04:50:17 PM PDT 24
Peak memory 213108 kb
Host smart-b38ec3e3-912c-40e5-99c1-9afa9a321141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509281821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1509281821
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1496718136
Short name T964
Test name
Test status
Simulation time 2016633386 ps
CPU time 4.82 seconds
Started Jun 27 04:49:44 PM PDT 24
Finished Jun 27 04:49:54 PM PDT 24
Peak memory 212996 kb
Host smart-45b52a1c-471a-455d-b225-99f7aa5d3b2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496718136 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1496718136
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.1085444157
Short name T749
Test name
Test status
Simulation time 153592652 ps
CPU time 0.95 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:49:48 PM PDT 24
Peak memory 204564 kb
Host smart-027b9aaf-47d3-4b55-9971-4b0e9179ba97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085444157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.1085444157
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.4213933214
Short name T518
Test name
Test status
Simulation time 229234411 ps
CPU time 1.02 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:49:49 PM PDT 24
Peak memory 204616 kb
Host smart-e6a912f6-75b4-44f9-8c99-7563de0f3d02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213933214 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.4213933214
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.2899663577
Short name T1132
Test name
Test status
Simulation time 567424868 ps
CPU time 2.82 seconds
Started Jun 27 04:49:53 PM PDT 24
Finished Jun 27 04:49:58 PM PDT 24
Peak memory 204852 kb
Host smart-ceb72256-c9e9-41fb-b9d4-fcd147f7892a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899663577 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.2899663577
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.3599475217
Short name T415
Test name
Test status
Simulation time 549252831 ps
CPU time 1.17 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:49:48 PM PDT 24
Peak memory 204588 kb
Host smart-cd587f10-5fcd-457e-85c7-6fe144fa5397
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599475217 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.3599475217
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.3166043130
Short name T13
Test name
Test status
Simulation time 2259183264 ps
CPU time 3.38 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 204936 kb
Host smart-d48e75ea-1bab-48c3-85ca-a00f0149613f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166043130 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_intr_smoke.3166043130
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.4243109101
Short name T800
Test name
Test status
Simulation time 14112987925 ps
CPU time 30.02 seconds
Started Jun 27 04:49:36 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 848568 kb
Host smart-b783fdd0-1563-43e1-8cc8-7680124862f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243109101 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.4243109101
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.3667805886
Short name T180
Test name
Test status
Simulation time 1256827592 ps
CPU time 10.06 seconds
Started Jun 27 04:49:49 PM PDT 24
Finished Jun 27 04:50:02 PM PDT 24
Peak memory 204736 kb
Host smart-d1930994-6612-46d4-bf43-39b5656377d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667805886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.3667805886
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.2517517343
Short name T319
Test name
Test status
Simulation time 833199659 ps
CPU time 34.79 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:50:23 PM PDT 24
Peak memory 204848 kb
Host smart-e6391a0d-c1e7-4aa5-a7ec-2d0760d2fe18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517517343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.2517517343
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.2601271721
Short name T356
Test name
Test status
Simulation time 58212131775 ps
CPU time 164 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:52:30 PM PDT 24
Peak memory 1976920 kb
Host smart-57dfc352-e3fe-48ac-a777-128c4072cc73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601271721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.2601271721
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1738496229
Short name T1019
Test name
Test status
Simulation time 10029254234 ps
CPU time 82.49 seconds
Started Jun 27 04:49:46 PM PDT 24
Finished Jun 27 04:51:14 PM PDT 24
Peak memory 704028 kb
Host smart-96c5d0e6-85e2-48c7-a7e9-dc4040f446c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738496229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1738496229
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.796997460
Short name T1380
Test name
Test status
Simulation time 5848106244 ps
CPU time 7.16 seconds
Started Jun 27 04:49:44 PM PDT 24
Finished Jun 27 04:49:57 PM PDT 24
Peak memory 213180 kb
Host smart-8646e879-027f-468e-93a1-18ad42af8356
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796997460 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 14.i2c_target_timeout.796997460
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_alert_test.111987742
Short name T1453
Test name
Test status
Simulation time 42793226 ps
CPU time 0.59 seconds
Started Jun 27 04:49:54 PM PDT 24
Finished Jun 27 04:49:57 PM PDT 24
Peak memory 204460 kb
Host smart-70283858-ecdf-4a9b-871f-a7e14d932352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111987742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.111987742
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3576208901
Short name T1377
Test name
Test status
Simulation time 562932516 ps
CPU time 4.93 seconds
Started Jun 27 04:49:56 PM PDT 24
Finished Jun 27 04:50:03 PM PDT 24
Peak memory 230352 kb
Host smart-24d2b267-dd41-466f-8fe7-454e30509601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576208901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3576208901
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.4184483750
Short name T1486
Test name
Test status
Simulation time 267250002 ps
CPU time 12.62 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:50:00 PM PDT 24
Peak memory 242676 kb
Host smart-fe6ac79b-31e7-4c7f-8f74-3a299be9b194
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184483750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.4184483750
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.1628369335
Short name T72
Test name
Test status
Simulation time 3065682619 ps
CPU time 223.12 seconds
Started Jun 27 04:49:47 PM PDT 24
Finished Jun 27 04:53:35 PM PDT 24
Peak memory 925380 kb
Host smart-c3b2f5ec-81c8-4638-a004-062fb7e46f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628369335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.1628369335
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.483563746
Short name T558
Test name
Test status
Simulation time 9669621435 ps
CPU time 86.13 seconds
Started Jun 27 04:49:41 PM PDT 24
Finished Jun 27 04:51:13 PM PDT 24
Peak memory 787144 kb
Host smart-bc7acbc5-2dd4-4679-91da-c5216851fd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483563746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.483563746
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.803611518
Short name T405
Test name
Test status
Simulation time 590147367 ps
CPU time 0.86 seconds
Started Jun 27 04:49:46 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 204556 kb
Host smart-2c2f8be7-a0e8-4025-8bfc-0a82f3841771
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803611518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_fm
t.803611518
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.539949658
Short name T858
Test name
Test status
Simulation time 739856361 ps
CPU time 5.3 seconds
Started Jun 27 04:49:54 PM PDT 24
Finished Jun 27 04:50:01 PM PDT 24
Peak memory 239744 kb
Host smart-75c30bad-8120-44a9-8590-9b86cfeb5acf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539949658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
539949658
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3203887877
Short name T337
Test name
Test status
Simulation time 4367882767 ps
CPU time 123.32 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:52:12 PM PDT 24
Peak memory 1249364 kb
Host smart-c663f220-13da-494f-8df5-702440614cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203887877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3203887877
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.2041127358
Short name T767
Test name
Test status
Simulation time 1159952599 ps
CPU time 3.75 seconds
Started Jun 27 04:49:58 PM PDT 24
Finished Jun 27 04:50:04 PM PDT 24
Peak memory 204728 kb
Host smart-6e321198-40ce-40c7-bd67-e0a9c8f62e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041127358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.2041127358
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.79733015
Short name T1198
Test name
Test status
Simulation time 115173040 ps
CPU time 0.62 seconds
Started Jun 27 04:49:54 PM PDT 24
Finished Jun 27 04:49:56 PM PDT 24
Peak memory 204552 kb
Host smart-74406bb6-a997-4581-be8c-f75ba03dc042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79733015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.79733015
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.143173694
Short name T10
Test name
Test status
Simulation time 1265942141 ps
CPU time 13.2 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:50:02 PM PDT 24
Peak memory 216128 kb
Host smart-e91bd47c-1ca6-4458-b5c1-fb308ace4c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143173694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.143173694
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.3630555821
Short name T426
Test name
Test status
Simulation time 104504846 ps
CPU time 4.02 seconds
Started Jun 27 04:50:09 PM PDT 24
Finished Jun 27 04:50:17 PM PDT 24
Peak memory 217956 kb
Host smart-43d3ddeb-a022-44e8-9110-ab6c5d641f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630555821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.3630555821
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.3370857570
Short name T480
Test name
Test status
Simulation time 17012049556 ps
CPU time 15.82 seconds
Started Jun 27 04:49:56 PM PDT 24
Finished Jun 27 04:50:14 PM PDT 24
Peak memory 231192 kb
Host smart-fc8ad4dc-855e-4bd7-a84a-b1454ca794a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370857570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.3370857570
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.2453955418
Short name T1124
Test name
Test status
Simulation time 1942028746 ps
CPU time 8.96 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:18 PM PDT 24
Peak memory 213048 kb
Host smart-4a23e857-793c-4bc6-8ff6-efb3c9d5a143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453955418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2453955418
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.1724180965
Short name T490
Test name
Test status
Simulation time 1147768343 ps
CPU time 2.91 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:50:13 PM PDT 24
Peak memory 204744 kb
Host smart-f7c202e6-45bc-4728-82e4-5a8ca14b7301
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724180965 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.1724180965
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.184176971
Short name T716
Test name
Test status
Simulation time 488532025 ps
CPU time 1.09 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 204592 kb
Host smart-15bcaccb-2ce3-451b-a310-e97de7e55827
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184176971 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.184176971
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1437894284
Short name T1355
Test name
Test status
Simulation time 2010674482 ps
CPU time 2.6 seconds
Started Jun 27 04:49:53 PM PDT 24
Finished Jun 27 04:49:58 PM PDT 24
Peak memory 204668 kb
Host smart-f6ab4485-9d75-421f-bb3c-9ffc0de21181
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437894284 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1437894284
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.2256666659
Short name T778
Test name
Test status
Simulation time 335416650 ps
CPU time 1.32 seconds
Started Jun 27 04:49:56 PM PDT 24
Finished Jun 27 04:49:59 PM PDT 24
Peak memory 204528 kb
Host smart-b5dd2b5c-6006-4600-82ff-601f84eeb818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256666659 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.2256666659
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.4039868288
Short name T320
Test name
Test status
Simulation time 4097916286 ps
CPU time 5.46 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:13 PM PDT 24
Peak memory 220572 kb
Host smart-62d69225-62ae-40ab-a7c9-4396e21bfd05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039868288 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.4039868288
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.3361825833
Short name T1346
Test name
Test status
Simulation time 12717669406 ps
CPU time 208.67 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:53:38 PM PDT 24
Peak memory 3217476 kb
Host smart-fd410daf-afb7-4475-8571-dbed01e47f51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361825833 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.3361825833
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3182586796
Short name T1467
Test name
Test status
Simulation time 953206272 ps
CPU time 28.76 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 204784 kb
Host smart-977ee712-0406-4b17-96fb-3e3f312eac9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182586796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3182586796
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.3992132729
Short name T873
Test name
Test status
Simulation time 355543562 ps
CPU time 5.66 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:15 PM PDT 24
Peak memory 204792 kb
Host smart-ce253e47-6a1d-4552-be8a-a7d57fb74082
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992132729 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.3992132729
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.3840463598
Short name T668
Test name
Test status
Simulation time 15383829937 ps
CPU time 8.28 seconds
Started Jun 27 04:50:06 PM PDT 24
Finished Jun 27 04:50:19 PM PDT 24
Peak memory 204828 kb
Host smart-5932878e-125d-437b-a489-9d755f77be24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840463598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.3840463598
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2342735673
Short name T1237
Test name
Test status
Simulation time 7258470680 ps
CPU time 174.16 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:52:43 PM PDT 24
Peak memory 871708 kb
Host smart-32ca23c0-a81f-46fc-9a34-0490098f538a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342735673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2342735673
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.385293945
Short name T507
Test name
Test status
Simulation time 1440333773 ps
CPU time 7.52 seconds
Started Jun 27 04:49:43 PM PDT 24
Finished Jun 27 04:49:57 PM PDT 24
Peak memory 218944 kb
Host smart-3eb7af9d-401f-4f46-8d58-be4262a6c45e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385293945 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.385293945
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_alert_test.2128642282
Short name T811
Test name
Test status
Simulation time 35670447 ps
CPU time 0.61 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 204388 kb
Host smart-400258f4-82a4-4f72-abd8-859b42b777a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128642282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.2128642282
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1797291310
Short name T1437
Test name
Test status
Simulation time 222498107 ps
CPU time 1.47 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:09 PM PDT 24
Peak memory 213072 kb
Host smart-fa0d04d1-6099-4a74-9974-45a5f1af7cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797291310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1797291310
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.2267285853
Short name T1352
Test name
Test status
Simulation time 225120842 ps
CPU time 10.51 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:12 PM PDT 24
Peak memory 247708 kb
Host smart-054e89ea-612f-49dc-a2b2-99933d99a5d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267285853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_emp
ty.2267285853
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.2739039655
Short name T333
Test name
Test status
Simulation time 10865975289 ps
CPU time 62.62 seconds
Started Jun 27 04:50:06 PM PDT 24
Finished Jun 27 04:51:14 PM PDT 24
Peak memory 688168 kb
Host smart-283c12ee-d6f4-4781-9fc0-3c0395f96afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739039655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.2739039655
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.3061799435
Short name T589
Test name
Test status
Simulation time 1581103202 ps
CPU time 48.04 seconds
Started Jun 27 04:49:57 PM PDT 24
Finished Jun 27 04:50:47 PM PDT 24
Peak memory 579228 kb
Host smart-f5e32a86-f798-4061-898d-cdfb0276bb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061799435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.3061799435
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.536862528
Short name T622
Test name
Test status
Simulation time 89813481 ps
CPU time 0.82 seconds
Started Jun 27 04:49:58 PM PDT 24
Finished Jun 27 04:50:01 PM PDT 24
Peak memory 204460 kb
Host smart-3a2153b2-77e3-4f82-830d-047d06eb74fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536862528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_fm
t.536862528
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.3759004873
Short name T849
Test name
Test status
Simulation time 451676250 ps
CPU time 2.8 seconds
Started Jun 27 04:49:52 PM PDT 24
Finished Jun 27 04:49:57 PM PDT 24
Peak memory 219232 kb
Host smart-3ee4a0d7-da5c-4ba9-ae6c-ad745969bf2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759004873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.3759004873
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.3698127763
Short name T106
Test name
Test status
Simulation time 5464023978 ps
CPU time 134.43 seconds
Started Jun 27 04:49:58 PM PDT 24
Finished Jun 27 04:52:15 PM PDT 24
Peak memory 1527600 kb
Host smart-c2b6e4df-7136-49d8-b7cc-def8de04575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698127763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.3698127763
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1733424216
Short name T1369
Test name
Test status
Simulation time 228366072 ps
CPU time 9.45 seconds
Started Jun 27 04:49:50 PM PDT 24
Finished Jun 27 04:50:03 PM PDT 24
Peak memory 204808 kb
Host smart-fa40a777-130b-49c4-9448-31d7f514d272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733424216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1733424216
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_override.989160675
Short name T329
Test name
Test status
Simulation time 28977706 ps
CPU time 0.75 seconds
Started Jun 27 04:50:07 PM PDT 24
Finished Jun 27 04:50:12 PM PDT 24
Peak memory 204460 kb
Host smart-9a8c6e95-33a3-4449-a084-c05cd0659665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989160675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.989160675
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.3576168367
Short name T568
Test name
Test status
Simulation time 8088639803 ps
CPU time 56.48 seconds
Started Jun 27 04:49:57 PM PDT 24
Finished Jun 27 04:50:55 PM PDT 24
Peak memory 666040 kb
Host smart-93c31083-2d57-4db1-a4b7-2eae40916ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576168367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.3576168367
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.989825641
Short name T1074
Test name
Test status
Simulation time 2762285036 ps
CPU time 8.96 seconds
Started Jun 27 04:49:58 PM PDT 24
Finished Jun 27 04:50:10 PM PDT 24
Peak memory 225776 kb
Host smart-ebee5637-5ef3-4b15-879b-05adeb3a367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989825641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.989825641
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.3382507684
Short name T1429
Test name
Test status
Simulation time 2522691890 ps
CPU time 19.58 seconds
Started Jun 27 04:49:57 PM PDT 24
Finished Jun 27 04:50:20 PM PDT 24
Peak memory 280960 kb
Host smart-ac6d3830-8ba1-47d3-8e05-51ba3b802c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382507684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.3382507684
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2648904349
Short name T75
Test name
Test status
Simulation time 71675606609 ps
CPU time 955.46 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 05:06:05 PM PDT 24
Peak memory 2868256 kb
Host smart-64c0decd-3e09-463f-8773-e4ed715ba58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648904349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2648904349
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.3577991879
Short name T391
Test name
Test status
Simulation time 366464575 ps
CPU time 15.46 seconds
Started Jun 27 04:50:09 PM PDT 24
Finished Jun 27 04:50:28 PM PDT 24
Peak memory 212968 kb
Host smart-858a8ce8-421c-42e7-a1e4-5646887111fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577991879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.3577991879
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.672387356
Short name T904
Test name
Test status
Simulation time 549030662 ps
CPU time 3.03 seconds
Started Jun 27 04:50:03 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 204740 kb
Host smart-fd1fec8e-1fd8-4da5-83f4-4e3f8946e0f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672387356 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.672387356
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2945144900
Short name T458
Test name
Test status
Simulation time 401543122 ps
CPU time 1.09 seconds
Started Jun 27 04:49:55 PM PDT 24
Finished Jun 27 04:49:57 PM PDT 24
Peak memory 204620 kb
Host smart-554485bf-b84b-4e6c-85d2-768b8d13ce51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945144900 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2945144900
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.2517593604
Short name T693
Test name
Test status
Simulation time 241630898 ps
CPU time 1.5 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:04 PM PDT 24
Peak memory 204744 kb
Host smart-11da0b27-40a4-4511-a547-c83ea45a75bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517593604 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.2517593604
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.3756152074
Short name T254
Test name
Test status
Simulation time 795158431 ps
CPU time 2.29 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:09 PM PDT 24
Peak memory 204692 kb
Host smart-e13ec3c4-9b1c-4ef1-ac75-2fd22d7bd68d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756152074 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.3756152074
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.3531605477
Short name T349
Test name
Test status
Simulation time 154663970 ps
CPU time 1.22 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 204516 kb
Host smart-6760ee68-5d79-40b6-988a-73054e8112d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531605477 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.3531605477
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.952914856
Short name T1068
Test name
Test status
Simulation time 366772889 ps
CPU time 3.06 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 204792 kb
Host smart-2618f765-54db-475e-8ce7-5b3fc350dcf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952914856 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.i2c_target_hrst.952914856
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3362130616
Short name T1029
Test name
Test status
Simulation time 915878320 ps
CPU time 4.78 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:12 PM PDT 24
Peak memory 212932 kb
Host smart-d702face-a854-4dfa-9456-5df4f5306a3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362130616 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3362130616
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.2385895629
Short name T741
Test name
Test status
Simulation time 23676117379 ps
CPU time 65.73 seconds
Started Jun 27 04:49:51 PM PDT 24
Finished Jun 27 04:50:59 PM PDT 24
Peak memory 959404 kb
Host smart-dff5c21d-d682-46fa-8675-60edc525ef19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385895629 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.2385895629
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.3719022833
Short name T5
Test name
Test status
Simulation time 3744541150 ps
CPU time 15.28 seconds
Started Jun 27 04:50:08 PM PDT 24
Finished Jun 27 04:50:28 PM PDT 24
Peak memory 204868 kb
Host smart-54c8289d-6e01-4161-9dd1-61ed07159d89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719022833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_ta
rget_smoke.3719022833
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1927663330
Short name T1028
Test name
Test status
Simulation time 58040815551 ps
CPU time 87.33 seconds
Started Jun 27 04:49:56 PM PDT 24
Finished Jun 27 04:51:26 PM PDT 24
Peak memory 1277572 kb
Host smart-d65e76e5-a421-4b56-abe0-a984a7aaea3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927663330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1927663330
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1718654477
Short name T1000
Test name
Test status
Simulation time 4890867851 ps
CPU time 78.03 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:51:21 PM PDT 24
Peak memory 538776 kb
Host smart-64c0b45d-80b4-4785-b3d4-3c0c7051cc4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718654477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1718654477
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.1317264306
Short name T722
Test name
Test status
Simulation time 2117314812 ps
CPU time 6.83 seconds
Started Jun 27 04:49:56 PM PDT 24
Finished Jun 27 04:50:05 PM PDT 24
Peak memory 211572 kb
Host smart-5030e91c-b841-4f72-8b34-130e475c1c4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317264306 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.1317264306
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_alert_test.1608973782
Short name T1015
Test name
Test status
Simulation time 157497460 ps
CPU time 0.64 seconds
Started Jun 27 04:50:07 PM PDT 24
Finished Jun 27 04:50:12 PM PDT 24
Peak memory 204500 kb
Host smart-9ce6aef6-5149-4d7c-abc3-6dc43a54bb13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608973782 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.1608973782
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.1072572534
Short name T111
Test name
Test status
Simulation time 84275427 ps
CPU time 1.31 seconds
Started Jun 27 04:49:44 PM PDT 24
Finished Jun 27 04:49:51 PM PDT 24
Peak memory 213076 kb
Host smart-591944cc-51e0-4f1c-9bae-2185814e6f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072572534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.1072572534
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2556413381
Short name T576
Test name
Test status
Simulation time 1396583789 ps
CPU time 6.06 seconds
Started Jun 27 04:49:40 PM PDT 24
Finished Jun 27 04:49:51 PM PDT 24
Peak memory 262600 kb
Host smart-cd38f231-291e-4c38-b7b5-3d527e52663b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556413381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2556413381
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.982880690
Short name T274
Test name
Test status
Simulation time 2881123860 ps
CPU time 166.38 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:52:49 PM PDT 24
Peak memory 609300 kb
Host smart-7b8d17d3-5cd8-4e51-9407-fb96ea8cec3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982880690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.982880690
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3817211866
Short name T547
Test name
Test status
Simulation time 1487279372 ps
CPU time 43.45 seconds
Started Jun 27 04:49:58 PM PDT 24
Finished Jun 27 04:50:45 PM PDT 24
Peak memory 537084 kb
Host smart-bb68a524-6f22-406b-8312-6e3e4b9bf913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817211866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3817211866
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.247803217
Short name T61
Test name
Test status
Simulation time 538288315 ps
CPU time 0.96 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 204452 kb
Host smart-dc926d81-7a44-486b-ae74-d4b671f0f15b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247803217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_fm
t.247803217
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.3060596056
Short name T1413
Test name
Test status
Simulation time 432469837 ps
CPU time 2.88 seconds
Started Jun 27 04:49:50 PM PDT 24
Finished Jun 27 04:49:55 PM PDT 24
Peak memory 219212 kb
Host smart-706d4b4f-7267-4ef5-aa04-b1713832b33c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060596056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.3060596056
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.2176414466
Short name T338
Test name
Test status
Simulation time 3080906242 ps
CPU time 176.66 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:53:01 PM PDT 24
Peak memory 886676 kb
Host smart-70b7f573-b2b7-45aa-b59a-5054b1385776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176414466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.2176414466
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1542132511
Short name T968
Test name
Test status
Simulation time 1310694555 ps
CPU time 13.56 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:21 PM PDT 24
Peak memory 204732 kb
Host smart-eb4362be-35a2-4676-850f-23fab6836efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542132511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1542132511
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.3958831927
Short name T1263
Test name
Test status
Simulation time 1599197987 ps
CPU time 32.25 seconds
Started Jun 27 04:50:08 PM PDT 24
Finished Jun 27 04:50:44 PM PDT 24
Peak memory 420032 kb
Host smart-6647edab-5d87-42bf-8e12-6cbd29d6c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958831927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.3958831927
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1625462172
Short name T887
Test name
Test status
Simulation time 38261954 ps
CPU time 0.62 seconds
Started Jun 27 04:49:50 PM PDT 24
Finished Jun 27 04:49:53 PM PDT 24
Peak memory 204044 kb
Host smart-1385946a-9ddf-445c-bd0c-46d2b8d5a933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625462172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1625462172
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.386086747
Short name T859
Test name
Test status
Simulation time 2811569055 ps
CPU time 61.99 seconds
Started Jun 27 04:49:50 PM PDT 24
Finished Jun 27 04:50:55 PM PDT 24
Peak memory 783728 kb
Host smart-35418529-cd75-4415-9e81-42054c4636e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386086747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.386086747
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.3192739217
Short name T1038
Test name
Test status
Simulation time 55049336 ps
CPU time 1.16 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 224996 kb
Host smart-6864665b-a832-4ad9-bcec-641a326b39c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192739217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.3192739217
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3704215005
Short name T939
Test name
Test status
Simulation time 1081149673 ps
CPU time 50.86 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 352664 kb
Host smart-403a6e93-4dc5-43d6-8e99-c5e04b10dd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704215005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3704215005
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.1383512938
Short name T1459
Test name
Test status
Simulation time 1831524159 ps
CPU time 14.38 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:22 PM PDT 24
Peak memory 221132 kb
Host smart-285b0764-654a-4259-b94e-c2ad05bdb5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383512938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.1383512938
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.683642397
Short name T746
Test name
Test status
Simulation time 2674267561 ps
CPU time 1.98 seconds
Started Jun 27 04:49:47 PM PDT 24
Finished Jun 27 04:49:53 PM PDT 24
Peak memory 204972 kb
Host smart-3040de20-970b-4fcf-a8fc-36482be1905b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683642397 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.683642397
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.196046939
Short name T553
Test name
Test status
Simulation time 334405768 ps
CPU time 0.74 seconds
Started Jun 27 04:49:52 PM PDT 24
Finished Jun 27 04:49:55 PM PDT 24
Peak memory 204436 kb
Host smart-1e77cb72-c169-4557-897d-8a3b667c7922
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196046939 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_acq.196046939
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.936229109
Short name T1140
Test name
Test status
Simulation time 493465178 ps
CPU time 1.16 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 204736 kb
Host smart-f95fec24-6a2f-439c-a836-09c0cdaa30d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936229109 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.936229109
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.897695323
Short name T627
Test name
Test status
Simulation time 281348321 ps
CPU time 1.61 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:04 PM PDT 24
Peak memory 204672 kb
Host smart-7ec724f7-b763-4759-8b42-3862967c32be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897695323 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.897695323
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.2275192215
Short name T1192
Test name
Test status
Simulation time 582645443 ps
CPU time 1.16 seconds
Started Jun 27 04:49:56 PM PDT 24
Finished Jun 27 04:50:00 PM PDT 24
Peak memory 204576 kb
Host smart-12a4a72a-bb90-4ae2-a87d-32d569fa8d7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275192215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.2275192215
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.3725512804
Short name T1042
Test name
Test status
Simulation time 374766284 ps
CPU time 2.6 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 204704 kb
Host smart-e7930885-4d20-4261-9536-701f39da5251
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725512804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.3725512804
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.4270355111
Short name T1241
Test name
Test status
Simulation time 3464900508 ps
CPU time 3.73 seconds
Started Jun 27 04:49:50 PM PDT 24
Finished Jun 27 04:49:56 PM PDT 24
Peak memory 204404 kb
Host smart-462730e6-f384-4e5d-8a2b-e9d673a9fe8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270355111 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.4270355111
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.3171243630
Short name T1176
Test name
Test status
Simulation time 13717934631 ps
CPU time 109.65 seconds
Started Jun 27 04:49:42 PM PDT 24
Finished Jun 27 04:51:38 PM PDT 24
Peak memory 1674700 kb
Host smart-4f828d1b-b2ad-44d9-950b-367518f4c295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171243630 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.3171243630
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.777453835
Short name T941
Test name
Test status
Simulation time 4058870726 ps
CPU time 39.9 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:50:45 PM PDT 24
Peak memory 204856 kb
Host smart-14741259-7740-48ae-bdf8-0fc510edf07b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777453835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_tar
get_smoke.777453835
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.3837779590
Short name T1120
Test name
Test status
Simulation time 1436148612 ps
CPU time 21.02 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:23 PM PDT 24
Peak memory 233008 kb
Host smart-3e48d349-2234-4353-a67a-484a3192d406
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837779590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.3837779590
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.972198417
Short name T1147
Test name
Test status
Simulation time 32999646518 ps
CPU time 283.14 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:54:50 PM PDT 24
Peak memory 3217132 kb
Host smart-9ca59413-4cf5-406d-a0ce-b6bb81e99e0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972198417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.972198417
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1954820132
Short name T835
Test name
Test status
Simulation time 42639849894 ps
CPU time 919.6 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 05:05:26 PM PDT 24
Peak memory 4794452 kb
Host smart-2eb76888-27e4-4f98-aea2-32863c032d44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954820132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1954820132
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1847881633
Short name T432
Test name
Test status
Simulation time 1320553851 ps
CPU time 6.6 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:13 PM PDT 24
Peak memory 219292 kb
Host smart-de3fa776-6121-426c-942a-c8415f4b0b29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847881633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1847881633
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_alert_test.2432910162
Short name T1269
Test name
Test status
Simulation time 17411386 ps
CPU time 0.63 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 204460 kb
Host smart-b6b0259e-7717-4f1c-bd5f-62719a4026cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432910162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.2432910162
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.1997606796
Short name T504
Test name
Test status
Simulation time 331473585 ps
CPU time 2.04 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 213004 kb
Host smart-5db7be79-5493-45a8-8de3-7d074fc031e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997606796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.1997606796
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.1690820004
Short name T1428
Test name
Test status
Simulation time 405765847 ps
CPU time 18.78 seconds
Started Jun 27 04:49:56 PM PDT 24
Finished Jun 27 04:50:17 PM PDT 24
Peak memory 272220 kb
Host smart-df64b067-f511-4e0a-8599-fcde0b96bd00
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690820004 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.1690820004
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.586912353
Short name T1446
Test name
Test status
Simulation time 6379697404 ps
CPU time 54.95 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:57 PM PDT 24
Peak memory 602112 kb
Host smart-45a22860-6435-4d48-88d9-a63fbc6b7176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586912353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.586912353
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.1044758444
Short name T1337
Test name
Test status
Simulation time 1469209441 ps
CPU time 39.49 seconds
Started Jun 27 04:49:58 PM PDT 24
Finished Jun 27 04:50:41 PM PDT 24
Peak memory 483740 kb
Host smart-fa665d93-a0c3-4c2e-8c3f-82ccae438028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044758444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.1044758444
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.621387071
Short name T922
Test name
Test status
Simulation time 337309312 ps
CPU time 0.87 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:50:05 PM PDT 24
Peak memory 204472 kb
Host smart-4d27a071-3a02-4081-a766-2619a852c730
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621387071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_fm
t.621387071
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3116508405
Short name T1053
Test name
Test status
Simulation time 359985982 ps
CPU time 4.22 seconds
Started Jun 27 04:49:56 PM PDT 24
Finished Jun 27 04:50:03 PM PDT 24
Peak memory 236856 kb
Host smart-c18e2cdd-6d61-46b8-a735-05bd442333de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116508405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3116508405
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.242900973
Short name T1356
Test name
Test status
Simulation time 4602959636 ps
CPU time 120.22 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:52:04 PM PDT 24
Peak memory 1313780 kb
Host smart-d27edf58-9d45-4772-9c66-efe4f8589aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242900973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.242900973
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.2999472824
Short name T498
Test name
Test status
Simulation time 670529496 ps
CPU time 2.79 seconds
Started Jun 27 04:50:06 PM PDT 24
Finished Jun 27 04:50:14 PM PDT 24
Peak memory 204864 kb
Host smart-674d00e2-0efd-4fb5-bf36-892010cf996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999472824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.2999472824
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.1489629965
Short name T1207
Test name
Test status
Simulation time 1692776084 ps
CPU time 77.08 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 374108 kb
Host smart-ca0f0031-dc98-4af2-bc04-b16315574df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489629965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.1489629965
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.203426652
Short name T626
Test name
Test status
Simulation time 42995094 ps
CPU time 0.64 seconds
Started Jun 27 04:50:03 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 204484 kb
Host smart-cfa0949e-fd81-46fa-847a-6af40e8cb57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203426652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.203426652
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.3473611085
Short name T491
Test name
Test status
Simulation time 12987517455 ps
CPU time 449.67 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:57:33 PM PDT 24
Peak memory 204864 kb
Host smart-68715d00-b471-4ed9-9f5b-c39aae19c231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473611085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.3473611085
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.2523419650
Short name T541
Test name
Test status
Simulation time 6171987581 ps
CPU time 80.85 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:51:30 PM PDT 24
Peak memory 550496 kb
Host smart-de63677e-a43d-43b6-98ff-400410e4a1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523419650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.2523419650
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.1332564630
Short name T616
Test name
Test status
Simulation time 1736704498 ps
CPU time 29.31 seconds
Started Jun 27 04:50:01 PM PDT 24
Finished Jun 27 04:50:35 PM PDT 24
Peak memory 381752 kb
Host smart-80145548-1e20-44f6-8ec4-e9cebe0cd1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332564630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.1332564630
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1395720382
Short name T1487
Test name
Test status
Simulation time 870607941 ps
CPU time 12.68 seconds
Started Jun 27 04:50:07 PM PDT 24
Finished Jun 27 04:50:24 PM PDT 24
Peak memory 221204 kb
Host smart-6d5cf477-e883-4b2a-9156-d2cdf00d5331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395720382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1395720382
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.917047718
Short name T429
Test name
Test status
Simulation time 2683773836 ps
CPU time 2.35 seconds
Started Jun 27 04:50:03 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 204888 kb
Host smart-e3f8e28d-86f4-4682-a013-7a2eae1c101e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917047718 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.917047718
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.1630446863
Short name T642
Test name
Test status
Simulation time 264443848 ps
CPU time 0.85 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:04 PM PDT 24
Peak memory 204628 kb
Host smart-8cdd1bb7-e7c4-47ba-b73c-581177c6c64f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630446863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.1630446863
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3052541838
Short name T132
Test name
Test status
Simulation time 282829394 ps
CPU time 0.92 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:10 PM PDT 24
Peak memory 204544 kb
Host smart-e6ed4495-08d2-45dc-8aaa-7d898334e6cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052541838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3052541838
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.2952302012
Short name T255
Test name
Test status
Simulation time 1051836715 ps
CPU time 2.45 seconds
Started Jun 27 04:49:55 PM PDT 24
Finished Jun 27 04:50:00 PM PDT 24
Peak memory 204824 kb
Host smart-f403c4ff-d0f4-472c-ba16-e38cba4e1857
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952302012 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.2952302012
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.3664345769
Short name T972
Test name
Test status
Simulation time 115684965 ps
CPU time 1.16 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:03 PM PDT 24
Peak memory 204488 kb
Host smart-55a8b8cb-d493-4291-97d2-9c7c77c107fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664345769 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.3664345769
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.1985990890
Short name T1070
Test name
Test status
Simulation time 396318416 ps
CPU time 2.51 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 204860 kb
Host smart-406b0be3-ae6c-49eb-87d1-c3ed47b067b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985990890 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.1985990890
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.2616349794
Short name T890
Test name
Test status
Simulation time 693126284 ps
CPU time 4.15 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:50:14 PM PDT 24
Peak memory 213048 kb
Host smart-6e50d51e-5fe2-4d69-b154-c8e9a908b6cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616349794 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.2616349794
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.4204565612
Short name T487
Test name
Test status
Simulation time 18326517667 ps
CPU time 30.11 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:50:40 PM PDT 24
Peak memory 634788 kb
Host smart-8587e233-81d0-4259-b9ef-2a9fd6ba4d7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204565612 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.4204565612
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.2207701547
Short name T1041
Test name
Test status
Simulation time 2522345073 ps
CPU time 46.55 seconds
Started Jun 27 04:49:58 PM PDT 24
Finished Jun 27 04:50:48 PM PDT 24
Peak memory 204940 kb
Host smart-9d6d3465-2493-4e0e-9036-f1a95b681a71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207701547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.2207701547
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.3859815717
Short name T984
Test name
Test status
Simulation time 811833126 ps
CPU time 32.55 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:41 PM PDT 24
Peak memory 204792 kb
Host smart-1feb1682-b9b1-4a19-9a15-041d22f377ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859815717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_rd.3859815717
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.958102598
Short name T22
Test name
Test status
Simulation time 57899774966 ps
CPU time 237.26 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:54:04 PM PDT 24
Peak memory 2553168 kb
Host smart-9f7bafce-d548-455b-9e61-aa3e1634e38a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958102598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.958102598
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.2976389283
Short name T522
Test name
Test status
Simulation time 11618766885 ps
CPU time 129.93 seconds
Started Jun 27 04:50:07 PM PDT 24
Finished Jun 27 04:52:21 PM PDT 24
Peak memory 1341956 kb
Host smart-c04526fd-ec86-47ce-adeb-9949c4994ab0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976389283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.2976389283
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3821765957
Short name T69
Test name
Test status
Simulation time 5225509187 ps
CPU time 6.83 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:50:10 PM PDT 24
Peak memory 221080 kb
Host smart-c6eaec08-2cea-4f2b-809a-c73be411bba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821765957 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3821765957
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_alert_test.2809026168
Short name T186
Test name
Test status
Simulation time 50149643 ps
CPU time 0.62 seconds
Started Jun 27 04:50:16 PM PDT 24
Finished Jun 27 04:50:18 PM PDT 24
Peak memory 204388 kb
Host smart-6c0b322a-a1b9-498c-aa92-3414baccb08a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809026168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.2809026168
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.1639125643
Short name T1392
Test name
Test status
Simulation time 464406017 ps
CPU time 2.64 seconds
Started Jun 27 04:50:06 PM PDT 24
Finished Jun 27 04:50:14 PM PDT 24
Peak memory 213136 kb
Host smart-225d4504-a2d5-41da-8c8a-c6981f0fd5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639125643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.1639125643
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.4174339471
Short name T152
Test name
Test status
Simulation time 2687536352 ps
CPU time 4.98 seconds
Started Jun 27 04:50:03 PM PDT 24
Finished Jun 27 04:50:13 PM PDT 24
Peak memory 261072 kb
Host smart-a6df3e14-b44a-4649-9a7e-51d7c32dcb05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174339471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.4174339471
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.2262503656
Short name T861
Test name
Test status
Simulation time 6174903810 ps
CPU time 32.72 seconds
Started Jun 27 04:49:58 PM PDT 24
Finished Jun 27 04:50:33 PM PDT 24
Peak memory 293160 kb
Host smart-ee2cc860-3eea-49a1-9761-d36605fc65b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262503656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.2262503656
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.461746294
Short name T335
Test name
Test status
Simulation time 4917971648 ps
CPU time 40.13 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:50 PM PDT 24
Peak memory 509064 kb
Host smart-b7c49962-5d1c-40cb-9ab4-f87273bd2bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461746294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.461746294
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.789146859
Short name T175
Test name
Test status
Simulation time 137819203 ps
CPU time 1.11 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 204548 kb
Host smart-a5d0fe73-e63b-4f41-a6e9-07f8e70c6de5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789146859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_fm
t.789146859
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.3784458041
Short name T979
Test name
Test status
Simulation time 243466817 ps
CPU time 6 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:50:12 PM PDT 24
Peak memory 251016 kb
Host smart-5698798e-f01b-4a66-8354-2188219f0dc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784458041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx
.3784458041
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3512733284
Short name T98
Test name
Test status
Simulation time 5682931016 ps
CPU time 152.49 seconds
Started Jun 27 04:50:13 PM PDT 24
Finished Jun 27 04:52:48 PM PDT 24
Peak memory 1592904 kb
Host smart-4b520a98-4cf6-48be-ac4b-1ec56da3892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512733284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3512733284
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2142548939
Short name T826
Test name
Test status
Simulation time 1269914910 ps
CPU time 12.15 seconds
Started Jun 27 04:50:12 PM PDT 24
Finished Jun 27 04:50:27 PM PDT 24
Peak memory 204744 kb
Host smart-31ae6266-0000-465d-9587-96053212a58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142548939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2142548939
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1690195698
Short name T1212
Test name
Test status
Simulation time 4670493264 ps
CPU time 101.44 seconds
Started Jun 27 04:50:10 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 349468 kb
Host smart-637d818c-cb07-4ed6-9b09-8145f609556d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690195698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1690195698
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.1043977136
Short name T137
Test name
Test status
Simulation time 50784953 ps
CPU time 0.64 seconds
Started Jun 27 04:49:59 PM PDT 24
Finished Jun 27 04:50:02 PM PDT 24
Peak memory 204424 kb
Host smart-13d64ad7-147d-4774-8303-96c2ed7b851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043977136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.1043977136
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.366452247
Short name T725
Test name
Test status
Simulation time 7978628434 ps
CPU time 160.81 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:52:50 PM PDT 24
Peak memory 266828 kb
Host smart-e2f0c46a-c5b9-4cf9-8616-a19f25faa21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366452247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.366452247
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.3294339650
Short name T886
Test name
Test status
Simulation time 2046939077 ps
CPU time 38.03 seconds
Started Jun 27 04:50:06 PM PDT 24
Finished Jun 27 04:50:49 PM PDT 24
Peak memory 204848 kb
Host smart-08e39a5d-2264-42c8-8f50-4cc3284fb0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294339650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.3294339650
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2272126490
Short name T322
Test name
Test status
Simulation time 4727035383 ps
CPU time 55.46 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:50:59 PM PDT 24
Peak memory 342680 kb
Host smart-62eda176-4c70-4d54-883f-b3b4a0fc96ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272126490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2272126490
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3783857175
Short name T281
Test name
Test status
Simulation time 21857153762 ps
CPU time 62.18 seconds
Started Jun 27 04:50:02 PM PDT 24
Finished Jun 27 04:51:08 PM PDT 24
Peak memory 581136 kb
Host smart-7644261a-e99b-4051-b529-05c09b43eb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783857175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3783857175
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.671462807
Short name T1217
Test name
Test status
Simulation time 1026737116 ps
CPU time 14.58 seconds
Started Jun 27 04:50:07 PM PDT 24
Finished Jun 27 04:50:26 PM PDT 24
Peak memory 229304 kb
Host smart-9ff609ae-0c79-4505-9076-16766089eeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671462807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.671462807
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.3683231082
Short name T1199
Test name
Test status
Simulation time 705914179 ps
CPU time 3.53 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:12 PM PDT 24
Peak memory 204716 kb
Host smart-ecb24bfc-86fa-4cbc-ac1e-296704da2b65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683231082 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.3683231082
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.1359737645
Short name T1458
Test name
Test status
Simulation time 276791024 ps
CPU time 1.09 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:10 PM PDT 24
Peak memory 204496 kb
Host smart-126477b1-7120-47da-ad50-666490b74f1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359737645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_fifo_reset_acq.1359737645
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.230881238
Short name T1048
Test name
Test status
Simulation time 141879366 ps
CPU time 1.01 seconds
Started Jun 27 04:50:12 PM PDT 24
Finished Jun 27 04:50:15 PM PDT 24
Peak memory 204500 kb
Host smart-d49de026-6698-4ac8-8246-a5a062a11500
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230881238 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.i2c_target_fifo_reset_tx.230881238
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.1275963321
Short name T1322
Test name
Test status
Simulation time 531911128 ps
CPU time 2.71 seconds
Started Jun 27 04:50:12 PM PDT 24
Finished Jun 27 04:50:17 PM PDT 24
Peak memory 204716 kb
Host smart-3da39eb3-17ab-476e-897a-2ee0b77d23c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275963321 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.1275963321
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.4020225384
Short name T817
Test name
Test status
Simulation time 148978063 ps
CPU time 1.28 seconds
Started Jun 27 04:50:12 PM PDT 24
Finished Jun 27 04:50:16 PM PDT 24
Peak memory 204500 kb
Host smart-5e501487-b6be-4850-98a7-5f63d5e8978d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020225384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.4020225384
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_hrst.2964550075
Short name T1261
Test name
Test status
Simulation time 1216658089 ps
CPU time 2.5 seconds
Started Jun 27 04:50:04 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 204792 kb
Host smart-6bb2cc93-b210-45cc-9156-019c9eaa5289
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964550075 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.2964550075
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.4037679104
Short name T162
Test name
Test status
Simulation time 1073323074 ps
CPU time 6.25 seconds
Started Jun 27 04:50:08 PM PDT 24
Finished Jun 27 04:50:18 PM PDT 24
Peak memory 220944 kb
Host smart-55e08c8a-1ed0-4f2e-b2cd-2cdb6aa50384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037679104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_intr_smoke.4037679104
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.830826648
Short name T407
Test name
Test status
Simulation time 2237398282 ps
CPU time 37.88 seconds
Started Jun 27 04:50:03 PM PDT 24
Finished Jun 27 04:50:46 PM PDT 24
Peak memory 204784 kb
Host smart-67318afb-2087-4107-9629-330028264c48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830826648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.830826648
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.902057379
Short name T540
Test name
Test status
Simulation time 1410722565 ps
CPU time 22.68 seconds
Started Jun 27 04:50:05 PM PDT 24
Finished Jun 27 04:50:33 PM PDT 24
Peak memory 220368 kb
Host smart-c0f95719-2700-4ebe-92ca-5245c723002f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902057379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_rd.902057379
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.1144299161
Short name T1246
Test name
Test status
Simulation time 57864808360 ps
CPU time 249.92 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:54:13 PM PDT 24
Peak memory 2484636 kb
Host smart-17212308-6d7d-4ee2-a682-c8618e660de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144299161 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.1144299161
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.1615152191
Short name T150
Test name
Test status
Simulation time 29917314396 ps
CPU time 1578.86 seconds
Started Jun 27 04:50:07 PM PDT 24
Finished Jun 27 05:16:30 PM PDT 24
Peak memory 5954908 kb
Host smart-1fff4088-0652-4f62-afcf-9dd8b452ba48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615152191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.1615152191
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2347704899
Short name T1462
Test name
Test status
Simulation time 1392758531 ps
CPU time 6.95 seconds
Started Jun 27 04:50:12 PM PDT 24
Finished Jun 27 04:50:21 PM PDT 24
Peak memory 212956 kb
Host smart-c062e2da-28db-4dd2-a695-74c3637252fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347704899 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2347704899
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_alert_test.3336012577
Short name T840
Test name
Test status
Simulation time 21306067 ps
CPU time 0.61 seconds
Started Jun 27 04:48:57 PM PDT 24
Finished Jun 27 04:49:00 PM PDT 24
Peak memory 204376 kb
Host smart-2c362605-6f1c-46bb-87c9-21767c88e7f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336012577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.3336012577
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2533777932
Short name T293
Test name
Test status
Simulation time 1201896977 ps
CPU time 6.86 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:23 PM PDT 24
Peak memory 279588 kb
Host smart-a8b863e6-ee29-433d-9467-0e64fd98d768
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533777932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2533777932
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.291988205
Short name T1256
Test name
Test status
Simulation time 7761690354 ps
CPU time 44.53 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:50:00 PM PDT 24
Peak memory 502896 kb
Host smart-7f17f9aa-0842-4877-aa11-934d1011b96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291988205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.291988205
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3674920808
Short name T822
Test name
Test status
Simulation time 1748664090 ps
CPU time 114.91 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:51:09 PM PDT 24
Peak memory 599632 kb
Host smart-ff9a8624-da66-4397-8983-0160b9a8c878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674920808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3674920808
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.860453720
Short name T1107
Test name
Test status
Simulation time 28427701342 ps
CPU time 111.73 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:51:12 PM PDT 24
Peak memory 1341876 kb
Host smart-e2348562-d18c-4599-97be-ad91eced2ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860453720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.860453720
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.2846182064
Short name T854
Test name
Test status
Simulation time 1076483158 ps
CPU time 3.21 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:24 PM PDT 24
Peak memory 205024 kb
Host smart-da41c955-b5a3-43c1-9e15-3d63a150c6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846182064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2846182064
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.687786242
Short name T315
Test name
Test status
Simulation time 14227490714 ps
CPU time 31.42 seconds
Started Jun 27 04:48:54 PM PDT 24
Finished Jun 27 04:49:29 PM PDT 24
Peak memory 364488 kb
Host smart-0fdbc2a6-8cb4-4b1f-ad02-99babc9db5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687786242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.687786242
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.1764569015
Short name T917
Test name
Test status
Simulation time 84185198 ps
CPU time 0.7 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:11 PM PDT 24
Peak memory 204548 kb
Host smart-ab16f912-652f-4203-9086-56f379b4900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764569015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.1764569015
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.1037988286
Short name T732
Test name
Test status
Simulation time 7010322899 ps
CPU time 29.28 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 04:49:53 PM PDT 24
Peak memory 298016 kb
Host smart-942672f9-0183-4636-8166-d225b085dd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037988286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.1037988286
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.745995086
Short name T510
Test name
Test status
Simulation time 278160620 ps
CPU time 1.37 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 04:49:25 PM PDT 24
Peak memory 204748 kb
Host smart-37e0d4c6-c5ac-4392-9a4b-33f47fa49737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745995086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.745995086
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.1667093624
Short name T1035
Test name
Test status
Simulation time 8498628967 ps
CPU time 29.38 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:44 PM PDT 24
Peak memory 334096 kb
Host smart-cab617d0-e7da-4c5c-93a3-cfd95e7e5a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667093624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1667093624
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3937122398
Short name T214
Test name
Test status
Simulation time 18170602043 ps
CPU time 1985.91 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 05:22:30 PM PDT 24
Peak memory 2724620 kb
Host smart-345818fc-79c9-4ad4-b647-9a8b22fb76a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937122398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3937122398
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.7827397
Short name T289
Test name
Test status
Simulation time 1197497487 ps
CPU time 10.77 seconds
Started Jun 27 04:48:59 PM PDT 24
Finished Jun 27 04:49:11 PM PDT 24
Peak memory 221204 kb
Host smart-dfbc5fb2-d962-41e7-b2c5-5daa7e0bde02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7827397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.7827397
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1588229986
Short name T192
Test name
Test status
Simulation time 251267897 ps
CPU time 0.92 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:48:56 PM PDT 24
Peak memory 223136 kb
Host smart-658ee35e-0840-4f74-a075-9eed46aa8bfd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588229986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1588229986
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1259991273
Short name T1109
Test name
Test status
Simulation time 3478727234 ps
CPU time 3.9 seconds
Started Jun 27 04:49:02 PM PDT 24
Finished Jun 27 04:49:07 PM PDT 24
Peak memory 213152 kb
Host smart-6b009052-8b2b-4a6c-8a88-7bf0032c7e87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259991273 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1259991273
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.1113402748
Short name T1418
Test name
Test status
Simulation time 575706938 ps
CPU time 1.22 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 204704 kb
Host smart-cbd02279-91bd-4fa0-8899-1d639e89790e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113402748 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.1113402748
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.1509663700
Short name T959
Test name
Test status
Simulation time 316141609 ps
CPU time 1.66 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:23 PM PDT 24
Peak memory 203788 kb
Host smart-dc7492ec-d136-4efd-973e-f4b3d31a1aac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509663700 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.1509663700
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.1541747828
Short name T769
Test name
Test status
Simulation time 93012593 ps
CPU time 0.93 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 204608 kb
Host smart-278250be-ad43-48de-b935-29bdd1792f8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541747828 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.1541747828
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.903821993
Short name T657
Test name
Test status
Simulation time 388251113 ps
CPU time 3.57 seconds
Started Jun 27 04:48:55 PM PDT 24
Finished Jun 27 04:49:02 PM PDT 24
Peak memory 204852 kb
Host smart-d3f853e7-de61-477f-b6b0-97ad54d9a61b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903821993 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.903821993
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2845829735
Short name T628
Test name
Test status
Simulation time 2650101007 ps
CPU time 5.6 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:49:35 PM PDT 24
Peak memory 213076 kb
Host smart-dfcffacd-10b2-4b28-9092-64ee600de025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845829735 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2845829735
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.268111589
Short name T353
Test name
Test status
Simulation time 8835451255 ps
CPU time 24.06 seconds
Started Jun 27 04:49:13 PM PDT 24
Finished Jun 27 04:49:48 PM PDT 24
Peak memory 500268 kb
Host smart-69b7576e-44d1-4477-8034-16bbd7835692
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268111589 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.268111589
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1239122534
Short name T654
Test name
Test status
Simulation time 11921040154 ps
CPU time 10.27 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:49:42 PM PDT 24
Peak memory 204868 kb
Host smart-e4599621-61fe-44ea-82e4-b55277ac5ee4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239122534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1239122534
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.2729307462
Short name T252
Test name
Test status
Simulation time 1700141590 ps
CPU time 72.2 seconds
Started Jun 27 04:49:31 PM PDT 24
Finished Jun 27 04:50:49 PM PDT 24
Peak memory 206964 kb
Host smart-0e747a53-ba0a-47cb-ba14-6d7e11db67a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729307462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.2729307462
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.1707892813
Short name T911
Test name
Test status
Simulation time 20651411343 ps
CPU time 38.77 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:45 PM PDT 24
Peak memory 278912 kb
Host smart-487125e8-d988-4c68-ad56-71668c607d65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707892813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.1707892813
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.2177532566
Short name T997
Test name
Test status
Simulation time 20894380908 ps
CPU time 2263.14 seconds
Started Jun 27 04:49:00 PM PDT 24
Finished Jun 27 05:26:45 PM PDT 24
Peak memory 5049980 kb
Host smart-c0aac521-1bfe-4c41-bac6-a83faf675030
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177532566 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.2177532566
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.2072905139
Short name T511
Test name
Test status
Simulation time 1289775948 ps
CPU time 7.11 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:49:37 PM PDT 24
Peak memory 219720 kb
Host smart-8972643f-72f4-48e6-a8eb-adee85619c52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072905139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.2072905139
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1446826309
Short name T468
Test name
Test status
Simulation time 17835728 ps
CPU time 0.69 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:26 PM PDT 24
Peak memory 204500 kb
Host smart-7ec66519-5bb7-4309-b457-4346adc1d9fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446826309 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1446826309
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.1245194303
Short name T528
Test name
Test status
Simulation time 210164821 ps
CPU time 10.78 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:42 PM PDT 24
Peak memory 246052 kb
Host smart-da10161a-92ce-47dc-ba57-a45e9ca64ab5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245194303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.1245194303
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.273052121
Short name T108
Test name
Test status
Simulation time 2345933828 ps
CPU time 71.34 seconds
Started Jun 27 04:50:15 PM PDT 24
Finished Jun 27 04:51:28 PM PDT 24
Peak memory 765444 kb
Host smart-280703c9-cb18-4afd-bdbe-21e505698d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273052121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.273052121
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.1465263233
Short name T1057
Test name
Test status
Simulation time 1861873006 ps
CPU time 42.77 seconds
Started Jun 27 04:50:17 PM PDT 24
Finished Jun 27 04:51:02 PM PDT 24
Peak memory 539952 kb
Host smart-e0be2909-debc-497c-8110-ef8b8fa23584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465263233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.1465263233
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.2625323383
Short name T398
Test name
Test status
Simulation time 592591999 ps
CPU time 1.07 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 204520 kb
Host smart-cfd9a8ec-1b43-43aa-9035-546c0608b84b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625323383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.2625323383
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.3573842591
Short name T951
Test name
Test status
Simulation time 492778203 ps
CPU time 8.54 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:50:30 PM PDT 24
Peak memory 204812 kb
Host smart-069499d3-21ce-442c-8076-53d3c90da3e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573842591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.3573842591
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.4035081314
Short name T608
Test name
Test status
Simulation time 69210357163 ps
CPU time 149.71 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:52:52 PM PDT 24
Peak memory 1442644 kb
Host smart-a5d9b0de-477b-4bee-8d31-c88f7e63e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035081314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.4035081314
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.168019582
Short name T647
Test name
Test status
Simulation time 1629171327 ps
CPU time 6.37 seconds
Started Jun 27 04:50:19 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 204832 kb
Host smart-a1bae1a4-2564-47e8-ad56-80e1ba817e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168019582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.168019582
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.944330661
Short name T63
Test name
Test status
Simulation time 1825620938 ps
CPU time 35.02 seconds
Started Jun 27 04:50:19 PM PDT 24
Finished Jun 27 04:51:00 PM PDT 24
Peak memory 366556 kb
Host smart-df2c697e-f153-4923-8c01-5ccebf390fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944330661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.944330661
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.1196727411
Short name T542
Test name
Test status
Simulation time 18704568 ps
CPU time 0.65 seconds
Started Jun 27 04:50:15 PM PDT 24
Finished Jun 27 04:50:17 PM PDT 24
Peak memory 204528 kb
Host smart-d4821921-ad95-471e-ae75-95ff1518ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196727411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.1196727411
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1341990404
Short name T301
Test name
Test status
Simulation time 368905248 ps
CPU time 4.5 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:34 PM PDT 24
Peak memory 205336 kb
Host smart-e2b5bb08-761b-4db5-956d-859385fbf4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341990404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1341990404
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.4270593120
Short name T605
Test name
Test status
Simulation time 246964136 ps
CPU time 1.35 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 225028 kb
Host smart-6762490c-7408-41fb-aa53-ea01ac2bee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270593120 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.4270593120
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.2747741823
Short name T894
Test name
Test status
Simulation time 1076565936 ps
CPU time 15.65 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:43 PM PDT 24
Peak memory 284608 kb
Host smart-a4a8b02f-d2f0-4402-b767-62320eb97e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747741823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.2747741823
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.2045377598
Short name T548
Test name
Test status
Simulation time 661162641 ps
CPU time 29.4 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:51:01 PM PDT 24
Peak memory 212948 kb
Host smart-682fb632-4f07-4204-8794-3f6ce53f3cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045377598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.2045377598
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3724541760
Short name T372
Test name
Test status
Simulation time 604200128 ps
CPU time 3.24 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:50:26 PM PDT 24
Peak memory 204744 kb
Host smart-1bd23317-beff-4adb-b1a3-232af4c8681b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724541760 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3724541760
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.4142769613
Short name T952
Test name
Test status
Simulation time 636030246 ps
CPU time 0.92 seconds
Started Jun 27 04:50:17 PM PDT 24
Finished Jun 27 04:50:20 PM PDT 24
Peak memory 204604 kb
Host smart-1d825a47-7d6e-46f5-bf75-34107ff59d94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142769613 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_fifo_reset_acq.4142769613
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.2760159848
Short name T611
Test name
Test status
Simulation time 596613830 ps
CPU time 2.91 seconds
Started Jun 27 04:50:15 PM PDT 24
Finished Jun 27 04:50:19 PM PDT 24
Peak memory 204760 kb
Host smart-04d20ae5-022e-4c0b-a534-a0e9d8296ed9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760159848 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.2760159848
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.1966494418
Short name T495
Test name
Test status
Simulation time 128792057 ps
CPU time 1.27 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:50:23 PM PDT 24
Peak memory 204616 kb
Host smart-4dc50cc8-bb8b-41d6-b8b6-f615c1f47b52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966494418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.1966494418
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.1045614910
Short name T706
Test name
Test status
Simulation time 2549932597 ps
CPU time 4.5 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:50:27 PM PDT 24
Peak memory 216064 kb
Host smart-9d8a4baf-c392-47d3-a85c-85f9691bee6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045614910 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.1045614910
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2420416506
Short name T1289
Test name
Test status
Simulation time 30371257985 ps
CPU time 85.54 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:51:49 PM PDT 24
Peak memory 1699480 kb
Host smart-d1c99155-16ed-4fd9-8c15-3f8a11a39465
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420416506 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2420416506
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2546567109
Short name T853
Test name
Test status
Simulation time 3416394964 ps
CPU time 18.32 seconds
Started Jun 27 04:50:17 PM PDT 24
Finished Jun 27 04:50:37 PM PDT 24
Peak memory 204988 kb
Host smart-c2a9f946-f5d8-4696-8518-68c05f2aa959
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546567109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2546567109
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.1294049754
Short name T304
Test name
Test status
Simulation time 462999400 ps
CPU time 7.66 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:50:30 PM PDT 24
Peak memory 204812 kb
Host smart-d9e7ae23-eb9a-4f49-9069-1a58c6ab5f00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294049754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.1294049754
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.976325614
Short name T1455
Test name
Test status
Simulation time 44969852349 ps
CPU time 797.25 seconds
Started Jun 27 04:50:15 PM PDT 24
Finished Jun 27 05:03:33 PM PDT 24
Peak memory 6391144 kb
Host smart-da9646dd-0c84-45b6-aba0-93acd4e04709
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976325614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.976325614
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.3607833906
Short name T1312
Test name
Test status
Simulation time 5025636344 ps
CPU time 215.44 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:54:05 PM PDT 24
Peak memory 1056716 kb
Host smart-f67c513c-ac81-478f-a8ef-c3cae03311b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607833906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_
target_stretch.3607833906
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.3755353275
Short name T174
Test name
Test status
Simulation time 2994029289 ps
CPU time 7.7 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:35 PM PDT 24
Peak memory 220216 kb
Host smart-f0485c3a-d654-4f0e-b385-fa606fa5a931
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755353275 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.3755353275
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_alert_test.3936330182
Short name T704
Test name
Test status
Simulation time 25225035 ps
CPU time 0.63 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 204416 kb
Host smart-cfa10054-e28d-4d92-a484-1680d7693802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936330182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.3936330182
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.1874965030
Short name T631
Test name
Test status
Simulation time 277421056 ps
CPU time 3.51 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:50:34 PM PDT 24
Peak memory 230792 kb
Host smart-d1924b05-13bf-428a-b3f2-b17d09f1470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874965030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.1874965030
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.2371941714
Short name T1484
Test name
Test status
Simulation time 314792331 ps
CPU time 4.7 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:33 PM PDT 24
Peak memory 237300 kb
Host smart-4a973744-9e36-4ae9-9b89-80a11b3498e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371941714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.2371941714
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3421804474
Short name T1366
Test name
Test status
Simulation time 4178860093 ps
CPU time 73.42 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:51:40 PM PDT 24
Peak memory 694324 kb
Host smart-4cddd98a-ee2e-4066-a0ec-178c4a3c4775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421804474 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3421804474
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.91275665
Short name T983
Test name
Test status
Simulation time 7894313375 ps
CPU time 64.79 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:51:36 PM PDT 24
Peak memory 676944 kb
Host smart-635b95e7-11ee-4828-b9a8-8fcac64b1515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91275665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.91275665
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.2425710173
Short name T561
Test name
Test status
Simulation time 166191458 ps
CPU time 0.9 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:29 PM PDT 24
Peak memory 204548 kb
Host smart-aa115f94-9e26-4fb7-ab2c-03cbb147e56c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425710173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.2425710173
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3604948731
Short name T168
Test name
Test status
Simulation time 199812686 ps
CPU time 4.67 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 204804 kb
Host smart-6907de6e-b4e6-437e-a3f1-790642c3e136
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604948731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3604948731
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.3686678003
Short name T1391
Test name
Test status
Simulation time 11009951700 ps
CPU time 139.17 seconds
Started Jun 27 04:50:14 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 1526700 kb
Host smart-dc13acda-b544-41aa-a59d-1d18e161c672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686678003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.3686678003
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.137763969
Short name T776
Test name
Test status
Simulation time 943824894 ps
CPU time 4.21 seconds
Started Jun 27 04:50:19 PM PDT 24
Finished Jun 27 04:50:30 PM PDT 24
Peak memory 204876 kb
Host smart-ed412fd3-3719-4efd-9e78-f9788c20ea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137763969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.137763969
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.2189714419
Short name T492
Test name
Test status
Simulation time 7015737619 ps
CPU time 24.55 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:51 PM PDT 24
Peak memory 313848 kb
Host smart-5d4b2362-9de9-42ac-a396-e99bfad03a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189714419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.2189714419
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_override.4200052142
Short name T986
Test name
Test status
Simulation time 26134496 ps
CPU time 0.67 seconds
Started Jun 27 04:50:17 PM PDT 24
Finished Jun 27 04:50:20 PM PDT 24
Peak memory 204548 kb
Host smart-79ed55eb-5776-4e78-a318-7a587ffe0ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200052142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.4200052142
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.1484794504
Short name T62
Test name
Test status
Simulation time 2872806091 ps
CPU time 102.1 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:52:04 PM PDT 24
Peak memory 224696 kb
Host smart-2a4346d0-a02d-491e-a29f-0c3f6c367116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484794504 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.1484794504
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.558739828
Short name T1280
Test name
Test status
Simulation time 54252389 ps
CPU time 1.08 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:29 PM PDT 24
Peak memory 204656 kb
Host smart-7a761e65-fd4f-4256-a613-108e62b5d589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558739828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.558739828
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1411297246
Short name T66
Test name
Test status
Simulation time 4771337388 ps
CPU time 22.26 seconds
Started Jun 27 04:50:17 PM PDT 24
Finished Jun 27 04:50:42 PM PDT 24
Peak memory 320248 kb
Host smart-32752484-c3ee-4604-8ca6-0027c40d58ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411297246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1411297246
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.1385264384
Short name T118
Test name
Test status
Simulation time 113219959302 ps
CPU time 229.86 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:54:16 PM PDT 24
Peak memory 1149644 kb
Host smart-6666c500-9c6b-4aa7-aa93-444d551bbc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385264384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.1385264384
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.1786501767
Short name T1300
Test name
Test status
Simulation time 1776736284 ps
CPU time 9.85 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:42 PM PDT 24
Peak memory 212988 kb
Host smart-6f56f33b-a95f-455a-8605-75086ece4e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786501767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1786501767
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3861182928
Short name T1226
Test name
Test status
Simulation time 833302898 ps
CPU time 4.13 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 213032 kb
Host smart-be90ada1-17f9-455a-9ebf-2fcb6d6c0ee1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861182928 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3861182928
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2483199178
Short name T788
Test name
Test status
Simulation time 330726579 ps
CPU time 1.32 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 204732 kb
Host smart-0c524fb8-2acb-4d38-a9a2-300de33b6bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483199178 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2483199178
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3125852663
Short name T308
Test name
Test status
Simulation time 487097086 ps
CPU time 1.16 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 204524 kb
Host smart-64a8d692-e7e2-4f79-946c-dfb45158b985
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125852663 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3125852663
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.322375507
Short name T267
Test name
Test status
Simulation time 553400233 ps
CPU time 2.45 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:50:33 PM PDT 24
Peak memory 204736 kb
Host smart-80eb4b06-ebd8-4bb0-bb56-42903b5af0de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322375507 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.322375507
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.1720730761
Short name T1231
Test name
Test status
Simulation time 431721506 ps
CPU time 1 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:29 PM PDT 24
Peak memory 204616 kb
Host smart-90f57b96-8828-46bf-a674-e1bdaebcdf32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720730761 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.1720730761
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.2193662881
Short name T955
Test name
Test status
Simulation time 209757809 ps
CPU time 2.29 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 204772 kb
Host smart-5a8413b5-1f75-4dd9-9cf2-3e86c45d7539
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193662881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.2193662881
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1139541343
Short name T1433
Test name
Test status
Simulation time 1154437151 ps
CPU time 6.79 seconds
Started Jun 27 04:50:19 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 221112 kb
Host smart-ee626e5f-50ee-45b0-8a8c-a21daa216c2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139541343 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1139541343
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.1785719132
Short name T961
Test name
Test status
Simulation time 20837031372 ps
CPU time 424.37 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:57:35 PM PDT 24
Peak memory 5106584 kb
Host smart-5ced8418-5dea-409c-8b93-34d18118bf61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785719132 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.1785719132
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1661011869
Short name T863
Test name
Test status
Simulation time 1159973739 ps
CPU time 7.1 seconds
Started Jun 27 04:50:19 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 204812 kb
Host smart-5472590b-f683-4ec8-8a9c-3d264f32f227
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661011869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1661011869
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.343155477
Short name T783
Test name
Test status
Simulation time 10418373527 ps
CPU time 23.25 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:50:46 PM PDT 24
Peak memory 227784 kb
Host smart-9ebb1ac9-b5d7-45cc-ae26-1a8bc06fd112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343155477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.343155477
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.3298512345
Short name T1307
Test name
Test status
Simulation time 45652680061 ps
CPU time 101.88 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:52:10 PM PDT 24
Peak memory 1575368 kb
Host smart-fde4a525-03e5-46d5-85ee-2f0eac5440d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298512345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.3298512345
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.4146780143
Short name T692
Test name
Test status
Simulation time 19509202317 ps
CPU time 158.27 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:53:09 PM PDT 24
Peak memory 725052 kb
Host smart-f233dd9e-49f7-42c5-8f33-48e0af481077
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146780143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.4146780143
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.2942607962
Short name T483
Test name
Test status
Simulation time 1540518833 ps
CPU time 7.63 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 220948 kb
Host smart-e52b3ca9-45e4-45f7-b13a-37ecaa966181
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942607962 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.2942607962
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_alert_test.79369665
Short name T187
Test name
Test status
Simulation time 15975527 ps
CPU time 0.62 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 204400 kb
Host smart-e11ba1e8-4c23-4768-b0af-10440db7cbef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79369665 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.79369665
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.2594823264
Short name T515
Test name
Test status
Simulation time 343611748 ps
CPU time 1.19 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 213012 kb
Host smart-09aebcb8-21ba-4a9e-ade0-db461807a913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594823264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.2594823264
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1061118868
Short name T995
Test name
Test status
Simulation time 775564042 ps
CPU time 8.89 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:37 PM PDT 24
Peak memory 290152 kb
Host smart-fb1cd10a-d2de-4d56-a151-ba32ddfa30b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061118868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1061118868
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1261187714
Short name T709
Test name
Test status
Simulation time 17663152353 ps
CPU time 97.4 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:52:08 PM PDT 24
Peak memory 822656 kb
Host smart-a8f00a13-73e0-41f5-a5ad-394f059005b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261187714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1261187714
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.2108111146
Short name T324
Test name
Test status
Simulation time 3551601630 ps
CPU time 50.41 seconds
Started Jun 27 04:50:19 PM PDT 24
Finished Jun 27 04:51:16 PM PDT 24
Peak memory 629056 kb
Host smart-292a817d-4a8b-4c36-9b2f-dfcfb24338f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108111146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.2108111146
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2849729924
Short name T1143
Test name
Test status
Simulation time 334236016 ps
CPU time 0.89 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:28 PM PDT 24
Peak memory 204540 kb
Host smart-82d6c515-79a7-4da3-8b55-ec7b94294afb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849729924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2849729924
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.2921918103
Short name T1378
Test name
Test status
Simulation time 215357278 ps
CPU time 5.53 seconds
Started Jun 27 04:50:19 PM PDT 24
Finished Jun 27 04:50:30 PM PDT 24
Peak memory 245424 kb
Host smart-b2732ec0-3296-48a6-8436-c99169106745
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921918103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.2921918103
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.4103313126
Short name T945
Test name
Test status
Simulation time 19957462661 ps
CPU time 137.54 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:52:44 PM PDT 24
Peak memory 1352972 kb
Host smart-c364d5a8-ffe2-4beb-bcd6-d52f972073c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103313126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.4103313126
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.198098911
Short name T1171
Test name
Test status
Simulation time 4800317741 ps
CPU time 4.91 seconds
Started Jun 27 04:50:25 PM PDT 24
Finished Jun 27 04:50:37 PM PDT 24
Peak memory 204860 kb
Host smart-28ee29c9-ca26-45ca-a2a2-b480aed56e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198098911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.198098911
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3019141984
Short name T712
Test name
Test status
Simulation time 3912793638 ps
CPU time 37.55 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:51:07 PM PDT 24
Peak memory 368244 kb
Host smart-e4c84010-c35f-4816-8412-128cd699f76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019141984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3019141984
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.2866595577
Short name T84
Test name
Test status
Simulation time 15495961 ps
CPU time 0.76 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:28 PM PDT 24
Peak memory 204512 kb
Host smart-71b725c7-2145-4d9d-bcd5-a4ae395b9137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866595577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.2866595577
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.3694601516
Short name T300
Test name
Test status
Simulation time 222157681 ps
CPU time 8.33 seconds
Started Jun 27 04:50:18 PM PDT 24
Finished Jun 27 04:50:30 PM PDT 24
Peak memory 222484 kb
Host smart-18860534-93a5-47a7-bc31-9080cfcdca70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694601516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.3694601516
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3048132834
Short name T659
Test name
Test status
Simulation time 1901013068 ps
CPU time 34.06 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:51:04 PM PDT 24
Peak memory 442156 kb
Host smart-a46ff1c6-1867-424b-9154-e2cc79b3b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048132834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3048132834
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.3811686612
Short name T39
Test name
Test status
Simulation time 7739996323 ps
CPU time 335.66 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:56:04 PM PDT 24
Peak memory 1855140 kb
Host smart-85af3e44-4a71-42cb-8d84-665101ef4bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811686612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.3811686612
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3314245287
Short name T1232
Test name
Test status
Simulation time 2456502137 ps
CPU time 10.62 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:40 PM PDT 24
Peak memory 213212 kb
Host smart-002a58ec-8b6f-4c4c-8022-7b8710b595fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314245287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3314245287
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.695077936
Short name T813
Test name
Test status
Simulation time 725552217 ps
CPU time 3.95 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:34 PM PDT 24
Peak memory 212944 kb
Host smart-7ebb3476-f7ab-49aa-ae28-03864418aaab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695077936 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.695077936
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2503520058
Short name T1304
Test name
Test status
Simulation time 462860331 ps
CPU time 1.1 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:28 PM PDT 24
Peak memory 204572 kb
Host smart-24ded2be-d84f-4e82-b744-676b4d5cd22c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503520058 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2503520058
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.2398377124
Short name T1276
Test name
Test status
Simulation time 798312018 ps
CPU time 1.39 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 204784 kb
Host smart-17c347eb-2316-47cf-aa92-89d91856e08b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398377124 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.2398377124
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1433030917
Short name T852
Test name
Test status
Simulation time 606209230 ps
CPU time 2.82 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 204720 kb
Host smart-e82c3543-10fc-4ab9-8ec5-04113d1b48f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433030917 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1433030917
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.2642114093
Short name T688
Test name
Test status
Simulation time 152640052 ps
CPU time 1.33 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 204528 kb
Host smart-83595f20-f1f9-49f8-88fb-c093826aff53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642114093 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.2642114093
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.4213335587
Short name T286
Test name
Test status
Simulation time 942486016 ps
CPU time 3.34 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:29 PM PDT 24
Peak memory 204776 kb
Host smart-e28d3dce-e4cd-4605-a79c-0ffef8a6be53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213335587 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.4213335587
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.1739095104
Short name T591
Test name
Test status
Simulation time 743891724 ps
CPU time 3.91 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:35 PM PDT 24
Peak memory 204720 kb
Host smart-930c94a3-94c7-4c9b-8a39-d1ab82e01b49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739095104 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.1739095104
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1601117227
Short name T149
Test name
Test status
Simulation time 18849701320 ps
CPU time 115.64 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:52:27 PM PDT 24
Peak memory 2280996 kb
Host smart-b6574106-2de8-4c64-95e9-c0ce45140dde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601117227 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1601117227
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.3857242177
Short name T519
Test name
Test status
Simulation time 1103576916 ps
CPU time 18.66 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:48 PM PDT 24
Peak memory 205076 kb
Host smart-fe12e958-9600-4434-9a23-c733f723f20d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857242177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_ta
rget_smoke.3857242177
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.2726367220
Short name T656
Test name
Test status
Simulation time 4090263538 ps
CPU time 43.42 seconds
Started Jun 27 04:50:28 PM PDT 24
Finished Jun 27 04:51:16 PM PDT 24
Peak memory 205396 kb
Host smart-bb79e4d6-dbb3-4dcd-bc97-8bbd931a37b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726367220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.2726367220
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1580781820
Short name T898
Test name
Test status
Simulation time 48902001280 ps
CPU time 123.27 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 1760192 kb
Host smart-93f55eb8-68cb-4af9-8532-d6717eec54a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580781820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1580781820
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.3224019123
Short name T249
Test name
Test status
Simulation time 14412416761 ps
CPU time 509.68 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:59:00 PM PDT 24
Peak memory 1635280 kb
Host smart-e8245e2f-adcb-4b0e-afb2-b14f68477070
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224019123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.3224019123
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.654702978
Short name T270
Test name
Test status
Simulation time 5980977357 ps
CPU time 6.97 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:35 PM PDT 24
Peak memory 221156 kb
Host smart-313e7360-22e5-41f5-b9a3-7312094ccd36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654702978 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_timeout.654702978
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_alert_test.1851037733
Short name T1255
Test name
Test status
Simulation time 17178437 ps
CPU time 0.72 seconds
Started Jun 27 04:50:50 PM PDT 24
Finished Jun 27 04:50:52 PM PDT 24
Peak memory 204488 kb
Host smart-7cc610dd-4aa8-422a-91f7-52e1020b4899
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851037733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.1851037733
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.4091465542
Short name T864
Test name
Test status
Simulation time 1006568262 ps
CPU time 3.24 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:35 PM PDT 24
Peak memory 204696 kb
Host smart-2d2abe3d-8ef9-435b-af37-89920a935b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091465542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.4091465542
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.174564948
Short name T682
Test name
Test status
Simulation time 705480265 ps
CPU time 4.14 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 228272 kb
Host smart-b99b79be-2c17-40bd-9bb6-3879053c7694
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174564948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_empt
y.174564948
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1312387957
Short name T687
Test name
Test status
Simulation time 7236107430 ps
CPU time 110.44 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:52:20 PM PDT 24
Peak memory 542080 kb
Host smart-b9fdfddf-527d-4445-b32e-72d3cda01682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312387957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1312387957
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.3829416394
Short name T903
Test name
Test status
Simulation time 5081030690 ps
CPU time 185.3 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:53:35 PM PDT 24
Peak memory 811384 kb
Host smart-c17f572a-84bd-4dda-bc31-4a74b9c3f516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829416394 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.3829416394
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2703666703
Short name T1444
Test name
Test status
Simulation time 590305737 ps
CPU time 1.12 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:50:31 PM PDT 24
Peak memory 204512 kb
Host smart-7919bd38-24d3-4f51-af90-939da38d39fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703666703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2703666703
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.313811899
Short name T367
Test name
Test status
Simulation time 613803936 ps
CPU time 5.91 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:37 PM PDT 24
Peak memory 219440 kb
Host smart-37eeec47-61d8-4d51-a24a-c3bb2cc62ec8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313811899 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx.
313811899
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3942805107
Short name T932
Test name
Test status
Simulation time 16107114655 ps
CPU time 260.05 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:54:52 PM PDT 24
Peak memory 1132712 kb
Host smart-76db23c1-1bb5-41bc-a579-3a79a40d2801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942805107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3942805107
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1371008608
Short name T1167
Test name
Test status
Simulation time 430940535 ps
CPU time 5.42 seconds
Started Jun 27 04:50:46 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 204880 kb
Host smart-5df6fa8a-e250-4aa6-8795-e5f8ae8e0c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371008608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1371008608
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3379575810
Short name T448
Test name
Test status
Simulation time 9142293020 ps
CPU time 38.48 seconds
Started Jun 27 04:50:47 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 352136 kb
Host smart-1314473f-c16d-4a22-a7e0-809305eb22d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379575810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3379575810
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.195263052
Short name T585
Test name
Test status
Simulation time 83680136 ps
CPU time 0.68 seconds
Started Jun 27 04:50:24 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 204492 kb
Host smart-1dc56020-ae64-4726-92d1-833700894e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195263052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.195263052
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.1206515099
Short name T727
Test name
Test status
Simulation time 4695441960 ps
CPU time 33.93 seconds
Started Jun 27 04:50:22 PM PDT 24
Finished Jun 27 04:51:05 PM PDT 24
Peak memory 247556 kb
Host smart-8c5d75c8-fd56-4ae2-89a7-fd84748de276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206515099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.1206515099
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.1024674269
Short name T1445
Test name
Test status
Simulation time 155865893 ps
CPU time 6.7 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:34 PM PDT 24
Peak memory 229196 kb
Host smart-673b4043-6d78-4d0a-9aac-e74d1fd5bd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024674269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.1024674269
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.2887966847
Short name T462
Test name
Test status
Simulation time 8723614260 ps
CPU time 45.7 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:51:13 PM PDT 24
Peak memory 478952 kb
Host smart-ba399da5-a35f-4db5-a91d-e4e16db6a5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887966847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.2887966847
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.738077539
Short name T1164
Test name
Test status
Simulation time 1359653369 ps
CPU time 30.63 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:59 PM PDT 24
Peak memory 212984 kb
Host smart-fda659e0-0df4-4114-98f9-f6f4c84e81a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738077539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.738077539
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.861298386
Short name T1051
Test name
Test status
Simulation time 10179019944 ps
CPU time 4.74 seconds
Started Jun 27 04:50:47 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 205024 kb
Host smart-f24f9de8-0e64-4d9f-9ddd-bf98d11b42f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861298386 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.861298386
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.2379156657
Short name T1081
Test name
Test status
Simulation time 292611309 ps
CPU time 0.92 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:29 PM PDT 24
Peak memory 204632 kb
Host smart-6ccc8348-8e93-4335-a340-ece013b26e7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379156657 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.2379156657
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.4181030521
Short name T1414
Test name
Test status
Simulation time 2401477900 ps
CPU time 1.22 seconds
Started Jun 27 04:50:16 PM PDT 24
Finished Jun 27 04:50:20 PM PDT 24
Peak memory 204948 kb
Host smart-65ce9c36-12de-44e3-ad59-4cb7cd2b7f77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181030521 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.4181030521
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.3133534084
Short name T868
Test name
Test status
Simulation time 184310224 ps
CPU time 1.25 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 204540 kb
Host smart-0d1b97bb-e943-4691-a609-827aa23d2e7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133534084 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.3133534084
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.1727285989
Short name T1108
Test name
Test status
Simulation time 99374070 ps
CPU time 1.1 seconds
Started Jun 27 04:50:45 PM PDT 24
Finished Jun 27 04:50:47 PM PDT 24
Peak memory 204564 kb
Host smart-a9c16d7d-6ecb-4c78-bd7c-7a9150dcb38a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727285989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.1727285989
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.476422083
Short name T247
Test name
Test status
Simulation time 349379927 ps
CPU time 2.85 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:50:59 PM PDT 24
Peak memory 204708 kb
Host smart-77e9a39f-5cdd-49b7-ab9c-69358a903024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476422083 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 23.i2c_target_hrst.476422083
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2263705710
Short name T1037
Test name
Test status
Simulation time 1538816417 ps
CPU time 4.6 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 213016 kb
Host smart-e8fa7095-5671-4272-b10f-96f2d82f5043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263705710 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2263705710
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.888900258
Short name T871
Test name
Test status
Simulation time 9462238858 ps
CPU time 121.3 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:52:29 PM PDT 24
Peak memory 2183816 kb
Host smart-6735cbc9-8bdc-44a7-9308-302fd546721d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888900258 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.888900258
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2186690478
Short name T954
Test name
Test status
Simulation time 1219013604 ps
CPU time 48.74 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204744 kb
Host smart-a38de920-a53f-408a-a5f8-6e8c3057f06c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186690478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2186690478
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1421791573
Short name T839
Test name
Test status
Simulation time 1137062808 ps
CPU time 12.03 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:50:42 PM PDT 24
Peak memory 204720 kb
Host smart-e4b8140e-56ff-4ab1-af7d-9f151b37fbdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421791573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1421791573
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.4275693637
Short name T1177
Test name
Test status
Simulation time 28172506336 ps
CPU time 8.09 seconds
Started Jun 27 04:50:21 PM PDT 24
Finished Jun 27 04:50:36 PM PDT 24
Peak memory 244920 kb
Host smart-870d9a62-76ce-4ba1-9940-79219ecf254e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275693637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.4275693637
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.3362733101
Short name T27
Test name
Test status
Simulation time 16074596691 ps
CPU time 1892.27 seconds
Started Jun 27 04:50:20 PM PDT 24
Finished Jun 27 05:22:00 PM PDT 24
Peak memory 3863460 kb
Host smart-72d187e3-e29f-4348-8726-197fcc98f307
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362733101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.3362733101
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3506335121
Short name T833
Test name
Test status
Simulation time 1227222721 ps
CPU time 6.52 seconds
Started Jun 27 04:50:23 PM PDT 24
Finished Jun 27 04:50:37 PM PDT 24
Peak memory 220992 kb
Host smart-27e47916-bfc8-4b39-9b00-f7d6624b4c4c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506335121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3506335121
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_alert_test.3626776706
Short name T782
Test name
Test status
Simulation time 51256657 ps
CPU time 0.6 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 204500 kb
Host smart-ec375bc6-9a7b-4767-8bf0-55c8087847ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626776706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.3626776706
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.400529634
Short name T395
Test name
Test status
Simulation time 866976916 ps
CPU time 5.03 seconds
Started Jun 27 04:50:50 PM PDT 24
Finished Jun 27 04:50:56 PM PDT 24
Peak memory 226232 kb
Host smart-724e2e48-e881-4b82-9c1f-677e5438ff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400529634 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.400529634
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.554714586
Short name T1158
Test name
Test status
Simulation time 1028816844 ps
CPU time 14.78 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:51:09 PM PDT 24
Peak memory 262880 kb
Host smart-c09f8b4f-5e4f-4b5e-94af-45e4be6963f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554714586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_empt
y.554714586
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.556130790
Short name T1219
Test name
Test status
Simulation time 12839955298 ps
CPU time 206.67 seconds
Started Jun 27 04:50:47 PM PDT 24
Finished Jun 27 04:54:16 PM PDT 24
Peak memory 880116 kb
Host smart-6f8cb184-4907-4ce6-97bd-167f4a62eed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556130790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.556130790
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.1326082348
Short name T1034
Test name
Test status
Simulation time 2199369012 ps
CPU time 64.57 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 742696 kb
Host smart-4c5140b9-de51-4af2-b34f-b32b10371aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326082348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.1326082348
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1893645611
Short name T3
Test name
Test status
Simulation time 555968683 ps
CPU time 1.08 seconds
Started Jun 27 04:50:49 PM PDT 24
Finished Jun 27 04:50:51 PM PDT 24
Peak memory 204548 kb
Host smart-2c508bf2-5603-4565-b586-7f33883056db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893645611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1893645611
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.179276014
Short name T82
Test name
Test status
Simulation time 132980463 ps
CPU time 3.47 seconds
Started Jun 27 04:50:46 PM PDT 24
Finished Jun 27 04:50:52 PM PDT 24
Peak memory 204808 kb
Host smart-252917d7-7b98-4512-b85d-653819a39a7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179276014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
179276014
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.1088754278
Short name T1344
Test name
Test status
Simulation time 17093710556 ps
CPU time 113.04 seconds
Started Jun 27 04:50:57 PM PDT 24
Finished Jun 27 04:52:55 PM PDT 24
Peak memory 1163272 kb
Host smart-de192d5e-7ab3-4eae-ac14-04209eae6c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088754278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.1088754278
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.4172292021
Short name T1203
Test name
Test status
Simulation time 2467994340 ps
CPU time 11.89 seconds
Started Jun 27 04:50:46 PM PDT 24
Finished Jun 27 04:51:00 PM PDT 24
Peak memory 204968 kb
Host smart-80c0c905-e4c2-4328-b983-903e28b0acee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172292021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.4172292021
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.520687843
Short name T1465
Test name
Test status
Simulation time 3897399162 ps
CPU time 40.65 seconds
Started Jun 27 04:50:45 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 253684 kb
Host smart-9c7efc14-a878-46e0-9191-2dab929ee24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520687843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.520687843
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.3472774318
Short name T701
Test name
Test status
Simulation time 25997514 ps
CPU time 0.68 seconds
Started Jun 27 04:50:46 PM PDT 24
Finished Jun 27 04:50:50 PM PDT 24
Peak memory 204520 kb
Host smart-54f922d0-0ccd-481a-bcaf-6efcc73727d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472774318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.3472774318
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.4067017152
Short name T1183
Test name
Test status
Simulation time 5083055281 ps
CPU time 19.02 seconds
Started Jun 27 04:50:46 PM PDT 24
Finished Jun 27 04:51:07 PM PDT 24
Peak memory 227896 kb
Host smart-451cfc64-1838-4cad-92b9-b0fe71657bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067017152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.4067017152
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.2854629117
Short name T387
Test name
Test status
Simulation time 1549835368 ps
CPU time 57.14 seconds
Started Jun 27 04:50:43 PM PDT 24
Finished Jun 27 04:51:41 PM PDT 24
Peak memory 204760 kb
Host smart-77e29d4b-1c5a-4f1a-9700-78baaa8f7126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854629117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.2854629117
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.2585885060
Short name T921
Test name
Test status
Simulation time 1354900398 ps
CPU time 23.4 seconds
Started Jun 27 04:50:46 PM PDT 24
Finished Jun 27 04:51:12 PM PDT 24
Peak memory 382228 kb
Host smart-d3140264-7740-4beb-ab28-2ce9ae1e7e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585885060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.2585885060
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.2860461017
Short name T58
Test name
Test status
Simulation time 353090005152 ps
CPU time 1587.83 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 05:17:24 PM PDT 24
Peak memory 4038932 kb
Host smart-4001d533-146a-404f-b61c-d5fedab9a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860461017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.2860461017
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.4071847250
Short name T318
Test name
Test status
Simulation time 5016420418 ps
CPU time 25.66 seconds
Started Jun 27 04:50:44 PM PDT 24
Finished Jun 27 04:51:10 PM PDT 24
Peak memory 213168 kb
Host smart-0f3e94a6-3592-44b0-840d-1932c6d5a899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071847250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.4071847250
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.1440152578
Short name T624
Test name
Test status
Simulation time 3831997129 ps
CPU time 4 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:51:00 PM PDT 24
Peak memory 213084 kb
Host smart-73135ecb-652b-40c6-84e6-a2f6ffeeca73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440152578 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.1440152578
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1745235358
Short name T1477
Test name
Test status
Simulation time 316580242 ps
CPU time 0.91 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:51:01 PM PDT 24
Peak memory 204552 kb
Host smart-6440687c-b638-4ca2-8651-569076298133
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745235358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1745235358
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.974180850
Short name T639
Test name
Test status
Simulation time 417011696 ps
CPU time 1.35 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 205680 kb
Host smart-dc086733-0106-4cee-bd75-36d11fe43b94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974180850 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.974180850
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.2885845668
Short name T261
Test name
Test status
Simulation time 544884106 ps
CPU time 2.88 seconds
Started Jun 27 04:50:46 PM PDT 24
Finished Jun 27 04:50:51 PM PDT 24
Peak memory 204752 kb
Host smart-2418dafd-011b-40fd-9844-cb6dabe3d111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885845668 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.2885845668
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.1339031753
Short name T496
Test name
Test status
Simulation time 87487091 ps
CPU time 0.86 seconds
Started Jun 27 04:50:44 PM PDT 24
Finished Jun 27 04:50:46 PM PDT 24
Peak memory 204532 kb
Host smart-ea75d05e-7ffc-481b-9178-2cb5c6635206
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339031753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.1339031753
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_hrst.3608755200
Short name T958
Test name
Test status
Simulation time 5178441710 ps
CPU time 2.44 seconds
Started Jun 27 04:50:54 PM PDT 24
Finished Jun 27 04:51:01 PM PDT 24
Peak memory 204848 kb
Host smart-eb7db0e1-16e2-4085-979a-84e9123c43f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608755200 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_hrst.3608755200
Directory /workspace/24.i2c_target_hrst/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.391400685
Short name T685
Test name
Test status
Simulation time 650260946 ps
CPU time 3.94 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:50:57 PM PDT 24
Peak memory 205164 kb
Host smart-be05bd59-5996-43bd-9727-9fb7d19b6f97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391400685 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 24.i2c_target_intr_smoke.391400685
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.3254960611
Short name T1056
Test name
Test status
Simulation time 4448107494 ps
CPU time 7.72 seconds
Started Jun 27 04:50:50 PM PDT 24
Finished Jun 27 04:50:59 PM PDT 24
Peak memory 408852 kb
Host smart-5bef9f4d-a92d-44f7-83f1-673184c4739b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254960611 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.3254960611
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.3945656941
Short name T991
Test name
Test status
Simulation time 3752564299 ps
CPU time 32.76 seconds
Started Jun 27 04:50:48 PM PDT 24
Finished Jun 27 04:51:23 PM PDT 24
Peak memory 204928 kb
Host smart-44cc6783-457c-415d-8e1b-66e9df98d0b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945656941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.3945656941
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.3970173131
Short name T646
Test name
Test status
Simulation time 6458876202 ps
CPU time 25.37 seconds
Started Jun 27 04:50:45 PM PDT 24
Finished Jun 27 04:51:13 PM PDT 24
Peak memory 236976 kb
Host smart-94dd00b7-2503-40dd-bb22-2d99d2187b37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970173131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.3970173131
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.204126960
Short name T960
Test name
Test status
Simulation time 27442760605 ps
CPU time 130.04 seconds
Started Jun 27 04:50:44 PM PDT 24
Finished Jun 27 04:52:55 PM PDT 24
Peak memory 1868840 kb
Host smart-e4cd8a3f-5491-43b4-b7c2-c6bd226ec274
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204126960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.204126960
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1872451809
Short name T946
Test name
Test status
Simulation time 9945516537 ps
CPU time 256.96 seconds
Started Jun 27 04:50:49 PM PDT 24
Finished Jun 27 04:55:07 PM PDT 24
Peak memory 2042692 kb
Host smart-151c134c-1f5e-4319-826d-bc45ed1120a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872451809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1872451809
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1155492809
Short name T1430
Test name
Test status
Simulation time 1676776933 ps
CPU time 8.27 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:51:05 PM PDT 24
Peak memory 213276 kb
Host smart-ddf14fcd-7b3c-4218-a443-c575c8159e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155492809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1155492809
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_alert_test.2338212805
Short name T467
Test name
Test status
Simulation time 26955345 ps
CPU time 0.69 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 204488 kb
Host smart-383d807b-9249-4701-8994-e828b5a93c7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338212805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.2338212805
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.4158121083
Short name T376
Test name
Test status
Simulation time 317601845 ps
CPU time 4.4 seconds
Started Jun 27 04:50:57 PM PDT 24
Finished Jun 27 04:51:06 PM PDT 24
Peak memory 221224 kb
Host smart-d509d4e2-684a-48e1-b496-81239a1c4b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158121083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.4158121083
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.3896227165
Short name T1361
Test name
Test status
Simulation time 2604393502 ps
CPU time 14.57 seconds
Started Jun 27 04:50:44 PM PDT 24
Finished Jun 27 04:50:59 PM PDT 24
Peak memory 339184 kb
Host smart-7a1063ce-3da8-4acd-b9b7-2d8994b5feec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896227165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.3896227165
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.3742400962
Short name T71
Test name
Test status
Simulation time 1510202942 ps
CPU time 38.61 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:51:33 PM PDT 24
Peak memory 371380 kb
Host smart-85a2d383-cd07-439b-876c-c03ca8138b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742400962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.3742400962
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.4068999791
Short name T571
Test name
Test status
Simulation time 2699960409 ps
CPU time 95.2 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:52:28 PM PDT 24
Peak memory 852900 kb
Host smart-5a090bb2-c6d1-476a-a3b9-f42e21ff2dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068999791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.4068999791
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.1188423379
Short name T655
Test name
Test status
Simulation time 230789034 ps
CPU time 0.97 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:50:56 PM PDT 24
Peak memory 204548 kb
Host smart-6f028900-f4ee-4a5a-9391-601dff370b96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188423379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.1188423379
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.3043608766
Short name T780
Test name
Test status
Simulation time 348546709 ps
CPU time 4.43 seconds
Started Jun 27 04:50:48 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 237756 kb
Host smart-6ef641a8-4932-408c-b3df-a944c5cc8e4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043608766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx
.3043608766
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3406219889
Short name T1348
Test name
Test status
Simulation time 18162008711 ps
CPU time 157.12 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:53:34 PM PDT 24
Peak memory 1443736 kb
Host smart-adee0aba-9981-47d4-9551-38441d10adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406219889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3406219889
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.1151630516
Short name T848
Test name
Test status
Simulation time 821523807 ps
CPU time 5.06 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:50:57 PM PDT 24
Peak memory 204784 kb
Host smart-6daa658f-68d4-4a6f-915a-fd70e45cf57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151630516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.1151630516
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.1607251172
Short name T67
Test name
Test status
Simulation time 2040564090 ps
CPU time 109.47 seconds
Started Jun 27 04:50:56 PM PDT 24
Finished Jun 27 04:52:50 PM PDT 24
Peak memory 486268 kb
Host smart-a7770524-c4cd-43a3-be53-3af9a511915b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607251172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.1607251172
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.695693828
Short name T919
Test name
Test status
Simulation time 27460393 ps
CPU time 0.67 seconds
Started Jun 27 04:50:46 PM PDT 24
Finished Jun 27 04:50:48 PM PDT 24
Peak memory 204460 kb
Host smart-c9d5d524-3cae-421a-89c1-6696887e4309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695693828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.695693828
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1026179574
Short name T526
Test name
Test status
Simulation time 33212518425 ps
CPU time 311.54 seconds
Started Jun 27 04:50:45 PM PDT 24
Finished Jun 27 04:55:59 PM PDT 24
Peak memory 204904 kb
Host smart-b9160b7f-c78f-4551-ab27-d68f9d52a047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026179574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1026179574
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.3727532940
Short name T756
Test name
Test status
Simulation time 2779535647 ps
CPU time 6.75 seconds
Started Jun 27 04:50:50 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 222300 kb
Host smart-c1eced92-0819-4686-9cd9-289c39de6f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727532940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.3727532940
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2371168843
Short name T172
Test name
Test status
Simulation time 9139341789 ps
CPU time 42.66 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:51:42 PM PDT 24
Peak memory 487760 kb
Host smart-90c537ce-e332-41f0-a824-731b737dfd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371168843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2371168843
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1856963988
Short name T56
Test name
Test status
Simulation time 159755027030 ps
CPU time 922.9 seconds
Started Jun 27 04:50:47 PM PDT 24
Finished Jun 27 05:06:12 PM PDT 24
Peak memory 2799768 kb
Host smart-1860085a-d707-41eb-86a4-c0dc9dadeade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856963988 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1856963988
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.1277493296
Short name T772
Test name
Test status
Simulation time 1744068173 ps
CPU time 6.6 seconds
Started Jun 27 04:50:47 PM PDT 24
Finished Jun 27 04:50:55 PM PDT 24
Peak memory 213172 kb
Host smart-58799456-8e23-488c-8766-fcf494e9d813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277493296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.1277493296
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.345601316
Short name T1166
Test name
Test status
Simulation time 11602291322 ps
CPU time 4.97 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:50:57 PM PDT 24
Peak memory 205768 kb
Host smart-8d647991-225a-4789-bdd3-759ebb7fe3db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345601316 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.345601316
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.318873325
Short name T846
Test name
Test status
Simulation time 741378226 ps
CPU time 1.39 seconds
Started Jun 27 04:50:49 PM PDT 24
Finished Jun 27 04:50:52 PM PDT 24
Peak memory 206572 kb
Host smart-635c39be-77b6-4502-baec-02a19e5399bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318873325 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.318873325
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.3766059014
Short name T549
Test name
Test status
Simulation time 269423319 ps
CPU time 0.91 seconds
Started Jun 27 04:50:57 PM PDT 24
Finished Jun 27 04:51:03 PM PDT 24
Peak memory 204836 kb
Host smart-fa27b12a-29b0-4896-8f37-d01399e542ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766059014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.3766059014
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.3263331272
Short name T1435
Test name
Test status
Simulation time 565413346 ps
CPU time 2.95 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:51:02 PM PDT 24
Peak memory 204708 kb
Host smart-86d25a1a-20b3-4ef8-9a23-7b5f51ac8e4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263331272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.3263331272
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.2821116420
Short name T401
Test name
Test status
Simulation time 580644315 ps
CPU time 1.31 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:50:55 PM PDT 24
Peak memory 204184 kb
Host smart-3d6962a8-7f62-4339-99a2-7f7b154baec4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821116420 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.2821116420
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_hrst.3741243461
Short name T1044
Test name
Test status
Simulation time 1308984152 ps
CPU time 2.55 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:50:55 PM PDT 24
Peak memory 204800 kb
Host smart-00c44804-000b-417e-a1c4-b294bbd1b564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741243461 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_hrst.3741243461
Directory /workspace/25.i2c_target_hrst/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.236444342
Short name T471
Test name
Test status
Simulation time 797622325 ps
CPU time 4.27 seconds
Started Jun 27 04:50:48 PM PDT 24
Finished Jun 27 04:50:54 PM PDT 24
Peak memory 205180 kb
Host smart-afdc8cf7-4f4f-46a1-8eca-f510be7448fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236444342 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.236444342
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.85505494
Short name T1265
Test name
Test status
Simulation time 25394443410 ps
CPU time 187.39 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:54:08 PM PDT 24
Peak memory 2804136 kb
Host smart-34a5e431-e8ab-4895-94a5-36d071026dea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85505494 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.85505494
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.1829553160
Short name T629
Test name
Test status
Simulation time 2497934965 ps
CPU time 9.52 seconds
Started Jun 27 04:50:47 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 204912 kb
Host smart-83048f81-85d6-4918-b8c7-a7d0f43a00c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829553160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.1829553160
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.403496234
Short name T752
Test name
Test status
Simulation time 1798788308 ps
CPU time 25.55 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:51:22 PM PDT 24
Peak memory 234028 kb
Host smart-6487078c-2e0b-432a-9e4f-d28c4f8b9448
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403496234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c
_target_stress_rd.403496234
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3122898041
Short name T670
Test name
Test status
Simulation time 55521392477 ps
CPU time 191.54 seconds
Started Jun 27 04:50:49 PM PDT 24
Finished Jun 27 04:54:02 PM PDT 24
Peak memory 2261540 kb
Host smart-c49751c4-66a2-4080-8871-c62ffb2b7fa6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122898041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3122898041
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.109083236
Short name T829
Test name
Test status
Simulation time 20119533193 ps
CPU time 88.04 seconds
Started Jun 27 04:50:49 PM PDT 24
Finished Jun 27 04:52:19 PM PDT 24
Peak memory 1147784 kb
Host smart-bf8b1530-eb74-4353-993d-8d08006bfb27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109083236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_t
arget_stretch.109083236
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.1674824152
Short name T1278
Test name
Test status
Simulation time 3157061123 ps
CPU time 7.41 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:51:01 PM PDT 24
Peak memory 213288 kb
Host smart-43d09fe2-825f-4bbf-b80b-4fd33de3ec1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674824152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.1674824152
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_alert_test.248382295
Short name T1106
Test name
Test status
Simulation time 34379925 ps
CPU time 0.66 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:50:56 PM PDT 24
Peak memory 204472 kb
Host smart-6b331757-696c-4ff4-aee4-1429c1badcac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248382295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.248382295
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.236579842
Short name T803
Test name
Test status
Simulation time 701672619 ps
CPU time 3.09 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 229268 kb
Host smart-50dc4193-4b86-4735-a4c6-8698d3ee8f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236579842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.236579842
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1692301271
Short name T590
Test name
Test status
Simulation time 648031254 ps
CPU time 6.94 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:51:02 PM PDT 24
Peak memory 269892 kb
Host smart-c425db32-1260-47ee-a384-3a39d106b11a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692301271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1692301271
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3092335114
Short name T1310
Test name
Test status
Simulation time 2192612001 ps
CPU time 62.33 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:51:56 PM PDT 24
Peak memory 705064 kb
Host smart-bc2592ca-7ad0-4e06-a331-d70ffc6c038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092335114 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3092335114
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.2108989325
Short name T970
Test name
Test status
Simulation time 10713146393 ps
CPU time 86.18 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:52:23 PM PDT 24
Peak memory 839492 kb
Host smart-e89c3b86-60c5-4f14-8612-180c0f380c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108989325 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.2108989325
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.1902877932
Short name T586
Test name
Test status
Simulation time 234031295 ps
CPU time 1.09 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:51:00 PM PDT 24
Peak memory 204528 kb
Host smart-fd7333bf-3d54-49ef-acea-1e652dcf2017
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902877932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.1902877932
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.1482717313
Short name T1105
Test name
Test status
Simulation time 709238310 ps
CPU time 4.38 seconds
Started Jun 27 04:50:50 PM PDT 24
Finished Jun 27 04:50:56 PM PDT 24
Peak memory 204804 kb
Host smart-fa7abb75-e83e-4e0b-bb4c-e36c5d912150
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482717313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.1482717313
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.3632189826
Short name T1175
Test name
Test status
Simulation time 7794710717 ps
CPU time 113.37 seconds
Started Jun 27 04:50:57 PM PDT 24
Finished Jun 27 04:52:55 PM PDT 24
Peak memory 1178716 kb
Host smart-cc51e93f-f558-48d9-b605-4cef9cd84fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632189826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.3632189826
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.236204937
Short name T1002
Test name
Test status
Simulation time 1114751872 ps
CPU time 3.66 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 204908 kb
Host smart-b95a418d-e2b5-47cf-9ca6-4615128299dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236204937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.236204937
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.2736419864
Short name T1316
Test name
Test status
Simulation time 2839402537 ps
CPU time 22.21 seconds
Started Jun 27 04:50:59 PM PDT 24
Finished Jun 27 04:51:25 PM PDT 24
Peak memory 267356 kb
Host smart-94cfa912-4a2d-43d1-b9fd-ec80f08ec1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736419864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.2736419864
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.3426687574
Short name T1397
Test name
Test status
Simulation time 21198796 ps
CPU time 0.66 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 204560 kb
Host smart-738a1b45-d275-473f-9ebe-e3c24987045d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426687574 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3426687574
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.3271623181
Short name T437
Test name
Test status
Simulation time 3076950338 ps
CPU time 81.82 seconds
Started Jun 27 04:50:47 PM PDT 24
Finished Jun 27 04:52:11 PM PDT 24
Peak memory 841924 kb
Host smart-23e652a7-04dd-41cb-a6bc-8e5ac95ed573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271623181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.3271623181
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.1318106354
Short name T1022
Test name
Test status
Simulation time 146856831 ps
CPU time 1.56 seconds
Started Jun 27 04:50:50 PM PDT 24
Finished Jun 27 04:50:53 PM PDT 24
Peak memory 229332 kb
Host smart-f8cf8008-f006-48ee-b5d5-025f36f688f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318106354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.1318106354
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.847428985
Short name T601
Test name
Test status
Simulation time 840067009 ps
CPU time 13.05 seconds
Started Jun 27 04:50:45 PM PDT 24
Finished Jun 27 04:51:00 PM PDT 24
Peak memory 293856 kb
Host smart-2524c24f-4a9b-44e1-a2ce-323d4fb05299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847428985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.847428985
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3515215386
Short name T76
Test name
Test status
Simulation time 17505805131 ps
CPU time 2148.15 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 05:26:43 PM PDT 24
Peak memory 3392632 kb
Host smart-7f4a7d51-cd74-42f5-9e8c-ee4ec4ced854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515215386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3515215386
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.698550209
Short name T926
Test name
Test status
Simulation time 1541946215 ps
CPU time 32.63 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:51:25 PM PDT 24
Peak memory 212956 kb
Host smart-e9210468-9ed1-4e05-bbba-41f2bb93a331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698550209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.698550209
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.4229927820
Short name T1225
Test name
Test status
Simulation time 1358447502 ps
CPU time 6.8 seconds
Started Jun 27 04:50:58 PM PDT 24
Finished Jun 27 04:51:09 PM PDT 24
Peak memory 216736 kb
Host smart-9510413e-3acf-435e-b817-3486ce311187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229927820 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.4229927820
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3385341294
Short name T1131
Test name
Test status
Simulation time 200630602 ps
CPU time 1.24 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:51:01 PM PDT 24
Peak memory 204516 kb
Host smart-477c211d-b4d6-4be8-98ad-5526b26c71a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385341294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3385341294
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.61893559
Short name T1243
Test name
Test status
Simulation time 223410845 ps
CPU time 1.15 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:50:57 PM PDT 24
Peak memory 204620 kb
Host smart-d2b97638-c698-4ee8-ab3d-619614cb2a33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61893559 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.i2c_target_fifo_reset_tx.61893559
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.788409379
Short name T4
Test name
Test status
Simulation time 1893505984 ps
CPU time 2.47 seconds
Started Jun 27 04:50:59 PM PDT 24
Finished Jun 27 04:51:05 PM PDT 24
Peak memory 204856 kb
Host smart-3b4ac3eb-85f6-42e5-9d36-e6eeaad5b863
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788409379 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.788409379
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.612072073
Short name T177
Test name
Test status
Simulation time 164355290 ps
CPU time 0.96 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:50:57 PM PDT 24
Peak memory 204648 kb
Host smart-5abf34b3-5a07-4b6c-b915-719e83982787
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612072073 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.612072073
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1116042112
Short name T1125
Test name
Test status
Simulation time 430770286 ps
CPU time 3.68 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 204880 kb
Host smart-8c588881-3c05-4e1f-9e6a-81b8140d11b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116042112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1116042112
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.1625536800
Short name T297
Test name
Test status
Simulation time 1709775780 ps
CPU time 4.46 seconds
Started Jun 27 04:50:57 PM PDT 24
Finished Jun 27 04:51:06 PM PDT 24
Peak memory 205192 kb
Host smart-a179442a-a121-47fe-80d7-e0349beb0532
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625536800 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.1625536800
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.2150864114
Short name T1466
Test name
Test status
Simulation time 10064971786 ps
CPU time 7.95 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:51:02 PM PDT 24
Peak memory 219636 kb
Host smart-98c88909-6ce5-4e43-9f69-a0d7d0acc2e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150864114 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.2150864114
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1069006562
Short name T699
Test name
Test status
Simulation time 1957455839 ps
CPU time 34.97 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:51:29 PM PDT 24
Peak memory 204844 kb
Host smart-aff4d029-2549-4aff-90d0-83019781179f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069006562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1069006562
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.2486083260
Short name T1475
Test name
Test status
Simulation time 2819610464 ps
CPU time 12.36 seconds
Started Jun 27 04:50:45 PM PDT 24
Finished Jun 27 04:50:59 PM PDT 24
Peak memory 204916 kb
Host smart-d46ffa27-5794-4e69-af92-c16804b510c8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486083260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.2486083260
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.1571481879
Short name T478
Test name
Test status
Simulation time 14355727730 ps
CPU time 8.32 seconds
Started Jun 27 04:50:52 PM PDT 24
Finished Jun 27 04:51:02 PM PDT 24
Peak memory 204888 kb
Host smart-c077461d-b492-4ea4-adb4-2bdeb150d467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571481879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.1571481879
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.2650558755
Short name T1210
Test name
Test status
Simulation time 15833020602 ps
CPU time 87.32 seconds
Started Jun 27 04:50:54 PM PDT 24
Finished Jun 27 04:52:25 PM PDT 24
Peak memory 1005744 kb
Host smart-f7269f88-8f37-450b-b8d9-2a9bc4a5c739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650558755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.2650558755
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.2987304183
Short name T791
Test name
Test status
Simulation time 1337125487 ps
CPU time 6.95 seconds
Started Jun 27 04:50:57 PM PDT 24
Finished Jun 27 04:51:09 PM PDT 24
Peak memory 212972 kb
Host smart-5cefd568-751f-4888-b88b-e178e28bf2e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987304183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.2987304183
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_alert_test.2209772733
Short name T947
Test name
Test status
Simulation time 16528092 ps
CPU time 0.64 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204396 kb
Host smart-03543413-a435-481e-b03e-4bf1e54efad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209772733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.2209772733
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2598014470
Short name T482
Test name
Test status
Simulation time 1037475329 ps
CPU time 2.96 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:16 PM PDT 24
Peak memory 233744 kb
Host smart-aab1c8af-81a9-4782-ac2e-b4de3a8308da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598014470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2598014470
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2482360624
Short name T579
Test name
Test status
Simulation time 296008064 ps
CPU time 6.47 seconds
Started Jun 27 04:50:47 PM PDT 24
Finished Jun 27 04:50:55 PM PDT 24
Peak memory 263396 kb
Host smart-227fba6b-1998-4f36-be2f-42d0cfa0ff6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482360624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2482360624
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.4184628630
Short name T744
Test name
Test status
Simulation time 1941252451 ps
CPU time 63.32 seconds
Started Jun 27 04:50:59 PM PDT 24
Finished Jun 27 04:52:06 PM PDT 24
Peak memory 662368 kb
Host smart-25c9616e-418b-431c-80ec-90bd656ff35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184628630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.4184628630
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3405154280
Short name T1080
Test name
Test status
Simulation time 3898341584 ps
CPU time 57.97 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 680932 kb
Host smart-8275be1d-0400-4d34-8b57-07f80e9ae16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405154280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3405154280
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.3067663547
Short name T1282
Test name
Test status
Simulation time 75916008 ps
CPU time 0.81 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:51:01 PM PDT 24
Peak memory 204448 kb
Host smart-1020cf8b-6447-45ae-8849-5c1733d40fd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067663547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.3067663547
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3989516982
Short name T1252
Test name
Test status
Simulation time 680513367 ps
CPU time 5.69 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:51:03 PM PDT 24
Peak memory 242984 kb
Host smart-a41f6079-965b-4eb9-8106-18f0e6753ee0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989516982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3989516982
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.2675073212
Short name T841
Test name
Test status
Simulation time 14233237722 ps
CPU time 225.54 seconds
Started Jun 27 04:50:56 PM PDT 24
Finished Jun 27 04:54:46 PM PDT 24
Peak memory 1056568 kb
Host smart-2b46c80b-5549-4f51-a59c-910180ec937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675073212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.2675073212
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.2174355095
Short name T795
Test name
Test status
Simulation time 1279164616 ps
CPU time 7.33 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204732 kb
Host smart-41de737c-80dc-403f-bf1f-e308d48965ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174355095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.2174355095
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.2386351780
Short name T1470
Test name
Test status
Simulation time 4343200372 ps
CPU time 41.31 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 401504 kb
Host smart-6a42dd88-42c3-4a31-8d27-6d691d029f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386351780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.2386351780
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.2202308850
Short name T362
Test name
Test status
Simulation time 94861371 ps
CPU time 0.7 seconds
Started Jun 27 04:50:53 PM PDT 24
Finished Jun 27 04:50:57 PM PDT 24
Peak memory 204580 kb
Host smart-61b3edab-0e76-465d-adbc-152d2698497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202308850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.2202308850
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.2627897946
Short name T621
Test name
Test status
Simulation time 8097378543 ps
CPU time 18.54 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:51:18 PM PDT 24
Peak memory 279752 kb
Host smart-fa5d34f6-4f8f-4f26-8dc4-76d63100b0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627897946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.2627897946
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.2929428381
Short name T1101
Test name
Test status
Simulation time 2578555361 ps
CPU time 8.84 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:51:01 PM PDT 24
Peak memory 222412 kb
Host smart-aac258ec-90b1-47b7-922d-71574502f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929428381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2929428381
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.3281594568
Short name T801
Test name
Test status
Simulation time 5910667331 ps
CPU time 27.03 seconds
Started Jun 27 04:50:55 PM PDT 24
Finished Jun 27 04:51:26 PM PDT 24
Peak memory 335316 kb
Host smart-92e7f7c7-4fe5-455f-84f4-b51b6d33df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281594568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.3281594568
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3047162776
Short name T985
Test name
Test status
Simulation time 5703305154 ps
CPU time 40.48 seconds
Started Jun 27 04:50:51 PM PDT 24
Finished Jun 27 04:51:33 PM PDT 24
Peak memory 213608 kb
Host smart-ecab0359-b063-4760-8102-72eacc97cd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047162776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3047162776
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3927362540
Short name T1016
Test name
Test status
Simulation time 1092436463 ps
CPU time 2.88 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:18 PM PDT 24
Peak memory 204840 kb
Host smart-fbd691df-b45c-4f64-8108-30d050dabc71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927362540 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3927362540
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.452170707
Short name T1174
Test name
Test status
Simulation time 144079660 ps
CPU time 0.76 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:21 PM PDT 24
Peak memory 204548 kb
Host smart-3aed0674-52c8-4902-af9f-ac4f9c78c754
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452170707 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.452170707
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.208706210
Short name T1311
Test name
Test status
Simulation time 183425826 ps
CPU time 1.2 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:17 PM PDT 24
Peak memory 215752 kb
Host smart-16e54024-bd07-4a71-9e72-71e12a753a05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208706210 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.i2c_target_fifo_reset_tx.208706210
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2245423008
Short name T896
Test name
Test status
Simulation time 1041543736 ps
CPU time 1.68 seconds
Started Jun 27 04:51:09 PM PDT 24
Finished Jun 27 04:51:12 PM PDT 24
Peak memory 204720 kb
Host smart-37ec3d28-0665-4255-a46e-3d117e4405ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245423008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2245423008
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.4050743646
Short name T1374
Test name
Test status
Simulation time 144956691 ps
CPU time 1.22 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:22 PM PDT 24
Peak memory 204580 kb
Host smart-8d9eb0f9-8194-47f9-9438-28bdce0cc0aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050743646 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.4050743646
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.3951634095
Short name T908
Test name
Test status
Simulation time 847854067 ps
CPU time 3.12 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:16 PM PDT 24
Peak memory 204792 kb
Host smart-1c98ea32-b933-4121-a8d7-e06363a45869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951634095 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.3951634095
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.3358302703
Short name T513
Test name
Test status
Simulation time 879188285 ps
CPU time 5.35 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:21 PM PDT 24
Peak memory 217704 kb
Host smart-0ee4bdc5-7767-488c-a4b2-b212789e5909
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358302703 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.3358302703
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.1103481629
Short name T950
Test name
Test status
Simulation time 11942276507 ps
CPU time 80.39 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 1338108 kb
Host smart-1bc6f77e-604e-4073-b083-2f338a5c77d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103481629 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.1103481629
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.747827565
Short name T181
Test name
Test status
Simulation time 1206336669 ps
CPU time 14.62 seconds
Started Jun 27 04:51:08 PM PDT 24
Finished Jun 27 04:51:23 PM PDT 24
Peak memory 204832 kb
Host smart-c3c69723-08cd-405f-8851-515170eda131
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747827565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_tar
get_smoke.747827565
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3740676249
Short name T1405
Test name
Test status
Simulation time 1956647551 ps
CPU time 16.09 seconds
Started Jun 27 04:51:07 PM PDT 24
Finished Jun 27 04:51:24 PM PDT 24
Peak memory 210412 kb
Host smart-441a9250-d252-49ca-a531-f7ffabccbe18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740676249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3740676249
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.2286092737
Short name T900
Test name
Test status
Simulation time 16929059237 ps
CPU time 15.68 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:28 PM PDT 24
Peak memory 204884 kb
Host smart-f2277353-c0f9-4e86-8f17-2ae041bf4120
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286092737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.2286092737
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.297167269
Short name T163
Test name
Test status
Simulation time 37471131107 ps
CPU time 163.18 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:54:09 PM PDT 24
Peak memory 1639608 kb
Host smart-5feea348-3f0a-48e7-b271-14e4ed7ade7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297167269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_t
arget_stretch.297167269
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3026442278
Short name T503
Test name
Test status
Simulation time 21057151469 ps
CPU time 5.95 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:18 PM PDT 24
Peak memory 205332 kb
Host smart-e813c31c-ef06-43ba-90d8-a3b21058a666
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026442278 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3026442278
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_alert_test.831197315
Short name T449
Test name
Test status
Simulation time 54488778 ps
CPU time 0.64 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:16 PM PDT 24
Peak memory 204364 kb
Host smart-32699c66-3466-4d5f-bdfa-f5d043dad5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831197315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.831197315
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.1194741019
Short name T486
Test name
Test status
Simulation time 141947290 ps
CPU time 1.77 seconds
Started Jun 27 04:51:09 PM PDT 24
Finished Jun 27 04:51:12 PM PDT 24
Peak memory 221236 kb
Host smart-febae7de-d446-4bfb-a7ec-53bedbb07410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194741019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.1194741019
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2843825569
Short name T359
Test name
Test status
Simulation time 822564805 ps
CPU time 3.91 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:22 PM PDT 24
Peak memory 247540 kb
Host smart-7ebc61ca-406f-4c53-8ae3-5591bc49335a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843825569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2843825569
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3892448811
Short name T876
Test name
Test status
Simulation time 10885067699 ps
CPU time 90.96 seconds
Started Jun 27 04:51:09 PM PDT 24
Finished Jun 27 04:52:41 PM PDT 24
Peak memory 766128 kb
Host smart-c26ed18b-462e-4f51-adbf-281bd3987a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892448811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3892448811
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.3458627192
Short name T842
Test name
Test status
Simulation time 22437377145 ps
CPU time 65.06 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:52:18 PM PDT 24
Peak memory 713536 kb
Host smart-cede858b-3b33-46a6-8226-f08a3746499f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458627192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.3458627192
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2890560798
Short name T1421
Test name
Test status
Simulation time 135754038 ps
CPU time 1.08 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:15 PM PDT 24
Peak memory 204748 kb
Host smart-1ad44317-f937-455a-ac36-f1749e1a627e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890560798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2890560798
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.894861849
Short name T1073
Test name
Test status
Simulation time 820495722 ps
CPU time 4.35 seconds
Started Jun 27 04:51:08 PM PDT 24
Finished Jun 27 04:51:14 PM PDT 24
Peak memory 204804 kb
Host smart-115e12fa-d281-46ba-a91d-da39469f789f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894861849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
894861849
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.3149291716
Short name T314
Test name
Test status
Simulation time 16047900177 ps
CPU time 105.36 seconds
Started Jun 27 04:51:08 PM PDT 24
Finished Jun 27 04:52:54 PM PDT 24
Peak memory 1073372 kb
Host smart-b908caed-d422-4d38-a937-b71e818d51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149291716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.3149291716
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.4161356109
Short name T1323
Test name
Test status
Simulation time 1313841558 ps
CPU time 13.52 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:34 PM PDT 24
Peak memory 204812 kb
Host smart-a5087da6-4932-475d-ac08-b6f93a5e74b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161356109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.4161356109
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.749913037
Short name T384
Test name
Test status
Simulation time 5553094655 ps
CPU time 19.8 seconds
Started Jun 27 04:51:15 PM PDT 24
Finished Jun 27 04:51:42 PM PDT 24
Peak memory 331584 kb
Host smart-a8f05df1-6f93-4ad1-9b09-a0023b4def3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749913037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.749913037
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.2199796479
Short name T1452
Test name
Test status
Simulation time 95815442 ps
CPU time 0.73 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:20 PM PDT 24
Peak memory 204512 kb
Host smart-32186efd-3276-4f46-abc9-a2131e0f3d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199796479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.2199796479
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.1282880289
Short name T925
Test name
Test status
Simulation time 29666781044 ps
CPU time 1098.24 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 05:09:32 PM PDT 24
Peak memory 217060 kb
Host smart-cb673740-ff97-406a-9b1b-98b8d4699880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282880289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.1282880289
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.2802248028
Short name T760
Test name
Test status
Simulation time 649989782 ps
CPU time 7.71 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:51:34 PM PDT 24
Peak memory 233180 kb
Host smart-47e5bb75-3ff8-4baa-8ebc-2eaa43477337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802248028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.2802248028
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1662929488
Short name T302
Test name
Test status
Simulation time 2094511049 ps
CPU time 96.38 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:52:49 PM PDT 24
Peak memory 364668 kb
Host smart-d4675784-fe44-4784-8f65-e1bc27362d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662929488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1662929488
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2325474265
Short name T392
Test name
Test status
Simulation time 3449639377 ps
CPU time 37.45 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:52:02 PM PDT 24
Peak memory 213600 kb
Host smart-67d81f46-8158-43d4-9fee-cddb99eeaeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325474265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2325474265
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.2067899438
Short name T620
Test name
Test status
Simulation time 1740918677 ps
CPU time 4.73 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:17 PM PDT 24
Peak memory 206664 kb
Host smart-70d81094-a144-4407-bc4e-505d0f25abd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067899438 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.2067899438
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.1758466387
Short name T796
Test name
Test status
Simulation time 623194220 ps
CPU time 1.39 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:15 PM PDT 24
Peak memory 204800 kb
Host smart-d40ee062-4daf-42ce-b72c-70e87d634a89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758466387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.1758466387
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3417255055
Short name T444
Test name
Test status
Simulation time 621026244 ps
CPU time 1.27 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:14 PM PDT 24
Peak memory 213940 kb
Host smart-97dd58f4-b832-4f8a-8bc6-240bb5aab8ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417255055 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3417255055
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.3321608994
Short name T1319
Test name
Test status
Simulation time 516749701 ps
CPU time 2.62 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:23 PM PDT 24
Peak memory 204828 kb
Host smart-2f6167d5-de51-493d-858b-569fb9ace911
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321608994 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.3321608994
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.3012851631
Short name T805
Test name
Test status
Simulation time 625707957 ps
CPU time 1.34 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:21 PM PDT 24
Peak memory 204528 kb
Host smart-4c8ba34c-d192-4f20-a0ca-4e898da99076
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012851631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.3012851631
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.2966247567
Short name T572
Test name
Test status
Simulation time 895089128 ps
CPU time 4.44 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204708 kb
Host smart-32920c3c-8ba4-42cc-bd41-14cccde953b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966247567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.2966247567
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1423255902
Short name T331
Test name
Test status
Simulation time 4544137337 ps
CPU time 6.46 seconds
Started Jun 27 04:51:08 PM PDT 24
Finished Jun 27 04:51:16 PM PDT 24
Peak memory 213196 kb
Host smart-7e1eb999-52bb-4ecb-9775-8cf48a2be707
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423255902 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1423255902
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.4109746020
Short name T1215
Test name
Test status
Simulation time 16529080649 ps
CPU time 209.09 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:54:56 PM PDT 24
Peak memory 2514916 kb
Host smart-a780e774-1cb5-43f0-bbad-705ae0adad41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109746020 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.4109746020
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.2884025147
Short name T1149
Test name
Test status
Simulation time 446154031 ps
CPU time 13.7 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 204844 kb
Host smart-e1ec6a66-70b6-4139-bd50-2d9eb4706549
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884025147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.2884025147
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.832070564
Short name T1382
Test name
Test status
Simulation time 1168351570 ps
CPU time 18.84 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:34 PM PDT 24
Peak memory 230468 kb
Host smart-7ece60c5-2521-4146-9840-40798f0d3cbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832070564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.832070564
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1863590763
Short name T948
Test name
Test status
Simulation time 11654819392 ps
CPU time 6.46 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 204864 kb
Host smart-dc317499-645d-4bf2-b905-ff8270422990
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863590763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1863590763
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.2230990345
Short name T836
Test name
Test status
Simulation time 2467752379 ps
CPU time 7.12 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:20 PM PDT 24
Peak memory 219408 kb
Host smart-fd2282aa-bca6-4f3f-84bc-bf4963773fae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230990345 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.2230990345
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_alert_test.1278985400
Short name T905
Test name
Test status
Simulation time 17664772 ps
CPU time 0.63 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204388 kb
Host smart-5df57d94-0102-4561-8e6e-23278f70d929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278985400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.1278985400
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.3363587559
Short name T447
Test name
Test status
Simulation time 94187187 ps
CPU time 3.17 seconds
Started Jun 27 04:51:15 PM PDT 24
Finished Jun 27 04:51:26 PM PDT 24
Peak memory 213048 kb
Host smart-f6b99a62-7cc3-4dbd-85f3-2953d3f0fa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363587559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.3363587559
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.3840429925
Short name T973
Test name
Test status
Simulation time 221124483 ps
CPU time 10.4 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 243852 kb
Host smart-617bf687-aef6-4f87-8a08-863ada26a269
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840429925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.3840429925
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.374541618
Short name T1007
Test name
Test status
Simulation time 3798870929 ps
CPU time 51.05 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:52:11 PM PDT 24
Peak memory 481060 kb
Host smart-8c0ca9bb-240a-4acc-b033-ad60de97b3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374541618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.374541618
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1007614418
Short name T793
Test name
Test status
Simulation time 2414511008 ps
CPU time 82.69 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:52:42 PM PDT 24
Peak memory 771944 kb
Host smart-00e8de0a-2737-4840-8b3b-14c905e5aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007614418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1007614418
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.271794573
Short name T764
Test name
Test status
Simulation time 106195942 ps
CPU time 1.05 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204696 kb
Host smart-046a01a9-2b63-4834-861c-a74932ea6aa1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271794573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_fm
t.271794573
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.981400920
Short name T731
Test name
Test status
Simulation time 127273860 ps
CPU time 2.85 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:24 PM PDT 24
Peak memory 204832 kb
Host smart-cbaaffea-9691-4497-bb07-fe7e1746357f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981400920 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
981400920
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.2584952889
Short name T102
Test name
Test status
Simulation time 7721250345 ps
CPU time 95.13 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:52:56 PM PDT 24
Peak memory 1147504 kb
Host smart-6fb5208e-4006-4eee-85d1-0d33f938bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584952889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.2584952889
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.3149614847
Short name T1066
Test name
Test status
Simulation time 1480026191 ps
CPU time 5.24 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:20 PM PDT 24
Peak memory 204840 kb
Host smart-1a4f4732-3f1d-4397-9247-7796e4f95de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149614847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.3149614847
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.784653839
Short name T1100
Test name
Test status
Simulation time 19193385734 ps
CPU time 27.8 seconds
Started Jun 27 04:51:22 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 346888 kb
Host smart-a4c72ed3-d06f-4c82-928e-d7bd9b104979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784653839 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.784653839
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3925169272
Short name T844
Test name
Test status
Simulation time 28139948 ps
CPU time 0.69 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:12 PM PDT 24
Peak memory 204520 kb
Host smart-1b257978-58ef-4294-b605-09fd03cc6047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925169272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3925169272
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.3564332489
Short name T1332
Test name
Test status
Simulation time 12584408541 ps
CPU time 259.98 seconds
Started Jun 27 04:51:15 PM PDT 24
Finished Jun 27 04:55:44 PM PDT 24
Peak memory 1332620 kb
Host smart-0cfa53a3-dc8e-4a72-9a0e-a23977518ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564332489 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.3564332489
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.1112626666
Short name T355
Test name
Test status
Simulation time 143564079 ps
CPU time 1.18 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:23 PM PDT 24
Peak memory 226300 kb
Host smart-0bbf2d32-01eb-429e-8020-efcaba6a57d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112626666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.1112626666
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.2354503238
Short name T762
Test name
Test status
Simulation time 27858456046 ps
CPU time 39.52 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 433916 kb
Host smart-63590a4c-361a-4594-94d1-3f1a42de5956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354503238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.2354503238
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.2047037158
Short name T272
Test name
Test status
Simulation time 19287814305 ps
CPU time 346.34 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:57:15 PM PDT 24
Peak memory 824372 kb
Host smart-cff84a8c-72be-4bf3-b508-77ec0b7b7521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047037158 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2047037158
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.1265888656
Short name T550
Test name
Test status
Simulation time 4425783582 ps
CPU time 11.85 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:34 PM PDT 24
Peak memory 229448 kb
Host smart-0804b4a0-b0fa-48f5-92c9-b56bdad84260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265888656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.1265888656
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.3255630526
Short name T12
Test name
Test status
Simulation time 786950367 ps
CPU time 3.65 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:51:30 PM PDT 24
Peak memory 213072 kb
Host smart-627e56b6-c28b-4396-a224-196ad22ba0b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255630526 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.3255630526
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.919720263
Short name T453
Test name
Test status
Simulation time 754721990 ps
CPU time 1.38 seconds
Started Jun 27 04:51:37 PM PDT 24
Finished Jun 27 04:51:40 PM PDT 24
Peak memory 207224 kb
Host smart-544d571d-b644-4577-9d5a-08e35cc063ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919720263 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.i2c_target_fifo_reset_tx.919720263
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.1016793819
Short name T994
Test name
Test status
Simulation time 285748195 ps
CPU time 1.78 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:36 PM PDT 24
Peak memory 204620 kb
Host smart-363c2ec0-e6d7-4d22-88fc-3294ce481e79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016793819 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.1016793819
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.1672274282
Short name T910
Test name
Test status
Simulation time 126228818 ps
CPU time 1.15 seconds
Started Jun 27 04:51:19 PM PDT 24
Finished Jun 27 04:51:29 PM PDT 24
Peak memory 204444 kb
Host smart-b66a88cc-3720-4455-9091-01366ecfb721
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672274282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.1672274282
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2312282508
Short name T721
Test name
Test status
Simulation time 3609099776 ps
CPU time 4.17 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:51:29 PM PDT 24
Peak memory 204896 kb
Host smart-3e9b502d-f027-4106-b1ae-0675e8e94fdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312282508 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2312282508
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2311699551
Short name T316
Test name
Test status
Simulation time 11754452755 ps
CPU time 27.13 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:51:53 PM PDT 24
Peak memory 640784 kb
Host smart-9f451fdd-d187-4bb1-965b-32db30069d15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311699551 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2311699551
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.153156444
Short name T763
Test name
Test status
Simulation time 2449542296 ps
CPU time 19.64 seconds
Started Jun 27 04:51:19 PM PDT 24
Finished Jun 27 04:51:48 PM PDT 24
Peak memory 204836 kb
Host smart-54b64f06-0eed-4220-8380-e63ab69d302e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153156444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.153156444
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.2017364304
Short name T1286
Test name
Test status
Simulation time 23069682235 ps
CPU time 58.92 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:52:24 PM PDT 24
Peak memory 211308 kb
Host smart-50f94760-2a95-410a-9fa7-b3ca50463bbb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017364304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.2017364304
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2908312757
Short name T775
Test name
Test status
Simulation time 7441008792 ps
CPU time 4.86 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:26 PM PDT 24
Peak memory 204836 kb
Host smart-e3210574-1a98-40da-95c5-d02818445836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908312757 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2908312757
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1078846979
Short name T115
Test name
Test status
Simulation time 15701767990 ps
CPU time 450.53 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:58:45 PM PDT 24
Peak memory 3015676 kb
Host smart-b056fb36-868b-4cd7-9479-7a203c07f279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078846979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1078846979
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1873065506
Short name T577
Test name
Test status
Simulation time 5230993894 ps
CPU time 6.42 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:51:33 PM PDT 24
Peak memory 213156 kb
Host smart-878ccf1e-bb82-4aaf-99eb-349973cd7bdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873065506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1873065506
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3443912423
Short name T1097
Test name
Test status
Simulation time 16610859 ps
CPU time 0.62 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:07 PM PDT 24
Peak memory 204428 kb
Host smart-bd2d6f4f-d656-4662-b9b7-51a086e51d41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443912423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3443912423
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.319119438
Short name T1461
Test name
Test status
Simulation time 1031981345 ps
CPU time 2.18 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:49:34 PM PDT 24
Peak memory 222432 kb
Host smart-2ced33ef-bd5f-46de-b7cd-8cb38e8acf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319119438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.319119438
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1180177018
Short name T1092
Test name
Test status
Simulation time 552099399 ps
CPU time 7.26 seconds
Started Jun 27 04:49:01 PM PDT 24
Finished Jun 27 04:49:10 PM PDT 24
Peak memory 294080 kb
Host smart-d90c4c2a-cc9f-47c3-8ea5-bc4594d4043e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180177018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1180177018
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.3136397802
Short name T671
Test name
Test status
Simulation time 2797143960 ps
CPU time 95.03 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:51:06 PM PDT 24
Peak memory 862352 kb
Host smart-02bdbd6b-aab5-40a4-ba48-e21418d0a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136397802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.3136397802
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.2207961308
Short name T879
Test name
Test status
Simulation time 10527362229 ps
CPU time 73.77 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:50:28 PM PDT 24
Peak memory 767132 kb
Host smart-194505e9-ed96-441b-8fc5-452b6c174e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207961308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.2207961308
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1487953038
Short name T1303
Test name
Test status
Simulation time 82615818 ps
CPU time 0.9 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 204564 kb
Host smart-84350b81-ca6a-42d8-96e7-911e27c91ed4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487953038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1487953038
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.1321315000
Short name T1238
Test name
Test status
Simulation time 883631310 ps
CPU time 5.21 seconds
Started Jun 27 04:48:57 PM PDT 24
Finished Jun 27 04:49:05 PM PDT 24
Peak memory 204840 kb
Host smart-ade6febb-d277-4df4-b158-e586b8d27b39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321315000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
1321315000
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.1890007976
Short name T1096
Test name
Test status
Simulation time 17791248338 ps
CPU time 98.07 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:50:49 PM PDT 24
Peak memory 1216188 kb
Host smart-8f44f11f-15a6-42aa-b6bd-5d9d65adf72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890007976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.1890007976
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.473300632
Short name T1249
Test name
Test status
Simulation time 1002903245 ps
CPU time 18.99 seconds
Started Jun 27 04:48:58 PM PDT 24
Finished Jun 27 04:49:19 PM PDT 24
Peak memory 204712 kb
Host smart-bb6fce28-e032-4b63-83e7-4f1c482075f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473300632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.473300632
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3111410192
Short name T1062
Test name
Test status
Simulation time 22106477062 ps
CPU time 70.19 seconds
Started Jun 27 04:49:19 PM PDT 24
Finished Jun 27 04:50:39 PM PDT 24
Peak memory 374428 kb
Host smart-718324b9-152f-449c-a539-d60539fb3105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111410192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3111410192
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.2441988549
Short name T1229
Test name
Test status
Simulation time 301671553 ps
CPU time 0.68 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:09 PM PDT 24
Peak memory 204472 kb
Host smart-4dc18a9b-4985-4b1a-a007-e7140a2c3591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441988549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.2441988549
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.1733464726
Short name T1157
Test name
Test status
Simulation time 7588056320 ps
CPU time 243.77 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:53:18 PM PDT 24
Peak memory 1467904 kb
Host smart-a71c3122-c26d-4c1e-ace8-948520f26586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733464726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.1733464726
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.1136676077
Short name T1236
Test name
Test status
Simulation time 6053184433 ps
CPU time 244.75 seconds
Started Jun 27 04:49:34 PM PDT 24
Finished Jun 27 04:53:44 PM PDT 24
Peak memory 1540168 kb
Host smart-51eb2989-5045-478d-9112-31a91a24eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136676077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.1136676077
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.994296929
Short name T488
Test name
Test status
Simulation time 2766615335 ps
CPU time 24.4 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:42 PM PDT 24
Peak memory 326364 kb
Host smart-46de0280-940c-4064-b6d3-0fa613772c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994296929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.994296929
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3256039940
Short name T296
Test name
Test status
Simulation time 3599754721 ps
CPU time 15.02 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:46 PM PDT 24
Peak memory 215328 kb
Host smart-456ff298-8d84-4ddd-beb8-e1b8c449413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256039940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3256039940
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2546591563
Short name T194
Test name
Test status
Simulation time 199780372 ps
CPU time 0.82 seconds
Started Jun 27 04:48:54 PM PDT 24
Finished Jun 27 04:48:58 PM PDT 24
Peak memory 222168 kb
Host smart-8d178b3d-8bab-4ac8-bce2-478f3ed3f4e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546591563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2546591563
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.2414085294
Short name T1055
Test name
Test status
Simulation time 533798087 ps
CPU time 2.9 seconds
Started Jun 27 04:49:02 PM PDT 24
Finished Jun 27 04:49:06 PM PDT 24
Peak memory 204768 kb
Host smart-1e2d6fb9-b6b5-41b3-9622-45e9daff734a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414085294 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.2414085294
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.1405386893
Short name T834
Test name
Test status
Simulation time 567085345 ps
CPU time 1.21 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 205416 kb
Host smart-d22f3d2a-943c-44ef-aba5-81b7618348ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405386893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.1405386893
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2111486581
Short name T523
Test name
Test status
Simulation time 255032527 ps
CPU time 1.06 seconds
Started Jun 27 04:49:03 PM PDT 24
Finished Jun 27 04:49:07 PM PDT 24
Peak memory 204596 kb
Host smart-7b39a2e8-6b29-4efd-9074-3036445f69f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111486581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2111486581
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.3637297849
Short name T258
Test name
Test status
Simulation time 497226965 ps
CPU time 2.62 seconds
Started Jun 27 04:49:21 PM PDT 24
Finished Jun 27 04:49:32 PM PDT 24
Peak memory 204680 kb
Host smart-51e15539-19c4-4e47-a598-5c8a99537aa3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637297849 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.3637297849
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.1660844565
Short name T1111
Test name
Test status
Simulation time 177338246 ps
CPU time 1.33 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:17 PM PDT 24
Peak memory 204616 kb
Host smart-2ccc3bc0-ebb3-4189-8a40-4d6264717714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660844565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1660844565
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.3356383480
Short name T1144
Test name
Test status
Simulation time 13178240337 ps
CPU time 4.48 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:25 PM PDT 24
Peak memory 218104 kb
Host smart-45abc0e0-9160-4e56-9794-f2b39b3029d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356383480 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.3356383480
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.3738755228
Short name T1130
Test name
Test status
Simulation time 21422353454 ps
CPU time 393.66 seconds
Started Jun 27 04:48:49 PM PDT 24
Finished Jun 27 04:55:25 PM PDT 24
Peak memory 4978268 kb
Host smart-b9883698-0a0f-4ec9-a5d4-330883e82963
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738755228 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.3738755228
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2039635646
Short name T1168
Test name
Test status
Simulation time 3681552425 ps
CPU time 25.59 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:49:55 PM PDT 24
Peak memory 204956 kb
Host smart-de8b9cd4-1e2a-4973-9c25-d3969139f786
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039635646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2039635646
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.3888419616
Short name T923
Test name
Test status
Simulation time 877844723 ps
CPU time 6.54 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:17 PM PDT 24
Peak memory 205024 kb
Host smart-28abba03-02c7-46ae-95b4-f6875040532f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888419616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.3888419616
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.2571691581
Short name T410
Test name
Test status
Simulation time 14680893627 ps
CPU time 30.12 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:47 PM PDT 24
Peak memory 204828 kb
Host smart-abd971c0-8516-4025-88fd-b212f1f6213c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571691581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.2571691581
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2320465045
Short name T740
Test name
Test status
Simulation time 10406129977 ps
CPU time 53.79 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 757184 kb
Host smart-35001f35-ba2e-4527-b3ae-17c585dbabd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320465045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2320465045
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.685207353
Short name T265
Test name
Test status
Simulation time 1209377142 ps
CPU time 5.83 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 212964 kb
Host smart-918be209-5d0f-4888-bde1-2a92f441bca4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685207353 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.685207353
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_alert_test.3531215126
Short name T874
Test name
Test status
Simulation time 19530521 ps
CPU time 0.63 seconds
Started Jun 27 04:51:19 PM PDT 24
Finished Jun 27 04:51:29 PM PDT 24
Peak memory 204476 kb
Host smart-fc3f6178-5898-406f-8776-ff44c6eaf493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531215126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.3531215126
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.3213982021
Short name T50
Test name
Test status
Simulation time 521718363 ps
CPU time 4.28 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:51:30 PM PDT 24
Peak memory 213092 kb
Host smart-2350f1c4-1083-4e91-951f-e99a950848da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213982021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.3213982021
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1934504775
Short name T1416
Test name
Test status
Simulation time 306655938 ps
CPU time 5.42 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:34 PM PDT 24
Peak memory 265056 kb
Host smart-0351fab1-a3e2-46fa-8c11-48fbb5f48247
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934504775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1934504775
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.1382293337
Short name T167
Test name
Test status
Simulation time 2214298426 ps
CPU time 151.06 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:53:51 PM PDT 24
Peak memory 682452 kb
Host smart-3fd353f8-baad-4cf4-9bdb-5c1462b29a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382293337 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.1382293337
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.2412805946
Short name T678
Test name
Test status
Simulation time 2108596999 ps
CPU time 126.77 seconds
Started Jun 27 04:51:25 PM PDT 24
Finished Jun 27 04:53:39 PM PDT 24
Peak memory 581196 kb
Host smart-11a42600-337e-4325-8f26-27ced8e33ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412805946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.2412805946
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.3849864191
Short name T748
Test name
Test status
Simulation time 206192107 ps
CPU time 0.9 seconds
Started Jun 27 04:51:24 PM PDT 24
Finished Jun 27 04:51:32 PM PDT 24
Peak memory 204504 kb
Host smart-95e45517-9b76-41f7-a46b-73f02cf55633
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849864191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.3849864191
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.1998729211
Short name T521
Test name
Test status
Simulation time 215978820 ps
CPU time 5.93 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:34 PM PDT 24
Peak memory 245596 kb
Host smart-53bde6d6-292e-4ce6-81bc-cf156e6ca8e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998729211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.1998729211
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2697209564
Short name T48
Test name
Test status
Simulation time 215722664 ps
CPU time 3.54 seconds
Started Jun 27 04:51:25 PM PDT 24
Finished Jun 27 04:51:35 PM PDT 24
Peak memory 204824 kb
Host smart-f87b16f1-7257-40d7-ab03-cce057700619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697209564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2697209564
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.1389379917
Short name T136
Test name
Test status
Simulation time 29562578 ps
CPU time 0.7 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204760 kb
Host smart-c065d481-f123-4d0c-a3f1-9729a972f8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389379917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1389379917
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.528447435
Short name T565
Test name
Test status
Simulation time 383151797 ps
CPU time 2.15 seconds
Started Jun 27 04:51:35 PM PDT 24
Finished Jun 27 04:51:40 PM PDT 24
Peak memory 229044 kb
Host smart-aafd7271-df8a-442c-a4c8-77f71d802229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528447435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.528447435
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.966861074
Short name T133
Test name
Test status
Simulation time 672425866 ps
CPU time 9.17 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:38 PM PDT 24
Peak memory 212948 kb
Host smart-fdac7c56-1e9f-4995-b019-c78bebc6a361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966861074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.966861074
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1485066950
Short name T321
Test name
Test status
Simulation time 1434841571 ps
CPU time 24.23 seconds
Started Jun 27 04:51:25 PM PDT 24
Finished Jun 27 04:51:56 PM PDT 24
Peak memory 285940 kb
Host smart-cc2654c6-6533-4615-8afc-f7e81c34709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485066950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1485066950
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.973208692
Short name T159
Test name
Test status
Simulation time 19716215707 ps
CPU time 399.65 seconds
Started Jun 27 04:51:19 PM PDT 24
Finished Jun 27 04:58:08 PM PDT 24
Peak memory 1229144 kb
Host smart-be3a14ac-bd81-4f85-8c4b-16189b4a8c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973208692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.973208692
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.3737001066
Short name T1315
Test name
Test status
Simulation time 3924492263 ps
CPU time 18.59 seconds
Started Jun 27 04:51:19 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 229440 kb
Host smart-e2f4ddd9-fe56-4c31-97ab-dcabbf9fc624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737001066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.3737001066
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.937599108
Short name T643
Test name
Test status
Simulation time 3336689471 ps
CPU time 3.73 seconds
Started Jun 27 04:51:15 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 213164 kb
Host smart-fd5dfcf9-3340-48db-b652-66802b1d2e76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937599108 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.937599108
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.352766431
Short name T1152
Test name
Test status
Simulation time 617922350 ps
CPU time 1.32 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:18 PM PDT 24
Peak memory 212932 kb
Host smart-1c3f6ecf-8389-4089-9447-e8a328c8997b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352766431 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_acq.352766431
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2067783498
Short name T927
Test name
Test status
Simulation time 273666270 ps
CPU time 1.56 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:22 PM PDT 24
Peak memory 204796 kb
Host smart-645f2d82-5088-4ec2-8223-fcaa944626ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067783498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2067783498
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.3495783441
Short name T112
Test name
Test status
Simulation time 406914582 ps
CPU time 2.09 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:31 PM PDT 24
Peak memory 204708 kb
Host smart-2fbef6a2-e720-4756-96cf-f640a2285e39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495783441 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.3495783441
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.1285905285
Short name T714
Test name
Test status
Simulation time 131070891 ps
CPU time 1.17 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:22 PM PDT 24
Peak memory 204528 kb
Host smart-02a6d5e4-5d4b-49b7-9a2e-15a38cbf1601
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285905285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.1285905285
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2797527300
Short name T1023
Test name
Test status
Simulation time 975616791 ps
CPU time 2.85 seconds
Started Jun 27 04:51:10 PM PDT 24
Finished Jun 27 04:51:16 PM PDT 24
Peak memory 204780 kb
Host smart-beccef52-5bb9-4a77-bb90-502c53c7b4eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797527300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2797527300
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2024863077
Short name T644
Test name
Test status
Simulation time 7100874620 ps
CPU time 4.88 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:25 PM PDT 24
Peak memory 220364 kb
Host smart-c70465ff-2773-416f-aa1d-22db616a31df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024863077 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2024863077
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1246968891
Short name T971
Test name
Test status
Simulation time 17472935485 ps
CPU time 300.82 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:56:17 PM PDT 24
Peak memory 4193872 kb
Host smart-c557369b-4f39-4273-90c6-6b33a01003f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246968891 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1246968891
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.450417952
Short name T169
Test name
Test status
Simulation time 4162240470 ps
CPU time 38.93 seconds
Started Jun 27 04:51:19 PM PDT 24
Finished Jun 27 04:52:07 PM PDT 24
Peak memory 204784 kb
Host smart-b8e20cfd-9aaa-49ca-92b1-07733f622818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450417952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.450417952
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3169458216
Short name T557
Test name
Test status
Simulation time 1478761928 ps
CPU time 59.26 seconds
Started Jun 27 04:51:15 PM PDT 24
Finished Jun 27 04:52:22 PM PDT 24
Peak memory 207864 kb
Host smart-a97c3a77-fdc5-412e-8424-9aafb891b5fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169458216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3169458216
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2697041872
Short name T350
Test name
Test status
Simulation time 66640269954 ps
CPU time 282.53 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:56:05 PM PDT 24
Peak memory 2894360 kb
Host smart-38ba5754-13c6-49ea-965e-969615009b69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697041872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2697041872
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.3522555209
Short name T1482
Test name
Test status
Simulation time 12611862884 ps
CPU time 161.28 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:54:06 PM PDT 24
Peak memory 811596 kb
Host smart-69d01ed7-ada0-4a9d-b946-f9fe7b1094df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522555209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.3522555209
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.1809826356
Short name T128
Test name
Test status
Simulation time 1393209777 ps
CPU time 7.39 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:51:34 PM PDT 24
Peak memory 220484 kb
Host smart-c02fbcb5-006f-4ec6-bc3d-87fa91376c12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809826356 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.1809826356
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3498236164
Short name T29
Test name
Test status
Simulation time 23647516 ps
CPU time 0.65 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:17 PM PDT 24
Peak memory 204404 kb
Host smart-a42a7064-3c8e-43ad-af03-9e32b8df4550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498236164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3498236164
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.3860420697
Short name T597
Test name
Test status
Simulation time 4183972035 ps
CPU time 5.05 seconds
Started Jun 27 04:51:35 PM PDT 24
Finished Jun 27 04:51:43 PM PDT 24
Peak memory 261808 kb
Host smart-d8a6c0b6-6342-4ef9-9b53-d30751592d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860420697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.3860420697
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2364844218
Short name T323
Test name
Test status
Simulation time 905837172 ps
CPU time 7.08 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:51:33 PM PDT 24
Peak memory 282448 kb
Host smart-e20f684e-890c-4951-ad05-0ac43674bd93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364844218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2364844218
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.3405164117
Short name T1301
Test name
Test status
Simulation time 2779505292 ps
CPU time 201.34 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:55:04 PM PDT 24
Peak memory 881420 kb
Host smart-ffdfb921-c474-4821-9951-02e8f44d44dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405164117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3405164117
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.871008979
Short name T1046
Test name
Test status
Simulation time 3294059870 ps
CPU time 53.61 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:52:20 PM PDT 24
Peak memory 624816 kb
Host smart-d99fee45-464b-41d9-a515-d5f80e666dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871008979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.871008979
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.731881823
Short name T1170
Test name
Test status
Simulation time 604286804 ps
CPU time 0.92 seconds
Started Jun 27 04:51:22 PM PDT 24
Finished Jun 27 04:51:31 PM PDT 24
Peak memory 204540 kb
Host smart-723d26e2-f50c-42d3-bf68-c7aff8a907e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731881823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_fm
t.731881823
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.2782535017
Short name T1273
Test name
Test status
Simulation time 861092689 ps
CPU time 4.01 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:51:48 PM PDT 24
Peak memory 204840 kb
Host smart-f79751ff-1a27-4c88-aff0-0bd57776a47e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782535017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.2782535017
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.4226091118
Short name T1297
Test name
Test status
Simulation time 23237322516 ps
CPU time 169.8 seconds
Started Jun 27 04:51:31 PM PDT 24
Finished Jun 27 04:54:25 PM PDT 24
Peak memory 1569944 kb
Host smart-ab426413-5075-4c2e-870e-3bad8bdd4941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226091118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.4226091118
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.4130721485
Short name T584
Test name
Test status
Simulation time 903319004 ps
CPU time 3.2 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:23 PM PDT 24
Peak memory 204772 kb
Host smart-39fa8394-d9f3-40ab-9953-da67f60f5377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130721485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.4130721485
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3884218912
Short name T256
Test name
Test status
Simulation time 12224063182 ps
CPU time 28.17 seconds
Started Jun 27 04:51:22 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 397428 kb
Host smart-8ff8436d-6587-4a9f-8627-1fd46a2c82c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884218912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3884218912
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1707953548
Short name T821
Test name
Test status
Simulation time 29746455 ps
CPU time 0.63 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:21 PM PDT 24
Peak memory 204492 kb
Host smart-94e3fafb-3ec8-428f-9ed8-8a3a0672d3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707953548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1707953548
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.3740916292
Short name T1264
Test name
Test status
Simulation time 20163870769 ps
CPU time 91.2 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:52:56 PM PDT 24
Peak memory 877564 kb
Host smart-a23a9dc0-0ef5-433a-83f6-60ca3e4f213a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740916292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.3740916292
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.3799009164
Short name T494
Test name
Test status
Simulation time 2526944620 ps
CPU time 91.91 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:52:51 PM PDT 24
Peak memory 205452 kb
Host smart-8ed2cb3b-1e2b-4d71-9fd1-28510e9cf8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799009164 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.3799009164
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.14456329
Short name T83
Test name
Test status
Simulation time 3617236934 ps
CPU time 79.76 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:52:44 PM PDT 24
Peak memory 337784 kb
Host smart-a7a4ea72-a3f8-453a-9f16-db82a4d17633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14456329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.14456329
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.1953313558
Short name T244
Test name
Test status
Simulation time 32580803980 ps
CPU time 642.11 seconds
Started Jun 27 04:51:24 PM PDT 24
Finished Jun 27 05:02:14 PM PDT 24
Peak memory 1860912 kb
Host smart-55b0ebac-2a20-4364-b7a3-a1ef42b7acc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953313558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1953313558
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.375490226
Short name T860
Test name
Test status
Simulation time 826301124 ps
CPU time 36.29 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:51:52 PM PDT 24
Peak memory 213056 kb
Host smart-134c835e-0590-464a-b995-8821fd4ebdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375490226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.375490226
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2345191439
Short name T943
Test name
Test status
Simulation time 3423000616 ps
CPU time 4.25 seconds
Started Jun 27 04:51:19 PM PDT 24
Finished Jun 27 04:51:32 PM PDT 24
Peak memory 213076 kb
Host smart-13a04e8b-db8a-4422-b977-8d243c5f6890
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345191439 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2345191439
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3965632815
Short name T178
Test name
Test status
Simulation time 431258371 ps
CPU time 0.97 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204644 kb
Host smart-63892c31-f749-4a23-a18a-e043d49ec4ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965632815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3965632815
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.1473448868
Short name T1443
Test name
Test status
Simulation time 297807541 ps
CPU time 0.84 seconds
Started Jun 27 04:51:38 PM PDT 24
Finished Jun 27 04:51:40 PM PDT 24
Peak memory 204516 kb
Host smart-1e190610-36c5-40e4-bce5-88a4534bd48d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473448868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.1473448868
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.1998165955
Short name T484
Test name
Test status
Simulation time 1642659608 ps
CPU time 2.17 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:51:28 PM PDT 24
Peak memory 204752 kb
Host smart-ae1f31c8-4d1a-4671-9a5e-18637a7d5a39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998165955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.1998165955
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.2062233827
Short name T691
Test name
Test status
Simulation time 362534155 ps
CPU time 0.97 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:51:26 PM PDT 24
Peak memory 204596 kb
Host smart-d4329154-7409-4d31-b477-04cc8572cc89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062233827 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.2062233827
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.2139318674
Short name T724
Test name
Test status
Simulation time 933503745 ps
CPU time 4.92 seconds
Started Jun 27 04:51:19 PM PDT 24
Finished Jun 27 04:51:33 PM PDT 24
Peak memory 212992 kb
Host smart-f064728e-a2d2-4436-a566-8d3c57b83619
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139318674 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.2139318674
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3212760118
Short name T164
Test name
Test status
Simulation time 6343027137 ps
CPU time 4.39 seconds
Started Jun 27 04:51:24 PM PDT 24
Finished Jun 27 04:51:35 PM PDT 24
Peak memory 204852 kb
Host smart-1bcc5738-2b44-42e0-9c26-1fd6db943613
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212760118 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3212760118
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.161284414
Short name T1347
Test name
Test status
Simulation time 940661577 ps
CPU time 14.68 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:44 PM PDT 24
Peak memory 204612 kb
Host smart-a5fe4f15-eda4-47b8-8cd1-a497df0783e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161284414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_tar
get_smoke.161284414
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.2623816257
Short name T1196
Test name
Test status
Simulation time 986201513 ps
CPU time 17.4 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 215520 kb
Host smart-ada541cb-171e-478a-bb6f-647ef841369c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623816257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.2623816257
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.642080193
Short name T346
Test name
Test status
Simulation time 48265472599 ps
CPU time 136.38 seconds
Started Jun 27 04:51:15 PM PDT 24
Finished Jun 27 04:53:40 PM PDT 24
Peak memory 1853780 kb
Host smart-2d15ebf0-31c3-4644-805a-a240bb6654f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642080193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c
_target_stress_wr.642080193
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2293285363
Short name T1064
Test name
Test status
Simulation time 12156446983 ps
CPU time 605.03 seconds
Started Jun 27 04:51:25 PM PDT 24
Finished Jun 27 05:01:36 PM PDT 24
Peak memory 3110356 kb
Host smart-7c54a94d-4690-4b9b-89db-6e7914f02cf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293285363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2293285363
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2692287436
Short name T895
Test name
Test status
Simulation time 1630424846 ps
CPU time 7.7 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:26 PM PDT 24
Peak memory 214308 kb
Host smart-af378acb-0be5-44bb-be93-eda869e690e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692287436 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2692287436
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1526187581
Short name T937
Test name
Test status
Simulation time 47413449 ps
CPU time 0.61 seconds
Started Jun 27 04:51:24 PM PDT 24
Finished Jun 27 04:51:31 PM PDT 24
Peak memory 204372 kb
Host smart-d34b3846-1e91-4bfe-a7a3-799202b98557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526187581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1526187581
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3580263791
Short name T1473
Test name
Test status
Simulation time 183167007 ps
CPU time 2.38 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 212556 kb
Host smart-64477202-2d69-4634-b86a-6aba55c556e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580263791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3580263791
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.3237149952
Short name T989
Test name
Test status
Simulation time 384405507 ps
CPU time 19.32 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:42 PM PDT 24
Peak memory 286236 kb
Host smart-4b553ef7-5c57-4aad-bc14-f480d46296e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237149952 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.3237149952
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.954405714
Short name T674
Test name
Test status
Simulation time 1609844910 ps
CPU time 42.64 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:52:03 PM PDT 24
Peak memory 597736 kb
Host smart-c92584b0-ef0a-4877-952b-715b6d884b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954405714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.954405714
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.21439184
Short name T1134
Test name
Test status
Simulation time 1627667202 ps
CPU time 45.28 seconds
Started Jun 27 04:51:17 PM PDT 24
Finished Jun 27 04:52:11 PM PDT 24
Peak memory 466836 kb
Host smart-97e9afc6-eaa2-4c1a-9d76-fc9148f29575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21439184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.21439184
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.1480059496
Short name T242
Test name
Test status
Simulation time 213239185 ps
CPU time 0.96 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:19 PM PDT 24
Peak memory 204452 kb
Host smart-8ee3ffa1-1a51-4c49-80ee-19d67278f4aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480059496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.1480059496
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.2676247090
Short name T1415
Test name
Test status
Simulation time 121156348 ps
CPU time 6.16 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:29 PM PDT 24
Peak memory 204812 kb
Host smart-b39f5940-ce02-4b13-b520-d04705d01e66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676247090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.2676247090
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.2357094820
Short name T461
Test name
Test status
Simulation time 9822156476 ps
CPU time 143.37 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:53:43 PM PDT 24
Peak memory 1334328 kb
Host smart-b4c36503-eaa5-4985-90b8-054854ceaa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357094820 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.2357094820
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.228464676
Short name T613
Test name
Test status
Simulation time 567188761 ps
CPU time 11.06 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 204572 kb
Host smart-bd676471-1f44-46ea-8ffd-281f0d7934ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228464676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.228464676
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.90941531
Short name T1193
Test name
Test status
Simulation time 1008999325 ps
CPU time 42.49 seconds
Started Jun 27 04:51:42 PM PDT 24
Finished Jun 27 04:52:27 PM PDT 24
Peak memory 257440 kb
Host smart-c3b4dfcc-3e79-43af-b12c-0e2042cce8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90941531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.90941531
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.1604432228
Short name T382
Test name
Test status
Simulation time 47372195 ps
CPU time 0.63 seconds
Started Jun 27 04:51:12 PM PDT 24
Finished Jun 27 04:51:18 PM PDT 24
Peak memory 204460 kb
Host smart-36a420d7-18b4-4e00-9fe8-5619ee46dff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604432228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.1604432228
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1040586399
Short name T1373
Test name
Test status
Simulation time 13364992394 ps
CPU time 128.27 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:53:24 PM PDT 24
Peak memory 734524 kb
Host smart-ce9906d2-fdf6-4a49-918a-6d0bef741a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040586399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1040586399
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.3760002256
Short name T1043
Test name
Test status
Simulation time 419906167 ps
CPU time 4.98 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:26 PM PDT 24
Peak memory 204664 kb
Host smart-370bb667-aec6-4fc7-8f00-8984d96db37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760002256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.3760002256
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.340234527
Short name T1360
Test name
Test status
Simulation time 1178552526 ps
CPU time 59.74 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:52:25 PM PDT 24
Peak memory 347268 kb
Host smart-a1feb402-ecdb-40bb-bbe8-17b994452832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340234527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.340234527
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1835006957
Short name T282
Test name
Test status
Simulation time 10100019514 ps
CPU time 162.87 seconds
Started Jun 27 04:51:23 PM PDT 24
Finished Jun 27 04:54:13 PM PDT 24
Peak memory 1007348 kb
Host smart-26c05eca-421a-4a23-b7cf-f19c8f8079e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835006957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1835006957
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2374296638
Short name T312
Test name
Test status
Simulation time 1270390710 ps
CPU time 20.81 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:49 PM PDT 24
Peak memory 212824 kb
Host smart-5e3f9572-2716-4815-bd0d-56dcd8411b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374296638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2374296638
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.628888966
Short name T711
Test name
Test status
Simulation time 429478296 ps
CPU time 2.63 seconds
Started Jun 27 04:51:32 PM PDT 24
Finished Jun 27 04:51:39 PM PDT 24
Peak memory 204848 kb
Host smart-9e418d64-0773-41ff-a5ad-c26927c3415f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628888966 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.628888966
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.2059674753
Short name T1258
Test name
Test status
Simulation time 179921984 ps
CPU time 1.01 seconds
Started Jun 27 04:51:16 PM PDT 24
Finished Jun 27 04:51:27 PM PDT 24
Peak memory 204576 kb
Host smart-237241b8-fa22-4b47-8b33-3467b2a1bb24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059674753 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.2059674753
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2685893382
Short name T567
Test name
Test status
Simulation time 697118944 ps
CPU time 1.32 seconds
Started Jun 27 04:51:22 PM PDT 24
Finished Jun 27 04:51:31 PM PDT 24
Peak memory 204796 kb
Host smart-12c9ba2a-269b-4b9d-ba0c-6f30fb55212a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685893382 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2685893382
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.1033246290
Short name T1287
Test name
Test status
Simulation time 2957164879 ps
CPU time 2.75 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:37 PM PDT 24
Peak memory 204760 kb
Host smart-bb63c1c7-9ff1-4ff2-b2c8-2f3bed287d20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033246290 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.1033246290
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.92413429
Short name T640
Test name
Test status
Simulation time 530071912 ps
CPU time 1.26 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:36 PM PDT 24
Peak memory 204444 kb
Host smart-1d56da68-39bb-41ee-b004-7c9f310aad43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92413429 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.92413429
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.3270102027
Short name T1018
Test name
Test status
Simulation time 856561951 ps
CPU time 4.95 seconds
Started Jun 27 04:51:24 PM PDT 24
Finished Jun 27 04:51:36 PM PDT 24
Peak memory 204800 kb
Host smart-7fdb097e-bf05-4a77-b534-d08e9109877c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270102027 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.3270102027
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1271708892
Short name T442
Test name
Test status
Simulation time 21707518940 ps
CPU time 470.24 seconds
Started Jun 27 04:51:29 PM PDT 24
Finished Jun 27 04:59:25 PM PDT 24
Peak memory 5324160 kb
Host smart-1e74dbaf-d7c9-4d0d-ba23-a1e97ff4b9db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271708892 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1271708892
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.889859642
Short name T814
Test name
Test status
Simulation time 861963508 ps
CPU time 11.27 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:39 PM PDT 24
Peak memory 204712 kb
Host smart-0e743ada-680b-4e33-9f5e-1461e40017ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889859642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_tar
get_smoke.889859642
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.1965624475
Short name T1009
Test name
Test status
Simulation time 2088407287 ps
CPU time 43.38 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:52:06 PM PDT 24
Peak memory 204760 kb
Host smart-63b6b9c5-137e-4ba1-8d37-d5e2364b532a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965624475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.1965624475
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.1532645326
Short name T915
Test name
Test status
Simulation time 57798420713 ps
CPU time 87.93 seconds
Started Jun 27 04:51:11 PM PDT 24
Finished Jun 27 04:52:44 PM PDT 24
Peak memory 1296168 kb
Host smart-ebdbcb1c-8bd9-4834-baf3-cec1c0d2029d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532645326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.1532645326
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1828473244
Short name T197
Test name
Test status
Simulation time 28251399543 ps
CPU time 441.4 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:58:50 PM PDT 24
Peak memory 1593268 kb
Host smart-b8a57575-8fb6-4def-b465-d323fd76b1cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828473244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1828473244
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.4210496179
Short name T956
Test name
Test status
Simulation time 17230591309 ps
CPU time 8.11 seconds
Started Jun 27 04:51:32 PM PDT 24
Finished Jun 27 04:51:44 PM PDT 24
Peak memory 221224 kb
Host smart-8c3aa547-fede-407b-91a9-2fd441a9dd86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210496179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.4210496179
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_alert_test.966133617
Short name T734
Test name
Test status
Simulation time 22587676 ps
CPU time 0.61 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:57 PM PDT 24
Peak memory 204360 kb
Host smart-9683361d-34ba-4e97-bec5-faadc66d33e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966133617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.966133617
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.2273452586
Short name T473
Test name
Test status
Simulation time 199343324 ps
CPU time 2.94 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:51:48 PM PDT 24
Peak memory 213532 kb
Host smart-734fde54-256a-40c2-917b-c93fcbad9ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273452586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.2273452586
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.3763955344
Short name T1189
Test name
Test status
Simulation time 530011084 ps
CPU time 9.65 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:38 PM PDT 24
Peak memory 241140 kb
Host smart-347e49ff-17ba-4745-87e9-d8623ee74f34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763955344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.3763955344
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.657130127
Short name T65
Test name
Test status
Simulation time 4215934904 ps
CPU time 46.29 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:52:30 PM PDT 24
Peak memory 409024 kb
Host smart-bcb11a6f-1387-457a-8965-7b24695a365e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657130127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.657130127
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.2687918669
Short name T1349
Test name
Test status
Simulation time 1918770413 ps
CPU time 64.97 seconds
Started Jun 27 04:51:15 PM PDT 24
Finished Jun 27 04:52:28 PM PDT 24
Peak memory 683084 kb
Host smart-89d04578-a665-414e-959c-360502bef1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687918669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.2687918669
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.3759004990
Short name T534
Test name
Test status
Simulation time 622652101 ps
CPU time 1.01 seconds
Started Jun 27 04:51:20 PM PDT 24
Finished Jun 27 04:51:30 PM PDT 24
Peak memory 204504 kb
Host smart-536ef2fa-0555-4782-bd30-382d2437da52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759004990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.3759004990
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.3625082674
Short name T433
Test name
Test status
Simulation time 179604720 ps
CPU time 3.86 seconds
Started Jun 27 04:51:14 PM PDT 24
Finished Jun 27 04:51:26 PM PDT 24
Peak memory 233536 kb
Host smart-5e12f7fa-2f17-4b16-97f4-f6c54b475d4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625082674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.3625082674
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.4089679166
Short name T1250
Test name
Test status
Simulation time 46796155771 ps
CPU time 262.91 seconds
Started Jun 27 04:51:25 PM PDT 24
Finished Jun 27 04:55:54 PM PDT 24
Peak memory 1125064 kb
Host smart-862dc52e-b40f-452d-9301-5086bcffb617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089679166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.4089679166
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.4083897623
Short name T675
Test name
Test status
Simulation time 2193513652 ps
CPU time 6.12 seconds
Started Jun 27 04:51:29 PM PDT 24
Finished Jun 27 04:51:40 PM PDT 24
Peak memory 204680 kb
Host smart-14e81843-0a17-4f2d-89c3-2b1929adc0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083897623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.4083897623
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.2159240641
Short name T524
Test name
Test status
Simulation time 2245345346 ps
CPU time 41.44 seconds
Started Jun 27 04:51:29 PM PDT 24
Finished Jun 27 04:52:15 PM PDT 24
Peak memory 380428 kb
Host smart-a14ad7fe-d228-46dc-bc53-65611326418e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159240641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.2159240641
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.413461726
Short name T630
Test name
Test status
Simulation time 18336799 ps
CPU time 0.65 seconds
Started Jun 27 04:51:13 PM PDT 24
Finished Jun 27 04:51:21 PM PDT 24
Peak memory 204548 kb
Host smart-d7566ead-df4e-44d1-8f89-91e20e38b2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413461726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.413461726
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.2936615999
Short name T1447
Test name
Test status
Simulation time 25624819759 ps
CPU time 423.01 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:59:00 PM PDT 24
Peak memory 898516 kb
Host smart-65587acc-313c-4c3b-82ee-51096c6b2287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936615999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.2936615999
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.4158014137
Short name T1288
Test name
Test status
Simulation time 2742207624 ps
CPU time 28.67 seconds
Started Jun 27 04:51:39 PM PDT 24
Finished Jun 27 04:52:11 PM PDT 24
Peak memory 255920 kb
Host smart-74bbb14a-05c1-4a51-9cbd-32cef9b2b086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158014137 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.4158014137
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.3801534973
Short name T1136
Test name
Test status
Simulation time 3630062043 ps
CPU time 27.78 seconds
Started Jun 27 04:51:25 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 381908 kb
Host smart-5ce0e482-63ca-40f0-8548-d7a0759f1339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801534973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.3801534973
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.850756006
Short name T1350
Test name
Test status
Simulation time 18204834911 ps
CPU time 273.46 seconds
Started Jun 27 04:51:26 PM PDT 24
Finished Jun 27 04:56:06 PM PDT 24
Peak memory 1811840 kb
Host smart-60e67fad-7de6-4dc1-bece-2d815c26d68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850756006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.850756006
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.4069114328
Short name T196
Test name
Test status
Simulation time 1262211466 ps
CPU time 26.85 seconds
Started Jun 27 04:51:31 PM PDT 24
Finished Jun 27 04:52:02 PM PDT 24
Peak memory 212976 kb
Host smart-33700629-7d4d-4f27-a8b3-d7f1995f0b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069114328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.4069114328
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.1920445867
Short name T1339
Test name
Test status
Simulation time 5876547033 ps
CPU time 4.77 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:51:48 PM PDT 24
Peak memory 213096 kb
Host smart-2be6139a-9eea-41b4-b56c-ba9cd3f5f00e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920445867 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.1920445867
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.286095607
Short name T435
Test name
Test status
Simulation time 166659683 ps
CPU time 1.05 seconds
Started Jun 27 04:51:42 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 204484 kb
Host smart-3677c084-c6c7-4a81-a43a-a1f497a1ebd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286095607 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_acq.286095607
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.4040418922
Short name T928
Test name
Test status
Simulation time 268856909 ps
CPU time 0.86 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:36 PM PDT 24
Peak memory 204616 kb
Host smart-910e6fcc-4edc-4d79-bee3-53fc0ee9ed1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040418922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.4040418922
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.3651612556
Short name T1076
Test name
Test status
Simulation time 2927110307 ps
CPU time 2.97 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:51:49 PM PDT 24
Peak memory 204964 kb
Host smart-f8335950-ce0a-4ae2-b505-3018a74df7d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651612556 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.3651612556
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.547887620
Short name T771
Test name
Test status
Simulation time 264272927 ps
CPU time 1.17 seconds
Started Jun 27 04:51:41 PM PDT 24
Finished Jun 27 04:51:45 PM PDT 24
Peak memory 204572 kb
Host smart-27878f83-4c27-46bc-860e-9634aa5ea203
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547887620 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.547887620
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.2665961897
Short name T403
Test name
Test status
Simulation time 1021946053 ps
CPU time 3.47 seconds
Started Jun 27 04:51:28 PM PDT 24
Finished Jun 27 04:51:37 PM PDT 24
Peak memory 204888 kb
Host smart-af36f5a0-d885-4cf7-9250-870436a84c38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665961897 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.2665961897
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.1813538516
Short name T402
Test name
Test status
Simulation time 3668510986 ps
CPU time 4.54 seconds
Started Jun 27 04:51:29 PM PDT 24
Finished Jun 27 04:51:39 PM PDT 24
Peak memory 213504 kb
Host smart-84632867-3306-4452-8c78-2fa306cab08c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813538516 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_intr_smoke.1813538516
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.3506153265
Short name T1441
Test name
Test status
Simulation time 15668081745 ps
CPU time 295.61 seconds
Started Jun 27 04:51:37 PM PDT 24
Finished Jun 27 04:56:35 PM PDT 24
Peak memory 3765928 kb
Host smart-cd4e17b5-16c6-4564-b690-72dedaff886d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506153265 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.3506153265
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.4225821294
Short name T1239
Test name
Test status
Simulation time 1029735088 ps
CPU time 15.51 seconds
Started Jun 27 04:51:31 PM PDT 24
Finished Jun 27 04:51:51 PM PDT 24
Peak memory 204832 kb
Host smart-37909e5d-e4e7-49e9-b391-f1ffb0442a70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225821294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.4225821294
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3428427580
Short name T1469
Test name
Test status
Simulation time 5122412640 ps
CPU time 20.32 seconds
Started Jun 27 04:51:31 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 223024 kb
Host smart-cc32bfc8-d4d1-4bb1-a2e7-403437e374c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428427580 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3428427580
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.2777062080
Short name T476
Test name
Test status
Simulation time 42211254687 ps
CPU time 679.72 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 05:03:03 PM PDT 24
Peak memory 5668904 kb
Host smart-a26e5d1e-9ecc-4e46-b532-73437b11deb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777062080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.2777062080
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3139784380
Short name T1425
Test name
Test status
Simulation time 5735240325 ps
CPU time 10.05 seconds
Started Jun 27 04:51:42 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 275340 kb
Host smart-26e0736b-cabc-4455-982b-acbee2287e58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139784380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3139784380
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.653316172
Short name T595
Test name
Test status
Simulation time 5280823156 ps
CPU time 6.89 seconds
Started Jun 27 04:51:29 PM PDT 24
Finished Jun 27 04:51:41 PM PDT 24
Peak memory 221100 kb
Host smart-86071590-3493-451f-8e76-340a40ab3f6e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653316172 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 33.i2c_target_timeout.653316172
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_alert_test.421354081
Short name T1082
Test name
Test status
Simulation time 26440211 ps
CPU time 0.59 seconds
Started Jun 27 04:51:42 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 204488 kb
Host smart-ef3c3d2c-a1a7-48c6-94ec-6db6151bb13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421354081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.421354081
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.4104774555
Short name T431
Test name
Test status
Simulation time 73291008 ps
CPU time 1.35 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 212780 kb
Host smart-0ad40794-d15b-4f81-a9d8-6eaecf11cf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104774555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.4104774555
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.1853476211
Short name T662
Test name
Test status
Simulation time 609534513 ps
CPU time 4.01 seconds
Started Jun 27 04:51:39 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 234264 kb
Host smart-06180764-bb84-4245-a3b7-7f2fba8771b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853476211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.1853476211
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2266659196
Short name T43
Test name
Test status
Simulation time 36574648241 ps
CPU time 189.9 seconds
Started Jun 27 04:51:26 PM PDT 24
Finished Jun 27 04:54:43 PM PDT 24
Peak memory 687528 kb
Host smart-ae295c73-0513-4ca6-a8cc-b3ba2ea72795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266659196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2266659196
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.2572285745
Short name T543
Test name
Test status
Simulation time 5500326717 ps
CPU time 35.09 seconds
Started Jun 27 04:51:28 PM PDT 24
Finished Jun 27 04:52:09 PM PDT 24
Peak memory 502880 kb
Host smart-2558cf85-2d4a-434f-b5ff-d29f729c0b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572285745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.2572285745
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3937115735
Short name T575
Test name
Test status
Simulation time 124886729 ps
CPU time 0.82 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:35 PM PDT 24
Peak memory 204520 kb
Host smart-25231c0d-e928-4e63-ba4f-b79bc59d3c54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937115735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3937115735
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.1542310867
Short name T635
Test name
Test status
Simulation time 915744212 ps
CPU time 5.41 seconds
Started Jun 27 04:51:44 PM PDT 24
Finished Jun 27 04:51:52 PM PDT 24
Peak memory 204756 kb
Host smart-cc329812-3282-408e-be3a-48fc6b0b7629
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542310867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.1542310867
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.3304329
Short name T1085
Test name
Test status
Simulation time 40254605401 ps
CPU time 70.32 seconds
Started Jun 27 04:51:39 PM PDT 24
Finished Jun 27 04:52:53 PM PDT 24
Peak memory 879340 kb
Host smart-7ab483dd-2eba-4250-a20e-37ec4d42f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.3304329
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.968158737
Short name T1030
Test name
Test status
Simulation time 195880337 ps
CPU time 3.37 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:51:49 PM PDT 24
Peak memory 204796 kb
Host smart-dbbd29f4-dc76-4a3a-8054-f80f40ac9bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968158737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.968158737
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.4012965198
Short name T385
Test name
Test status
Simulation time 4791228121 ps
CPU time 81.99 seconds
Started Jun 27 04:51:37 PM PDT 24
Finished Jun 27 04:53:01 PM PDT 24
Peak memory 362148 kb
Host smart-199ccadf-11e5-4fdf-9e31-68436d6f2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012965198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.4012965198
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.764099951
Short name T139
Test name
Test status
Simulation time 219569617 ps
CPU time 0.64 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:35 PM PDT 24
Peak memory 204376 kb
Host smart-77004f8b-7490-4816-8a16-c1a9778e6566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764099951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.764099951
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2087045994
Short name T1283
Test name
Test status
Simulation time 25956623159 ps
CPU time 58.46 seconds
Started Jun 27 04:51:31 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 262468 kb
Host smart-31573c9b-1a23-4eb9-a32a-3351f622d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087045994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2087045994
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.3602631673
Short name T378
Test name
Test status
Simulation time 133625888 ps
CPU time 5.66 seconds
Started Jun 27 04:51:38 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 229216 kb
Host smart-fb2a94ef-ae66-4dcf-9a65-5a632a586b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602631673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.3602631673
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.704796651
Short name T53
Test name
Test status
Simulation time 8884697761 ps
CPU time 76.15 seconds
Started Jun 27 04:51:39 PM PDT 24
Finished Jun 27 04:52:58 PM PDT 24
Peak memory 359408 kb
Host smart-a0269108-4f6a-4fae-8d6b-ceb7b7de7166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704796651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.704796651
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.307141440
Short name T216
Test name
Test status
Simulation time 62872525234 ps
CPU time 1818.1 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 05:22:16 PM PDT 24
Peak memory 3584852 kb
Host smart-81da5566-d098-40a6-9897-a00196274c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307141440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.307141440
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.4225253344
Short name T604
Test name
Test status
Simulation time 3800346974 ps
CPU time 16.67 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:51:59 PM PDT 24
Peak memory 221252 kb
Host smart-d705571d-20ef-4389-99c2-24d257091427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225253344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.4225253344
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.1088010033
Short name T1292
Test name
Test status
Simulation time 1072883059 ps
CPU time 2.74 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:59 PM PDT 24
Peak memory 204740 kb
Host smart-5aa20e2a-3d52-4866-b255-296945e24018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088010033 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.1088010033
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2841121331
Short name T544
Test name
Test status
Simulation time 462072765 ps
CPU time 1 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:36 PM PDT 24
Peak memory 204524 kb
Host smart-475be9fb-d8aa-4f84-8909-2e705a99ae0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841121331 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2841121331
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.1434679091
Short name T465
Test name
Test status
Simulation time 1947975971 ps
CPU time 1.06 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 204404 kb
Host smart-4c523508-c185-4faf-b65e-9398c402dc65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434679091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.1434679091
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.3466709506
Short name T1318
Test name
Test status
Simulation time 1121161867 ps
CPU time 2.87 seconds
Started Jun 27 04:51:41 PM PDT 24
Finished Jun 27 04:51:47 PM PDT 24
Peak memory 204820 kb
Host smart-2439b8a5-94b0-4808-bc0d-7d9dbdfde767
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466709506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.3466709506
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.2598044373
Short name T1432
Test name
Test status
Simulation time 200833083 ps
CPU time 1.05 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 204436 kb
Host smart-6f516114-fad1-4863-93e2-1f89fd623bcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598044373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.2598044373
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1180236733
Short name T906
Test name
Test status
Simulation time 1485054162 ps
CPU time 3.05 seconds
Started Jun 27 04:51:42 PM PDT 24
Finished Jun 27 04:51:48 PM PDT 24
Peak memory 204812 kb
Host smart-5e3f6f10-ec7f-4824-8222-87b4bdb4aa5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180236733 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1180236733
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.3734786182
Short name T1468
Test name
Test status
Simulation time 1226385997 ps
CPU time 5.23 seconds
Started Jun 27 04:51:29 PM PDT 24
Finished Jun 27 04:51:39 PM PDT 24
Peak memory 214324 kb
Host smart-0f4b1101-50a2-43cb-ac27-2d0c5854947a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734786182 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_intr_smoke.3734786182
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2414113019
Short name T733
Test name
Test status
Simulation time 5193604450 ps
CPU time 37.13 seconds
Started Jun 27 04:51:46 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 1126728 kb
Host smart-f1398385-fb3d-4aaa-aa68-a787c945b475
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414113019 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2414113019
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.69458421
Short name T1334
Test name
Test status
Simulation time 3333107807 ps
CPU time 13.73 seconds
Started Jun 27 04:51:28 PM PDT 24
Finished Jun 27 04:51:47 PM PDT 24
Peak memory 204956 kb
Host smart-bfbc7c00-15af-4a03-b3fe-2f6ce90b46b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69458421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_targ
et_smoke.69458421
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2892075789
Short name T309
Test name
Test status
Simulation time 1493035238 ps
CPU time 5.4 seconds
Started Jun 27 04:51:37 PM PDT 24
Finished Jun 27 04:51:44 PM PDT 24
Peak memory 204712 kb
Host smart-c611e477-d2f4-4ac6-a594-b3d9f62e0e2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892075789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2892075789
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.4156410606
Short name T827
Test name
Test status
Simulation time 52673849592 ps
CPU time 194.66 seconds
Started Jun 27 04:51:28 PM PDT 24
Finished Jun 27 04:54:48 PM PDT 24
Peak memory 2141164 kb
Host smart-a9c61c4a-2025-4c02-9e60-b25eb2dbcff9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156410606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.4156410606
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2367841041
Short name T570
Test name
Test status
Simulation time 5084572155 ps
CPU time 7.48 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 213540 kb
Host smart-ae62935e-119b-422f-b0db-8bbea9701d3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367841041 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2367841041
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_alert_test.2194013488
Short name T145
Test name
Test status
Simulation time 41835836 ps
CPU time 0.66 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 204388 kb
Host smart-e0a0da94-b67d-41c4-aad6-e39913996edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194013488 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.2194013488
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.2236860410
Short name T885
Test name
Test status
Simulation time 446382524 ps
CPU time 1.78 seconds
Started Jun 27 04:51:41 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 213060 kb
Host smart-935ed56c-f51e-43c7-adc4-c78282a0b93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236860410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.2236860410
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.68428766
Short name T866
Test name
Test status
Simulation time 493458879 ps
CPU time 23.29 seconds
Started Jun 27 04:51:47 PM PDT 24
Finished Jun 27 04:52:13 PM PDT 24
Peak memory 302304 kb
Host smart-0849b438-e097-442a-830f-b1da2501ed80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68428766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_empty
.68428766
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1734039395
Short name T469
Test name
Test status
Simulation time 3281715671 ps
CPU time 47.22 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:52:40 PM PDT 24
Peak memory 528380 kb
Host smart-5bdd940e-0c2c-4d04-b2ff-3831ec81da13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734039395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1734039395
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.2339793522
Short name T612
Test name
Test status
Simulation time 1765501578 ps
CPU time 114.01 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:53:37 PM PDT 24
Peak memory 582940 kb
Host smart-565ce5d9-f0e1-49f8-9837-877195bc0b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339793522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.2339793522
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.486235901
Short name T702
Test name
Test status
Simulation time 459749048 ps
CPU time 0.93 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 204388 kb
Host smart-4c3265ed-8905-4482-ba48-5f3342dc3ddf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486235901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm
t.486235901
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3462550995
Short name T1223
Test name
Test status
Simulation time 276765996 ps
CPU time 3.68 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 204816 kb
Host smart-db0345ec-4aef-44fd-be78-94ff3d33b73c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462550995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3462550995
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.1135181200
Short name T104
Test name
Test status
Simulation time 18787783824 ps
CPU time 124.14 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:53:39 PM PDT 24
Peak memory 1376580 kb
Host smart-1d3cd066-65e7-41c8-bfc9-fbe5691b8f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135181200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.1135181200
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1948872117
Short name T615
Test name
Test status
Simulation time 661882769 ps
CPU time 4.67 seconds
Started Jun 27 04:51:37 PM PDT 24
Finished Jun 27 04:51:43 PM PDT 24
Peak memory 204804 kb
Host smart-4ecbf62b-1279-4ac4-93f9-c1de3b42beda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948872117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1948872117
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.2017192516
Short name T559
Test name
Test status
Simulation time 7222229870 ps
CPU time 82.22 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:53:05 PM PDT 24
Peak memory 409836 kb
Host smart-bda29967-26f3-4714-97d1-9a9d863f2ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017192516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.2017192516
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.627864260
Short name T142
Test name
Test status
Simulation time 29444700 ps
CPU time 0.7 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 204388 kb
Host smart-235d968e-f3d7-4e93-8a38-f1fcea8fa46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627864260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.627864260
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1126409168
Short name T313
Test name
Test status
Simulation time 1150088766 ps
CPU time 10.79 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 304168 kb
Host smart-210d0e13-4b90-4420-9d0f-f6e50240c1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126409168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1126409168
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.2864313023
Short name T36
Test name
Test status
Simulation time 2385578482 ps
CPU time 13.17 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:51:56 PM PDT 24
Peak memory 222756 kb
Host smart-468f2eb9-6a6a-4b6a-8eeb-263d35339103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864313023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2864313023
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.2792825323
Short name T1431
Test name
Test status
Simulation time 2227086295 ps
CPU time 103.99 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:53:41 PM PDT 24
Peak memory 366256 kb
Host smart-3e50d5f8-0de2-4e44-95c4-a3c0b63cd096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792825323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.2792825323
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.2767211923
Short name T1145
Test name
Test status
Simulation time 17953608929 ps
CPU time 1801.4 seconds
Started Jun 27 04:51:41 PM PDT 24
Finished Jun 27 05:21:46 PM PDT 24
Peak memory 2047040 kb
Host smart-09a171dd-f59f-43c6-8eb3-2873d24171fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767211923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.2767211923
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.2427040454
Short name T679
Test name
Test status
Simulation time 3615762062 ps
CPU time 16.09 seconds
Started Jun 27 04:51:45 PM PDT 24
Finished Jun 27 04:52:04 PM PDT 24
Peak memory 218592 kb
Host smart-8b212582-f8d0-4cc7-ad1b-4c0f48457d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427040454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2427040454
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3295439268
Short name T268
Test name
Test status
Simulation time 772265239 ps
CPU time 3.83 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:51:49 PM PDT 24
Peak memory 213032 kb
Host smart-510a3db9-3e75-4440-8b1e-cd0922518eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295439268 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3295439268
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.757701912
Short name T460
Test name
Test status
Simulation time 134505660 ps
CPU time 0.74 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 204496 kb
Host smart-ae213975-6e41-4685-a3d3-52104f3f414f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757701912 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.757701912
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.1309161986
Short name T1012
Test name
Test status
Simulation time 213004837 ps
CPU time 0.97 seconds
Started Jun 27 04:51:31 PM PDT 24
Finished Jun 27 04:51:36 PM PDT 24
Peak memory 204552 kb
Host smart-ff82d4c9-1b1f-46fb-a097-cc7d6a0e6f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309161986 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.1309161986
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.32526543
Short name T457
Test name
Test status
Simulation time 260849352 ps
CPU time 1.59 seconds
Started Jun 27 04:51:45 PM PDT 24
Finished Jun 27 04:51:49 PM PDT 24
Peak memory 204504 kb
Host smart-f547bedd-ec52-4a78-87f5-f568541902fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32526543 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.32526543
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.2276102332
Short name T298
Test name
Test status
Simulation time 100595758 ps
CPU time 1.02 seconds
Started Jun 27 04:51:42 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 204616 kb
Host smart-93862f39-ae9f-40ec-aa61-1ccaeb3b19b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276102332 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.2276102332
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.167111096
Short name T1065
Test name
Test status
Simulation time 777728306 ps
CPU time 3.28 seconds
Started Jun 27 04:51:30 PM PDT 24
Finished Jun 27 04:51:38 PM PDT 24
Peak memory 204840 kb
Host smart-8b8b834c-2768-4527-b1d5-63927e1c633a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167111096 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.i2c_target_hrst.167111096
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.3295363070
Short name T1119
Test name
Test status
Simulation time 10977396069 ps
CPU time 5.65 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:51:49 PM PDT 24
Peak memory 215952 kb
Host smart-837541ca-0d6e-4e99-8987-f9067ae43d58
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295363070 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.3295363070
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.3012714476
Short name T1388
Test name
Test status
Simulation time 14879531404 ps
CPU time 32.07 seconds
Started Jun 27 04:51:39 PM PDT 24
Finished Jun 27 04:52:14 PM PDT 24
Peak memory 919368 kb
Host smart-5f96f361-a130-4b5a-92b1-81f028670525
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012714476 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.3012714476
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.4022787873
Short name T857
Test name
Test status
Simulation time 854173169 ps
CPU time 33.81 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:52:17 PM PDT 24
Peak memory 204684 kb
Host smart-27bcab5d-a58c-42de-a36f-78739888aedc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022787873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.4022787873
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.1118387513
Short name T1331
Test name
Test status
Simulation time 1781535738 ps
CPU time 34.36 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:52:17 PM PDT 24
Peak memory 205052 kb
Host smart-b0c6e7ba-f58b-4319-96b0-f1a8ee62904f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118387513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.1118387513
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.246782963
Short name T1454
Test name
Test status
Simulation time 48300139178 ps
CPU time 329.42 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:57:22 PM PDT 24
Peak memory 3480176 kb
Host smart-6dcdd59f-df8a-4b78-bf85-ba002f9f5e84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246782963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_wr.246782963
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.3972853947
Short name T1277
Test name
Test status
Simulation time 6123584590 ps
CPU time 118.79 seconds
Started Jun 27 04:51:37 PM PDT 24
Finished Jun 27 04:53:38 PM PDT 24
Peak memory 671836 kb
Host smart-f149c9f8-6977-46bf-8d0b-942ace9ffbd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972853947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.3972853947
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.213882802
Short name T352
Test name
Test status
Simulation time 1723272111 ps
CPU time 7.18 seconds
Started Jun 27 04:51:29 PM PDT 24
Finished Jun 27 04:51:41 PM PDT 24
Peak memory 212796 kb
Host smart-1ffd7554-78c4-4b21-955b-423d7b58eadb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213882802 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_timeout.213882802
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.650885892
Short name T768
Test name
Test status
Simulation time 19474820 ps
CPU time 0.64 seconds
Started Jun 27 04:51:54 PM PDT 24
Finished Jun 27 04:51:59 PM PDT 24
Peak memory 204464 kb
Host smart-f55fb065-11e8-4654-bf5b-4b38238792ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650885892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.650885892
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.570567493
Short name T1368
Test name
Test status
Simulation time 343770475 ps
CPU time 3.48 seconds
Started Jun 27 04:51:46 PM PDT 24
Finished Jun 27 04:51:52 PM PDT 24
Peak memory 226188 kb
Host smart-f514e2b2-afee-48de-9a10-9ed1a68ffcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570567493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.570567493
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2442117308
Short name T454
Test name
Test status
Simulation time 1656437002 ps
CPU time 22.65 seconds
Started Jun 27 04:51:42 PM PDT 24
Finished Jun 27 04:52:08 PM PDT 24
Peak memory 299888 kb
Host smart-933c6f0c-0367-40eb-a64e-b127bcd1abb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442117308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2442117308
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.767707953
Short name T807
Test name
Test status
Simulation time 6346870226 ps
CPU time 40.58 seconds
Started Jun 27 04:51:31 PM PDT 24
Finished Jun 27 04:52:16 PM PDT 24
Peak memory 554980 kb
Host smart-174e7f78-2afe-4882-9526-882c5ed8ac48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767707953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.767707953
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.4016791797
Short name T1353
Test name
Test status
Simulation time 1982456335 ps
CPU time 61.62 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:52:47 PM PDT 24
Peak memory 641020 kb
Host smart-06b17d15-569d-4e52-ab15-3347082776d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016791797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.4016791797
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3842578733
Short name T60
Test name
Test status
Simulation time 78795607 ps
CPU time 0.92 seconds
Started Jun 27 04:51:33 PM PDT 24
Finished Jun 27 04:51:38 PM PDT 24
Peak memory 204548 kb
Host smart-78fc8225-ec75-482b-b72c-b74428947e79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842578733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3842578733
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.2810678728
Short name T344
Test name
Test status
Simulation time 844597505 ps
CPU time 11.29 seconds
Started Jun 27 04:51:47 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 244080 kb
Host smart-2ea6c8c0-8d4c-4be4-9240-d7447d5c330f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810678728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.2810678728
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.357333202
Short name T472
Test name
Test status
Simulation time 54601560950 ps
CPU time 227.25 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:55:30 PM PDT 24
Peak memory 1024508 kb
Host smart-7ace3cdf-5cc3-453b-af36-750322b18ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357333202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.357333202
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.3879743893
Short name T1032
Test name
Test status
Simulation time 2099046988 ps
CPU time 6.92 seconds
Started Jun 27 04:51:39 PM PDT 24
Finished Jun 27 04:51:48 PM PDT 24
Peak memory 204756 kb
Host smart-30291914-8635-4ea2-9efd-1efd04632ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879743893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.3879743893
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.3261917556
Short name T1061
Test name
Test status
Simulation time 5269686575 ps
CPU time 20.65 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:52:07 PM PDT 24
Peak memory 329992 kb
Host smart-c63c3073-86f0-45c2-a2fc-837de4f992ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261917556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.3261917556
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.2417579160
Short name T129
Test name
Test status
Simulation time 29600831 ps
CPU time 0.7 seconds
Started Jun 27 04:51:42 PM PDT 24
Finished Jun 27 04:51:46 PM PDT 24
Peak memory 204448 kb
Host smart-f8639368-d433-4ffc-b287-1ff750e9f735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417579160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.2417579160
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.3487434399
Short name T672
Test name
Test status
Simulation time 27339433277 ps
CPU time 223.96 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:55:27 PM PDT 24
Peak memory 1584252 kb
Host smart-594c6405-6765-4a89-9219-9a823a4485b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487434399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.3487434399
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.4129505746
Short name T869
Test name
Test status
Simulation time 85453047 ps
CPU time 1.05 seconds
Started Jun 27 04:51:39 PM PDT 24
Finished Jun 27 04:51:42 PM PDT 24
Peak memory 205192 kb
Host smart-30c1b0b8-cd9b-4c64-ab6f-c369180138f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129505746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.4129505746
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.568452867
Short name T545
Test name
Test status
Simulation time 1556781235 ps
CPU time 69.82 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:53:03 PM PDT 24
Peak memory 328192 kb
Host smart-eef892a2-1eca-4169-a18b-4a26879fe29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568452867 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.568452867
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.4150221035
Short name T935
Test name
Test status
Simulation time 1654869307 ps
CPU time 2.62 seconds
Started Jun 27 04:51:48 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 204816 kb
Host smart-842d08e0-af21-4f14-9e45-e849e55900e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150221035 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.4150221035
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.2517045160
Short name T1314
Test name
Test status
Simulation time 163803276 ps
CPU time 1.2 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 204600 kb
Host smart-9dea1183-f544-4f9c-98df-b682a4a04154
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517045160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.2517045160
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.2289471054
Short name T161
Test name
Test status
Simulation time 287011070 ps
CPU time 1.4 seconds
Started Jun 27 04:51:48 PM PDT 24
Finished Jun 27 04:51:52 PM PDT 24
Peak memory 204856 kb
Host smart-3f82d89e-4222-4aff-910a-72f1eeeda885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289471054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.2289471054
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.2080586567
Short name T832
Test name
Test status
Simulation time 515816371 ps
CPU time 1.66 seconds
Started Jun 27 04:51:53 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 204724 kb
Host smart-cd8bb64c-5490-463b-b260-7d8218d8799d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080586567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.2080586567
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.2981642677
Short name T110
Test name
Test status
Simulation time 117163459 ps
CPU time 1.09 seconds
Started Jun 27 04:51:47 PM PDT 24
Finished Jun 27 04:51:51 PM PDT 24
Peak memory 204564 kb
Host smart-b4e35251-60c3-43e0-9441-07adc2bb4b13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981642677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.2981642677
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.1144129173
Short name T1294
Test name
Test status
Simulation time 1049045083 ps
CPU time 2.94 seconds
Started Jun 27 04:51:48 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 204836 kb
Host smart-231da0c3-bc52-47ce-8f7d-ec4a5a24eec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144129173 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.1144129173
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.3500710802
Short name T1464
Test name
Test status
Simulation time 6422849931 ps
CPU time 8.52 seconds
Started Jun 27 04:51:59 PM PDT 24
Finished Jun 27 04:52:10 PM PDT 24
Peak memory 223056 kb
Host smart-a8f83c4e-0574-4c0c-b513-bcc3ec574293
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500710802 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.3500710802
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.3547356162
Short name T1234
Test name
Test status
Simulation time 12915763369 ps
CPU time 122.35 seconds
Started Jun 27 04:51:43 PM PDT 24
Finished Jun 27 04:53:48 PM PDT 24
Peak memory 2316052 kb
Host smart-1a720fff-b82b-4694-87dc-b7335969f4b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547356162 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.3547356162
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.2556091710
Short name T179
Test name
Test status
Simulation time 1321544288 ps
CPU time 20.32 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 04:52:03 PM PDT 24
Peak memory 204864 kb
Host smart-b500a414-30df-4b59-9ad0-70ecd8afe7a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556091710 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.2556091710
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.303558392
Short name T404
Test name
Test status
Simulation time 4336227745 ps
CPU time 43.42 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 204884 kb
Host smart-bb3c6a45-037a-44bb-858f-56ffc9b5b91a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303558392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.303558392
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.1184141998
Short name T1359
Test name
Test status
Simulation time 36176161998 ps
CPU time 56.1 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:52:48 PM PDT 24
Peak memory 1086656 kb
Host smart-4c6acce2-6132-4913-a1f4-53896f04b803
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184141998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.1184141998
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.2971541593
Short name T411
Test name
Test status
Simulation time 18269222381 ps
CPU time 2505.59 seconds
Started Jun 27 04:51:40 PM PDT 24
Finished Jun 27 05:33:29 PM PDT 24
Peak memory 4490464 kb
Host smart-b78272b6-2871-4b9d-8695-0b9d16106825
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971541593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.2971541593
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1302306271
Short name T754
Test name
Test status
Simulation time 1288141604 ps
CPU time 6.43 seconds
Started Jun 27 04:51:44 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 219628 kb
Host smart-8d4f9759-916d-4b3e-83d4-346525efa06d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302306271 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1302306271
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_alert_test.3612584917
Short name T452
Test name
Test status
Simulation time 48788832 ps
CPU time 0.61 seconds
Started Jun 27 04:51:48 PM PDT 24
Finished Jun 27 04:51:51 PM PDT 24
Peak memory 204400 kb
Host smart-f7addabd-6109-411a-a6c3-595dec8dbb29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612584917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.3612584917
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.2256991491
Short name T423
Test name
Test status
Simulation time 1231628919 ps
CPU time 5.57 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:52:01 PM PDT 24
Peak memory 242796 kb
Host smart-4933188e-0c59-45f4-acf0-b0e33c4b5f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256991491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.2256991491
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.1663664212
Short name T1242
Test name
Test status
Simulation time 464450535 ps
CPU time 11.32 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:52:04 PM PDT 24
Peak memory 248412 kb
Host smart-0bb56196-9148-4e9f-8722-4c5d2cbf2c4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663664212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.1663664212
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.399550015
Short name T42
Test name
Test status
Simulation time 14143369327 ps
CPU time 105.44 seconds
Started Jun 27 04:51:58 PM PDT 24
Finished Jun 27 04:53:46 PM PDT 24
Peak memory 546836 kb
Host smart-5acf38ee-21c0-4d54-8e72-60abb79fbab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399550015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.399550015
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.4244528387
Short name T328
Test name
Test status
Simulation time 41040597638 ps
CPU time 62.22 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:52:57 PM PDT 24
Peak memory 604864 kb
Host smart-e5bb2f8f-afbe-4e6f-9b3c-19b01251efd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244528387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.4244528387
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.2369463696
Short name T999
Test name
Test status
Simulation time 115545291 ps
CPU time 0.99 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:51:57 PM PDT 24
Peak memory 204480 kb
Host smart-e7618c9c-4866-4b38-b833-f39f46116584
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369463696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_f
mt.2369463696
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.4074937789
Short name T236
Test name
Test status
Simulation time 161239039 ps
CPU time 8.05 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:52:02 PM PDT 24
Peak memory 228284 kb
Host smart-be57c42e-360b-4272-86ef-8237f13ee86e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074937789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.4074937789
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.3736468043
Short name T1478
Test name
Test status
Simulation time 13923730199 ps
CPU time 217.25 seconds
Started Jun 27 04:51:56 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 1005264 kb
Host smart-2afbf86a-22ff-43fc-9eec-d16fcf8c9fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736468043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.3736468043
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.2654830732
Short name T977
Test name
Test status
Simulation time 1490310970 ps
CPU time 3.31 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:59 PM PDT 24
Peak memory 204732 kb
Host smart-bb33a37d-2d82-490a-bd58-c1610b426da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654830732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.2654830732
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.2092953409
Short name T1379
Test name
Test status
Simulation time 9066989044 ps
CPU time 116.84 seconds
Started Jun 27 04:51:53 PM PDT 24
Finished Jun 27 04:53:54 PM PDT 24
Peak memory 407860 kb
Host smart-9f01a63b-3900-4697-bb24-6230d36d4299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092953409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.2092953409
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.3143115802
Short name T143
Test name
Test status
Simulation time 25715967 ps
CPU time 0.68 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:51:56 PM PDT 24
Peak memory 204520 kb
Host smart-eff827e3-19dd-4527-9c53-56a301cb3c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143115802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.3143115802
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.1945123169
Short name T625
Test name
Test status
Simulation time 26847879944 ps
CPU time 64.88 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:52:59 PM PDT 24
Peak memory 234436 kb
Host smart-610dfbb8-29d1-49f6-b81c-2cf9c7af1b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945123169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.1945123169
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.1329377110
Short name T1067
Test name
Test status
Simulation time 221549889 ps
CPU time 2.34 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 214920 kb
Host smart-af790063-fe93-434a-acce-6444bd1e31e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329377110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.1329377110
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3947670142
Short name T1112
Test name
Test status
Simulation time 1637114988 ps
CPU time 78.62 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:53:13 PM PDT 24
Peak memory 358448 kb
Host smart-3fe4fc9c-2436-4190-b8bb-1417c199f09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947670142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3947670142
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.4024696763
Short name T121
Test name
Test status
Simulation time 14251317211 ps
CPU time 453.94 seconds
Started Jun 27 04:51:47 PM PDT 24
Finished Jun 27 04:59:24 PM PDT 24
Peak memory 1831976 kb
Host smart-f4210f6d-c14f-43b9-83d8-20b4ed911a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024696763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.4024696763
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.1245356625
Short name T1417
Test name
Test status
Simulation time 1703443344 ps
CPU time 22.16 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:52:14 PM PDT 24
Peak memory 213048 kb
Host smart-810bf90e-2986-4df4-83de-4b9da5f52445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245356625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1245356625
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.994274139
Short name T1137
Test name
Test status
Simulation time 2727890115 ps
CPU time 3.93 seconds
Started Jun 27 04:51:56 PM PDT 24
Finished Jun 27 04:52:04 PM PDT 24
Peak memory 213124 kb
Host smart-961fc902-a219-41ef-9685-0d2ba9c86e3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994274139 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.994274139
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.1272073567
Short name T377
Test name
Test status
Simulation time 289372828 ps
CPU time 0.99 seconds
Started Jun 27 04:51:54 PM PDT 24
Finished Jun 27 04:51:59 PM PDT 24
Peak memory 204596 kb
Host smart-90c28637-4110-4904-b33e-47273de048cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272073567 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_fifo_reset_acq.1272073567
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.4262291283
Short name T340
Test name
Test status
Simulation time 680499862 ps
CPU time 1.08 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 205064 kb
Host smart-9a15a5b5-377f-4a3c-82f8-9e6cf3aa4d7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262291283 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.4262291283
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.834450333
Short name T1027
Test name
Test status
Simulation time 585101739 ps
CPU time 2.67 seconds
Started Jun 27 04:51:56 PM PDT 24
Finished Jun 27 04:52:02 PM PDT 24
Peak memory 204740 kb
Host smart-114d4022-1286-4e6f-8f61-bdb8c7e8d4ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834450333 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.834450333
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.3143891744
Short name T1244
Test name
Test status
Simulation time 60683890 ps
CPU time 0.66 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:51:56 PM PDT 24
Peak memory 204520 kb
Host smart-3a436db0-f21f-41bf-8f0f-53f41f5e1f52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143891744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.3143891744
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_hrst.1564806506
Short name T292
Test name
Test status
Simulation time 1792554032 ps
CPU time 3.93 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 204852 kb
Host smart-05bd74f0-503a-49df-ae1c-80f10e91c13b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564806506 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_hrst.1564806506
Directory /workspace/37.i2c_target_hrst/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2049778513
Short name T757
Test name
Test status
Simulation time 2479798153 ps
CPU time 7.11 seconds
Started Jun 27 04:51:53 PM PDT 24
Finished Jun 27 04:52:05 PM PDT 24
Peak memory 218460 kb
Host smart-af01b85c-fc12-492c-a0b5-9750296e0502
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049778513 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2049778513
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.168504118
Short name T218
Test name
Test status
Simulation time 8060750546 ps
CPU time 4.87 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 204956 kb
Host smart-e2375daa-b693-402d-b8ce-0568ec439f20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168504118 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.168504118
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.509521613
Short name T546
Test name
Test status
Simulation time 1172854801 ps
CPU time 13.92 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:52:06 PM PDT 24
Peak memory 204732 kb
Host smart-45b77047-49c7-4ee5-ab09-142bcfffc88a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509521613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_tar
get_smoke.509521613
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1427276019
Short name T792
Test name
Test status
Simulation time 2608522702 ps
CPU time 33.16 seconds
Started Jun 27 04:51:56 PM PDT 24
Finished Jun 27 04:52:32 PM PDT 24
Peak memory 225532 kb
Host smart-99b7d332-d2d0-4d5d-96be-8051d35ba73a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427276019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1427276019
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.1006919221
Short name T533
Test name
Test status
Simulation time 44979170777 ps
CPU time 80.39 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:53:15 PM PDT 24
Peak memory 1355828 kb
Host smart-8cc4bbe9-0dde-4837-8601-daeebf131ccb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006919221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.1006919221
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.2061097878
Short name T1390
Test name
Test status
Simulation time 13986621843 ps
CPU time 1005.13 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 05:08:40 PM PDT 24
Peak memory 2420740 kb
Host smart-94ccc48d-b37c-465e-8340-17550d6e4a3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061097878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.2061097878
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.3223932350
Short name T1025
Test name
Test status
Simulation time 5535743289 ps
CPU time 7.88 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:52:01 PM PDT 24
Peak memory 204976 kb
Host smart-eaab0846-8f3b-4da0-b9b6-578f8e17c16d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223932350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.3223932350
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2602517694
Short name T614
Test name
Test status
Simulation time 19258747 ps
CPU time 0.62 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 204384 kb
Host smart-5c2095d3-46b6-4200-9045-84d5b5b22225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602517694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2602517694
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.3724625411
Short name T1036
Test name
Test status
Simulation time 223591180 ps
CPU time 2.46 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:52:00 PM PDT 24
Peak memory 212832 kb
Host smart-17c42dd4-5bd0-4972-9dd3-339283f65baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724625411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.3724625411
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1867829148
Short name T1165
Test name
Test status
Simulation time 449772551 ps
CPU time 22.42 seconds
Started Jun 27 04:51:57 PM PDT 24
Finished Jun 27 04:52:22 PM PDT 24
Peak memory 288748 kb
Host smart-8f3f0267-1841-4711-8b69-45630590361f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867829148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1867829148
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1097635345
Short name T1268
Test name
Test status
Simulation time 4258301738 ps
CPU time 81.67 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:53:15 PM PDT 24
Peak memory 738184 kb
Host smart-70bab4dd-13ba-4c4d-8dab-ac257e5f7a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097635345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1097635345
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.4181575921
Short name T761
Test name
Test status
Simulation time 2450542447 ps
CPU time 77.52 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:53:10 PM PDT 24
Peak memory 723552 kb
Host smart-a5c3eb92-3aaa-4c9a-a7e5-f9026d60fef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181575921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.4181575921
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.745336191
Short name T1295
Test name
Test status
Simulation time 141165458 ps
CPU time 0.94 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:51:57 PM PDT 24
Peak memory 204484 kb
Host smart-26b9d71c-9b8e-4d67-b58a-95c544abcae0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745336191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_fm
t.745336191
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.709466557
Short name T1011
Test name
Test status
Simulation time 527821082 ps
CPU time 7.81 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:52:04 PM PDT 24
Peak memory 229504 kb
Host smart-483c4cb0-909b-4c07-8e35-d9ebada5381e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709466557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
709466557
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.755095047
Short name T696
Test name
Test status
Simulation time 4650538514 ps
CPU time 310.4 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:57:03 PM PDT 24
Peak memory 1319264 kb
Host smart-bc71c065-373a-4a88-b950-f00c9d71c547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755095047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.755095047
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.975484457
Short name T259
Test name
Test status
Simulation time 1142776060 ps
CPU time 7.18 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:52:03 PM PDT 24
Peak memory 204832 kb
Host smart-ec1d176f-67b7-4184-acd4-541851c1b929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975484457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.975484457
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1762387813
Short name T1479
Test name
Test status
Simulation time 4849249362 ps
CPU time 40.92 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:52:33 PM PDT 24
Peak memory 461384 kb
Host smart-b9aa4aa4-ee10-4a72-944f-34802a9d5273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762387813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1762387813
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.1136828351
Short name T364
Test name
Test status
Simulation time 18651133 ps
CPU time 0.65 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:51:52 PM PDT 24
Peak memory 204516 kb
Host smart-b9a37870-7658-4fc2-bf18-88000a59bcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136828351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.1136828351
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2104443752
Short name T369
Test name
Test status
Simulation time 8091044348 ps
CPU time 54.01 seconds
Started Jun 27 04:51:48 PM PDT 24
Finished Jun 27 04:52:45 PM PDT 24
Peak memory 605244 kb
Host smart-181a51a4-b1f2-4fb0-b983-de50617e55f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104443752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2104443752
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.627304339
Short name T942
Test name
Test status
Simulation time 134180750 ps
CPU time 1.56 seconds
Started Jun 27 04:51:46 PM PDT 24
Finished Jun 27 04:51:50 PM PDT 24
Peak memory 213172 kb
Host smart-e0e9f9b3-1cbd-4ede-9fe8-9afc4c064fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627304339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.627304339
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.769505038
Short name T974
Test name
Test status
Simulation time 2027722092 ps
CPU time 31.36 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:52:24 PM PDT 24
Peak memory 387300 kb
Host smart-166b348c-fc5f-4ae3-a07e-f0734b2f39f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769505038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.769505038
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.1207074852
Short name T1460
Test name
Test status
Simulation time 13668169482 ps
CPU time 72.07 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:53:08 PM PDT 24
Peak memory 402788 kb
Host smart-8e46509c-84e2-4843-b6e9-1c7f29e1f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207074852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.1207074852
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.1469728336
Short name T371
Test name
Test status
Simulation time 919808136 ps
CPU time 16.35 seconds
Started Jun 27 04:51:47 PM PDT 24
Finished Jun 27 04:52:06 PM PDT 24
Peak memory 212964 kb
Host smart-3d1e79ae-d5db-47c9-9893-9d55a3f34158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469728336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.1469728336
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.358200238
Short name T1141
Test name
Test status
Simulation time 7308954922 ps
CPU time 5.24 seconds
Started Jun 27 04:51:53 PM PDT 24
Finished Jun 27 04:52:03 PM PDT 24
Peak memory 213164 kb
Host smart-f974f680-04a8-4e6c-82e3-b4b43dd43184
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358200238 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.358200238
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2574444023
Short name T1399
Test name
Test status
Simulation time 200256821 ps
CPU time 1.26 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:51:57 PM PDT 24
Peak memory 204632 kb
Host smart-8d1cd16a-9ea1-49ad-a458-7a3658e6a122
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574444023 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2574444023
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3239441142
Short name T14
Test name
Test status
Simulation time 166255469 ps
CPU time 1.09 seconds
Started Jun 27 04:51:53 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 204644 kb
Host smart-e7f1fec2-7d88-4f66-84b2-301a83411c37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239441142 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3239441142
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.58434642
Short name T21
Test name
Test status
Simulation time 3861846118 ps
CPU time 2.55 seconds
Started Jun 27 04:52:13 PM PDT 24
Finished Jun 27 04:52:18 PM PDT 24
Peak memory 204976 kb
Host smart-bc9d74a3-8ca4-4835-b99b-4c2f2ff0a793
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58434642 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.58434642
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.1565507682
Short name T380
Test name
Test status
Simulation time 119178157 ps
CPU time 1.06 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 04:51:55 PM PDT 24
Peak memory 204616 kb
Host smart-a3cd7d25-ec77-4f04-9d53-8294df52bde7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565507682 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.1565507682
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3166358565
Short name T332
Test name
Test status
Simulation time 2055415606 ps
CPU time 1.96 seconds
Started Jun 27 04:51:53 PM PDT 24
Finished Jun 27 04:51:59 PM PDT 24
Peak memory 204796 kb
Host smart-49ebddf9-f996-4922-88cb-12283579e1e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166358565 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3166358565
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.3310823147
Short name T330
Test name
Test status
Simulation time 5270193168 ps
CPU time 6.1 seconds
Started Jun 27 04:51:49 PM PDT 24
Finished Jun 27 04:51:58 PM PDT 24
Peak memory 220040 kb
Host smart-a0ef6ccf-1c95-447c-a1ed-0adf90977f7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310823147 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.3310823147
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.1685855729
Short name T982
Test name
Test status
Simulation time 8956409073 ps
CPU time 28.81 seconds
Started Jun 27 04:51:59 PM PDT 24
Finished Jun 27 04:52:30 PM PDT 24
Peak memory 789400 kb
Host smart-0da29923-1610-4cb9-a72e-e689bfc1620f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685855729 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.1685855729
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.2676006378
Short name T1341
Test name
Test status
Simulation time 448879993 ps
CPU time 6.97 seconds
Started Jun 27 04:51:54 PM PDT 24
Finished Jun 27 04:52:05 PM PDT 24
Peak memory 204832 kb
Host smart-3c6265f7-2d3a-4956-9eaa-5d691b5f85ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676006378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.2676006378
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2764560906
Short name T445
Test name
Test status
Simulation time 5194023652 ps
CPU time 12.84 seconds
Started Jun 27 04:51:52 PM PDT 24
Finished Jun 27 04:52:09 PM PDT 24
Peak memory 208360 kb
Host smart-390e3c5f-8617-4d5f-bdca-8221bcc5c72d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764560906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2764560906
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.920776019
Short name T1476
Test name
Test status
Simulation time 33153976654 ps
CPU time 283.05 seconds
Started Jun 27 04:51:48 PM PDT 24
Finished Jun 27 04:56:34 PM PDT 24
Peak memory 3229264 kb
Host smart-ba005bf7-18e7-4981-b9a9-8a40f41eec28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920776019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_wr.920776019
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.1254605943
Short name T819
Test name
Test status
Simulation time 9687326823 ps
CPU time 885.16 seconds
Started Jun 27 04:51:50 PM PDT 24
Finished Jun 27 05:06:40 PM PDT 24
Peak memory 2422872 kb
Host smart-2d57b2db-de79-4f15-a774-eb61b22ea317
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254605943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_
target_stretch.1254605943
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.2309765183
Short name T892
Test name
Test status
Simulation time 6144979102 ps
CPU time 7.04 seconds
Started Jun 27 04:51:48 PM PDT 24
Finished Jun 27 04:51:57 PM PDT 24
Peak memory 218940 kb
Host smart-28e77b3b-dc44-4690-bb17-ff036bd29029
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309765183 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 38.i2c_target_timeout.2309765183
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_alert_test.4105807329
Short name T851
Test name
Test status
Simulation time 39435713 ps
CPU time 0.61 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:11 PM PDT 24
Peak memory 204500 kb
Host smart-909f25e5-3133-47b5-a347-e78feb6231eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105807329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.4105807329
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.3022155094
Short name T888
Test name
Test status
Simulation time 191180526 ps
CPU time 1.99 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:14 PM PDT 24
Peak memory 213072 kb
Host smart-5cd10b4f-3bc8-4bbc-b1b2-c93c088c4ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022155094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.3022155094
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.170815253
Short name T877
Test name
Test status
Simulation time 3736082518 ps
CPU time 29.25 seconds
Started Jun 27 04:51:48 PM PDT 24
Finished Jun 27 04:52:20 PM PDT 24
Peak memory 325164 kb
Host smart-b01ec814-50e9-43c6-8c6f-b6ecb8d8f70b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170815253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_empt
y.170815253
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.1636567451
Short name T215
Test name
Test status
Simulation time 10026594145 ps
CPU time 87.98 seconds
Started Jun 27 04:52:03 PM PDT 24
Finished Jun 27 04:53:33 PM PDT 24
Peak memory 884060 kb
Host smart-5e714407-b197-4a17-add3-dd72867c1900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636567451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.1636567451
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.669854096
Short name T509
Test name
Test status
Simulation time 1908552922 ps
CPU time 127.34 seconds
Started Jun 27 04:51:59 PM PDT 24
Finished Jun 27 04:54:09 PM PDT 24
Peak memory 655620 kb
Host smart-a6394ca4-7507-4a9c-9284-d29ca312249e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669854096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.669854096
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3507895216
Short name T1480
Test name
Test status
Simulation time 104415495 ps
CPU time 0.95 seconds
Started Jun 27 04:52:01 PM PDT 24
Finished Jun 27 04:52:04 PM PDT 24
Peak memory 204552 kb
Host smart-a5d6c8a7-21a6-42b3-9f3b-37beb8f7bdc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507895216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3507895216
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.3558188090
Short name T1262
Test name
Test status
Simulation time 412060628 ps
CPU time 4.97 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:16 PM PDT 24
Peak memory 204812 kb
Host smart-e97ae229-7da1-44e5-ae2f-4a11b427e794
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558188090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.3558188090
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.1165931248
Short name T1178
Test name
Test status
Simulation time 5442227479 ps
CPU time 158.53 seconds
Started Jun 27 04:51:56 PM PDT 24
Finished Jun 27 04:54:38 PM PDT 24
Peak memory 804876 kb
Host smart-e43bf6fc-93ee-46af-ae5c-a0853e19d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165931248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.1165931248
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.269745520
Short name T1194
Test name
Test status
Simulation time 422918787 ps
CPU time 6.46 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:18 PM PDT 24
Peak memory 204712 kb
Host smart-6851c48f-2ba0-42d5-a806-a0763f5b1cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269745520 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.269745520
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.2866479990
Short name T929
Test name
Test status
Simulation time 1549178013 ps
CPU time 71.84 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:53:24 PM PDT 24
Peak memory 361372 kb
Host smart-f16cb161-c561-49b6-8f2a-aa9db2d5b50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866479990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.2866479990
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.1599970282
Short name T552
Test name
Test status
Simulation time 18710206 ps
CPU time 0.69 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:51:56 PM PDT 24
Peak memory 204532 kb
Host smart-02cabb1a-5b8f-4ad9-bd20-008e0b58d492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599970282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.1599970282
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.108720344
Short name T527
Test name
Test status
Simulation time 7955348900 ps
CPU time 11 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:19 PM PDT 24
Peak memory 333452 kb
Host smart-fb62014f-f7ca-47bd-ae7b-be4b7472b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108720344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.108720344
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.3743171364
Short name T78
Test name
Test status
Simulation time 265796662 ps
CPU time 4.15 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:16 PM PDT 24
Peak memory 222720 kb
Host smart-9c3664cc-685e-4d54-b880-14434daca7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743171364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.3743171364
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1039694651
Short name T936
Test name
Test status
Simulation time 1681501366 ps
CPU time 85.28 seconds
Started Jun 27 04:51:51 PM PDT 24
Finished Jun 27 04:53:21 PM PDT 24
Peak memory 382748 kb
Host smart-4ca04e52-b851-4aed-ae45-7c2540eef809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039694651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1039694651
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.3582298094
Short name T123
Test name
Test status
Simulation time 10520539608 ps
CPU time 294.96 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:57:03 PM PDT 24
Peak memory 1782620 kb
Host smart-15684feb-8a66-4c48-8cb8-1b952bdb8481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582298094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.3582298094
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.2019236621
Short name T1218
Test name
Test status
Simulation time 1589135812 ps
CPU time 35.7 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:42 PM PDT 24
Peak memory 212972 kb
Host smart-4b8b9221-789b-4c33-853f-f21c6b3962b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019236621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2019236621
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.2975486819
Short name T824
Test name
Test status
Simulation time 5201236513 ps
CPU time 5.37 seconds
Started Jun 27 04:52:03 PM PDT 24
Finished Jun 27 04:52:11 PM PDT 24
Peak memory 215924 kb
Host smart-c16eb950-0475-47a1-8f99-ac7de4f359c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975486819 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.2975486819
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.596862270
Short name T1260
Test name
Test status
Simulation time 618467078 ps
CPU time 0.9 seconds
Started Jun 27 04:52:10 PM PDT 24
Finished Jun 27 04:52:16 PM PDT 24
Peak memory 204628 kb
Host smart-5fe10efc-d9dc-40cc-b21d-a46e7d60b0eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596862270 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_acq.596862270
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.1976146013
Short name T466
Test name
Test status
Simulation time 110204389 ps
CPU time 0.97 seconds
Started Jun 27 04:52:01 PM PDT 24
Finished Jun 27 04:52:04 PM PDT 24
Peak memory 204596 kb
Host smart-c2d1c2eb-2cb1-4e86-b2e7-76ecddc06fb3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976146013 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.1976146013
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.2085440429
Short name T1420
Test name
Test status
Simulation time 3193254119 ps
CPU time 2.49 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:11 PM PDT 24
Peak memory 204976 kb
Host smart-fbac8fbe-fab9-4bba-baf4-6b51eeb0d3bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085440429 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.2085440429
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.1385861804
Short name T729
Test name
Test status
Simulation time 1175661032 ps
CPU time 1.11 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:12 PM PDT 24
Peak memory 204616 kb
Host smart-55c0ec80-1020-47a6-a41a-ab2735fb1389
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385861804 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.1385861804
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.2880318138
Short name T500
Test name
Test status
Simulation time 593245682 ps
CPU time 2.65 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:52:15 PM PDT 24
Peak memory 204816 kb
Host smart-38b66254-04fe-45da-9f2b-b73d0f0456c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880318138 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.2880318138
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.1523441262
Short name T1450
Test name
Test status
Simulation time 23467609002 ps
CPU time 5.76 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:15 PM PDT 24
Peak memory 212984 kb
Host smart-3a259d71-128b-4d0f-9a5d-a23ce8a75f00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523441262 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.1523441262
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.142142892
Short name T838
Test name
Test status
Simulation time 11014493279 ps
CPU time 54.44 seconds
Started Jun 27 04:52:09 PM PDT 24
Finished Jun 27 04:53:08 PM PDT 24
Peak memory 1044612 kb
Host smart-e4f3bbc4-8149-4241-a62c-ec23559fe109
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142142892 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.142142892
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2069935044
Short name T26
Test name
Test status
Simulation time 5677307469 ps
CPU time 23.59 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:31 PM PDT 24
Peak memory 204856 kb
Host smart-3621c53f-ccda-4936-afe4-1826d9677714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069935044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2069935044
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.2540797677
Short name T394
Test name
Test status
Simulation time 749105130 ps
CPU time 29.75 seconds
Started Jun 27 04:52:08 PM PDT 24
Finished Jun 27 04:52:43 PM PDT 24
Peak memory 204660 kb
Host smart-e3b34f8f-16a6-4242-91d9-076269bbd3a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540797677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_rd.2540797677
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.2392113215
Short name T307
Test name
Test status
Simulation time 7623723470 ps
CPU time 14.42 seconds
Started Jun 27 04:52:03 PM PDT 24
Finished Jun 27 04:52:19 PM PDT 24
Peak memory 204860 kb
Host smart-e996bef3-a965-45a9-8512-3fdb0508aba2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392113215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.2392113215
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.2650059081
Short name T430
Test name
Test status
Simulation time 14395870206 ps
CPU time 91.47 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:53:39 PM PDT 24
Peak memory 866956 kb
Host smart-f7e7b3a0-ffb2-43c2-85ba-fdca04ff00c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650059081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.2650059081
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.2742458409
Short name T1169
Test name
Test status
Simulation time 5193952884 ps
CPU time 7.59 seconds
Started Jun 27 04:52:00 PM PDT 24
Finished Jun 27 04:52:10 PM PDT 24
Peak memory 221248 kb
Host smart-f892a04c-9099-4340-a8b9-1af2fa2f1476
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742458409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.2742458409
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_alert_test.2685893771
Short name T477
Test name
Test status
Simulation time 18687421 ps
CPU time 0.62 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:31 PM PDT 24
Peak memory 204360 kb
Host smart-985cc9d0-b877-4f7b-bc43-8864a05a4e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685893771 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.2685893771
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.3076909000
Short name T1407
Test name
Test status
Simulation time 169430821 ps
CPU time 2.46 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:22 PM PDT 24
Peak memory 223432 kb
Host smart-6f90b6c9-e13e-47e7-9b41-eca0677453fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076909000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.3076909000
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2983666812
Short name T1456
Test name
Test status
Simulation time 163081392 ps
CPU time 3.64 seconds
Started Jun 27 04:48:55 PM PDT 24
Finished Jun 27 04:49:02 PM PDT 24
Peak memory 228784 kb
Host smart-eda3970e-a289-41fa-96e9-507dbfa823ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983666812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2983666812
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3925390791
Short name T830
Test name
Test status
Simulation time 6674630291 ps
CPU time 101.61 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:50:38 PM PDT 24
Peak memory 589540 kb
Host smart-12548516-7cc8-47b5-9070-a081c59861ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925390791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3925390791
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.175458424
Short name T1274
Test name
Test status
Simulation time 13227846847 ps
CPU time 79.5 seconds
Started Jun 27 04:49:00 PM PDT 24
Finished Jun 27 04:50:21 PM PDT 24
Peak memory 670084 kb
Host smart-5b7ea565-d171-462e-8041-4588eb3b0127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175458424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.175458424
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.123852715
Short name T425
Test name
Test status
Simulation time 740738371 ps
CPU time 1.04 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:48:56 PM PDT 24
Peak memory 204476 kb
Host smart-3b771e15-82cc-484f-b625-bde85e56a51f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123852715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fmt
.123852715
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2822421947
Short name T770
Test name
Test status
Simulation time 190012826 ps
CPU time 4.63 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:48:57 PM PDT 24
Peak memory 241596 kb
Host smart-7b626198-a0d3-4507-923a-0998ceb7c7d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822421947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2822421947
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.4272242585
Short name T865
Test name
Test status
Simulation time 25392413197 ps
CPU time 290.09 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:53:57 PM PDT 24
Peak memory 1154716 kb
Host smart-bf6a3a73-8268-4731-b30d-6f4cfecec859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272242585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.4272242585
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3214745706
Short name T46
Test name
Test status
Simulation time 408961723 ps
CPU time 5.04 seconds
Started Jun 27 04:49:03 PM PDT 24
Finished Jun 27 04:49:11 PM PDT 24
Peak memory 204736 kb
Host smart-8b59d0ca-42ff-4c11-8a8d-f591fe183f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214745706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3214745706
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.2954166466
Short name T1483
Test name
Test status
Simulation time 1526262610 ps
CPU time 28.91 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:50 PM PDT 24
Peak memory 316596 kb
Host smart-d973fc92-1897-47c9-a197-a8b2fbeaedce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954166466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.2954166466
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.2138727186
Short name T388
Test name
Test status
Simulation time 29325186 ps
CPU time 0.67 seconds
Started Jun 27 04:48:54 PM PDT 24
Finished Jun 27 04:48:57 PM PDT 24
Peak memory 204532 kb
Host smart-b8ddfa32-7f48-48ef-821a-15de852ffbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138727186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.2138727186
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.132010957
Short name T531
Test name
Test status
Simulation time 228874566 ps
CPU time 5.25 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:26 PM PDT 24
Peak memory 215012 kb
Host smart-0fc870a5-63ed-43a2-b563-43d54d2e5029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132010957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.132010957
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.1213046849
Short name T1008
Test name
Test status
Simulation time 96128176 ps
CPU time 2.27 seconds
Started Jun 27 04:48:47 PM PDT 24
Finished Jun 27 04:48:56 PM PDT 24
Peak memory 225408 kb
Host smart-387884b1-835b-4ea2-84b3-c5060369c22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213046849 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.1213046849
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3347109493
Short name T427
Test name
Test status
Simulation time 5432533658 ps
CPU time 61.7 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:49:56 PM PDT 24
Peak memory 284648 kb
Host smart-2a3bf7d0-14b3-4357-be4a-8c0d2b924001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347109493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3347109493
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.2087394563
Short name T1372
Test name
Test status
Simulation time 548712335 ps
CPU time 8.66 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:49:05 PM PDT 24
Peak memory 213020 kb
Host smart-dd3ffd8a-7cbb-4a8f-a5cc-3f69e8f52f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087394563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.2087394563
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.483047611
Short name T1071
Test name
Test status
Simulation time 3199401808 ps
CPU time 4.4 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:15 PM PDT 24
Peak memory 213624 kb
Host smart-e84891af-c82f-4565-81b3-02e0307b9683
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483047611 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.483047611
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.1622586368
Short name T823
Test name
Test status
Simulation time 218565679 ps
CPU time 0.96 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 212796 kb
Host smart-855eb164-eb37-417b-ad08-2f44dbb1fa1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622586368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.1622586368
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.2129985422
Short name T933
Test name
Test status
Simulation time 282996326 ps
CPU time 0.81 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 212420 kb
Host smart-85e6d904-28b4-4772-ad8d-1df676ddf5f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129985422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.2129985422
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.2134342904
Short name T1324
Test name
Test status
Simulation time 616387700 ps
CPU time 3.08 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:34 PM PDT 24
Peak memory 204736 kb
Host smart-8127cafa-7cf6-4733-9147-aa5f0aa969ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134342904 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.2134342904
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.2868965480
Short name T1087
Test name
Test status
Simulation time 428759076 ps
CPU time 1.25 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:48:57 PM PDT 24
Peak memory 204628 kb
Host smart-73651691-a599-470d-b292-5062bb0806ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868965480 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.2868965480
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.3418804050
Short name T1133
Test name
Test status
Simulation time 2116519874 ps
CPU time 3.13 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:16 PM PDT 24
Peak memory 204668 kb
Host smart-c6e0246d-a0b4-4b99-9f00-183c34b1c32a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418804050 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.3418804050
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.3186977391
Short name T463
Test name
Test status
Simulation time 5239561199 ps
CPU time 3.56 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:24 PM PDT 24
Peak memory 204984 kb
Host smart-b177e909-f51b-415a-b7ed-e7e4c55ac6a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186977391 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.3186977391
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3043488637
Short name T160
Test name
Test status
Simulation time 2928068174 ps
CPU time 27.71 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 204772 kb
Host smart-8ab3e94e-46e3-45f6-8ff7-06b03e2d4ee3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043488637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3043488637
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1995713365
Short name T665
Test name
Test status
Simulation time 1452248343 ps
CPU time 59.06 seconds
Started Jun 27 04:48:57 PM PDT 24
Finished Jun 27 04:49:59 PM PDT 24
Peak memory 206904 kb
Host smart-c0c225bc-5c2f-4ae9-b690-1c3971c609b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995713365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1995713365
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1716896722
Short name T588
Test name
Test status
Simulation time 14833314258 ps
CPU time 8.45 seconds
Started Jun 27 04:48:59 PM PDT 24
Finished Jun 27 04:49:10 PM PDT 24
Peak memory 204908 kb
Host smart-42406f8a-7518-4a1e-ba0e-61b73181cc0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716896722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1716896722
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.356372613
Short name T475
Test name
Test status
Simulation time 38151507378 ps
CPU time 89.07 seconds
Started Jun 27 04:48:49 PM PDT 24
Finished Jun 27 04:50:20 PM PDT 24
Peak memory 906176 kb
Host smart-70c7466c-8039-4d96-a6c6-f7e3bde2f6af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356372613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.356372613
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.4265599965
Short name T1146
Test name
Test status
Simulation time 3374535583 ps
CPU time 7.21 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 212904 kb
Host smart-4be09476-6491-4df3-9fbd-540f293617b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265599965 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.4265599965
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_alert_test.3844199077
Short name T1220
Test name
Test status
Simulation time 15921745 ps
CPU time 0.63 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:52:13 PM PDT 24
Peak memory 204460 kb
Host smart-df799f19-6f17-4ce2-82a2-79aacff649b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844199077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.3844199077
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1873107391
Short name T40
Test name
Test status
Simulation time 418265310 ps
CPU time 3.61 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:10 PM PDT 24
Peak memory 220240 kb
Host smart-112df1a7-a697-4023-8408-0f293d0d59d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873107391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1873107391
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.1223810062
Short name T1155
Test name
Test status
Simulation time 804755440 ps
CPU time 3.97 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:13 PM PDT 24
Peak memory 243888 kb
Host smart-52656469-3bd0-486c-896a-eddc8bb6138f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223810062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.1223810062
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.3790480159
Short name T183
Test name
Test status
Simulation time 7159471179 ps
CPU time 149.87 seconds
Started Jun 27 04:52:03 PM PDT 24
Finished Jun 27 04:54:34 PM PDT 24
Peak memory 741956 kb
Host smart-6dd0021a-c9e7-4f2c-ae51-97f4da55869e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790480159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.3790480159
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.4152480712
Short name T436
Test name
Test status
Simulation time 1703401567 ps
CPU time 117.32 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:54:05 PM PDT 24
Peak memory 628196 kb
Host smart-26ee7173-66c5-4b41-99fe-e45bea524514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152480712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.4152480712
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1200764443
Short name T1298
Test name
Test status
Simulation time 564181971 ps
CPU time 1.2 seconds
Started Jun 27 04:52:03 PM PDT 24
Finished Jun 27 04:52:06 PM PDT 24
Peak memory 204692 kb
Host smart-d7218059-cfa4-4f5b-a1f2-26a918fdc932
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200764443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1200764443
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.616302080
Short name T705
Test name
Test status
Simulation time 197031117 ps
CPU time 9.81 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:16 PM PDT 24
Peak memory 204804 kb
Host smart-1171235e-672e-4abb-a91f-b61dd4d0963f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616302080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx.
616302080
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.113592342
Short name T1179
Test name
Test status
Simulation time 8246528530 ps
CPU time 122.39 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:54:15 PM PDT 24
Peak memory 1235260 kb
Host smart-22b97aa6-37ee-4295-8008-7d337042efaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113592342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.113592342
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2361868428
Short name T1398
Test name
Test status
Simulation time 397327279 ps
CPU time 4.72 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:14 PM PDT 24
Peak memory 204836 kb
Host smart-dc6f7ea0-e8c2-4e55-a72b-323064b89b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361868428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2361868428
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3638498306
Short name T882
Test name
Test status
Simulation time 843802873 ps
CPU time 13.46 seconds
Started Jun 27 04:52:09 PM PDT 24
Finished Jun 27 04:52:27 PM PDT 24
Peak memory 276944 kb
Host smart-81bafd20-ecad-418d-96c4-45c5155d8c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638498306 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3638498306
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_perf.3183938998
Short name T798
Test name
Test status
Simulation time 5621478556 ps
CPU time 24.1 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:36 PM PDT 24
Peak memory 371648 kb
Host smart-7d06f8c8-90fc-4cc2-9f86-5d5499695c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183938998 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.3183938998
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.3234942696
Short name T569
Test name
Test status
Simulation time 215316571 ps
CPU time 8.76 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:16 PM PDT 24
Peak memory 204772 kb
Host smart-3afcb040-cec7-47a1-a2c4-89eec3936a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234942696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.3234942696
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.2907928406
Short name T742
Test name
Test status
Simulation time 1584136716 ps
CPU time 26.03 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:32 PM PDT 24
Peak memory 356080 kb
Host smart-e440530d-90d4-4a02-ba06-97b15ef5acb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907928406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.2907928406
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.2224412214
Short name T641
Test name
Test status
Simulation time 23368718362 ps
CPU time 418.14 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:59:09 PM PDT 24
Peak memory 1869256 kb
Host smart-b9ff80c8-361f-4874-9152-46b7fcdd2167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224412214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.2224412214
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3212769247
Short name T277
Test name
Test status
Simulation time 3258345392 ps
CPU time 35.7 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:43 PM PDT 24
Peak memory 214204 kb
Host smart-c8cf1b4f-6c92-4b60-bf1e-d47b2c546ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212769247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3212769247
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2779667344
Short name T1419
Test name
Test status
Simulation time 3783972197 ps
CPU time 4.66 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:14 PM PDT 24
Peak memory 204972 kb
Host smart-53867bc7-6757-48b7-bd8d-b6fab09c114e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779667344 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2779667344
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.3348059089
Short name T1329
Test name
Test status
Simulation time 204235230 ps
CPU time 1.32 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:52:13 PM PDT 24
Peak memory 204784 kb
Host smart-7f6b4381-ca57-47c9-a42a-5ef0c922253e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348059089 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.3348059089
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.388419811
Short name T412
Test name
Test status
Simulation time 182147973 ps
CPU time 0.88 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:12 PM PDT 24
Peak memory 204604 kb
Host smart-5a7d7dab-ca5c-4b34-8648-4ee66ac2585e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388419811 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.388419811
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.2136945237
Short name T1345
Test name
Test status
Simulation time 208856930 ps
CPU time 0.79 seconds
Started Jun 27 04:52:09 PM PDT 24
Finished Jun 27 04:52:14 PM PDT 24
Peak memory 204508 kb
Host smart-a99708e0-3510-4c96-9889-e7c2038143bc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136945237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.2136945237
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.3687532578
Short name T1285
Test name
Test status
Simulation time 292175222 ps
CPU time 1.28 seconds
Started Jun 27 04:52:10 PM PDT 24
Finished Jun 27 04:52:16 PM PDT 24
Peak memory 204588 kb
Host smart-e2c87995-4530-4dda-9354-103e6f69b9bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687532578 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.3687532578
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.2728680744
Short name T1209
Test name
Test status
Simulation time 361156833 ps
CPU time 3.12 seconds
Started Jun 27 04:52:10 PM PDT 24
Finished Jun 27 04:52:17 PM PDT 24
Peak memory 204840 kb
Host smart-ce90478e-9ab0-45a9-844c-1df5a5422b39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728680744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.2728680744
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.3781435248
Short name T996
Test name
Test status
Simulation time 764780391 ps
CPU time 4.52 seconds
Started Jun 27 04:52:03 PM PDT 24
Finished Jun 27 04:52:10 PM PDT 24
Peak memory 204808 kb
Host smart-d185c8c8-5d9a-41b0-b30f-28a1826fe370
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781435248 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.3781435248
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.101274446
Short name T726
Test name
Test status
Simulation time 15555196738 ps
CPU time 135.9 seconds
Started Jun 27 04:52:10 PM PDT 24
Finished Jun 27 04:54:31 PM PDT 24
Peak memory 2098604 kb
Host smart-8821eb33-1d12-49bf-a462-90936c741a84
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101274446 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.101274446
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.3511734775
Short name T1427
Test name
Test status
Simulation time 755251698 ps
CPU time 27.17 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:36 PM PDT 24
Peak memory 204780 kb
Host smart-75a09a28-d384-4e39-9abd-987c3c85235a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511734775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_ta
rget_smoke.3511734775
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2005693598
Short name T1271
Test name
Test status
Simulation time 7931349755 ps
CPU time 11.63 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:52:24 PM PDT 24
Peak memory 211424 kb
Host smart-8be3e3e6-0d2f-41f5-8040-31f58d3fd3e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005693598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2005693598
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.171160305
Short name T303
Test name
Test status
Simulation time 51002233108 ps
CPU time 1073.45 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 05:10:06 PM PDT 24
Peak memory 7629848 kb
Host smart-99952959-1142-4070-ad42-8f2e0c3896f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171160305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c
_target_stress_wr.171160305
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.2681596896
Short name T1440
Test name
Test status
Simulation time 31648313084 ps
CPU time 522.24 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 05:00:49 PM PDT 24
Peak memory 1824044 kb
Host smart-4507e6a1-64d4-4b6f-95f2-6b99685d1ec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681596896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.2681596896
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.872405031
Short name T363
Test name
Test status
Simulation time 1572633385 ps
CPU time 7.03 seconds
Started Jun 27 04:52:08 PM PDT 24
Finished Jun 27 04:52:20 PM PDT 24
Peak memory 213136 kb
Host smart-7c60ae5e-dd14-44ec-afc4-e9b69ed3ff99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872405031 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_timeout.872405031
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_alert_test.677775993
Short name T1328
Test name
Test status
Simulation time 42797472 ps
CPU time 0.61 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:29 PM PDT 24
Peak memory 204488 kb
Host smart-34bfd7a3-cada-442b-a856-17b848a1c133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677775993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.677775993
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3566061107
Short name T479
Test name
Test status
Simulation time 228356996 ps
CPU time 1.84 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:52:13 PM PDT 24
Peak memory 213036 kb
Host smart-e3b7458d-d09e-4440-8d4a-d6641ee5cee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566061107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3566061107
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.183271222
Short name T730
Test name
Test status
Simulation time 931533031 ps
CPU time 7.58 seconds
Started Jun 27 04:52:09 PM PDT 24
Finished Jun 27 04:52:22 PM PDT 24
Peak memory 283956 kb
Host smart-ac60cfdb-8843-45e8-aede-ef464f41f733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183271222 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.183271222
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3832990429
Short name T1128
Test name
Test status
Simulation time 3495563866 ps
CPU time 53.14 seconds
Started Jun 27 04:52:12 PM PDT 24
Finished Jun 27 04:53:08 PM PDT 24
Peak memory 578124 kb
Host smart-1246db76-a0fa-4e90-98c3-4bab61e5f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832990429 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3832990429
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1824203985
Short name T1439
Test name
Test status
Simulation time 10131785403 ps
CPU time 87.88 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:53:40 PM PDT 24
Peak memory 803732 kb
Host smart-0be3d731-e74b-4b88-9989-9a5733ff696a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824203985 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1824203985
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.3108593921
Short name T1095
Test name
Test status
Simulation time 1526447835 ps
CPU time 0.9 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:52:13 PM PDT 24
Peak memory 204460 kb
Host smart-6369335a-67b2-4155-bf9b-16ce1e6c302d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108593921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.3108593921
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.425934717
Short name T1423
Test name
Test status
Simulation time 150241776 ps
CPU time 8.87 seconds
Started Jun 27 04:52:15 PM PDT 24
Finished Jun 27 04:52:25 PM PDT 24
Peak memory 231256 kb
Host smart-d0e4de4b-00dc-4f76-a188-508c8f7e87cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425934717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
425934717
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.4157212547
Short name T185
Test name
Test status
Simulation time 23339373076 ps
CPU time 127.6 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:54:19 PM PDT 24
Peak memory 1255840 kb
Host smart-bdebd725-ed22-4853-bf5c-3a9354de49da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157212547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.4157212547
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.1893144842
Short name T566
Test name
Test status
Simulation time 4525455635 ps
CPU time 7.62 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:52:32 PM PDT 24
Peak memory 204884 kb
Host smart-141bd61e-fb20-4f27-b79a-8d41d9f5e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893144842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.1893144842
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.995976646
Short name T1474
Test name
Test status
Simulation time 2974008744 ps
CPU time 19.84 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:51 PM PDT 24
Peak memory 295124 kb
Host smart-6da911c8-9e4e-4b83-85c5-83cfaf3b7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995976646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.995976646
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.495844055
Short name T535
Test name
Test status
Simulation time 128831117 ps
CPU time 0.64 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:10 PM PDT 24
Peak memory 204520 kb
Host smart-d3212481-f581-4e1d-8135-f1366dc86bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495844055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.495844055
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.2108654836
Short name T366
Test name
Test status
Simulation time 50471186707 ps
CPU time 234.21 seconds
Started Jun 27 04:52:09 PM PDT 24
Finished Jun 27 04:56:08 PM PDT 24
Peak memory 204828 kb
Host smart-ec5077c3-6845-43cf-af8a-d0e26bdbf4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108654836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.2108654836
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.1526780948
Short name T1410
Test name
Test status
Simulation time 2928533744 ps
CPU time 31.59 seconds
Started Jun 27 04:52:04 PM PDT 24
Finished Jun 27 04:52:39 PM PDT 24
Peak memory 204916 kb
Host smart-8527a1a0-119e-48ab-8bb6-41a3ec2087a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526780948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.1526780948
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.2802657375
Short name T360
Test name
Test status
Simulation time 1634825860 ps
CPU time 51.74 seconds
Started Jun 27 04:52:06 PM PDT 24
Finished Jun 27 04:53:03 PM PDT 24
Peak memory 232612 kb
Host smart-11439282-8e65-406d-884f-0c030eed56cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802657375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.2802657375
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1187480389
Short name T278
Test name
Test status
Simulation time 1477817835 ps
CPU time 10.62 seconds
Started Jun 27 04:52:10 PM PDT 24
Finished Jun 27 04:52:25 PM PDT 24
Peak memory 221236 kb
Host smart-b60b8991-9964-4e00-aafb-1c6b7247a07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187480389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1187480389
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.936283249
Short name T516
Test name
Test status
Simulation time 744504748 ps
CPU time 4.12 seconds
Started Jun 27 04:52:21 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 213068 kb
Host smart-ce341fa4-1619-4587-b349-357ecfd6567f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936283249 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.936283249
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3672153333
Short name T1075
Test name
Test status
Simulation time 394800943 ps
CPU time 1.14 seconds
Started Jun 27 04:52:07 PM PDT 24
Finished Jun 27 04:52:13 PM PDT 24
Peak memory 204780 kb
Host smart-11c1af9d-705c-485f-bf43-48298f55081e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672153333 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3672153333
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.2812311749
Short name T870
Test name
Test status
Simulation time 159164220 ps
CPU time 1.1 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:32 PM PDT 24
Peak memory 204592 kb
Host smart-fe30c284-bd4a-4ebd-8b83-6dfb6c4be716
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812311749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.2812311749
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.356971844
Short name T1045
Test name
Test status
Simulation time 1436565612 ps
CPU time 2.35 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:33 PM PDT 24
Peak memory 204788 kb
Host smart-381c74b9-203d-444c-a330-eb69bfcc4e74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356971844 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.356971844
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.3823725549
Short name T1079
Test name
Test status
Simulation time 97796856 ps
CPU time 0.82 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 204520 kb
Host smart-eacd892f-b441-43e6-915b-5b2698362bf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823725549 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3823725549
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.1832167267
Short name T1181
Test name
Test status
Simulation time 901303532 ps
CPU time 2.85 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:52:27 PM PDT 24
Peak memory 204840 kb
Host smart-51cc524e-190e-457f-8383-8d89f6e37fc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832167267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.1832167267
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.997000930
Short name T1014
Test name
Test status
Simulation time 4685792403 ps
CPU time 6.15 seconds
Started Jun 27 04:52:15 PM PDT 24
Finished Jun 27 04:52:22 PM PDT 24
Peak memory 217160 kb
Host smart-a96c79b6-87cd-417c-8b5f-a0f2f634b6cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997000930 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.997000930
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2046031375
Short name T1370
Test name
Test status
Simulation time 6647739714 ps
CPU time 3.76 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:13 PM PDT 24
Peak memory 254792 kb
Host smart-9cf4d5f2-5e13-4e46-8edf-98cdac434231
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046031375 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2046031375
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.429147410
Short name T1259
Test name
Test status
Simulation time 1005754312 ps
CPU time 12.99 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 04:52:22 PM PDT 24
Peak memory 204736 kb
Host smart-f74fbd49-a1fe-4fee-8b88-de4b3d4b660a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429147410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.429147410
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.796760767
Short name T916
Test name
Test status
Simulation time 2588479037 ps
CPU time 26.17 seconds
Started Jun 27 04:52:09 PM PDT 24
Finished Jun 27 04:52:40 PM PDT 24
Peak memory 204828 kb
Host smart-5982d39c-c2b4-48fd-a96c-f284f28ae497
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796760767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_rd.796760767
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.365542040
Short name T20
Test name
Test status
Simulation time 47688466733 ps
CPU time 121.7 seconds
Started Jun 27 04:52:09 PM PDT 24
Finished Jun 27 04:54:15 PM PDT 24
Peak memory 1858700 kb
Host smart-15e8560c-c347-448d-8884-8416876a68f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365542040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c
_target_stress_wr.365542040
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.855240569
Short name T1188
Test name
Test status
Simulation time 20635498129 ps
CPU time 1155.13 seconds
Started Jun 27 04:52:05 PM PDT 24
Finished Jun 27 05:11:24 PM PDT 24
Peak memory 5026752 kb
Host smart-32b47138-ae14-4e39-8f83-ab9dc317624f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855240569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_t
arget_stretch.855240569
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.1428446612
Short name T1187
Test name
Test status
Simulation time 1165360784 ps
CPU time 7.15 seconds
Started Jun 27 04:52:13 PM PDT 24
Finished Jun 27 04:52:23 PM PDT 24
Peak memory 212736 kb
Host smart-81ea2b50-06f4-47cf-a92a-43babada56a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428446612 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.1428446612
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_alert_test.920875135
Short name T598
Test name
Test status
Simulation time 24499072 ps
CPU time 0.6 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:52:32 PM PDT 24
Peak memory 204444 kb
Host smart-2b1476e9-9238-40c0-b5b2-9ea27f1a2c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920875135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.920875135
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.3457143964
Short name T697
Test name
Test status
Simulation time 197818739 ps
CPU time 1.56 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 221208 kb
Host smart-7d31a587-ec24-4bd1-8925-90f3b92908c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457143964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.3457143964
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.2117517817
Short name T634
Test name
Test status
Simulation time 719136137 ps
CPU time 17.76 seconds
Started Jun 27 04:52:31 PM PDT 24
Finished Jun 27 04:52:52 PM PDT 24
Peak memory 265976 kb
Host smart-3fb7ba84-9dec-4eea-a94b-ba42ed4218d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117517817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_emp
ty.2117517817
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.2852563802
Short name T1078
Test name
Test status
Simulation time 1290900399 ps
CPU time 36.62 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:53:06 PM PDT 24
Peak memory 475816 kb
Host smart-b1c86041-c9ae-408f-a59f-f83843e90d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852563802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.2852563802
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.2685310633
Short name T131
Test name
Test status
Simulation time 13929214500 ps
CPU time 46.71 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:53:11 PM PDT 24
Peak memory 582800 kb
Host smart-e05bc6bf-a11b-4310-843e-6912f2e645e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685310633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.2685310633
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.641764767
Short name T689
Test name
Test status
Simulation time 114119188 ps
CPU time 0.97 seconds
Started Jun 27 04:52:22 PM PDT 24
Finished Jun 27 04:52:25 PM PDT 24
Peak memory 204476 kb
Host smart-ff77286a-8fa8-419d-9065-c734afcc3a04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641764767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_fm
t.641764767
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.331382393
Short name T673
Test name
Test status
Simulation time 149495804 ps
CPU time 3.52 seconds
Started Jun 27 04:52:21 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 204864 kb
Host smart-cebc23f4-3718-4be6-b01a-5a10f21248a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331382393 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx.
331382393
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.539301594
Short name T600
Test name
Test status
Simulation time 5851976643 ps
CPU time 117.19 seconds
Started Jun 27 04:52:21 PM PDT 24
Finished Jun 27 04:54:19 PM PDT 24
Peak memory 1198868 kb
Host smart-738c569c-459c-4bca-a9d2-e2150762f083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539301594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.539301594
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.416077047
Short name T49
Test name
Test status
Simulation time 295985010 ps
CPU time 12 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:41 PM PDT 24
Peak memory 204864 kb
Host smart-e9771911-ea16-438d-828f-1e62b6c0b690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416077047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.416077047
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.1545201476
Short name T966
Test name
Test status
Simulation time 6655658916 ps
CPU time 87.74 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:53:57 PM PDT 24
Peak memory 459272 kb
Host smart-4171ce20-3896-4dc5-9e05-3cf546673b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545201476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.1545201476
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.4017873177
Short name T1270
Test name
Test status
Simulation time 18417286 ps
CPU time 0.63 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:30 PM PDT 24
Peak memory 204472 kb
Host smart-dfbc9835-2dea-4aa4-8226-6d3a5bf07cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017873177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.4017873177
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.189440185
Short name T2
Test name
Test status
Simulation time 934601387 ps
CPU time 22.45 seconds
Started Jun 27 04:52:20 PM PDT 24
Finished Jun 27 04:52:43 PM PDT 24
Peak memory 204820 kb
Host smart-f6ea81d3-3cf3-4433-8026-57ee6ce157f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189440185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.189440185
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.1337579970
Short name T114
Test name
Test status
Simulation time 229503579 ps
CPU time 1.36 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:52:33 PM PDT 24
Peak memory 204760 kb
Host smart-25dc9c18-9297-48d6-b226-9961bd684428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337579970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.1337579970
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.580838097
Short name T7
Test name
Test status
Simulation time 4053166361 ps
CPU time 29.55 seconds
Started Jun 27 04:52:22 PM PDT 24
Finished Jun 27 04:52:54 PM PDT 24
Peak memory 332832 kb
Host smart-20e1a78e-f370-4d2e-ae4f-182ff2067114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580838097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.580838097
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.2221870229
Short name T1364
Test name
Test status
Simulation time 7676811141 ps
CPU time 221.87 seconds
Started Jun 27 04:52:21 PM PDT 24
Finished Jun 27 04:56:05 PM PDT 24
Peak memory 1092576 kb
Host smart-c95b380f-cc79-4891-a8b9-6ccaea8d0196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221870229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2221870229
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1687855602
Short name T965
Test name
Test status
Simulation time 1581905809 ps
CPU time 14.93 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:46 PM PDT 24
Peak memory 214108 kb
Host smart-827b10ed-a843-4262-b047-184e15986e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687855602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1687855602
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.1081813864
Short name T1214
Test name
Test status
Simulation time 3442394130 ps
CPU time 3.31 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:33 PM PDT 24
Peak memory 213088 kb
Host smart-9377716a-9daa-4bb1-b289-9d0065b8539c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081813864 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.1081813864
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3673329181
Short name T975
Test name
Test status
Simulation time 292003648 ps
CPU time 1.7 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:33 PM PDT 24
Peak memory 211236 kb
Host smart-520c3756-b79e-4749-8fff-d75b384ec9a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673329181 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3673329181
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.3400351953
Short name T1240
Test name
Test status
Simulation time 186512766 ps
CPU time 1.32 seconds
Started Jun 27 04:52:22 PM PDT 24
Finished Jun 27 04:52:25 PM PDT 24
Peak memory 213012 kb
Host smart-77175635-f46f-4a75-b7eb-afd54b868f47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400351953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.3400351953
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.197175588
Short name T1114
Test name
Test status
Simulation time 5688711898 ps
CPU time 2.46 seconds
Started Jun 27 04:52:28 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 204896 kb
Host smart-8603da8e-f32d-474e-870b-768a9baff7b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197175588 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.197175588
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.2828607040
Short name T173
Test name
Test status
Simulation time 475506831 ps
CPU time 1.12 seconds
Started Jun 27 04:52:20 PM PDT 24
Finished Jun 27 04:52:22 PM PDT 24
Peak memory 204552 kb
Host smart-dacd33f9-819c-42b8-8acb-a3af803a6b3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828607040 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.2828607040
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.1134220734
Short name T1104
Test name
Test status
Simulation time 1464552554 ps
CPU time 2.99 seconds
Started Jun 27 04:52:28 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 204684 kb
Host smart-ebc05ad7-632a-413b-8632-0f6988c9e535
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134220734 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.1134220734
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2119552361
Short name T931
Test name
Test status
Simulation time 3348258294 ps
CPU time 4.35 seconds
Started Jun 27 04:52:21 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 213260 kb
Host smart-48afb83d-c9eb-468e-99b9-3d32d6a75b44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119552361 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2119552361
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.1683001224
Short name T1077
Test name
Test status
Simulation time 3052513883 ps
CPU time 4.79 seconds
Started Jun 27 04:52:21 PM PDT 24
Finished Jun 27 04:52:28 PM PDT 24
Peak memory 326556 kb
Host smart-772cfc61-30da-469a-807c-9ce3e1269d5a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683001224 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.1683001224
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3288281699
Short name T1122
Test name
Test status
Simulation time 1167295599 ps
CPU time 42.1 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:53:10 PM PDT 24
Peak memory 204768 kb
Host smart-3432f8b5-611a-4986-892b-3a94696b36e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288281699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3288281699
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.390904860
Short name T636
Test name
Test status
Simulation time 1549669577 ps
CPU time 14.1 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:45 PM PDT 24
Peak memory 209984 kb
Host smart-88c66ad6-5816-4f41-a303-cc342888ba9b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390904860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.390904860
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.457723960
Short name T1235
Test name
Test status
Simulation time 9309521126 ps
CPU time 5.16 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 204840 kb
Host smart-c3b9ea4b-ab37-45a7-86f3-239e6071c6bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457723960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.457723960
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.1345896738
Short name T1327
Test name
Test status
Simulation time 19088126968 ps
CPU time 2066.92 seconds
Started Jun 27 04:52:29 PM PDT 24
Finished Jun 27 05:27:00 PM PDT 24
Peak memory 4273188 kb
Host smart-51f204f1-123e-46d6-87ea-a704f893ff89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345896738 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.1345896738
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2629352482
Short name T1436
Test name
Test status
Simulation time 6331881759 ps
CPU time 8.22 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:52:40 PM PDT 24
Peak memory 221228 kb
Host smart-eecc85c7-170b-4def-9692-02efc40ef20f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629352482 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2629352482
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_alert_test.945135642
Short name T881
Test name
Test status
Simulation time 47189362 ps
CPU time 0.62 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 204488 kb
Host smart-85e75af5-f39b-4831-94e9-94cc759857ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945135642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.945135642
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1117735274
Short name T963
Test name
Test status
Simulation time 908916005 ps
CPU time 13.78 seconds
Started Jun 27 04:52:21 PM PDT 24
Finished Jun 27 04:52:37 PM PDT 24
Peak memory 257452 kb
Host smart-c678dc95-723d-480b-8b1b-640471ccbf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117735274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1117735274
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.945959215
Short name T1069
Test name
Test status
Simulation time 891762635 ps
CPU time 7.44 seconds
Started Jun 27 04:52:22 PM PDT 24
Finished Jun 27 04:52:31 PM PDT 24
Peak memory 299524 kb
Host smart-1c3c0b37-a2b0-4aa0-beed-f7964d36de11
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945959215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_empt
y.945959215
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.4284626056
Short name T1072
Test name
Test status
Simulation time 10266069330 ps
CPU time 164.92 seconds
Started Jun 27 04:52:33 PM PDT 24
Finished Jun 27 04:55:20 PM PDT 24
Peak memory 693524 kb
Host smart-3c23990b-83f1-409c-8fea-93e8e796900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284626056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.4284626056
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.3745172445
Short name T336
Test name
Test status
Simulation time 13211410660 ps
CPU time 53.26 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:53:18 PM PDT 24
Peak memory 599960 kb
Host smart-bab04838-9fa9-40f3-ba41-fbb1dd581676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745172445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.3745172445
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.130739382
Short name T421
Test name
Test status
Simulation time 145316917 ps
CPU time 0.87 seconds
Started Jun 27 04:52:30 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 204472 kb
Host smart-193f3135-5447-4fd4-900d-eac7fa14e410
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130739382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_fm
t.130739382
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1605542371
Short name T867
Test name
Test status
Simulation time 203837244 ps
CPU time 10.36 seconds
Started Jun 27 04:52:24 PM PDT 24
Finished Jun 27 04:52:36 PM PDT 24
Peak memory 241144 kb
Host smart-16b68314-b091-489a-ac5f-5cb29a6c64fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605542371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1605542371
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.1873504414
Short name T1116
Test name
Test status
Simulation time 25291030234 ps
CPU time 380.47 seconds
Started Jun 27 04:53:38 PM PDT 24
Finished Jun 27 05:00:04 PM PDT 24
Peak memory 1466948 kb
Host smart-688999d8-e968-4d08-b38c-0d7a640f81c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873504414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.1873504414
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.4112751808
Short name T862
Test name
Test status
Simulation time 825580399 ps
CPU time 6.45 seconds
Started Jun 27 04:52:29 PM PDT 24
Finished Jun 27 04:52:39 PM PDT 24
Peak memory 204840 kb
Host smart-059c0adf-5e91-4730-b8fd-e98f9f91ffee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112751808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.4112751808
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3245235756
Short name T34
Test name
Test status
Simulation time 4699729509 ps
CPU time 51.98 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:53:23 PM PDT 24
Peak memory 269524 kb
Host smart-917aa86c-7e10-4387-9215-22a015eff681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245235756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3245235756
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.2728421501
Short name T582
Test name
Test status
Simulation time 88642473 ps
CPU time 0.62 seconds
Started Jun 27 04:52:22 PM PDT 24
Finished Jun 27 04:52:25 PM PDT 24
Peak memory 204576 kb
Host smart-3ac2e9b3-4e6c-40bc-a1d8-ca143e249f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728421501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2728421501
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.637879591
Short name T1115
Test name
Test status
Simulation time 848551890 ps
CPU time 5.32 seconds
Started Jun 27 04:52:24 PM PDT 24
Finished Jun 27 04:52:33 PM PDT 24
Peak memory 205152 kb
Host smart-d8c14c57-d023-4cca-9805-d1379d7471f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637879591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.637879591
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.3542879404
Short name T1340
Test name
Test status
Simulation time 157695158 ps
CPU time 2.26 seconds
Started Jun 27 04:52:34 PM PDT 24
Finished Jun 27 04:52:37 PM PDT 24
Peak memory 204664 kb
Host smart-80c1d704-beec-4589-a20e-cc3f28eee0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542879404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.3542879404
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.1492232496
Short name T373
Test name
Test status
Simulation time 1532794380 ps
CPU time 64.51 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:53:35 PM PDT 24
Peak memory 278404 kb
Host smart-38caf821-d450-4520-b668-567685c8d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492232496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.1492232496
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.3175567641
Short name T283
Test name
Test status
Simulation time 65276194490 ps
CPU time 996.25 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 05:09:05 PM PDT 24
Peak memory 1938124 kb
Host smart-adc5a16d-73a9-4fda-9fd2-bc4af1722404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175567641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.3175567641
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.1354172085
Short name T992
Test name
Test status
Simulation time 1033209761 ps
CPU time 23.01 seconds
Started Jun 27 04:52:22 PM PDT 24
Finished Jun 27 04:52:47 PM PDT 24
Peak memory 213008 kb
Host smart-c6c88bde-eb56-43d4-bf8a-655a3bfb3f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354172085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.1354172085
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2982879897
Short name T1153
Test name
Test status
Simulation time 956330491 ps
CPU time 3.55 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 204756 kb
Host smart-9e326651-54c3-480b-8689-907d40da8cc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982879897 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2982879897
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.3181283863
Short name T266
Test name
Test status
Simulation time 203623514 ps
CPU time 1 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:32 PM PDT 24
Peak memory 204576 kb
Host smart-7d6267ea-1088-402f-90fc-9c08c835854e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181283863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.3181283863
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.2242936009
Short name T1333
Test name
Test status
Simulation time 494941009 ps
CPU time 2.91 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 204552 kb
Host smart-0267b781-a909-4d38-be91-c18b916bc9ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242936009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.2242936009
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.826158674
Short name T907
Test name
Test status
Simulation time 164905941 ps
CPU time 1.01 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:30 PM PDT 24
Peak memory 204528 kb
Host smart-839f2a09-aae3-4190-9abe-dc47178b9265
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826158674 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.826158674
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.3512205636
Short name T251
Test name
Test status
Simulation time 924102807 ps
CPU time 4.53 seconds
Started Jun 27 04:52:28 PM PDT 24
Finished Jun 27 04:52:37 PM PDT 24
Peak memory 212952 kb
Host smart-832d392b-1edb-4f19-95fe-2d5bd149f3ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512205636 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_intr_smoke.3512205636
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.962869170
Short name T1005
Test name
Test status
Simulation time 11063296508 ps
CPU time 5.53 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:36 PM PDT 24
Peak memory 204892 kb
Host smart-031b81f2-c1e4-47f1-bd25-e1f6d3eb5a2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962869170 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.962869170
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.2435764868
Short name T1211
Test name
Test status
Simulation time 684823085 ps
CPU time 8.35 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:37 PM PDT 24
Peak memory 204744 kb
Host smart-9f7289d3-4ef4-4795-a124-01dc4c73f68b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435764868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.2435764868
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.1245211663
Short name T1039
Test name
Test status
Simulation time 1675754480 ps
CPU time 34.71 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:53:05 PM PDT 24
Peak memory 204812 kb
Host smart-8652490d-8d65-4a8e-ad99-7d32a593b6ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245211663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.1245211663
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.1138106201
Short name T443
Test name
Test status
Simulation time 29179085759 ps
CPU time 177.76 seconds
Started Jun 27 04:52:28 PM PDT 24
Finished Jun 27 04:55:30 PM PDT 24
Peak memory 2356384 kb
Host smart-afdbba19-05c8-4909-8fdb-5725ce1be397
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138106201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.1138106201
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.1799795238
Short name T998
Test name
Test status
Simulation time 15434413297 ps
CPU time 798.13 seconds
Started Jun 27 04:52:22 PM PDT 24
Finished Jun 27 05:05:42 PM PDT 24
Peak memory 3882776 kb
Host smart-bd2ddce6-fec8-406f-8b6e-5ff0ad11dfba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799795238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.1799795238
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.2767970428
Short name T1197
Test name
Test status
Simulation time 4047024487 ps
CPU time 7.75 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:37 PM PDT 24
Peak memory 213992 kb
Host smart-77bdf670-fc6e-4b1f-8687-b90b75d2326c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767970428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.2767970428
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_alert_test.3255296082
Short name T720
Test name
Test status
Simulation time 50450747 ps
CPU time 0.68 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:52:32 PM PDT 24
Peak memory 204136 kb
Host smart-3a3a238d-a5a5-49d1-a046-be8aa8c10850
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255296082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.3255296082
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3287491694
Short name T815
Test name
Test status
Simulation time 152375878 ps
CPU time 4.95 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 212980 kb
Host smart-788f0d20-767e-427b-a0ed-9dd87c4343e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287491694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3287491694
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1795095652
Short name T413
Test name
Test status
Simulation time 1110544559 ps
CPU time 14.02 seconds
Started Jun 27 04:52:28 PM PDT 24
Finished Jun 27 04:52:46 PM PDT 24
Peak memory 262460 kb
Host smart-02cccf69-679f-40cb-b8e0-c04222a36188
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795095652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1795095652
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.3590896060
Short name T713
Test name
Test status
Simulation time 13134253957 ps
CPU time 99.01 seconds
Started Jun 27 04:52:30 PM PDT 24
Finished Jun 27 04:54:13 PM PDT 24
Peak memory 897224 kb
Host smart-0d1900f6-d151-4e3d-bd74-85b81f91386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590896060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.3590896060
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.4096596430
Short name T1117
Test name
Test status
Simulation time 2656256088 ps
CPU time 82.41 seconds
Started Jun 27 04:52:32 PM PDT 24
Finished Jun 27 04:53:57 PM PDT 24
Peak memory 859872 kb
Host smart-9dc84d85-c86c-428c-a774-fea7e57b9aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096596430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.4096596430
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.2965367467
Short name T562
Test name
Test status
Simulation time 434044569 ps
CPU time 0.98 seconds
Started Jun 27 04:52:37 PM PDT 24
Finished Jun 27 04:52:39 PM PDT 24
Peak memory 204492 kb
Host smart-44d92560-d69c-4c2a-80f1-347f6f85e8ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965367467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.2965367467
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.3737863776
Short name T677
Test name
Test status
Simulation time 886468508 ps
CPU time 5.57 seconds
Started Jun 27 04:52:38 PM PDT 24
Finished Jun 27 04:52:45 PM PDT 24
Peak memory 204812 kb
Host smart-7a5670ff-5362-4c7e-b130-3cf57c79bfc2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737863776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.3737863776
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.131208040
Short name T556
Test name
Test status
Simulation time 53846247274 ps
CPU time 206.69 seconds
Started Jun 27 04:52:24 PM PDT 24
Finished Jun 27 04:55:54 PM PDT 24
Peak memory 973408 kb
Host smart-92741959-aa1a-4040-b35f-9687520539c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131208040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.131208040
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.472519712
Short name T884
Test name
Test status
Simulation time 1757663203 ps
CPU time 24.71 seconds
Started Jun 27 04:52:31 PM PDT 24
Finished Jun 27 04:52:59 PM PDT 24
Peak memory 283584 kb
Host smart-ff53011b-f040-4a43-8694-b546dec2c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472519712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.472519712
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.3365245601
Short name T140
Test name
Test status
Simulation time 19769350 ps
CPU time 0.64 seconds
Started Jun 27 04:52:23 PM PDT 24
Finished Jun 27 04:52:26 PM PDT 24
Peak memory 204548 kb
Host smart-36ca4e60-c891-4b49-b4b1-f36a5b0a55ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365245601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.3365245601
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.1261081947
Short name T1163
Test name
Test status
Simulation time 7960655266 ps
CPU time 260.31 seconds
Started Jun 27 04:52:24 PM PDT 24
Finished Jun 27 04:56:48 PM PDT 24
Peak memory 1625544 kb
Host smart-ef80ef86-8be4-4939-a91b-5bfcddeca69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261081947 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.1261081947
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.1543445853
Short name T653
Test name
Test status
Simulation time 533830852 ps
CPU time 5.42 seconds
Started Jun 27 04:52:32 PM PDT 24
Finished Jun 27 04:52:40 PM PDT 24
Peak memory 204728 kb
Host smart-7af7da1e-68c6-4908-bb5c-663e84f57bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543445853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.1543445853
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.3770131992
Short name T738
Test name
Test status
Simulation time 3403116410 ps
CPU time 25.73 seconds
Started Jun 27 04:52:32 PM PDT 24
Finished Jun 27 04:53:00 PM PDT 24
Peak memory 327636 kb
Host smart-b5782b84-4bb7-4fcc-b2ce-228bd313f7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770131992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.3770131992
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1102215563
Short name T856
Test name
Test status
Simulation time 1988023391 ps
CPU time 43.09 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:53:15 PM PDT 24
Peak memory 213048 kb
Host smart-b9dabb88-ae39-4bf4-bd80-3f6347b3d7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102215563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1102215563
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.860204254
Short name T1148
Test name
Test status
Simulation time 1981440106 ps
CPU time 4.93 seconds
Started Jun 27 04:52:29 PM PDT 24
Finished Jun 27 04:52:38 PM PDT 24
Peak memory 214508 kb
Host smart-a573e134-db4b-4333-bc26-8ed5a3309af4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860204254 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.860204254
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1303052648
Short name T1335
Test name
Test status
Simulation time 199118307 ps
CPU time 1.2 seconds
Started Jun 27 04:52:28 PM PDT 24
Finished Jun 27 04:52:33 PM PDT 24
Peak memory 204780 kb
Host smart-e6063f03-94ae-4e57-9ec7-fd82c0f348a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303052648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1303052648
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.1409522431
Short name T1448
Test name
Test status
Simulation time 429490047 ps
CPU time 0.88 seconds
Started Jun 27 04:52:26 PM PDT 24
Finished Jun 27 04:52:31 PM PDT 24
Peak memory 204584 kb
Host smart-ba29c664-99d8-458d-83e5-dfaff015885e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409522431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.1409522431
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.1423153446
Short name T1126
Test name
Test status
Simulation time 516678830 ps
CPU time 1.76 seconds
Started Jun 27 04:52:30 PM PDT 24
Finished Jun 27 04:52:35 PM PDT 24
Peak memory 204092 kb
Host smart-a2baae0d-bdbc-4352-9d28-9fc36e50d134
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423153446 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.1423153446
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.1655889469
Short name T1424
Test name
Test status
Simulation time 206823287 ps
CPU time 1.01 seconds
Started Jun 27 04:52:30 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 204528 kb
Host smart-abfe3f2c-13d6-44e2-bb55-464c56ff62d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655889469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.1655889469
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.2229363768
Short name T520
Test name
Test status
Simulation time 993716777 ps
CPU time 2.12 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 204868 kb
Host smart-67de8f5a-4d56-4c06-b963-c7b3dca67d93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229363768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.2229363768
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.1193635867
Short name T1284
Test name
Test status
Simulation time 2520097199 ps
CPU time 6.3 seconds
Started Jun 27 04:52:31 PM PDT 24
Finished Jun 27 04:52:40 PM PDT 24
Peak memory 213196 kb
Host smart-e1c9bd6d-3b9b-45a5-a6cf-9e7726306f77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193635867 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.1193635867
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.887702346
Short name T1481
Test name
Test status
Simulation time 17598066995 ps
CPU time 346.58 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 04:58:19 PM PDT 24
Peak memory 4389008 kb
Host smart-d51408dd-5bcf-4d27-ad55-28893ccd45ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887702346 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.887702346
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.2933104338
Short name T698
Test name
Test status
Simulation time 2055859128 ps
CPU time 14.91 seconds
Started Jun 27 04:52:28 PM PDT 24
Finished Jun 27 04:52:47 PM PDT 24
Peak memory 204644 kb
Host smart-22b6efbf-a2cf-4923-ba20-e1f3d57aa543
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933104338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.2933104338
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.1357109542
Short name T135
Test name
Test status
Simulation time 1887690596 ps
CPU time 14.56 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:43 PM PDT 24
Peak memory 220960 kb
Host smart-d68d2fd1-db41-4488-84fe-a88bdc1e695d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357109542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.1357109542
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2719035822
Short name T828
Test name
Test status
Simulation time 44058223497 ps
CPU time 94.66 seconds
Started Jun 27 04:52:28 PM PDT 24
Finished Jun 27 04:54:07 PM PDT 24
Peak memory 1544572 kb
Host smart-44f2da66-ac2a-41cb-bb69-69dc60bd9ccc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719035822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2719035822
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.2555064607
Short name T250
Test name
Test status
Simulation time 16247555138 ps
CPU time 652.45 seconds
Started Jun 27 04:52:27 PM PDT 24
Finished Jun 27 05:03:25 PM PDT 24
Peak memory 4043544 kb
Host smart-d904c2c6-7ca8-498b-a852-f38ab1a0826e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555064607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.2555064607
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.927497877
Short name T1221
Test name
Test status
Simulation time 2867010339 ps
CPU time 6.5 seconds
Started Jun 27 04:52:24 PM PDT 24
Finished Jun 27 04:52:34 PM PDT 24
Peak memory 217748 kb
Host smart-749d93b4-0eb1-4f37-9baa-cd7bdf50b42a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927497877 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.927497877
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_alert_test.2062454462
Short name T1184
Test name
Test status
Simulation time 27975738 ps
CPU time 0.64 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:53:07 PM PDT 24
Peak memory 204380 kb
Host smart-a6703e4e-f52d-41df-b1f2-0c8882fd7d77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062454462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.2062454462
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3769911562
Short name T1381
Test name
Test status
Simulation time 327697067 ps
CPU time 1.59 seconds
Started Jun 27 04:53:00 PM PDT 24
Finished Jun 27 04:53:03 PM PDT 24
Peak memory 213100 kb
Host smart-ef21ee39-7ef8-472e-b899-fd7760716f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769911562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3769911562
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.3465958442
Short name T1088
Test name
Test status
Simulation time 628116501 ps
CPU time 15.72 seconds
Started Jun 27 04:52:56 PM PDT 24
Finished Jun 27 04:53:13 PM PDT 24
Peak memory 253540 kb
Host smart-127e6506-ddea-4850-83e6-0f7eaf91450f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465958442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.3465958442
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1367333620
Short name T74
Test name
Test status
Simulation time 1685413300 ps
CPU time 105.37 seconds
Started Jun 27 04:52:53 PM PDT 24
Finished Jun 27 04:54:39 PM PDT 24
Peak memory 607936 kb
Host smart-7c51dffb-031d-438c-b18e-b1107dc6d2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367333620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1367333620
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.4287871477
Short name T85
Test name
Test status
Simulation time 1835718374 ps
CPU time 47.93 seconds
Started Jun 27 04:52:24 PM PDT 24
Finished Jun 27 04:53:14 PM PDT 24
Peak memory 630296 kb
Host smart-590cb87a-ca00-4f58-8d15-9d6a41f9ad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287871477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.4287871477
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1197197433
Short name T938
Test name
Test status
Simulation time 1111941804 ps
CPU time 1.02 seconds
Started Jun 27 04:52:56 PM PDT 24
Finished Jun 27 04:52:59 PM PDT 24
Peak memory 204508 kb
Host smart-8be70ef1-2e84-4b58-93aa-1e6cdd7ae1bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197197433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1197197433
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.2552687329
Short name T940
Test name
Test status
Simulation time 1015818812 ps
CPU time 4.6 seconds
Started Jun 27 04:52:56 PM PDT 24
Finished Jun 27 04:53:02 PM PDT 24
Peak memory 234024 kb
Host smart-950b904e-cd01-41b7-b5ac-e72c3666bcaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552687329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.2552687329
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1684186276
Short name T105
Test name
Test status
Simulation time 2808626098 ps
CPU time 61.3 seconds
Started Jun 27 04:52:29 PM PDT 24
Finished Jun 27 04:53:34 PM PDT 24
Peak memory 904928 kb
Host smart-c4eaef71-5006-49c5-a26b-d7362a735028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684186276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1684186276
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2330481172
Short name T893
Test name
Test status
Simulation time 2966185996 ps
CPU time 7.03 seconds
Started Jun 27 04:52:59 PM PDT 24
Finished Jun 27 04:53:07 PM PDT 24
Peak memory 204812 kb
Host smart-e04c5cde-052c-4671-b815-8af85a108a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330481172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2330481172
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.2716161455
Short name T246
Test name
Test status
Simulation time 8280111086 ps
CPU time 32.51 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:53:39 PM PDT 24
Peak memory 435344 kb
Host smart-e599af08-58c5-4712-980c-ec5b033f7ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716161455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.2716161455
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.125272186
Short name T818
Test name
Test status
Simulation time 16927211 ps
CPU time 0.64 seconds
Started Jun 27 04:52:25 PM PDT 24
Finished Jun 27 04:52:29 PM PDT 24
Peak memory 204460 kb
Host smart-944aba43-2633-4681-a16b-b634ad96edd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125272186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.125272186
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2310685347
Short name T428
Test name
Test status
Simulation time 6206743548 ps
CPU time 279.61 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:57:45 PM PDT 24
Peak memory 318636 kb
Host smart-afd77824-8ef7-4455-8bfe-61f25e82b77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310685347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2310685347
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.1981670649
Short name T365
Test name
Test status
Simulation time 94668622 ps
CPU time 3.74 seconds
Started Jun 27 04:52:59 PM PDT 24
Finished Jun 27 04:53:04 PM PDT 24
Peak memory 204760 kb
Host smart-ffd5e73a-1b27-440d-aa78-66bfc27ae0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981670649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1981670649
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.1456666500
Short name T695
Test name
Test status
Simulation time 6266439518 ps
CPU time 31.95 seconds
Started Jun 27 04:52:29 PM PDT 24
Finished Jun 27 04:53:05 PM PDT 24
Peak memory 350048 kb
Host smart-119882f4-b72c-48aa-8bd2-ebac9405bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456666500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.1456666500
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.1879278421
Short name T1403
Test name
Test status
Simulation time 74840602755 ps
CPU time 1105.25 seconds
Started Jun 27 04:52:56 PM PDT 24
Finished Jun 27 05:11:22 PM PDT 24
Peak memory 3598536 kb
Host smart-ad4b51bc-c927-476f-93e9-305bbebfc4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879278421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.1879278421
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.2765187745
Short name T883
Test name
Test status
Simulation time 820954589 ps
CPU time 13.63 seconds
Started Jun 27 04:52:57 PM PDT 24
Finished Jun 27 04:53:12 PM PDT 24
Peak memory 216528 kb
Host smart-1ca84cfc-827d-4885-bda4-ebb7d1a4ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765187745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.2765187745
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.2661074563
Short name T375
Test name
Test status
Simulation time 1981889729 ps
CPU time 2.95 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:53:08 PM PDT 24
Peak memory 204768 kb
Host smart-04f2255a-de90-45c7-8642-8e1b3734c70c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661074563 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.2661074563
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.2061870243
Short name T1139
Test name
Test status
Simulation time 245350958 ps
CPU time 1.06 seconds
Started Jun 27 04:53:03 PM PDT 24
Finished Jun 27 04:53:06 PM PDT 24
Peak memory 213044 kb
Host smart-a7795889-4a78-4f65-ba26-4c0a2088a72a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061870243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.2061870243
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.2277816206
Short name T347
Test name
Test status
Simulation time 372298723 ps
CPU time 0.96 seconds
Started Jun 27 04:52:55 PM PDT 24
Finished Jun 27 04:52:57 PM PDT 24
Peak memory 204624 kb
Host smart-b62d8b4e-6640-4d15-bda3-7db879c0e40b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277816206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.2277816206
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.1182303689
Short name T623
Test name
Test status
Simulation time 1123430595 ps
CPU time 2.75 seconds
Started Jun 27 04:52:58 PM PDT 24
Finished Jun 27 04:53:02 PM PDT 24
Peak memory 204764 kb
Host smart-64beabc2-c49d-49df-9187-a6da4f5646de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182303689 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.1182303689
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.3531637509
Short name T1385
Test name
Test status
Simulation time 137797555 ps
CPU time 1.27 seconds
Started Jun 27 04:52:56 PM PDT 24
Finished Jun 27 04:52:59 PM PDT 24
Peak memory 204616 kb
Host smart-c78579e9-f647-43e4-85a0-f39ca5ed3af9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531637509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.3531637509
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.3995264557
Short name T1182
Test name
Test status
Simulation time 21182013971 ps
CPU time 7.2 seconds
Started Jun 27 04:52:54 PM PDT 24
Finished Jun 27 04:53:02 PM PDT 24
Peak memory 213880 kb
Host smart-32be1de8-c52f-4b99-a819-a2bd5ea4b6f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995264557 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.3995264557
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.2381031325
Short name T529
Test name
Test status
Simulation time 15553321854 ps
CPU time 30.62 seconds
Started Jun 27 04:52:54 PM PDT 24
Finished Jun 27 04:53:26 PM PDT 24
Peak memory 865008 kb
Host smart-59cf3d48-c44f-4130-b210-60a99df0e53d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381031325 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.2381031325
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.3266987482
Short name T1438
Test name
Test status
Simulation time 1727164288 ps
CPU time 10.57 seconds
Started Jun 27 04:52:54 PM PDT 24
Finished Jun 27 04:53:06 PM PDT 24
Peak memory 204756 kb
Host smart-d577b876-0632-42c7-a139-19a54d1cde56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266987482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.3266987482
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.2248645247
Short name T1393
Test name
Test status
Simulation time 1438045553 ps
CPU time 60.27 seconds
Started Jun 27 04:53:01 PM PDT 24
Finished Jun 27 04:54:02 PM PDT 24
Peak memory 205808 kb
Host smart-7fa125cc-c631-43c3-8989-16a4cb4e4116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248645247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.2248645247
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.1671972716
Short name T1098
Test name
Test status
Simulation time 28567755732 ps
CPU time 133.8 seconds
Started Jun 27 04:53:00 PM PDT 24
Finished Jun 27 04:55:14 PM PDT 24
Peak memory 2018636 kb
Host smart-3151a30f-d480-4454-865b-31d241193499
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671972716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.1671972716
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1815186557
Short name T1457
Test name
Test status
Simulation time 5595092364 ps
CPU time 7.26 seconds
Started Jun 27 04:52:54 PM PDT 24
Finished Jun 27 04:53:02 PM PDT 24
Peak memory 213136 kb
Host smart-43100598-e5fe-4b81-bd6f-e34759f87faf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815186557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1815186557
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_alert_test.192254697
Short name T389
Test name
Test status
Simulation time 16687553 ps
CPU time 0.66 seconds
Started Jun 27 04:53:03 PM PDT 24
Finished Jun 27 04:53:05 PM PDT 24
Peak memory 204420 kb
Host smart-dd993c1c-4dc9-4ea9-919f-b80b798fcfd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192254697 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.192254697
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.1901559828
Short name T51
Test name
Test status
Simulation time 1148836203 ps
CPU time 2.05 seconds
Started Jun 27 04:52:55 PM PDT 24
Finished Jun 27 04:52:58 PM PDT 24
Peak memory 221124 kb
Host smart-5cece86e-62f7-4537-b8ee-ef34e37f961e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901559828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.1901559828
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.3829025418
Short name T976
Test name
Test status
Simulation time 1305807643 ps
CPU time 5.71 seconds
Started Jun 27 04:52:56 PM PDT 24
Finished Jun 27 04:53:03 PM PDT 24
Peak memory 239952 kb
Host smart-a4daa5d8-e311-462b-8c56-7767d957c32e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829025418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_emp
ty.3829025418
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.2800991412
Short name T41
Test name
Test status
Simulation time 1709502856 ps
CPU time 94.36 seconds
Started Jun 27 04:52:54 PM PDT 24
Finished Jun 27 04:54:29 PM PDT 24
Peak memory 457052 kb
Host smart-607ed09c-e649-4f88-a914-8c093dd693d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800991412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2800991412
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.2299167111
Short name T1449
Test name
Test status
Simulation time 8155944398 ps
CPU time 129.77 seconds
Started Jun 27 04:52:57 PM PDT 24
Finished Jun 27 04:55:08 PM PDT 24
Peak memory 648976 kb
Host smart-0f106d7e-2929-4987-93a9-294ae079a77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299167111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.2299167111
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.4258707316
Short name T1375
Test name
Test status
Simulation time 194503455 ps
CPU time 1.25 seconds
Started Jun 27 04:53:03 PM PDT 24
Finished Jun 27 04:53:05 PM PDT 24
Peak memory 204272 kb
Host smart-dd87d8c2-3214-4900-a66a-6a783bc626ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258707316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.4258707316
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.2349554822
Short name T774
Test name
Test status
Simulation time 2953636444 ps
CPU time 9.3 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:53:15 PM PDT 24
Peak memory 204856 kb
Host smart-a27f1129-a416-4afc-98d6-419d114cfdee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349554822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.2349554822
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.2511041605
Short name T1293
Test name
Test status
Simulation time 2722939220 ps
CPU time 68.75 seconds
Started Jun 27 04:52:56 PM PDT 24
Finished Jun 27 04:54:06 PM PDT 24
Peak memory 827924 kb
Host smart-1ebecf17-98cc-4e70-b751-0b598f3432dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511041605 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.2511041605
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.1825382579
Short name T1060
Test name
Test status
Simulation time 1630263432 ps
CPU time 16.94 seconds
Started Jun 27 04:53:02 PM PDT 24
Finished Jun 27 04:53:20 PM PDT 24
Peak memory 204732 kb
Host smart-0c352a1c-65a2-4492-a092-7c1c8d782e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825382579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.1825382579
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.2955751913
Short name T1058
Test name
Test status
Simulation time 2304103509 ps
CPU time 105.73 seconds
Started Jun 27 04:52:58 PM PDT 24
Finished Jun 27 04:54:45 PM PDT 24
Peak memory 379532 kb
Host smart-f5d6d993-4f11-4df5-9ae1-1682d4737eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955751913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.2955751913
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.1364846885
Short name T514
Test name
Test status
Simulation time 135785591 ps
CPU time 0.64 seconds
Started Jun 27 04:52:59 PM PDT 24
Finished Jun 27 04:53:01 PM PDT 24
Peak memory 204520 kb
Host smart-a38c33d5-0ffd-4ba0-921f-61792ecb63ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364846885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.1364846885
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.2201240373
Short name T664
Test name
Test status
Simulation time 24489042146 ps
CPU time 682.6 seconds
Started Jun 27 04:52:55 PM PDT 24
Finished Jun 27 05:04:18 PM PDT 24
Peak memory 2352104 kb
Host smart-9ddb859d-9b94-4e55-add4-a53be463cf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201240373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.2201240373
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.3799470530
Short name T1367
Test name
Test status
Simulation time 97850674 ps
CPU time 1.15 seconds
Started Jun 27 04:52:57 PM PDT 24
Finished Jun 27 04:52:59 PM PDT 24
Peak memory 204792 kb
Host smart-34026d47-2a24-4479-92e1-208e08364e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799470530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.3799470530
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.636516641
Short name T1050
Test name
Test status
Simulation time 1242707125 ps
CPU time 60.89 seconds
Started Jun 27 04:52:57 PM PDT 24
Finished Jun 27 04:53:59 PM PDT 24
Peak memory 351400 kb
Host smart-531df904-9b43-42b4-892b-b3630e046795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636516641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.636516641
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.2017201343
Short name T1387
Test name
Test status
Simulation time 42104098877 ps
CPU time 255.09 seconds
Started Jun 27 04:52:58 PM PDT 24
Finished Jun 27 04:57:14 PM PDT 24
Peak memory 1681684 kb
Host smart-5623d112-6241-4014-b7dc-266d8e10a954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017201343 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.2017201343
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.3781902972
Short name T978
Test name
Test status
Simulation time 1236277827 ps
CPU time 10.2 seconds
Started Jun 27 04:53:03 PM PDT 24
Finished Jun 27 04:53:14 PM PDT 24
Peak memory 220964 kb
Host smart-0554fea3-c13f-4acc-80a5-cb4e14800ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781902972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.3781902972
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.2184554434
Short name T1306
Test name
Test status
Simulation time 199606067 ps
CPU time 1.17 seconds
Started Jun 27 04:52:59 PM PDT 24
Finished Jun 27 04:53:01 PM PDT 24
Peak memory 203824 kb
Host smart-391c7757-14d5-4dde-89ff-ea028efc3a14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184554434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.2184554434
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.524495833
Short name T967
Test name
Test status
Simulation time 514954391 ps
CPU time 1.05 seconds
Started Jun 27 04:52:56 PM PDT 24
Finished Jun 27 04:52:58 PM PDT 24
Peak memory 204524 kb
Host smart-c79ef983-2978-4724-8087-6079b683ec97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524495833 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.524495833
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.3269602171
Short name T263
Test name
Test status
Simulation time 1094837888 ps
CPU time 2.97 seconds
Started Jun 27 04:53:03 PM PDT 24
Finished Jun 27 04:53:07 PM PDT 24
Peak memory 205032 kb
Host smart-382176b8-387a-4f99-9490-f535249258aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269602171 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.3269602171
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.247487257
Short name T944
Test name
Test status
Simulation time 75212703 ps
CPU time 1.02 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:53:07 PM PDT 24
Peak memory 204616 kb
Host smart-bae5d421-59a2-4dc3-ab15-c720b4615c72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247487257 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.247487257
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2102775608
Short name T245
Test name
Test status
Simulation time 297921304 ps
CPU time 2.46 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:53:08 PM PDT 24
Peak memory 204880 kb
Host smart-9f43e1be-d46b-4100-b66e-3989ecdbbab8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102775608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2102775608
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.2484527980
Short name T370
Test name
Test status
Simulation time 1782112918 ps
CPU time 3.15 seconds
Started Jun 27 04:53:00 PM PDT 24
Finished Jun 27 04:53:04 PM PDT 24
Peak memory 204728 kb
Host smart-f5484f4d-efda-4139-8cb2-4e18a849b99c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484527980 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.2484527980
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.261136811
Short name T1213
Test name
Test status
Simulation time 32498733220 ps
CPU time 19.85 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:53:25 PM PDT 24
Peak memory 539052 kb
Host smart-783dd9e0-ea03-4ea2-8f8f-7f61a9f4670a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261136811 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.261136811
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.1955699798
Short name T753
Test name
Test status
Simulation time 2728966970 ps
CPU time 10.36 seconds
Started Jun 27 04:53:00 PM PDT 24
Finished Jun 27 04:53:12 PM PDT 24
Peak memory 208488 kb
Host smart-3ac456fa-a42e-479f-ab59-90d621bf1deb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955699798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.1955699798
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.2904842815
Short name T530
Test name
Test status
Simulation time 50718703757 ps
CPU time 164.79 seconds
Started Jun 27 04:53:03 PM PDT 24
Finished Jun 27 04:55:49 PM PDT 24
Peak memory 2169432 kb
Host smart-85eb4616-26d1-440d-b232-86fcd36b4551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904842815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.2904842815
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.665176480
Short name T1162
Test name
Test status
Simulation time 34269294299 ps
CPU time 585.39 seconds
Started Jun 27 04:52:59 PM PDT 24
Finished Jun 27 05:02:45 PM PDT 24
Peak memory 4134916 kb
Host smart-e26ffde9-9226-49ec-a8ec-6d7534f16ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665176480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_t
arget_stretch.665176480
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.833338819
Short name T269
Test name
Test status
Simulation time 5986268796 ps
CPU time 6.59 seconds
Started Jun 27 04:53:02 PM PDT 24
Finished Jun 27 04:53:10 PM PDT 24
Peak memory 213080 kb
Host smart-b908bc13-3ce9-449d-9b8b-1b6829199d68
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833338819 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_timeout.833338819
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_alert_test.178791081
Short name T418
Test name
Test status
Simulation time 21531657 ps
CPU time 0.63 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:53:06 PM PDT 24
Peak memory 204416 kb
Host smart-460090d3-5524-4edd-b53f-3ee0e7227382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178791081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.178791081
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.3226967900
Short name T379
Test name
Test status
Simulation time 293504615 ps
CPU time 4.37 seconds
Started Jun 27 04:53:02 PM PDT 24
Finished Jun 27 04:53:08 PM PDT 24
Peak memory 215588 kb
Host smart-3036b232-7090-47a9-abe2-b34868bd3e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226967900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.3226967900
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.1285435567
Short name T1033
Test name
Test status
Simulation time 1690656215 ps
CPU time 22.52 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:53:29 PM PDT 24
Peak memory 297124 kb
Host smart-2feae1b1-2d2e-41c3-80af-da67694f8e4b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285435567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.1285435567
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.3171065871
Short name T648
Test name
Test status
Simulation time 9235796861 ps
CPU time 74.63 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:54:22 PM PDT 24
Peak memory 705700 kb
Host smart-4b85c133-ef15-4855-862f-eaea47804221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171065871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.3171065871
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2951622423
Short name T1291
Test name
Test status
Simulation time 2161840074 ps
CPU time 154.1 seconds
Started Jun 27 04:53:01 PM PDT 24
Finished Jun 27 04:55:37 PM PDT 24
Peak memory 707608 kb
Host smart-010f7149-9806-4d5a-b39a-6749c407ebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951622423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2951622423
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.2208771288
Short name T1010
Test name
Test status
Simulation time 112896916 ps
CPU time 1.11 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:53:08 PM PDT 24
Peak memory 204712 kb
Host smart-7d06400a-4870-414f-a2fa-76ccf1f7f2a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208771288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.2208771288
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.1298443149
Short name T166
Test name
Test status
Simulation time 147037930 ps
CPU time 8.32 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:53:15 PM PDT 24
Peak memory 231320 kb
Host smart-107649c9-a25e-4e12-bb7b-f66b5c350f54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298443149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.1298443149
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.2393690426
Short name T97
Test name
Test status
Simulation time 4617108688 ps
CPU time 108.65 seconds
Started Jun 27 04:53:04 PM PDT 24
Finished Jun 27 04:54:54 PM PDT 24
Peak memory 1286876 kb
Host smart-8043684f-8dbc-49f3-ae46-bffdcf5f51d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393690426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.2393690426
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2893637203
Short name T1113
Test name
Test status
Simulation time 388572039 ps
CPU time 4.97 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:53:12 PM PDT 24
Peak memory 204584 kb
Host smart-9f713876-0d1d-4ead-bbfc-b71c65601244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893637203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2893637203
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.3112929446
Short name T718
Test name
Test status
Simulation time 2387054896 ps
CPU time 53.78 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:54:01 PM PDT 24
Peak memory 304976 kb
Host smart-1a52bee4-daf0-48f6-94df-82b1a132f197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112929446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.3112929446
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.2381757174
Short name T889
Test name
Test status
Simulation time 27818718 ps
CPU time 0.69 seconds
Started Jun 27 04:53:02 PM PDT 24
Finished Jun 27 04:53:03 PM PDT 24
Peak memory 204548 kb
Host smart-9389f384-3fb0-4a8e-9ba9-e120b9ab745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381757174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.2381757174
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2531355269
Short name T440
Test name
Test status
Simulation time 6809142959 ps
CPU time 17.71 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:53:25 PM PDT 24
Peak memory 230312 kb
Host smart-b1e89196-cfbb-4956-b9e4-1ca6593cbfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531355269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2531355269
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.1505556085
Short name T1200
Test name
Test status
Simulation time 56170083 ps
CPU time 1.02 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 04:53:08 PM PDT 24
Peak memory 205360 kb
Host smart-1ee6845f-3a63-4032-a1bb-14af2f04a309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505556085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.1505556085
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.2014478087
Short name T397
Test name
Test status
Simulation time 4209649289 ps
CPU time 44.53 seconds
Started Jun 27 04:53:02 PM PDT 24
Finished Jun 27 04:53:47 PM PDT 24
Peak memory 296444 kb
Host smart-c8b349f7-74e8-4681-8d36-e459d944a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014478087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.2014478087
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.2679599618
Short name T1084
Test name
Test status
Simulation time 46579130774 ps
CPU time 800.92 seconds
Started Jun 27 04:53:05 PM PDT 24
Finished Jun 27 05:06:28 PM PDT 24
Peak memory 2083792 kb
Host smart-9a63c9ec-46e2-488f-96c8-0ea48a5b34fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679599618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.2679599618
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.355610451
Short name T357
Test name
Test status
Simulation time 3165513889 ps
CPU time 34.11 seconds
Started Jun 27 04:53:00 PM PDT 24
Finished Jun 27 04:53:35 PM PDT 24
Peak memory 213124 kb
Host smart-fac77670-21c5-4a77-965a-f01f958993b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355610451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.355610451
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.2311666294
Short name T24
Test name
Test status
Simulation time 867513202 ps
CPU time 4.47 seconds
Started Jun 27 04:53:06 PM PDT 24
Finished Jun 27 04:53:12 PM PDT 24
Peak memory 213064 kb
Host smart-7b5dd6bb-53a0-4fea-8683-cd43606ff9cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311666294 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.2311666294
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.4016960671
Short name T1083
Test name
Test status
Simulation time 196821702 ps
CPU time 1.14 seconds
Started Jun 27 04:53:06 PM PDT 24
Finished Jun 27 04:53:09 PM PDT 24
Peak memory 204540 kb
Host smart-9e672a89-eea2-4614-8adf-1b0e3cfc9d72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016960671 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_fifo_reset_acq.4016960671
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2703889767
Short name T327
Test name
Test status
Simulation time 329551682 ps
CPU time 1.14 seconds
Started Jun 27 04:53:03 PM PDT 24
Finished Jun 27 04:53:05 PM PDT 24
Peak memory 204540 kb
Host smart-7103f79b-e0b1-455a-b1ef-85f21b696066
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703889767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2703889767
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.3947449970
Short name T1224
Test name
Test status
Simulation time 262109081 ps
CPU time 1.58 seconds
Started Jun 27 04:53:06 PM PDT 24
Finished Jun 27 04:53:09 PM PDT 24
Peak memory 204588 kb
Host smart-6ad4f312-a64f-4591-8636-fc56387c6b90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947449970 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.3947449970
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.2629501921
Short name T650
Test name
Test status
Simulation time 749408360 ps
CPU time 1.43 seconds
Started Jun 27 04:53:07 PM PDT 24
Finished Jun 27 04:53:10 PM PDT 24
Peak memory 204548 kb
Host smart-dd0fd1e6-9fea-41eb-81b9-0d32af9bac2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629501921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.2629501921
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_hrst.3008807799
Short name T850
Test name
Test status
Simulation time 1591762835 ps
CPU time 3.13 seconds
Started Jun 27 04:53:06 PM PDT 24
Finished Jun 27 04:53:11 PM PDT 24
Peak memory 204788 kb
Host smart-843c1029-bcef-41b3-80d2-0347d93a5ce9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008807799 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 47.i2c_target_hrst.3008807799
Directory /workspace/47.i2c_target_hrst/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2892359150
Short name T676
Test name
Test status
Simulation time 995113897 ps
CPU time 5.62 seconds
Started Jun 27 04:53:06 PM PDT 24
Finished Jun 27 04:53:14 PM PDT 24
Peak memory 219984 kb
Host smart-68aa4963-8a51-4020-9061-dda34a7f03c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892359150 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2892359150
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.3673819745
Short name T508
Test name
Test status
Simulation time 8363346395 ps
CPU time 21.18 seconds
Started Jun 27 04:53:07 PM PDT 24
Finished Jun 27 04:53:30 PM PDT 24
Peak memory 407008 kb
Host smart-505a905e-7d6f-4152-bf3b-e3c9735f904c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673819745 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3673819745
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.1468679096
Short name T271
Test name
Test status
Simulation time 8166040103 ps
CPU time 19.5 seconds
Started Jun 27 04:53:03 PM PDT 24
Finished Jun 27 04:53:24 PM PDT 24
Peak memory 204920 kb
Host smart-acb47be2-a7dc-4a39-a485-3b83324e0927
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468679096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.1468679096
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.1385543196
Short name T414
Test name
Test status
Simulation time 8043428917 ps
CPU time 36.67 seconds
Started Jun 27 04:53:07 PM PDT 24
Finished Jun 27 04:53:45 PM PDT 24
Peak memory 231628 kb
Host smart-f423689c-92f3-425c-b8a8-9b2fed7cf0f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385543196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.1385543196
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.2570794866
Short name T1386
Test name
Test status
Simulation time 11392719794 ps
CPU time 9.61 seconds
Started Jun 27 04:53:06 PM PDT 24
Finished Jun 27 04:53:17 PM PDT 24
Peak memory 204864 kb
Host smart-b3062948-af19-4422-af1e-1bf201965d28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570794866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.2570794866
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.3127863641
Short name T747
Test name
Test status
Simulation time 9672817082 ps
CPU time 52.5 seconds
Started Jun 27 04:53:06 PM PDT 24
Finished Jun 27 04:54:00 PM PDT 24
Peak memory 800540 kb
Host smart-3e86a197-56fc-4ff2-8f4c-bca8e92d2766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127863641 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.3127863641
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1267478301
Short name T737
Test name
Test status
Simulation time 1373009834 ps
CPU time 7.66 seconds
Started Jun 27 04:53:07 PM PDT 24
Finished Jun 27 04:53:16 PM PDT 24
Peak memory 219264 kb
Host smart-32ebbb77-43a5-4327-8112-86fbf77c0c18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267478301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1267478301
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_alert_test.2490082135
Short name T506
Test name
Test status
Simulation time 15430598 ps
CPU time 0.66 seconds
Started Jun 27 04:53:20 PM PDT 24
Finished Jun 27 04:53:23 PM PDT 24
Peak memory 204460 kb
Host smart-6139fe3e-e459-4b18-b18f-a947d2608de9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490082135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.2490082135
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3828765208
Short name T789
Test name
Test status
Simulation time 562530041 ps
CPU time 3.46 seconds
Started Jun 27 04:53:28 PM PDT 24
Finished Jun 27 04:53:39 PM PDT 24
Peak memory 214444 kb
Host smart-35d15406-a0e4-4bf4-8043-553e77b9aacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828765208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3828765208
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.3885021189
Short name T399
Test name
Test status
Simulation time 303650061 ps
CPU time 14.57 seconds
Started Jun 27 04:53:28 PM PDT 24
Finished Jun 27 04:53:50 PM PDT 24
Peak memory 263644 kb
Host smart-e24ccd8e-8072-4607-bcb0-c4ecfa1c71df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885021189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.3885021189
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.1551672503
Short name T802
Test name
Test status
Simulation time 3112354505 ps
CPU time 96.18 seconds
Started Jun 27 04:53:14 PM PDT 24
Finished Jun 27 04:54:52 PM PDT 24
Peak memory 534204 kb
Host smart-bc6ce84c-6825-4eba-9133-4393b0f7837e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551672503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.1551672503
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1974757421
Short name T1336
Test name
Test status
Simulation time 2277754814 ps
CPU time 160.21 seconds
Started Jun 27 04:53:22 PM PDT 24
Finished Jun 27 04:56:06 PM PDT 24
Peak memory 700148 kb
Host smart-08415556-e11c-4846-8c31-2134c38174ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974757421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1974757421
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.2720717354
Short name T619
Test name
Test status
Simulation time 347376641 ps
CPU time 0.96 seconds
Started Jun 27 04:53:16 PM PDT 24
Finished Jun 27 04:53:18 PM PDT 24
Peak memory 204540 kb
Host smart-1843fc57-5f54-45e3-b2c6-4e20c16f9fed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720717354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_f
mt.2720717354
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.409822176
Short name T1302
Test name
Test status
Simulation time 971002330 ps
CPU time 4.35 seconds
Started Jun 27 04:53:17 PM PDT 24
Finished Jun 27 04:53:22 PM PDT 24
Peak memory 204748 kb
Host smart-ade0f331-a8de-4624-bf77-f546528c3b0a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409822176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
409822176
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.4249812571
Short name T902
Test name
Test status
Simulation time 20043113785 ps
CPU time 149.14 seconds
Started Jun 27 04:53:16 PM PDT 24
Finished Jun 27 04:55:46 PM PDT 24
Peak memory 1405172 kb
Host smart-e0794378-0e66-47dd-b72b-81371e547b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249812571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.4249812571
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.3985489024
Short name T645
Test name
Test status
Simulation time 3074388028 ps
CPU time 7.16 seconds
Started Jun 27 04:53:19 PM PDT 24
Finished Jun 27 04:53:28 PM PDT 24
Peak memory 204940 kb
Host smart-3f924e6e-a8b5-4bdb-9537-0be7cf29174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985489024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.3985489024
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.2867988321
Short name T1357
Test name
Test status
Simulation time 9572822965 ps
CPU time 49.99 seconds
Started Jun 27 04:53:18 PM PDT 24
Finished Jun 27 04:54:10 PM PDT 24
Peak memory 496576 kb
Host smart-5c6724a2-2947-4aaa-a7a3-949c60b4346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867988321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.2867988321
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.884689228
Short name T33
Test name
Test status
Simulation time 25876209 ps
CPU time 0.67 seconds
Started Jun 27 04:53:17 PM PDT 24
Finished Jun 27 04:53:18 PM PDT 24
Peak memory 204548 kb
Host smart-7ee6e19d-971f-4d0c-be14-32618f7513c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884689228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.884689228
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.4054115220
Short name T1204
Test name
Test status
Simulation time 5871227318 ps
CPU time 169.17 seconds
Started Jun 27 04:53:15 PM PDT 24
Finished Jun 27 04:56:06 PM PDT 24
Peak memory 665272 kb
Host smart-b402db81-ce8a-468d-b7a1-199a9234d840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054115220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.4054115220
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.2324603001
Short name T847
Test name
Test status
Simulation time 361949132 ps
CPU time 1 seconds
Started Jun 27 04:53:25 PM PDT 24
Finished Jun 27 04:53:31 PM PDT 24
Peak memory 204572 kb
Host smart-e6b78c65-a6ce-4a91-aee9-039557f98cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324603001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.2324603001
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.3587742385
Short name T1253
Test name
Test status
Simulation time 5475038617 ps
CPU time 23.83 seconds
Started Jun 27 04:53:26 PM PDT 24
Finished Jun 27 04:53:56 PM PDT 24
Peak memory 322716 kb
Host smart-0eddaf9d-5c0e-471f-81f8-155fb1f8303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587742385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.3587742385
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.2858650929
Short name T47
Test name
Test status
Simulation time 67250459890 ps
CPU time 1501.79 seconds
Started Jun 27 04:53:18 PM PDT 24
Finished Jun 27 05:18:23 PM PDT 24
Peak memory 2343052 kb
Host smart-84fff29c-c115-4105-a9ec-12a125d0b750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858650929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.2858650929
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.1804495420
Short name T81
Test name
Test status
Simulation time 758294296 ps
CPU time 14.6 seconds
Started Jun 27 04:53:22 PM PDT 24
Finished Jun 27 04:53:41 PM PDT 24
Peak memory 215880 kb
Host smart-cfd11b14-5f47-4f64-a96a-e31e0172cac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804495420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.1804495420
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.3857690316
Short name T990
Test name
Test status
Simulation time 1965942306 ps
CPU time 3.02 seconds
Started Jun 27 04:53:19 PM PDT 24
Finished Jun 27 04:53:25 PM PDT 24
Peak memory 204904 kb
Host smart-ca1f896d-e42c-4a73-aece-11b621c8d759
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857690316 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.3857690316
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.787241703
Short name T1471
Test name
Test status
Simulation time 269491667 ps
CPU time 1.04 seconds
Started Jun 27 04:53:20 PM PDT 24
Finished Jun 27 04:53:24 PM PDT 24
Peak memory 204600 kb
Host smart-0b9a8aa1-14f8-406f-a0d3-9cee417ec84c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787241703 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_acq.787241703
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.4244625611
Short name T170
Test name
Test status
Simulation time 193811325 ps
CPU time 1.2 seconds
Started Jun 27 04:53:20 PM PDT 24
Finished Jun 27 04:53:23 PM PDT 24
Peak memory 212796 kb
Host smart-dd92377b-3179-4d99-a017-cea80b62634b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244625611 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.4244625611
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.464568962
Short name T797
Test name
Test status
Simulation time 586979050 ps
CPU time 2.86 seconds
Started Jun 27 04:53:23 PM PDT 24
Finished Jun 27 04:53:30 PM PDT 24
Peak memory 204720 kb
Host smart-aeff5abe-c033-42ad-857e-7436e09c10d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464568962 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.464568962
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.687108150
Short name T969
Test name
Test status
Simulation time 144356935 ps
CPU time 1.2 seconds
Started Jun 27 04:53:21 PM PDT 24
Finished Jun 27 04:53:25 PM PDT 24
Peak memory 204588 kb
Host smart-2587cf79-3c9d-4d0c-bddf-40b535e67a97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687108150 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.687108150
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.302849481
Short name T897
Test name
Test status
Simulation time 1689918199 ps
CPU time 2.83 seconds
Started Jun 27 04:53:22 PM PDT 24
Finished Jun 27 04:53:28 PM PDT 24
Peak memory 204776 kb
Host smart-1972677c-b315-4446-a114-7a8f003bf6ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302849481 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.i2c_target_hrst.302849481
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3275584019
Short name T680
Test name
Test status
Simulation time 1235496122 ps
CPU time 6.8 seconds
Started Jun 27 04:53:21 PM PDT 24
Finished Jun 27 04:53:32 PM PDT 24
Peak memory 213004 kb
Host smart-1fbb012e-700b-452d-9c59-ccb513bc5276
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275584019 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3275584019
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.3478595910
Short name T1451
Test name
Test status
Simulation time 13798398617 ps
CPU time 6.3 seconds
Started Jun 27 04:53:18 PM PDT 24
Finished Jun 27 04:53:26 PM PDT 24
Peak memory 204900 kb
Host smart-daaa12ff-b482-42c9-9be6-e33310598bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478595910 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.3478595910
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.417954341
Short name T580
Test name
Test status
Simulation time 1102671777 ps
CPU time 15.97 seconds
Started Jun 27 04:53:17 PM PDT 24
Finished Jun 27 04:53:34 PM PDT 24
Peak memory 205076 kb
Host smart-66b23a92-6b43-4277-819f-d82b4ad14815
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417954341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_tar
get_smoke.417954341
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1701215690
Short name T667
Test name
Test status
Simulation time 4985958830 ps
CPU time 23.47 seconds
Started Jun 27 04:53:18 PM PDT 24
Finished Jun 27 04:53:44 PM PDT 24
Peak memory 221396 kb
Host smart-bb809331-029d-4edc-a028-a542dde3b5b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701215690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1701215690
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3994712840
Short name T1129
Test name
Test status
Simulation time 36678130315 ps
CPU time 432.58 seconds
Started Jun 27 04:53:23 PM PDT 24
Finished Jun 27 05:00:40 PM PDT 24
Peak memory 4300552 kb
Host smart-d6775437-286c-4674-91f4-6521cd66d0b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994712840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3994712840
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.2736722602
Short name T424
Test name
Test status
Simulation time 8184688704 ps
CPU time 94.76 seconds
Started Jun 27 04:53:14 PM PDT 24
Finished Jun 27 04:54:50 PM PDT 24
Peak memory 600656 kb
Host smart-dfff7168-9507-46e5-9990-dcdc233ec52d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736722602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.2736722602
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.1479363588
Short name T459
Test name
Test status
Simulation time 1396181652 ps
CPU time 7.4 seconds
Started Jun 27 04:53:18 PM PDT 24
Finished Jun 27 04:53:28 PM PDT 24
Peak memory 212992 kb
Host smart-f73fc98e-0ef2-4fdf-a067-66e7ba557727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479363588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.1479363588
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_alert_test.2110124383
Short name T1396
Test name
Test status
Simulation time 37561851 ps
CPU time 0.59 seconds
Started Jun 27 04:53:26 PM PDT 24
Finished Jun 27 04:53:33 PM PDT 24
Peak memory 204500 kb
Host smart-ee4d839c-3b9b-4259-80d3-7ec3b4e128b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110124383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.2110124383
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2110601507
Short name T1305
Test name
Test status
Simulation time 641443817 ps
CPU time 4.64 seconds
Started Jun 27 04:53:26 PM PDT 24
Finished Jun 27 04:53:37 PM PDT 24
Peak memory 213116 kb
Host smart-1df50a7e-5183-49fb-a0f4-0fba4b0a63c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110601507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2110601507
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.4199080292
Short name T1086
Test name
Test status
Simulation time 7436739159 ps
CPU time 9.98 seconds
Started Jun 27 04:53:28 PM PDT 24
Finished Jun 27 04:53:45 PM PDT 24
Peak memory 306060 kb
Host smart-a88ea543-0167-44e9-950e-d17d30e81a2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199080292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.4199080292
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.3966617690
Short name T77
Test name
Test status
Simulation time 6982644835 ps
CPU time 45.99 seconds
Started Jun 27 04:53:19 PM PDT 24
Finished Jun 27 04:54:07 PM PDT 24
Peak memory 547308 kb
Host smart-e44601da-d578-46aa-96f0-8a024b897a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966617690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.3966617690
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.4045537271
Short name T470
Test name
Test status
Simulation time 24551019084 ps
CPU time 197.67 seconds
Started Jun 27 04:53:20 PM PDT 24
Finished Jun 27 04:56:41 PM PDT 24
Peak memory 819336 kb
Host smart-a66047a3-6abb-48b7-8565-782b188ae1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045537271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.4045537271
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.1531034850
Short name T934
Test name
Test status
Simulation time 112037131 ps
CPU time 0.96 seconds
Started Jun 27 04:53:19 PM PDT 24
Finished Jun 27 04:53:23 PM PDT 24
Peak memory 204492 kb
Host smart-8306fee7-e586-451c-8301-3fc72623b4c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531034850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.1531034850
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.1141924967
Short name T953
Test name
Test status
Simulation time 132679549 ps
CPU time 7.2 seconds
Started Jun 27 04:53:18 PM PDT 24
Finished Jun 27 04:53:27 PM PDT 24
Peak memory 225072 kb
Host smart-2e0079fd-1762-42de-9601-ef9205e9bc7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141924967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.1141924967
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.1006416617
Short name T101
Test name
Test status
Simulation time 3199035923 ps
CPU time 66.94 seconds
Started Jun 27 04:53:22 PM PDT 24
Finished Jun 27 04:54:34 PM PDT 24
Peak memory 958004 kb
Host smart-d46dddf2-994d-40fe-81ce-f261a4879a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006416617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.1006416617
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.3065497775
Short name T260
Test name
Test status
Simulation time 1834822832 ps
CPU time 6.78 seconds
Started Jun 27 04:53:21 PM PDT 24
Finished Jun 27 04:53:30 PM PDT 24
Peak memory 204688 kb
Host smart-c94eb621-5c7f-401c-823a-4e28caf579e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065497775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.3065497775
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.337856269
Short name T1412
Test name
Test status
Simulation time 6535612334 ps
CPU time 70.5 seconds
Started Jun 27 04:53:18 PM PDT 24
Finished Jun 27 04:54:31 PM PDT 24
Peak memory 337956 kb
Host smart-8d75d144-839a-4e45-819d-1c86b4139343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337856269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.337856269
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3563831751
Short name T138
Test name
Test status
Simulation time 386144769 ps
CPU time 0.69 seconds
Started Jun 27 04:53:17 PM PDT 24
Finished Jun 27 04:53:18 PM PDT 24
Peak memory 204460 kb
Host smart-88338379-7549-4663-8873-f82bc9079ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563831751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3563831751
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.1032342366
Short name T599
Test name
Test status
Simulation time 48401098416 ps
CPU time 480.04 seconds
Started Jun 27 04:53:22 PM PDT 24
Finished Jun 27 05:01:27 PM PDT 24
Peak memory 213172 kb
Host smart-451576bb-7f34-486a-a1f5-a808fc841e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032342366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.1032342366
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.4204355575
Short name T1472
Test name
Test status
Simulation time 163044980 ps
CPU time 3.17 seconds
Started Jun 27 04:53:19 PM PDT 24
Finished Jun 27 04:53:24 PM PDT 24
Peak memory 220872 kb
Host smart-bcd93fea-1503-4df4-9cd6-7190f8cd25da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204355575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.4204355575
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1491097414
Short name T1151
Test name
Test status
Simulation time 12633402906 ps
CPU time 63 seconds
Started Jun 27 04:53:17 PM PDT 24
Finished Jun 27 04:54:22 PM PDT 24
Peak memory 266176 kb
Host smart-86395fe4-1952-4173-b22b-dc01afccc78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491097414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1491097414
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.3118371531
Short name T122
Test name
Test status
Simulation time 21529180197 ps
CPU time 101.72 seconds
Started Jun 27 04:53:21 PM PDT 24
Finished Jun 27 04:55:06 PM PDT 24
Peak memory 544736 kb
Host smart-fb0dd984-958c-4573-aa63-11ad77e51ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118371531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.3118371531
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.629061171
Short name T306
Test name
Test status
Simulation time 2049373219 ps
CPU time 23.84 seconds
Started Jun 27 04:53:19 PM PDT 24
Finished Jun 27 04:53:45 PM PDT 24
Peak memory 212908 kb
Host smart-c38a5a05-77c3-4b27-81f3-3612dbe3c6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629061171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.629061171
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.4125539499
Short name T406
Test name
Test status
Simulation time 4375387209 ps
CPU time 5.24 seconds
Started Jun 27 04:53:26 PM PDT 24
Finished Jun 27 04:53:38 PM PDT 24
Peak memory 213208 kb
Host smart-8a22d3ff-0b94-4701-862c-44209d1ac342
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125539499 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.4125539499
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2629371009
Short name T777
Test name
Test status
Simulation time 512769866 ps
CPU time 0.75 seconds
Started Jun 27 04:53:19 PM PDT 24
Finished Jun 27 04:53:23 PM PDT 24
Peak memory 204612 kb
Host smart-6426dacf-c0da-42ad-9f07-5cc82965305c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629371009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2629371009
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.918968746
Short name T1059
Test name
Test status
Simulation time 453039846 ps
CPU time 1.08 seconds
Started Jun 27 04:53:18 PM PDT 24
Finished Jun 27 04:53:22 PM PDT 24
Peak memory 204780 kb
Host smart-e973666b-f4d2-4807-8474-561b507c358c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918968746 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.918968746
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.1083776548
Short name T1091
Test name
Test status
Simulation time 2042607859 ps
CPU time 1.79 seconds
Started Jun 27 04:53:20 PM PDT 24
Finished Jun 27 04:53:25 PM PDT 24
Peak memory 204796 kb
Host smart-e6f0ea5e-8d12-4e0e-af85-14207937b8af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083776548 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.1083776548
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.2232308453
Short name T1406
Test name
Test status
Simulation time 184932656 ps
CPU time 1.36 seconds
Started Jun 27 04:53:20 PM PDT 24
Finished Jun 27 04:53:25 PM PDT 24
Peak memory 204588 kb
Host smart-355ce1ae-22a1-455d-9068-ef84a98c4f3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232308453 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.2232308453
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.870049719
Short name T1257
Test name
Test status
Simulation time 280162657 ps
CPU time 2.62 seconds
Started Jun 27 04:53:25 PM PDT 24
Finished Jun 27 04:53:33 PM PDT 24
Peak memory 204824 kb
Host smart-0e9beb3b-b474-48ae-a516-1ad20fec5901
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870049719 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 49.i2c_target_hrst.870049719
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.3929316484
Short name T633
Test name
Test status
Simulation time 4666380756 ps
CPU time 5.53 seconds
Started Jun 27 04:53:28 PM PDT 24
Finished Jun 27 04:53:41 PM PDT 24
Peak memory 213160 kb
Host smart-427895bb-17f5-4fe1-98c6-48dc9a711b54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929316484 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.3929316484
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.977707813
Short name T1191
Test name
Test status
Simulation time 27283920037 ps
CPU time 211.86 seconds
Started Jun 27 04:53:19 PM PDT 24
Finished Jun 27 04:56:53 PM PDT 24
Peak memory 3269100 kb
Host smart-a4a6e9a2-90d6-45a3-b7a4-b3fd625440d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977707813 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.977707813
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.3795977793
Short name T368
Test name
Test status
Simulation time 3212798835 ps
CPU time 21.82 seconds
Started Jun 27 04:53:17 PM PDT 24
Finished Jun 27 04:53:41 PM PDT 24
Peak memory 204844 kb
Host smart-3e9d8871-6dab-4c58-bce3-957e559ea958
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795977793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.3795977793
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.3306720890
Short name T28
Test name
Test status
Simulation time 7799250785 ps
CPU time 26.56 seconds
Started Jun 27 04:53:24 PM PDT 24
Finished Jun 27 04:53:56 PM PDT 24
Peak memory 205008 kb
Host smart-5d5f7b09-cb3b-40f9-9789-62f0a263252c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306720890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_rd.3306720890
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3389443177
Short name T1102
Test name
Test status
Simulation time 55152372432 ps
CPU time 566.6 seconds
Started Jun 27 04:53:24 PM PDT 24
Finished Jun 27 05:02:55 PM PDT 24
Peak memory 4502536 kb
Host smart-c9a17e99-954e-49a2-97be-5fc5893423b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389443177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3389443177
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.1859746720
Short name T804
Test name
Test status
Simulation time 18063716740 ps
CPU time 747.49 seconds
Started Jun 27 04:53:22 PM PDT 24
Finished Jun 27 05:05:53 PM PDT 24
Peak memory 3411840 kb
Host smart-a4ac6151-3812-437a-810f-3544dbecf55a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859746720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.1859746720
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3460063809
Short name T810
Test name
Test status
Simulation time 1184383789 ps
CPU time 6.34 seconds
Started Jun 27 04:53:20 PM PDT 24
Finished Jun 27 04:53:28 PM PDT 24
Peak memory 216648 kb
Host smart-c6ab0860-0744-4daa-b20f-9c96ece7e7c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460063809 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3460063809
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_alert_test.1194260246
Short name T758
Test name
Test status
Simulation time 24744190 ps
CPU time 0.59 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 04:49:24 PM PDT 24
Peak memory 204504 kb
Host smart-1d0ab0d7-ae8f-4010-b85a-245688937353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194260246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1194260246
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2614853554
Short name T924
Test name
Test status
Simulation time 151593406 ps
CPU time 2.85 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:49:03 PM PDT 24
Peak memory 234464 kb
Host smart-26cff17f-1062-4706-a260-8912b7b6838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614853554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2614853554
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2152087774
Short name T456
Test name
Test status
Simulation time 815143677 ps
CPU time 3.87 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:24 PM PDT 24
Peak memory 246576 kb
Host smart-d7cc2597-269c-44d0-af98-aebc423ff8f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152087774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2152087774
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.1283967714
Short name T342
Test name
Test status
Simulation time 2644359393 ps
CPU time 79.63 seconds
Started Jun 27 04:49:20 PM PDT 24
Finished Jun 27 04:50:48 PM PDT 24
Peak memory 791316 kb
Host smart-b080d14c-370e-4a7b-a402-179c05dae013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283967714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.1283967714
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.3620720198
Short name T396
Test name
Test status
Simulation time 2867811354 ps
CPU time 64.82 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 04:50:28 PM PDT 24
Peak memory 685256 kb
Host smart-e48d75d5-e485-4e9b-9ad0-7dc25d68ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620720198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.3620720198
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2390176372
Short name T241
Test name
Test status
Simulation time 609889830 ps
CPU time 0.79 seconds
Started Jun 27 04:49:15 PM PDT 24
Finished Jun 27 04:49:27 PM PDT 24
Peak memory 204456 kb
Host smart-c0ee21fd-6604-4cbe-b7d6-576e5eea0546
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390176372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2390176372
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.3158864352
Short name T1110
Test name
Test status
Simulation time 127850063 ps
CPU time 3.23 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:48:54 PM PDT 24
Peak memory 204816 kb
Host smart-e33e2699-686f-44cc-8047-3d85bdd137c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158864352 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
3158864352
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.2550095846
Short name T99
Test name
Test status
Simulation time 22514386223 ps
CPU time 55.19 seconds
Started Jun 27 04:49:15 PM PDT 24
Finished Jun 27 04:50:21 PM PDT 24
Peak memory 878020 kb
Host smart-20004702-dbe1-4955-95ce-aba98b301586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550095846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.2550095846
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.838169911
Short name T44
Test name
Test status
Simulation time 252498371 ps
CPU time 3.87 seconds
Started Jun 27 04:48:59 PM PDT 24
Finished Jun 27 04:49:05 PM PDT 24
Peak memory 204784 kb
Host smart-16e41f15-92d5-401e-997f-66ba1d6dae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838169911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.838169911
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.1235715845
Short name T843
Test name
Test status
Simulation time 27787220186 ps
CPU time 31.52 seconds
Started Jun 27 04:48:55 PM PDT 24
Finished Jun 27 04:49:29 PM PDT 24
Peak memory 350656 kb
Host smart-e414cb53-48cc-4c17-a088-c3df0f50a930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235715845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.1235715845
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.1563834984
Short name T592
Test name
Test status
Simulation time 25737121 ps
CPU time 0.66 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 204516 kb
Host smart-595163d0-c67f-4cf9-afbc-1237a0d77a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563834984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1563834984
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.2221902355
Short name T1325
Test name
Test status
Simulation time 1150263936 ps
CPU time 2.09 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:19 PM PDT 24
Peak memory 205244 kb
Host smart-c27a25db-5c5e-46ce-bd78-02ac82681871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221902355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.2221902355
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.2058166391
Short name T700
Test name
Test status
Simulation time 237067747 ps
CPU time 3.19 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 225332 kb
Host smart-69b470fe-01d2-4a97-96f6-a7f32f793a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058166391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.2058166391
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.1485458645
Short name T1186
Test name
Test status
Simulation time 3366594798 ps
CPU time 32.28 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:50:04 PM PDT 24
Peak memory 399112 kb
Host smart-c408ac8d-6c92-420e-8a97-afd123de6304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485458645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.1485458645
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.2984875187
Short name T52
Test name
Test status
Simulation time 10616505922 ps
CPU time 123.41 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:51:13 PM PDT 24
Peak memory 742028 kb
Host smart-6bd5908a-f142-42d5-877a-a0635891d043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984875187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.2984875187
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.4157667051
Short name T474
Test name
Test status
Simulation time 2246035375 ps
CPU time 9.18 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 213156 kb
Host smart-a38be5d9-d24e-44a8-91b0-99dc741d83f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157667051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.4157667051
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.104606695
Short name T750
Test name
Test status
Simulation time 3810789776 ps
CPU time 4.65 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:25 PM PDT 24
Peak memory 204860 kb
Host smart-ab82491b-ac12-4031-a581-86652387ab4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104606695 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.104606695
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.2110415437
Short name T1208
Test name
Test status
Simulation time 567674527 ps
CPU time 1.06 seconds
Started Jun 27 04:48:54 PM PDT 24
Finished Jun 27 04:48:58 PM PDT 24
Peak memory 204580 kb
Host smart-06c989c1-741f-4b53-97eb-49211c998589
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110415437 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_fifo_reset_acq.2110415437
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.1557989888
Short name T291
Test name
Test status
Simulation time 185286497 ps
CPU time 1.19 seconds
Started Jun 27 04:48:59 PM PDT 24
Finished Jun 27 04:49:03 PM PDT 24
Peak memory 204576 kb
Host smart-0e280188-67bb-405c-b2a8-9eb14da508c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557989888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.1557989888
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.3482560303
Short name T1127
Test name
Test status
Simulation time 416481826 ps
CPU time 2.49 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:22 PM PDT 24
Peak memory 204824 kb
Host smart-a88c24f8-2f6b-43b9-b81a-a5ab61c76fe6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482560303 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.3482560303
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.4022424956
Short name T1422
Test name
Test status
Simulation time 120036880 ps
CPU time 1.14 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:16 PM PDT 24
Peak memory 204616 kb
Host smart-f1b659e9-7064-459a-a579-d589f24e3f1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022424956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.4022424956
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.453276047
Short name T434
Test name
Test status
Simulation time 1927516692 ps
CPU time 2.57 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 204844 kb
Host smart-6ad3e897-152a-4137-a695-4da980916156
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453276047 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 5.i2c_target_hrst.453276047
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2023964253
Short name T1135
Test name
Test status
Simulation time 853217000 ps
CPU time 4.71 seconds
Started Jun 27 04:48:53 PM PDT 24
Finished Jun 27 04:49:01 PM PDT 24
Peak memory 205628 kb
Host smart-7d7ff8c7-5b84-48f7-8b37-a35f0fd6701f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023964253 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2023964253
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3785153379
Short name T806
Test name
Test status
Simulation time 23455982833 ps
CPU time 487.98 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:57:28 PM PDT 24
Peak memory 5679244 kb
Host smart-8fbb0763-7a23-479b-a344-31723d4fd52b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785153379 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3785153379
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3932723492
Short name T182
Test name
Test status
Simulation time 2290236649 ps
CPU time 16.75 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:49:10 PM PDT 24
Peak memory 204912 kb
Host smart-9dd7cb36-ab87-41dd-a299-550f5a1dd2b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932723492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3932723492
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.280251883
Short name T1442
Test name
Test status
Simulation time 849887353 ps
CPU time 13.34 seconds
Started Jun 27 04:48:51 PM PDT 24
Finished Jun 27 04:49:12 PM PDT 24
Peak memory 213664 kb
Host smart-35c522aa-3e61-4914-a253-eaffc69fb20a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280251883 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_
target_stress_rd.280251883
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2409625457
Short name T551
Test name
Test status
Simulation time 13809692303 ps
CPU time 7.76 seconds
Started Jun 27 04:48:56 PM PDT 24
Finished Jun 27 04:49:06 PM PDT 24
Peak memory 204964 kb
Host smart-01e143de-b74c-4a1a-8c08-72a1d98544e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409625457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2409625457
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.1194688781
Short name T812
Test name
Test status
Simulation time 22055538991 ps
CPU time 15.51 seconds
Started Jun 27 04:48:57 PM PDT 24
Finished Jun 27 04:49:15 PM PDT 24
Peak memory 307264 kb
Host smart-0397588b-d8ac-45d1-8c0b-0d3d732b69dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194688781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.1194688781
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.1707868256
Short name T962
Test name
Test status
Simulation time 1222912153 ps
CPU time 6.38 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 213080 kb
Host smart-fbed687d-7334-44fd-8a55-ce7763d35e34
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707868256 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.1707868256
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_alert_test.4128894928
Short name T79
Test name
Test status
Simulation time 56606517 ps
CPU time 0.58 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:48:55 PM PDT 24
Peak memory 204400 kb
Host smart-eaec9b99-fb71-491b-abf4-02502ac37b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128894928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.4128894928
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.127272956
Short name T610
Test name
Test status
Simulation time 151796561 ps
CPU time 1.25 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 212996 kb
Host smart-8c47f13e-4068-4c8f-8f15-5977771fc656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127272956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.127272956
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3377888559
Short name T31
Test name
Test status
Simulation time 676987643 ps
CPU time 6.19 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:26 PM PDT 24
Peak memory 265528 kb
Host smart-a7dad44f-a76c-41aa-b28a-5d7d6fb41411
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377888559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3377888559
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.1244190105
Short name T525
Test name
Test status
Simulation time 4564588323 ps
CPU time 54.38 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:50:08 PM PDT 24
Peak memory 662032 kb
Host smart-05274852-df2c-4de4-980b-f76928dd0229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244190105 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.1244190105
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3432579466
Short name T855
Test name
Test status
Simulation time 2583780132 ps
CPU time 80.89 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:50:42 PM PDT 24
Peak memory 518680 kb
Host smart-6a24faf5-b96e-4387-a747-fa9dd3515484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432579466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3432579466
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.158148846
Short name T872
Test name
Test status
Simulation time 95968826 ps
CPU time 0.92 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:22 PM PDT 24
Peak memory 204548 kb
Host smart-1533e05b-354e-4bfc-9f0a-43fa95d5363e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158148846 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.158148846
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.1406344677
Short name T325
Test name
Test status
Simulation time 184816899 ps
CPU time 3.77 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 204720 kb
Host smart-2bc35640-61cf-4657-8aa7-2cad7af43730
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406344677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
1406344677
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.1659123411
Short name T280
Test name
Test status
Simulation time 3050921292 ps
CPU time 73.27 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:50:24 PM PDT 24
Peak memory 901856 kb
Host smart-17988645-67e7-433c-98e5-7d8111835547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659123411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.1659123411
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.3100768297
Short name T1463
Test name
Test status
Simulation time 2510257766 ps
CPU time 25.78 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 204928 kb
Host smart-d7a55383-3463-4ba8-b00b-7e15d91a1ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100768297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.3100768297
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.3751756421
Short name T745
Test name
Test status
Simulation time 6841882201 ps
CPU time 24.58 seconds
Started Jun 27 04:48:52 PM PDT 24
Finished Jun 27 04:49:19 PM PDT 24
Peak memory 317460 kb
Host smart-5f32c1a3-6876-4373-b1bb-29d93b94a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751756421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.3751756421
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.258235645
Short name T1227
Test name
Test status
Simulation time 28481427 ps
CPU time 0.64 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:19 PM PDT 24
Peak memory 204464 kb
Host smart-b61378d5-da53-4b85-a909-5d21517d7ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258235645 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.258235645
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.4024126433
Short name T663
Test name
Test status
Simulation time 1910569230 ps
CPU time 8 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:16 PM PDT 24
Peak memory 258920 kb
Host smart-7cbbfc41-9476-4852-aeb4-52385542128e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024126433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.4024126433
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.922292596
Short name T683
Test name
Test status
Simulation time 2886716333 ps
CPU time 43.92 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:54 PM PDT 24
Peak memory 204828 kb
Host smart-2d8fc4e3-a343-4af9-ae8d-e273dc05c495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922292596 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.922292596
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.209077703
Short name T1266
Test name
Test status
Simulation time 4716426911 ps
CPU time 97.05 seconds
Started Jun 27 04:49:15 PM PDT 24
Finished Jun 27 04:51:03 PM PDT 24
Peak memory 323260 kb
Host smart-8ace2593-1f2b-4060-81f7-21015bd510bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209077703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.209077703
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1745524555
Short name T694
Test name
Test status
Simulation time 1467339468 ps
CPU time 31.64 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:53 PM PDT 24
Peak memory 212904 kb
Host smart-7297b824-1589-49e6-b199-5401b3a8e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745524555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1745524555
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.4039350675
Short name T652
Test name
Test status
Simulation time 4067063886 ps
CPU time 2.8 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 204960 kb
Host smart-fabf920c-b49b-425c-a85d-9587e6073e4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039350675 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4039350675
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2144207702
Short name T127
Test name
Test status
Simulation time 126737430 ps
CPU time 0.82 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:49:31 PM PDT 24
Peak memory 204488 kb
Host smart-420cb6e7-729d-41f3-bcdd-557300faad9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144207702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2144207702
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.71522227
Short name T593
Test name
Test status
Simulation time 256913004 ps
CPU time 1.45 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 204736 kb
Host smart-26a06f98-9f72-42c5-92f0-37df0a850211
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71522227 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.i2c_target_fifo_reset_tx.71522227
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.2063090362
Short name T326
Test name
Test status
Simulation time 354129608 ps
CPU time 2.16 seconds
Started Jun 27 04:48:54 PM PDT 24
Finished Jun 27 04:49:03 PM PDT 24
Peak memory 204812 kb
Host smart-50061a15-0ad1-4a46-bf74-8f2ec60ce9fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063090362 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.2063090362
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.744444767
Short name T1409
Test name
Test status
Simulation time 492290000 ps
CPU time 1.14 seconds
Started Jun 27 04:49:03 PM PDT 24
Finished Jun 27 04:49:07 PM PDT 24
Peak memory 204616 kb
Host smart-ecb8b773-8ff6-4ab1-83c2-5d697860e8d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744444767 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.744444767
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1542234129
Short name T781
Test name
Test status
Simulation time 407063439 ps
CPU time 4.69 seconds
Started Jun 27 04:48:58 PM PDT 24
Finished Jun 27 04:49:05 PM PDT 24
Peak memory 204724 kb
Host smart-299d5004-0546-40ff-8db5-bc2bfa8280d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542234129 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1542234129
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.2418633284
Short name T1222
Test name
Test status
Simulation time 3798060788 ps
CPU time 5.25 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:48:57 PM PDT 24
Peak memory 219576 kb
Host smart-2480a0f7-a4b3-429e-9fd6-e335104b54f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418633284 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.2418633284
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.731339337
Short name T1248
Test name
Test status
Simulation time 21384406504 ps
CPU time 330.65 seconds
Started Jun 27 04:49:20 PM PDT 24
Finished Jun 27 04:55:04 PM PDT 24
Peak memory 4005716 kb
Host smart-63ff0d1d-d569-4d2c-8b96-d193166941d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731339337 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.731339337
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.4055640935
Short name T837
Test name
Test status
Simulation time 1802047489 ps
CPU time 15.02 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:28 PM PDT 24
Peak memory 204716 kb
Host smart-cc1a5f98-f440-4cb0-8c03-5e17ec00c1da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055640935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.4055640935
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.4112384240
Short name T109
Test name
Test status
Simulation time 1781543233 ps
CPU time 7.68 seconds
Started Jun 27 04:49:18 PM PDT 24
Finished Jun 27 04:49:36 PM PDT 24
Peak memory 204852 kb
Host smart-e768b611-18c1-479d-828b-66609203729c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112384240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.4112384240
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1414650578
Short name T563
Test name
Test status
Simulation time 24319974297 ps
CPU time 14.49 seconds
Started Jun 27 04:48:50 PM PDT 24
Finished Jun 27 04:49:07 PM PDT 24
Peak memory 310988 kb
Host smart-8dd2550e-6365-444f-80e8-a8255a35e1ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414650578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1414650578
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.307083297
Short name T880
Test name
Test status
Simulation time 17850614812 ps
CPU time 14.71 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:45 PM PDT 24
Peak memory 305740 kb
Host smart-4af88149-20f2-4b2b-bad0-ada8d1a6f2f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307083297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.307083297
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1691756130
Short name T305
Test name
Test status
Simulation time 49527332 ps
CPU time 0.6 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 204464 kb
Host smart-d1d39f60-e4a8-448a-9ce4-a8ba506035b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691756130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1691756130
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.3839499451
Short name T1279
Test name
Test status
Simulation time 96442798 ps
CPU time 2.54 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 04:49:26 PM PDT 24
Peak memory 213104 kb
Host smart-1137db00-9a51-4d9f-ae97-0b0448c0e2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839499451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.3839499451
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.2766484602
Short name T684
Test name
Test status
Simulation time 257318109 ps
CPU time 2.49 seconds
Started Jun 27 04:49:11 PM PDT 24
Finished Jun 27 04:49:25 PM PDT 24
Peak memory 223824 kb
Host smart-8e3348a7-e54c-4c2c-98a2-edd1c354764e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766484602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empt
y.2766484602
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.409086904
Short name T901
Test name
Test status
Simulation time 2089369772 ps
CPU time 63.52 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:50:13 PM PDT 24
Peak memory 616980 kb
Host smart-409c2507-7d41-4fbc-8189-119243e49c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409086904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.409086904
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.546183733
Short name T1383
Test name
Test status
Simulation time 3126351738 ps
CPU time 48.22 seconds
Started Jun 27 04:48:58 PM PDT 24
Finished Jun 27 04:49:48 PM PDT 24
Peak memory 563308 kb
Host smart-ad91ef5b-b356-4dc9-aaa3-807c50a21330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546183733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.546183733
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.2886192396
Short name T1389
Test name
Test status
Simulation time 155362273 ps
CPU time 1.11 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:12 PM PDT 24
Peak memory 204548 kb
Host smart-ab3cf904-fd74-4255-99b6-3e46e04e9570
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886192396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.2886192396
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.1071769858
Short name T311
Test name
Test status
Simulation time 377242700 ps
CPU time 10.86 seconds
Started Jun 27 04:48:56 PM PDT 24
Finished Jun 27 04:49:09 PM PDT 24
Peak memory 242072 kb
Host smart-634efbb8-173e-4ae9-a8ae-bc4fd126f37f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071769858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
1071769858
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.167490162
Short name T113
Test name
Test status
Simulation time 19065907130 ps
CPU time 159.39 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:51:59 PM PDT 24
Peak memory 851196 kb
Host smart-dc0a6324-5ba4-42f4-ae8b-bc8098d6f0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167490162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.167490162
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3254605130
Short name T176
Test name
Test status
Simulation time 1595573156 ps
CPU time 3.66 seconds
Started Jun 27 04:49:20 PM PDT 24
Finished Jun 27 04:49:32 PM PDT 24
Peak memory 204776 kb
Host smart-b9a2df9b-5b19-4d5d-a7f3-368635acc3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254605130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3254605130
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1691677888
Short name T891
Test name
Test status
Simulation time 1508891383 ps
CPU time 66.11 seconds
Started Jun 27 04:49:11 PM PDT 24
Finished Jun 27 04:50:28 PM PDT 24
Peak memory 335208 kb
Host smart-808ded40-ed74-4b33-b616-33aa50a38291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691677888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1691677888
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1115281231
Short name T141
Test name
Test status
Simulation time 68156355 ps
CPU time 0.66 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 204448 kb
Host smart-cfdb39e7-7614-49d6-9db9-edb9b63ed1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115281231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1115281231
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.2165307469
Short name T1354
Test name
Test status
Simulation time 3619413815 ps
CPU time 24.86 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:38 PM PDT 24
Peak memory 204988 kb
Host smart-e372a929-38f7-4bb0-afd0-66297f8aa448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165307469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.2165307469
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.2864944218
Short name T1434
Test name
Test status
Simulation time 595598083 ps
CPU time 4.62 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 04:49:28 PM PDT 24
Peak memory 212952 kb
Host smart-ef55805a-a670-4978-b2ed-2636f92cfa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864944218 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.2864944218
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.3316252243
Short name T1338
Test name
Test status
Simulation time 1779813028 ps
CPU time 30.97 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:38 PM PDT 24
Peak memory 329596 kb
Host smart-ed4d3a2a-9bca-4fd7-a71b-b5748bbfa416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316252243 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.3316252243
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.2400489911
Short name T284
Test name
Test status
Simulation time 20842525261 ps
CPU time 695.41 seconds
Started Jun 27 04:48:57 PM PDT 24
Finished Jun 27 05:00:35 PM PDT 24
Peak memory 1838624 kb
Host smart-b20a15dd-5896-4f9c-ac70-e77468ac3898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400489911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.2400489911
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.3380664716
Short name T1049
Test name
Test status
Simulation time 684655346 ps
CPU time 27.82 seconds
Started Jun 27 04:49:02 PM PDT 24
Finished Jun 27 04:49:32 PM PDT 24
Peak memory 213024 kb
Host smart-f1ac0522-c0b9-4034-90c2-4c15793780e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380664716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.3380664716
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3643166241
Short name T669
Test name
Test status
Simulation time 5358801230 ps
CPU time 3.8 seconds
Started Jun 27 04:49:03 PM PDT 24
Finished Jun 27 04:49:09 PM PDT 24
Peak memory 213068 kb
Host smart-1053d137-5040-462f-b31f-31ebb559afe0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643166241 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3643166241
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.2332555485
Short name T578
Test name
Test status
Simulation time 194256202 ps
CPU time 1.15 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 204612 kb
Host smart-94a06290-1f4e-40f3-8e21-1ba95351c0ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332555485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.2332555485
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.1754301358
Short name T148
Test name
Test status
Simulation time 43562466 ps
CPU time 0.75 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:31 PM PDT 24
Peak memory 204580 kb
Host smart-bf1bd55b-c7e8-46bd-9c76-515df72dbed6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754301358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.1754301358
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.1729599988
Short name T1267
Test name
Test status
Simulation time 391083602 ps
CPU time 1.05 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:49:34 PM PDT 24
Peak memory 204528 kb
Host smart-8c010cae-7c4e-403d-a3bd-784b8ba8728c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729599988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.1729599988
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.46156672
Short name T151
Test name
Test status
Simulation time 351271202 ps
CPU time 3.22 seconds
Started Jun 27 04:48:56 PM PDT 24
Finished Jun 27 04:49:02 PM PDT 24
Peak memory 204764 kb
Host smart-4228bcc7-7639-428a-8a55-5ef268fbcc36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46156672 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.i2c_target_hrst.46156672
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.2681297815
Short name T666
Test name
Test status
Simulation time 538307179 ps
CPU time 3.12 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 204712 kb
Host smart-9502c9d6-7eb1-40fa-a276-9f3e5aeaeaf0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681297815 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.2681297815
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.685255372
Short name T1093
Test name
Test status
Simulation time 13952235261 ps
CPU time 19.78 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 489628 kb
Host smart-1b25e53d-0c84-498b-b8f2-f5f2a4fe7174
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685255372 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.685255372
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.2990672366
Short name T499
Test name
Test status
Simulation time 4489842523 ps
CPU time 45.85 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:50:06 PM PDT 24
Peak memory 204976 kb
Host smart-e0685b8c-d471-4659-842b-819c920b2617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990672366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.2990672366
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.56330923
Short name T19
Test name
Test status
Simulation time 746527496 ps
CPU time 28.74 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 204836 kb
Host smart-96dfca66-0b03-471e-8b02-063df7b1d9b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56330923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stress_rd.56330923
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.2723042769
Short name T609
Test name
Test status
Simulation time 57196152417 ps
CPU time 158.04 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:51:54 PM PDT 24
Peak memory 2024064 kb
Host smart-d43e4013-595d-4609-aaae-9c5eec920cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723042769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.2723042769
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2948124776
Short name T918
Test name
Test status
Simulation time 14089762397 ps
CPU time 42.88 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:54 PM PDT 24
Peak memory 693984 kb
Host smart-d11b715f-7181-4a33-b178-d84717895c44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948124776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2948124776
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.964304023
Short name T766
Test name
Test status
Simulation time 2188376030 ps
CPU time 5.92 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:12 PM PDT 24
Peak memory 204884 kb
Host smart-f50c8116-40f4-4144-8985-bbc821a07d9c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964304023 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_timeout.964304023
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3784535986
Short name T1150
Test name
Test status
Simulation time 17973589 ps
CPU time 0.63 seconds
Started Jun 27 04:49:21 PM PDT 24
Finished Jun 27 04:49:30 PM PDT 24
Peak memory 204344 kb
Host smart-422468b3-468e-4bd2-b7b4-e7300798061f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784535986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3784535986
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.1971337236
Short name T1309
Test name
Test status
Simulation time 132177640 ps
CPU time 1.79 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 213108 kb
Host smart-7b8b1067-4588-4c7b-90b1-86f4b0060217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971337236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.1971337236
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.1887164136
Short name T400
Test name
Test status
Simulation time 790775242 ps
CPU time 7.01 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:33 PM PDT 24
Peak memory 289840 kb
Host smart-1ef7bcdf-2529-47ca-8178-c3da3c6d41cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887164136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.1887164136
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.3505777816
Short name T1376
Test name
Test status
Simulation time 2123193469 ps
CPU time 56.07 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:50:04 PM PDT 24
Peak memory 627972 kb
Host smart-5b6e2ee2-05e2-4cd0-856b-b37cf6d0b83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505777816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.3505777816
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.749932070
Short name T1118
Test name
Test status
Simulation time 5776189190 ps
CPU time 35.74 seconds
Started Jun 27 04:49:27 PM PDT 24
Finished Jun 27 04:50:10 PM PDT 24
Peak memory 487576 kb
Host smart-5cdeea8d-c183-4a4f-8020-1dc5d76a8817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749932070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.749932070
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.2690389618
Short name T1052
Test name
Test status
Simulation time 580749009 ps
CPU time 0.8 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:23 PM PDT 24
Peak memory 204548 kb
Host smart-6866d925-25d4-449c-83b1-27f97fa75b2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690389618 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.2690389618
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.148403972
Short name T393
Test name
Test status
Simulation time 812557895 ps
CPU time 9.61 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:49:45 PM PDT 24
Peak memory 204876 kb
Host smart-a218dc46-1614-4ab1-8adb-449c5cd7b88b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148403972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.148403972
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.88288073
Short name T1411
Test name
Test status
Simulation time 3380420557 ps
CPU time 215.65 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:53:06 PM PDT 24
Peak memory 1020868 kb
Host smart-5263d005-b7c9-4617-b599-d7f0dce2cca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88288073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.88288073
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.320205495
Short name T799
Test name
Test status
Simulation time 2557783571 ps
CPU time 9.72 seconds
Started Jun 27 04:49:22 PM PDT 24
Finished Jun 27 04:49:40 PM PDT 24
Peak memory 205000 kb
Host smart-7413b7d9-ffe4-4948-9d58-9096bcabbaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320205495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.320205495
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.1341404976
Short name T64
Test name
Test status
Simulation time 11973949325 ps
CPU time 19.42 seconds
Started Jun 27 04:49:03 PM PDT 24
Finished Jun 27 04:49:25 PM PDT 24
Peak memory 312980 kb
Host smart-1ebbd030-1d49-414b-84b3-9db2ab97ec5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341404976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.1341404976
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.1953253737
Short name T808
Test name
Test status
Simulation time 50971911 ps
CPU time 0.67 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:20 PM PDT 24
Peak memory 204472 kb
Host smart-aa672dff-78e0-43f4-8411-4b765bf55e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953253737 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1953253737
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.2546143693
Short name T957
Test name
Test status
Simulation time 5219816444 ps
CPU time 296.4 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:54:17 PM PDT 24
Peak memory 794616 kb
Host smart-cd1535da-f6fb-4c09-aea9-e0b6f4494150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546143693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.2546143693
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.2563593392
Short name T536
Test name
Test status
Simulation time 2537693838 ps
CPU time 2.91 seconds
Started Jun 27 04:49:13 PM PDT 24
Finished Jun 27 04:49:27 PM PDT 24
Peak memory 240580 kb
Host smart-ecc2aa72-8086-48ac-bc34-f0a337c2ff57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563593392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.2563593392
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.202002683
Short name T765
Test name
Test status
Simulation time 6080388759 ps
CPU time 20.56 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:49:52 PM PDT 24
Peak memory 328412 kb
Host smart-69501a82-628b-46b9-aedd-d292d539ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202002683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.202002683
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2840372410
Short name T120
Test name
Test status
Simulation time 90377658143 ps
CPU time 1246.6 seconds
Started Jun 27 04:49:14 PM PDT 24
Finished Jun 27 05:10:12 PM PDT 24
Peak memory 2201532 kb
Host smart-608a1262-eb22-45aa-a2ba-0aa466dc604e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840372410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2840372410
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.2891735603
Short name T649
Test name
Test status
Simulation time 1046428577 ps
CPU time 45.83 seconds
Started Jun 27 04:49:13 PM PDT 24
Finished Jun 27 04:50:09 PM PDT 24
Peak memory 213992 kb
Host smart-29c2f14c-2686-4318-8ac1-0bdbf4134f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891735603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.2891735603
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.1112639035
Short name T25
Test name
Test status
Simulation time 2184306534 ps
CPU time 3.42 seconds
Started Jun 27 04:49:04 PM PDT 24
Finished Jun 27 04:49:12 PM PDT 24
Peak memory 204960 kb
Host smart-79110550-83f2-4d9b-af97-40899d262458
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112639035 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.1112639035
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2642766280
Short name T1485
Test name
Test status
Simulation time 190634996 ps
CPU time 0.84 seconds
Started Jun 27 04:49:39 PM PDT 24
Finished Jun 27 04:49:45 PM PDT 24
Peak memory 204604 kb
Host smart-645ae728-8e9c-418b-9a1a-c445600d5693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642766280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2642766280
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2574028742
Short name T820
Test name
Test status
Simulation time 536869818 ps
CPU time 1.06 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:17 PM PDT 24
Peak memory 204628 kb
Host smart-2224e3c2-53f3-4272-987d-c3c0387f475e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574028742 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2574028742
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.2934994372
Short name T618
Test name
Test status
Simulation time 726393033 ps
CPU time 1.99 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:16 PM PDT 24
Peak memory 204736 kb
Host smart-d5ecd7bf-3ba0-43ff-9d7e-af4a34b7e330
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934994372 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.2934994372
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.3029403690
Short name T23
Test name
Test status
Simulation time 131540199 ps
CPU time 1.18 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:12 PM PDT 24
Peak memory 204336 kb
Host smart-0bbefcc5-9cc7-440e-b06c-ab97edd80d97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029403690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.3029403690
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.1178588636
Short name T1004
Test name
Test status
Simulation time 1155140689 ps
CPU time 2.29 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 204724 kb
Host smart-ee0e09d2-ee4a-497a-8898-0d019d47b844
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178588636 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.1178588636
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.2332282828
Short name T1040
Test name
Test status
Simulation time 2911433910 ps
CPU time 4.18 seconds
Started Jun 27 04:49:09 PM PDT 24
Finished Jun 27 04:49:24 PM PDT 24
Peak memory 213040 kb
Host smart-a4e8089a-8f33-4fb1-bd6e-85a8c6c4a578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332282828 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.2332282828
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.1558388974
Short name T345
Test name
Test status
Simulation time 33505053961 ps
CPU time 35.52 seconds
Started Jun 27 04:49:30 PM PDT 24
Finished Jun 27 04:50:12 PM PDT 24
Peak memory 841180 kb
Host smart-bda01ceb-7169-48d1-b0bb-05ea9bad3221
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558388974 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.1558388974
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.1561174104
Short name T1138
Test name
Test status
Simulation time 1234085050 ps
CPU time 14.58 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:49:46 PM PDT 24
Peak memory 204784 kb
Host smart-02ca8b78-337c-4816-9307-2ac69cc27753
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561174104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.1561174104
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.4119690502
Short name T1362
Test name
Test status
Simulation time 1276221053 ps
CPU time 6.16 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 04:49:33 PM PDT 24
Peak memory 206864 kb
Host smart-e87f0c83-bda2-455b-b830-e739dc15cb2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119690502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.4119690502
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.3071678176
Short name T603
Test name
Test status
Simulation time 34896199129 ps
CPU time 8.31 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:23 PM PDT 24
Peak memory 246368 kb
Host smart-aeec56b4-eaa0-4538-85b4-501f5983dbac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071678176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.3071678176
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.4113504732
Short name T787
Test name
Test status
Simulation time 40644991802 ps
CPU time 888.5 seconds
Started Jun 27 04:49:12 PM PDT 24
Finished Jun 27 05:04:12 PM PDT 24
Peak memory 4895768 kb
Host smart-6936c7ea-9039-4cf1-8400-741698ca9d54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113504732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.4113504732
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3574414358
Short name T1272
Test name
Test status
Simulation time 20066139080 ps
CPU time 7.58 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:24 PM PDT 24
Peak memory 217904 kb
Host smart-9f3c01e8-8773-4e41-892b-bfb0a5936adb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574414358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3574414358
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_alert_test.406734217
Short name T1384
Test name
Test status
Simulation time 16157279 ps
CPU time 0.62 seconds
Started Jun 27 04:49:06 PM PDT 24
Finished Jun 27 04:49:14 PM PDT 24
Peak memory 204492 kb
Host smart-9e8c30c5-da72-44f7-84bc-57ad86df4b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406734217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.406734217
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.1199171124
Short name T717
Test name
Test status
Simulation time 192016105 ps
CPU time 1.52 seconds
Started Jun 27 04:49:19 PM PDT 24
Finished Jun 27 04:49:30 PM PDT 24
Peak memory 212960 kb
Host smart-a8da4004-1126-4388-b5b2-9638b49f054d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199171124 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.1199171124
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.705494457
Short name T489
Test name
Test status
Simulation time 733437676 ps
CPU time 6.94 seconds
Started Jun 27 04:49:07 PM PDT 24
Finished Jun 27 04:49:24 PM PDT 24
Peak memory 282312 kb
Host smart-642f1fb5-807b-4307-a8b4-095b54ccc435
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705494457 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empty
.705494457
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.169434650
Short name T73
Test name
Test status
Simulation time 1878907933 ps
CPU time 60.53 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 04:50:32 PM PDT 24
Peak memory 631528 kb
Host smart-5549a9fd-7666-4fa4-92cc-610f06cbefd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169434650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.169434650
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.2237584086
Short name T86
Test name
Test status
Simulation time 9799202500 ps
CPU time 72.54 seconds
Started Jun 27 04:50:00 PM PDT 24
Finished Jun 27 04:51:16 PM PDT 24
Peak memory 627524 kb
Host smart-e3439691-7c3d-4c2a-8873-0b79c1c15689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237584086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.2237584086
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1250109925
Short name T1321
Test name
Test status
Simulation time 533806182 ps
CPU time 0.79 seconds
Started Jun 27 04:49:33 PM PDT 24
Finished Jun 27 04:49:39 PM PDT 24
Peak memory 204500 kb
Host smart-394a5a93-4d73-4623-b454-28cd0beebaa4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250109925 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1250109925
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.1597185172
Short name T785
Test name
Test status
Simulation time 1160517465 ps
CPU time 4.2 seconds
Started Jun 27 04:49:08 PM PDT 24
Finished Jun 27 04:49:21 PM PDT 24
Peak memory 229900 kb
Host smart-5209eb32-3b08-4391-874c-acbd4e3513e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597185172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
1597185172
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.3514065592
Short name T707
Test name
Test status
Simulation time 37874916554 ps
CPU time 336 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:55:11 PM PDT 24
Peak memory 1333836 kb
Host smart-1661306b-dce7-4e5a-9b96-875e41621921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514065592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.3514065592
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.1746901072
Short name T1063
Test name
Test status
Simulation time 700496891 ps
CPU time 4.57 seconds
Started Jun 27 04:49:40 PM PDT 24
Finished Jun 27 04:49:49 PM PDT 24
Peak memory 204796 kb
Host smart-e873bbfd-b882-4203-a5a5-50b4da93ef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746901072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.1746901072
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.2472065195
Short name T1195
Test name
Test status
Simulation time 14659935022 ps
CPU time 37.88 seconds
Started Jun 27 04:49:26 PM PDT 24
Finished Jun 27 04:50:11 PM PDT 24
Peak memory 335652 kb
Host smart-2a7c3ab8-376c-4ce6-bd4d-4f3817b83870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472065195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.2472065195
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.918076888
Short name T710
Test name
Test status
Simulation time 189376392 ps
CPU time 0.69 seconds
Started Jun 27 04:49:27 PM PDT 24
Finished Jun 27 04:49:35 PM PDT 24
Peak memory 204428 kb
Host smart-485b3c15-1ccc-409f-8011-06ad2236d9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918076888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.918076888
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.939638119
Short name T1099
Test name
Test status
Simulation time 23752563805 ps
CPU time 932.23 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 05:05:03 PM PDT 24
Peak memory 213128 kb
Host smart-9b8ea59d-661f-4c2c-bed6-395a80537050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939638119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.939638119
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.1290332889
Short name T1156
Test name
Test status
Simulation time 31131101 ps
CPU time 1.73 seconds
Started Jun 27 04:49:10 PM PDT 24
Finished Jun 27 04:49:23 PM PDT 24
Peak memory 223216 kb
Host smart-d127b453-d6e2-4a24-aad6-c129f12fb5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290332889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.1290332889
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.1764107560
Short name T1371
Test name
Test status
Simulation time 1390767477 ps
CPU time 25.64 seconds
Started Jun 27 04:49:18 PM PDT 24
Finished Jun 27 04:49:54 PM PDT 24
Peak memory 331172 kb
Host smart-3231c8c5-928d-4626-bc97-8e4ff48340d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764107560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.1764107560
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.3730748186
Short name T681
Test name
Test status
Simulation time 91720322698 ps
CPU time 3132.38 seconds
Started Jun 27 04:49:24 PM PDT 24
Finished Jun 27 05:41:44 PM PDT 24
Peak memory 2290272 kb
Host smart-2a274fb5-99d1-440d-945c-a94b0f8667b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730748186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.3730748186
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.3079768284
Short name T107
Test name
Test status
Simulation time 595234530 ps
CPU time 8.98 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:40 PM PDT 24
Peak memory 220824 kb
Host smart-10c655ff-7e73-420e-8f43-d6a482a69c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079768284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.3079768284
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.1224793509
Short name T1326
Test name
Test status
Simulation time 1069421678 ps
CPU time 4.93 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:49:37 PM PDT 24
Peak memory 215084 kb
Host smart-544a6e13-5c40-4045-9332-05f7950660ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224793509 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.1224793509
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.908616676
Short name T1308
Test name
Test status
Simulation time 170248656 ps
CPU time 1.1 seconds
Started Jun 27 04:49:38 PM PDT 24
Finished Jun 27 04:49:44 PM PDT 24
Peak memory 204496 kb
Host smart-b318c08a-2043-46c2-b45c-5b9ae2f5aefb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908616676 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_acq.908616676
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.1124650337
Short name T1021
Test name
Test status
Simulation time 458635078 ps
CPU time 0.92 seconds
Started Jun 27 04:49:27 PM PDT 24
Finished Jun 27 04:49:35 PM PDT 24
Peak memory 204412 kb
Host smart-a7ebb6e4-6974-4753-b8dc-40a14dd393e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124650337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.1124650337
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.2013833632
Short name T1245
Test name
Test status
Simulation time 1329883183 ps
CPU time 1.99 seconds
Started Jun 27 04:49:39 PM PDT 24
Finished Jun 27 04:49:45 PM PDT 24
Peak memory 204784 kb
Host smart-81e847be-426c-45ac-81f6-2512d574c380
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013833632 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.2013833632
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.507709975
Short name T751
Test name
Test status
Simulation time 184771435 ps
CPU time 1.34 seconds
Started Jun 27 04:49:26 PM PDT 24
Finished Jun 27 04:49:35 PM PDT 24
Peak memory 204548 kb
Host smart-029d1790-9684-4a76-baf8-8119b31008d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507709975 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.507709975
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.585326682
Short name T564
Test name
Test status
Simulation time 336807365 ps
CPU time 2.81 seconds
Started Jun 27 04:49:25 PM PDT 24
Finished Jun 27 04:49:36 PM PDT 24
Peak memory 204768 kb
Host smart-1cb2871d-4d15-49b7-9dfe-9874dd822018
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585326682 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.i2c_target_hrst.585326682
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.821182674
Short name T339
Test name
Test status
Simulation time 1870537888 ps
CPU time 4.67 seconds
Started Jun 27 04:49:23 PM PDT 24
Finished Jun 27 04:49:36 PM PDT 24
Peak memory 204752 kb
Host smart-32723dc3-b69d-4da4-8f63-7f9370706681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821182674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.821182674
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.854802138
Short name T1003
Test name
Test status
Simulation time 8059498303 ps
CPU time 80.49 seconds
Started Jun 27 04:49:31 PM PDT 24
Finished Jun 27 04:50:58 PM PDT 24
Peak memory 1757604 kb
Host smart-bd96a7fc-32aa-42d3-aa60-5d0d84ca21bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854802138 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.854802138
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.4055385028
Short name T1185
Test name
Test status
Simulation time 4618858005 ps
CPU time 7.7 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:49:43 PM PDT 24
Peak memory 204900 kb
Host smart-8b157a4b-77d8-4549-8ad1-bb0293b52a05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055385028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.4055385028
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2026620826
Short name T144
Test name
Test status
Simulation time 3023839216 ps
CPU time 31.29 seconds
Started Jun 27 04:49:28 PM PDT 24
Finished Jun 27 04:50:07 PM PDT 24
Peak memory 204936 kb
Host smart-1a12bb78-ffe4-4a05-8060-ce9988c6cb10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026620826 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2026620826
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.933402029
Short name T158
Test name
Test status
Simulation time 22168248806 ps
CPU time 12.86 seconds
Started Jun 27 04:49:18 PM PDT 24
Finished Jun 27 04:49:41 PM PDT 24
Peak memory 204880 kb
Host smart-c5294721-c6a8-4964-ba07-a63d21b03d02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933402029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.933402029
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.3770592405
Short name T441
Test name
Test status
Simulation time 28066366001 ps
CPU time 171.59 seconds
Started Jun 27 04:49:19 PM PDT 24
Finished Jun 27 04:52:20 PM PDT 24
Peak memory 1515288 kb
Host smart-d93ecb4f-5104-444e-b631-591d24ad3b21
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770592405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.3770592405
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.3933685694
Short name T32
Test name
Test status
Simulation time 3621752354 ps
CPU time 7.27 seconds
Started Jun 27 04:49:05 PM PDT 24
Finished Jun 27 04:49:18 PM PDT 24
Peak memory 221048 kb
Host smart-15737231-472e-423d-8e4b-0d4211ff8763
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933685694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.3933685694
Directory /workspace/9.i2c_target_timeout/latest
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