Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	899281	1			T1	2		T2	287		T3	1
all_values[1]	899281	1			T1	2		T2	287		T3	1
all_values[2]	899281	1			T1	2		T2	287		T3	1
all_values[3]	899281	1			T1	2		T2	287		T3	1
all_values[4]	899281	1			T1	2		T2	287		T3	1
all_values[5]	899281	1			T1	2		T2	287		T3	1
all_values[6]	899281	1			T1	2		T2	287		T3	1
all_values[7]	899281	1			T1	2		T2	287		T3	1
all_values[8]	899281	1			T1	2		T2	287		T3	1
all_values[9]	899281	1			T1	2		T2	287		T3	1
all_values[10]	899281	1			T1	2		T2	287		T3	1
all_values[11]	899281	1			T1	2		T2	287		T3	1
all_values[12]	899281	1			T1	2		T2	287		T3	1
all_values[13]	899281	1			T1	2		T2	287		T3	1
all_values[14]	899281	1			T1	2		T2	287		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11077344

1

T1

26

T2

3944

T3

15

auto[1]

2411871

1

T1

4

T2

361

T4

450

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12121464

1

T1

30

T2

4305

T3

15

auto[1]

1367751

1

T62

213749

T106

5818

T82

112

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	120672	1			T2	215		T3	1		T4	6
all_values[0]	auto[0]	auto[1]	4783	1			T62	603		T106	22		T212	1
all_values[0]	auto[1]	auto[0]	715720	1			T1	2		T2	72		T4	193
all_values[0]	auto[1]	auto[1]	58106	1			T62	13647		T106	367		T212	13
all_values[1]	auto[0]	auto[0]	835939	1			T1	2		T2	287		T3	1
all_values[1]	auto[0]	auto[1]	62722	1			T62	14244		T106	378		T82	6
all_values[1]	auto[1]	auto[0]	444	1			T41	5		T233	6		T234	4
all_values[1]	auto[1]	auto[1]	176	1			T62	7		T106	11		T82	3
all_values[2]	auto[0]	auto[0]	797605	1			T1	2		T2	287		T3	1
all_values[2]	auto[0]	auto[1]	101446	1			T62	14242		T106	378		T82	7
all_values[2]	auto[1]	auto[0]	50	1			T176	1		T117	1		T235	1
all_values[2]	auto[1]	auto[1]	180	1			T62	8		T106	11		T82	2
all_values[3]	auto[0]	auto[0]	836387	1			T1	2		T2	287		T3	1
all_values[3]	auto[0]	auto[1]	62700	1			T62	14243		T106	381		T82	6
all_values[3]	auto[1]	auto[1]	194	1			T62	8		T106	8		T82	2
all_values[4]	auto[0]	auto[0]	799252	1			T1	2		T2	287		T3	1
all_values[4]	auto[0]	auto[1]	99843	1			T62	14241		T106	373		T82	6
all_values[4]	auto[1]	auto[0]	19	1			T38	1		T40	1		T236	1
all_values[4]	auto[1]	auto[1]	167	1			T62	6		T106	8		T82	2
all_values[5]	auto[0]	auto[0]	797649	1			T1	2		T2	287		T3	1
all_values[5]	auto[0]	auto[1]	101427	1			T62	14243		T106	377		T82	8
all_values[5]	auto[1]	auto[1]	205	1			T62	8		T106	10		T82	1
all_values[6]	auto[0]	auto[0]	797628	1			T1	2		T2	287		T3	1
all_values[6]	auto[0]	auto[1]	101455	1			T62	14238		T106	385		T82	8
all_values[6]	auto[1]	auto[1]	198	1			T62	11		T106	4		T82	1
all_values[7]	auto[0]	auto[0]	769918	1			T1	2		T2	284		T3	1
all_values[7]	auto[0]	auto[1]	98730	1			T62	13748		T106	323		T82	5
all_values[7]	auto[1]	auto[0]	27725	1			T2	3		T4	47		T7	185
all_values[7]	auto[1]	auto[1]	2908	1			T62	499		T106	66		T82	4
all_values[8]	auto[0]	auto[0]	797635	1			T1	2		T2	287		T3	1
all_values[8]	auto[0]	auto[1]	101438	1			T62	14239		T106	380		T82	7
all_values[8]	auto[1]	auto[1]	208	1			T62	11		T106	9		T82	2
all_values[9]	auto[0]	auto[0]	180281	1			T1	2		T2	284		T3	1
all_values[9]	auto[0]	auto[1]	10165	1			T62	1190		T106	352		T82	4
all_values[9]	auto[1]	auto[0]	617352	1			T2	3		T4	15		T7	13390
all_values[9]	auto[1]	auto[1]	91483	1			T62	13061		T106	37		T82	4
all_values[10]	auto[0]	auto[0]	797649	1			T1	2		T2	287		T3	1
all_values[10]	auto[0]	auto[1]	101457	1			T62	14245		T106	377		T82	8
all_values[10]	auto[1]	auto[1]	175	1			T62	6		T106	7		T82	1
all_values[11]	auto[0]	auto[0]	2949	1			T2	4		T3	1		T4	4
all_values[11]	auto[0]	auto[1]	358	1			T62	47		T106	13		T82	3
all_values[11]	auto[1]	auto[0]	794911	1			T1	2		T2	283		T4	195
all_values[11]	auto[1]	auto[1]	101063	1			T62	14203		T106	375		T82	6
all_values[12]	auto[0]	auto[0]	797637	1			T1	2		T2	287		T3	1
all_values[12]	auto[0]	auto[1]	101447	1			T62	14241		T106	381		T82	7
all_values[12]	auto[1]	auto[0]	13	1			T237	1		T238	1		T239	1
all_values[12]	auto[1]	auto[1]	184	1			T62	9		T106	8		T82	2
all_values[13]	auto[0]	auto[0]	797649	1			T1	2		T2	287		T3	1
all_values[13]	auto[0]	auto[1]	101442	1			T62	14243		T106	374		T82	5
all_values[13]	auto[1]	auto[1]	190	1			T62	8		T106	14		T82	2
all_values[14]	auto[0]	auto[0]	836380	1			T1	2		T2	287		T3	1
all_values[14]	auto[0]	auto[1]	62701	1			T62	14242		T106	382		T212	8
all_values[14]	auto[1]	auto[1]	200	1			T62	8		T106	7		T212	6