Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	899281	1			T1	2		T2	287		T3	1
all_pins[1]	899281	1			T1	2		T2	287		T3	1
all_pins[2]	899281	1			T1	2		T2	287		T3	1
all_pins[3]	899281	1			T1	2		T2	287		T3	1
all_pins[4]	899281	1			T1	2		T2	287		T3	1
all_pins[5]	899281	1			T1	2		T2	287		T3	1
all_pins[6]	899281	1			T1	2		T2	287		T3	1
all_pins[7]	899281	1			T1	2		T2	287		T3	1
all_pins[8]	899281	1			T1	2		T2	287		T3	1
all_pins[9]	899281	1			T1	2		T2	287		T3	1
all_pins[10]	899281	1			T1	2		T2	287		T3	1
all_pins[11]	899281	1			T1	2		T2	287		T3	1
all_pins[12]	899281	1			T1	2		T2	287		T3	1
all_pins[13]	899281	1			T1	2		T2	287		T3	1
all_pins[14]	899281	1			T1	2		T2	287		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11083239	1			T1	26		T2	3944		T3	15
values[0x1]	2405976	1			T1	4		T2	361		T4	455
transitions[0x0=>0x1]	2405100	1			T1	4		T2	361		T4	455
transitions[0x1=>0x0]	2403945	1			T1	3		T2	360		T4	454

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	129114	1			T2	215		T3	1		T4	6
all_pins[0]	values[0x1]	770167	1			T1	2		T2	72		T4	193
all_pins[0]	transitions[0x0=>0x1]	769675	1			T1	2		T2	72		T4	193
all_pins[0]	transitions[0x1=>0x0]	136	1			T62	3		T106	1		T252	1
all_pins[1]	values[0x0]	898653	1			T1	2		T2	287		T3	1
all_pins[1]	values[0x1]	628	1			T62	3		T41	6		T233	8
all_pins[1]	transitions[0x0=>0x1]	608	1			T62	2		T41	6		T233	8
all_pins[1]	transitions[0x1=>0x0]	121	1			T62	4		T176	1		T117	1
all_pins[2]	values[0x0]	899140	1			T1	2		T2	287		T3	1
all_pins[2]	values[0x1]	141	1			T62	5		T176	1		T117	1
all_pins[2]	transitions[0x0=>0x1]	120	1			T62	5		T176	1		T117	1
all_pins[2]	transitions[0x1=>0x0]	85	1			T62	4		T106	1		T212	2
all_pins[3]	values[0x0]	899175	1			T1	2		T2	287		T3	1
all_pins[3]	values[0x1]	106	1			T62	4		T106	2		T212	3
all_pins[3]	transitions[0x0=>0x1]	83	1			T62	3		T106	2		T212	3
all_pins[3]	transitions[0x1=>0x0]	82	1			T38	1		T62	2		T40	1
all_pins[4]	values[0x0]	899176	1			T1	2		T2	287		T3	1
all_pins[4]	values[0x1]	105	1			T38	1		T62	3		T40	1
all_pins[4]	transitions[0x0=>0x1]	87	1			T38	1		T62	1		T40	1
all_pins[4]	transitions[0x1=>0x0]	79	1			T62	3		T106	3		T82	1
all_pins[5]	values[0x0]	899184	1			T1	2		T2	287		T3	1
all_pins[5]	values[0x1]	97	1			T62	5		T106	5		T82	1
all_pins[5]	transitions[0x0=>0x1]	68	1			T62	5		T106	3		T212	2
all_pins[5]	transitions[0x1=>0x0]	80	1			T62	2		T106	2		T212	1
all_pins[6]	values[0x0]	899172	1			T1	2		T2	287		T3	1
all_pins[6]	values[0x1]	109	1			T62	2		T106	4		T82	1
all_pins[6]	transitions[0x0=>0x1]	69	1			T62	2		T106	3		T82	1
all_pins[6]	transitions[0x1=>0x0]	33532	1			T2	3		T4	52		T7	225
all_pins[7]	values[0x0]	865709	1			T1	2		T2	284		T3	1
all_pins[7]	values[0x1]	33572	1			T2	3		T4	52		T7	225
all_pins[7]	transitions[0x0=>0x1]	33544	1			T2	3		T4	52		T7	225
all_pins[7]	transitions[0x1=>0x0]	75	1			T62	8		T106	2		T63	2
all_pins[8]	values[0x0]	899178	1			T1	2		T2	287		T3	1
all_pins[8]	values[0x1]	103	1			T62	8		T106	3		T212	1
all_pins[8]	transitions[0x0=>0x1]	72	1			T62	5		T106	2		T216	2
all_pins[8]	transitions[0x1=>0x0]	708729	1			T2	3		T4	15		T7	13390
all_pins[9]	values[0x0]	190521	1			T1	2		T2	284		T3	1
all_pins[9]	values[0x1]	708760	1			T2	3		T4	15		T7	13390
all_pins[9]	transitions[0x0=>0x1]	708738	1			T2	3		T4	15		T7	13390
all_pins[9]	transitions[0x1=>0x0]	77	1			T62	3		T106	3		T82	1
all_pins[10]	values[0x0]	899182	1			T1	2		T2	287		T3	1
all_pins[10]	values[0x1]	99	1			T62	5		T106	4		T82	1
all_pins[10]	transitions[0x0=>0x1]	74	1			T62	3		T106	3		T82	1
all_pins[10]	transitions[0x1=>0x0]	891757	1			T1	2		T2	283		T4	195
all_pins[11]	values[0x0]	7499	1			T2	4		T3	1		T4	4
all_pins[11]	values[0x1]	891782	1			T1	2		T2	283		T4	195
all_pins[11]	transitions[0x0=>0x1]	891744	1			T1	2		T2	283		T4	195
all_pins[11]	transitions[0x1=>0x0]	67	1			T62	3		T106	4		T82	1
all_pins[12]	values[0x0]	899176	1			T1	2		T2	287		T3	1
all_pins[12]	values[0x1]	105	1			T62	4		T106	6		T82	1
all_pins[12]	transitions[0x0=>0x1]	84	1			T62	4		T106	5		T82	1
all_pins[12]	transitions[0x1=>0x0]	78	1			T62	4		T106	5		T212	4
all_pins[13]	values[0x0]	899182	1			T1	2		T2	287		T3	1
all_pins[13]	values[0x1]	99	1			T62	4		T106	6		T212	4
all_pins[13]	transitions[0x0=>0x1]	74	1			T62	3		T106	6		T63	2
all_pins[13]	transitions[0x1=>0x0]	78	1			T62	2		T106	3		T212	2
all_pins[14]	values[0x0]	899178	1			T1	2		T2	287		T3	1
all_pins[14]	values[0x1]	103	1			T62	3		T106	3		T212	6
all_pins[14]	transitions[0x0=>0x1]	60	1			T62	2		T106	2		T212	2
all_pins[14]	transitions[0x1=>0x0]	768969	1			T1	1		T2	71		T4	192