Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	419	1			T62	18		T106	21		T82	4
all_values[1]	419	1			T62	18		T106	21		T82	4
all_values[2]	419	1			T62	18		T106	21		T82	4
all_values[3]	419	1			T62	18		T106	21		T82	4
all_values[4]	419	1			T62	18		T106	21		T82	4
all_values[5]	419	1			T62	18		T106	21		T82	4
all_values[6]	419	1			T62	18		T106	21		T82	4
all_values[7]	419	1			T62	18		T106	21		T82	4
all_values[8]	419	1			T62	18		T106	21		T82	4
all_values[9]	419	1			T62	18		T106	21		T82	4
all_values[10]	419	1			T62	18		T106	21		T82	4
all_values[11]	419	1			T62	18		T106	21		T82	4
all_values[12]	419	1			T62	18		T106	21		T82	4
all_values[13]	419	1			T62	18		T106	21		T82	4
all_values[14]	419	1			T62	18		T106	21		T82	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3244

1

T62

125

T106

147

T82

32

auto[1]

3041

1

T62

145

T106

168

T82

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

955

1

T62

16

T106

16

T82

13

auto[1]

5330

1

T62

254

T106

299

T82

47

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3699

1

T62

158

T106

196

T82

35

auto[1]

2586

1

T62

112

T106

119

T82

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	45	1			T82	4		T212	1		T211	2
all_values[0]	auto[0]	auto[0]	auto[1]	86	1			T62	4		T106	6		T212	1
all_values[0]	auto[0]	auto[1]	auto[0]	24	1			T62	1		T253	2		T254	2
all_values[0]	auto[0]	auto[1]	auto[1]	113	1			T62	7		T106	6		T212	2
all_values[0]	auto[1]	auto[0]	auto[1]	81	1			T62	3		T106	3		T212	1
all_values[0]	auto[1]	auto[1]	auto[1]	70	1			T62	3		T106	6		T212	2
all_values[1]	auto[0]	auto[0]	auto[0]	33	1			T255	1		T122	1		T124	2
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T62	6		T106	5		T82	1
all_values[1]	auto[0]	auto[1]	auto[0]	30	1			T212	1		T254	4		T255	3
all_values[1]	auto[0]	auto[1]	auto[1]	106	1			T62	5		T106	10		T212	1
all_values[1]	auto[1]	auto[0]	auto[1]	80	1			T62	2		T106	2		T82	3
all_values[1]	auto[1]	auto[1]	auto[1]	88	1			T62	5		T106	4		T212	1
all_values[2]	auto[0]	auto[0]	auto[0]	43	1			T62	1		T211	3		T51	3
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T62	4		T106	4		T82	2
all_values[2]	auto[0]	auto[1]	auto[0]	30	1			T212	2		T63	1		T211	1
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T62	5		T106	6		T63	1
all_values[2]	auto[1]	auto[0]	auto[1]	91	1			T62	2		T106	2		T212	1
all_values[2]	auto[1]	auto[1]	auto[1]	89	1			T62	6		T106	9		T82	2
all_values[3]	auto[0]	auto[0]	auto[0]	34	1			T82	1		T212	2		T211	1
all_values[3]	auto[0]	auto[0]	auto[1]	92	1			T62	3		T106	10		T82	1
all_values[3]	auto[0]	auto[1]	auto[0]	33	1			T63	1		T211	2		T253	3
all_values[3]	auto[0]	auto[1]	auto[1]	91	1			T62	7		T106	4		T212	2
all_values[3]	auto[1]	auto[0]	auto[1]	88	1			T62	2		T106	6		T82	2
all_values[3]	auto[1]	auto[1]	auto[1]	81	1			T62	6		T106	1		T212	1
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T62	2		T106	1		T51	1
all_values[4]	auto[0]	auto[0]	auto[1]	98	1			T62	6		T106	4		T82	1
all_values[4]	auto[0]	auto[1]	auto[0]	36	1			T62	2		T106	6		T82	1
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T62	2		T106	2		T63	1
all_values[4]	auto[1]	auto[0]	auto[1]	86	1			T62	1		T106	4		T82	1
all_values[4]	auto[1]	auto[1]	auto[1]	81	1			T62	5		T106	4		T82	1
all_values[5]	auto[0]	auto[0]	auto[0]	35	1			T253	2		T52	1		T256	1
all_values[5]	auto[0]	auto[0]	auto[1]	91	1			T62	4		T106	5		T63	2
all_values[5]	auto[0]	auto[1]	auto[0]	32	1			T106	2		T216	1		T253	3
all_values[5]	auto[0]	auto[1]	auto[1]	91	1			T62	6		T106	6		T82	3
all_values[5]	auto[1]	auto[0]	auto[1]	82	1			T62	4		T106	3		T212	4
all_values[5]	auto[1]	auto[1]	auto[1]	88	1			T62	4		T106	5		T82	1
all_values[6]	auto[0]	auto[0]	auto[0]	26	1			T253	1		T254	1		T257	2
all_values[6]	auto[0]	auto[0]	auto[1]	85	1			T62	4		T106	5		T82	2
all_values[6]	auto[0]	auto[1]	auto[0]	22	1			T62	2		T63	1		T257	4
all_values[6]	auto[0]	auto[1]	auto[1]	105	1			T62	2		T106	12		T212	2
all_values[6]	auto[1]	auto[0]	auto[1]	77	1			T62	5		T212	2		T63	1
all_values[6]	auto[1]	auto[1]	auto[1]	104	1			T62	5		T106	4		T82	2
all_values[7]	auto[0]	auto[0]	auto[0]	42	1			T62	2		T212	4		T51	1
all_values[7]	auto[0]	auto[0]	auto[1]	99	1			T62	3		T106	4		T82	1
all_values[7]	auto[0]	auto[1]	auto[0]	22	1			T62	2		T51	1		T121	1
all_values[7]	auto[0]	auto[1]	auto[1]	78	1			T62	5		T106	6		T82	1
all_values[7]	auto[1]	auto[0]	auto[1]	81	1			T62	5		T106	5		T82	1
all_values[7]	auto[1]	auto[1]	auto[1]	97	1			T62	1		T106	6		T82	1
all_values[8]	auto[0]	auto[0]	auto[0]	26	1			T216	1		T211	1		T52	1
all_values[8]	auto[0]	auto[0]	auto[1]	107	1			T62	3		T106	9		T82	1
all_values[8]	auto[0]	auto[1]	auto[0]	28	1			T62	1		T216	1		T257	4
all_values[8]	auto[0]	auto[1]	auto[1]	97	1			T62	6		T106	2		T82	1
all_values[8]	auto[1]	auto[0]	auto[1]	97	1			T62	4		T106	6		T82	1
all_values[8]	auto[1]	auto[1]	auto[1]	64	1			T62	4		T106	4		T82	1
all_values[9]	auto[0]	auto[0]	auto[0]	35	1			T82	1		T212	1		T216	1
all_values[9]	auto[0]	auto[0]	auto[1]	101	1			T62	7		T106	6		T63	1
all_values[9]	auto[0]	auto[1]	auto[0]	19	1			T216	1		T254	1		T257	1
all_values[9]	auto[0]	auto[1]	auto[1]	81	1			T62	2		T106	7		T82	1
all_values[9]	auto[1]	auto[0]	auto[1]	103	1			T62	4		T106	2		T82	1
all_values[9]	auto[1]	auto[1]	auto[1]	80	1			T62	5		T106	6		T82	1
all_values[10]	auto[0]	auto[0]	auto[0]	39	1			T106	3		T121	1		T258	1
all_values[10]	auto[0]	auto[0]	auto[1]	83	1			T62	9		T106	5		T212	2
all_values[10]	auto[0]	auto[1]	auto[0]	29	1			T106	2		T254	1		T257	2
all_values[10]	auto[0]	auto[1]	auto[1]	93	1			T62	3		T106	4		T82	3
all_values[10]	auto[1]	auto[0]	auto[1]	92	1			T62	2		T106	4		T212	2
all_values[10]	auto[1]	auto[1]	auto[1]	83	1			T62	4		T106	3		T82	1
all_values[11]	auto[0]	auto[0]	auto[0]	41	1			T212	2		T63	1		T253	1
all_values[11]	auto[0]	auto[0]	auto[1]	87	1			T62	5		T106	9		T212	3
all_values[11]	auto[0]	auto[1]	auto[0]	15	1			T62	1		T106	1		T253	2
all_values[11]	auto[0]	auto[1]	auto[1]	99	1			T62	8		T106	5		T82	1
all_values[11]	auto[1]	auto[0]	auto[1]	101	1			T62	2		T106	4		T82	2
all_values[11]	auto[1]	auto[1]	auto[1]	76	1			T62	2		T106	2		T82	1
all_values[12]	auto[0]	auto[0]	auto[0]	47	1			T212	1		T253	2		T123	2
all_values[12]	auto[0]	auto[0]	auto[1]	84	1			T62	5		T106	5		T82	1
all_values[12]	auto[0]	auto[1]	auto[0]	23	1			T62	1		T253	1		T257	1
all_values[12]	auto[0]	auto[1]	auto[1]	81	1			T62	3		T106	8		T82	1
all_values[12]	auto[1]	auto[0]	auto[1]	93	1			T62	4		T106	2		T82	1
all_values[12]	auto[1]	auto[1]	auto[1]	91	1			T62	5		T106	6		T82	1
all_values[13]	auto[0]	auto[0]	auto[0]	36	1			T106	1		T216	1		T51	4
all_values[13]	auto[0]	auto[0]	auto[1]	88	1			T62	5		T106	7		T82	1
all_values[13]	auto[0]	auto[1]	auto[0]	30	1			T82	2		T212	1		T216	2
all_values[13]	auto[0]	auto[1]	auto[1]	96	1			T62	5		T106	5		T212	2
all_values[13]	auto[1]	auto[0]	auto[1]	91	1			T62	7		T106	5		T82	1
all_values[13]	auto[1]	auto[1]	auto[1]	78	1			T62	1		T106	3		T212	3
all_values[14]	auto[0]	auto[0]	auto[0]	31	1			T82	2		T212	1		T216	1
all_values[14]	auto[0]	auto[0]	auto[1]	98	1			T62	3		T106	6		T63	1
all_values[14]	auto[0]	auto[1]	auto[0]	28	1			T62	1		T82	2		T216	1
all_values[14]	auto[0]	auto[1]	auto[1]	89	1			T62	5		T106	7		T212	3
all_values[14]	auto[1]	auto[0]	auto[1]	91	1			T62	2		T106	4		T212	1
all_values[14]	auto[1]	auto[1]	auto[1]	82	1			T62	7		T106	4		T212	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal