Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1063882	1			T1	22776		T2	3		T3	2
all_values[1]	1063882	1			T1	22776		T2	3		T3	2
all_values[2]	1063882	1			T1	22776		T2	3		T3	2
all_values[3]	1063882	1			T1	22776		T2	3		T3	2
all_values[4]	1063882	1			T1	22776		T2	3		T3	2
all_values[5]	1063882	1			T1	22776		T2	3		T3	2
all_values[6]	1063882	1			T1	22776		T2	3		T3	2
all_values[7]	1063882	1			T1	22776		T2	3		T3	2
all_values[8]	1063882	1			T1	22776		T2	3		T3	2
all_values[9]	1063882	1			T1	22776		T2	3		T3	2
all_values[10]	1063882	1			T1	22776		T2	3		T3	2
all_values[11]	1063882	1			T1	22776		T2	3		T3	2
all_values[12]	1063882	1			T1	22776		T2	3		T3	2
all_values[13]	1063882	1			T1	22776		T2	3		T3	2
all_values[14]	1063882	1			T1	22776		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13039614

1

T1

275033

T2

38

T3

26

auto[1]

2918616

1

T1

66607

T2

7

T3

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13396286

1

T1

341640

T2

45

T3

30

auto[1]

2561944

1

T76

105358

T155

239633

T156

5604

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92199	1			T1	1897		T4	4		T5	1
all_values[0]	auto[0]	auto[1]	16820	1			T155	1253		T156	16		T61	2085
all_values[0]	auto[1]	auto[0]	819310	1			T1	20879		T2	3		T3	2
all_values[0]	auto[1]	auto[1]	135553	1			T155	14723		T156	358		T61	16508
all_values[1]	auto[0]	auto[0]	883742	1			T1	22732		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	179186	1			T76	8712		T155	15967		T156	372
all_values[1]	auto[1]	auto[0]	600	1			T1	44		T4	2		T192	52
all_values[1]	auto[1]	auto[1]	354	1			T76	68		T155	10		T156	3
all_values[2]	auto[0]	auto[0]	892953	1			T1	22776		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	170662	1			T76	8778		T155	15969		T156	369
all_values[2]	auto[1]	auto[0]	52	1			T157	1		T203	1		T17	1
all_values[2]	auto[1]	auto[1]	215	1			T76	2		T155	8		T156	2
all_values[3]	auto[0]	auto[0]	884602	1			T1	22776		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	179055	1			T76	8779		T155	15972		T156	370
all_values[3]	auto[1]	auto[1]	225	1			T76	1		T155	4		T156	4
all_values[4]	auto[0]	auto[0]	884690	1			T1	22776		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	178978	1			T76	8779		T155	15970		T156	370
all_values[4]	auto[1]	auto[0]	9	1			T52	1		T279	1		T280	1
all_values[4]	auto[1]	auto[1]	205	1			T76	1		T155	7		T156	2
all_values[5]	auto[0]	auto[0]	884347	1			T1	22776		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	179279	1			T76	8777		T155	15966		T156	368
all_values[5]	auto[1]	auto[1]	256	1			T76	3		T155	11		T156	6
all_values[6]	auto[0]	auto[0]	896723	1			T1	22776		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	166908	1			T76	8779		T155	15968		T156	368
all_values[6]	auto[1]	auto[1]	251	1			T155	8		T156	4		T61	6
all_values[7]	auto[0]	auto[0]	866322	1			T1	22504		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	167082	1			T155	15799		T156	292		T61	36505
all_values[7]	auto[1]	auto[0]	26849	1			T1	272		T4	57		T5	1
all_values[7]	auto[1]	auto[1]	3629	1			T155	168		T156	82		T61	515
all_values[8]	auto[0]	auto[0]	896713	1			T1	22776		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	166939	1			T76	8780		T155	15968		T156	369
all_values[8]	auto[1]	auto[1]	230	1			T155	6		T156	3		T61	1
all_values[9]	auto[0]	auto[0]	169516	1			T1	131		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	25194	1			T76	3393		T155	497		T156	347
all_values[9]	auto[1]	auto[0]	732299	1			T1	22645		T2	1		T4	20
all_values[9]	auto[1]	auto[1]	136873	1			T76	5387		T155	15480		T156	27
all_values[10]	auto[0]	auto[0]	896724	1			T1	22776		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	166939	1			T76	8777		T155	15969		T156	370
all_values[10]	auto[1]	auto[1]	219	1			T76	3		T155	5		T156	4
all_values[11]	auto[0]	auto[0]	2633	1			T1	9		T4	3		T5	1
all_values[11]	auto[0]	auto[1]	457	1			T155	19		T156	6		T61	37
all_values[11]	auto[1]	auto[0]	903170	1			T1	22767		T2	3		T3	2
all_values[11]	auto[1]	auto[1]	157622	1			T155	15958		T156	368		T61	36983
all_values[12]	auto[0]	auto[0]	887591	1			T1	22776		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	176061	1			T76	8779		T155	15968		T156	371
all_values[12]	auto[1]	auto[0]	9	1			T17	1		T281	1		T282	1
all_values[12]	auto[1]	auto[1]	221	1			T76	1		T155	7		T156	3
all_values[13]	auto[0]	auto[0]	887621	1			T1	22776		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	176025	1			T76	8778		T155	15975		T156	370
all_values[13]	auto[1]	auto[1]	236	1			T76	2		T155	2		T156	5
all_values[14]	auto[0]	auto[0]	887612	1			T1	22776		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	176041	1			T76	8778		T155	15971		T156	372
all_values[14]	auto[1]	auto[1]	229	1			T76	1		T155	5		T156	3