Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	1063882	1			T1	22776		T2	3		T3	2
all_pins[1]	1063882	1			T1	22776		T2	3		T3	2
all_pins[2]	1063882	1			T1	22776		T2	3		T3	2
all_pins[3]	1063882	1			T1	22776		T2	3		T3	2
all_pins[4]	1063882	1			T1	22776		T2	3		T3	2
all_pins[5]	1063882	1			T1	22776		T2	3		T3	2
all_pins[6]	1063882	1			T1	22776		T2	3		T3	2
all_pins[7]	1063882	1			T1	22776		T2	3		T3	2
all_pins[8]	1063882	1			T1	22776		T2	3		T3	2
all_pins[9]	1063882	1			T1	22776		T2	3		T3	2
all_pins[10]	1063882	1			T1	22776		T2	3		T3	2
all_pins[11]	1063882	1			T1	22776		T2	3		T3	2
all_pins[12]	1063882	1			T1	22776		T2	3		T3	2
all_pins[13]	1063882	1			T1	22776		T2	3		T3	2
all_pins[14]	1063882	1			T1	22776		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	13044517	1			T1	274949		T2	38		T3	26
values[0x1]	2913713	1			T1	66691		T2	7		T3	4
transitions[0x0=>0x1]	2912401	1			T1	66631		T2	7		T3	4
transitions[0x1=>0x0]	2911252	1			T1	66630		T2	6		T3	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	112311	1			T1	1900		T4	4		T5	1
all_pins[0]	values[0x1]	951571	1			T1	20876		T2	3		T3	2
all_pins[0]	transitions[0x0=>0x1]	950649	1			T1	20816		T2	3		T3	2
all_pins[0]	transitions[0x1=>0x0]	74	1			T27	1		T37	1		T156	1
all_pins[1]	values[0x0]	1062886	1			T1	22716		T2	3		T3	2
all_pins[1]	values[0x1]	996	1			T1	60		T4	3		T192	58
all_pins[1]	transitions[0x0=>0x1]	968	1			T1	60		T4	3		T192	58
all_pins[1]	transitions[0x1=>0x0]	128	1			T157	1		T203	1		T17	1
all_pins[2]	values[0x0]	1063726	1			T1	22776		T2	3		T3	2
all_pins[2]	values[0x1]	156	1			T157	1		T203	1		T17	1
all_pins[2]	transitions[0x0=>0x1]	130	1			T157	1		T203	1		T17	1
all_pins[2]	transitions[0x1=>0x0]	74	1			T156	2		T61	2		T53	1
all_pins[3]	values[0x0]	1063782	1			T1	22776		T2	3		T3	2
all_pins[3]	values[0x1]	100	1			T156	2		T61	3		T53	2
all_pins[3]	transitions[0x0=>0x1]	80	1			T156	2		T61	2		T53	2
all_pins[3]	transitions[0x1=>0x0]	88	1			T76	1		T155	5		T61	3
all_pins[4]	values[0x0]	1063774	1			T1	22776		T2	3		T3	2
all_pins[4]	values[0x1]	108	1			T76	1		T155	5		T61	4
all_pins[4]	transitions[0x0=>0x1]	87	1			T155	4		T61	3		T266	2
all_pins[4]	transitions[0x1=>0x0]	110	1			T155	5		T156	4		T61	2
all_pins[5]	values[0x0]	1063751	1			T1	22776		T2	3		T3	2
all_pins[5]	values[0x1]	131	1			T76	1		T155	6		T156	4
all_pins[5]	transitions[0x0=>0x1]	98	1			T76	1		T155	5		T156	3
all_pins[5]	transitions[0x1=>0x0]	87	1			T155	2		T61	3		T266	3
all_pins[6]	values[0x0]	1063762	1			T1	22776		T2	3		T3	2
all_pins[6]	values[0x1]	120	1			T155	3		T156	1		T61	3
all_pins[6]	transitions[0x0=>0x1]	101	1			T155	3		T156	1		T61	3
all_pins[6]	transitions[0x1=>0x0]	33708	1			T1	342		T4	63		T5	1
all_pins[7]	values[0x0]	1030155	1			T1	22434		T2	3		T3	2
all_pins[7]	values[0x1]	33727	1			T1	342		T4	63		T5	1
all_pins[7]	transitions[0x0=>0x1]	33707	1			T1	342		T4	63		T5	1
all_pins[7]	transitions[0x1=>0x0]	99	1			T155	2		T156	3		T61	1
all_pins[8]	values[0x0]	1063763	1			T1	22776		T2	3		T3	2
all_pins[8]	values[0x1]	119	1			T155	2		T156	3		T61	1
all_pins[8]	transitions[0x0=>0x1]	90	1			T155	2		T156	1		T61	1
all_pins[8]	transitions[0x1=>0x0]	869041	1			T1	22646		T2	1		T4	20
all_pins[9]	values[0x0]	194812	1			T1	130		T2	2		T3	2
all_pins[9]	values[0x1]	869070	1			T1	22646		T2	1		T4	20
all_pins[9]	transitions[0x0=>0x1]	869046	1			T1	22646		T2	1		T4	20
all_pins[9]	transitions[0x1=>0x0]	85	1			T76	2		T155	2		T53	3
all_pins[10]	values[0x0]	1063773	1			T1	22776		T2	3		T3	2
all_pins[10]	values[0x1]	109	1			T76	2		T155	3		T156	1
all_pins[10]	transitions[0x0=>0x1]	73	1			T76	2		T155	2		T156	1
all_pins[10]	transitions[0x1=>0x0]	1057141	1			T1	22767		T2	3		T3	2
all_pins[11]	values[0x0]	6705	1			T1	9		T4	3		T5	1
all_pins[11]	values[0x1]	1057177	1			T1	22767		T2	3		T3	2
all_pins[11]	transitions[0x0=>0x1]	1057137	1			T1	22767		T2	3		T3	2
all_pins[11]	transitions[0x1=>0x0]	80	1			T76	1		T155	2		T266	1
all_pins[12]	values[0x0]	1063762	1			T1	22776		T2	3		T3	2
all_pins[12]	values[0x1]	120	1			T17	1		T76	1		T155	2
all_pins[12]	transitions[0x0=>0x1]	98	1			T17	1		T155	2		T61	1
all_pins[12]	transitions[0x1=>0x0]	79	1			T155	1		T156	1		T61	1
all_pins[13]	values[0x0]	1063781	1			T1	22776		T2	3		T3	2
all_pins[13]	values[0x1]	101	1			T76	1		T155	1		T156	1
all_pins[13]	transitions[0x0=>0x1]	77	1			T76	1		T155	1		T156	1
all_pins[13]	transitions[0x1=>0x0]	84	1			T76	1		T155	2		T156	1
all_pins[14]	values[0x0]	1063774	1			T1	22776		T2	3		T3	2
all_pins[14]	values[0x1]	108	1			T76	1		T155	2		T156	1
all_pins[14]	transitions[0x0=>0x1]	60	1			T76	1		T155	1		T156	1
all_pins[14]	transitions[0x1=>0x0]	950374	1			T1	20875		T2	2		T3	1