Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	508	1			T76	4		T155	14		T156	7
all_values[1]	508	1			T76	4		T155	14		T156	7
all_values[2]	508	1			T76	4		T155	14		T156	7
all_values[3]	508	1			T76	4		T155	14		T156	7
all_values[4]	508	1			T76	4		T155	14		T156	7
all_values[5]	508	1			T76	4		T155	14		T156	7
all_values[6]	508	1			T76	4		T155	14		T156	7
all_values[7]	508	1			T76	4		T155	14		T156	7
all_values[8]	508	1			T76	4		T155	14		T156	7
all_values[9]	508	1			T76	4		T155	14		T156	7
all_values[10]	508	1			T76	4		T155	14		T156	7
all_values[11]	508	1			T76	4		T155	14		T156	7
all_values[12]	508	1			T76	4		T155	14		T156	7
all_values[13]	508	1			T76	4		T155	14		T156	7
all_values[14]	508	1			T76	4		T155	14		T156	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4159

1

T76

35

T155

109

T156

62

auto[1]

3461

1

T76

25

T155

101

T156

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T76

14

T155

21

T156

21

auto[1]

6541

1

T76

46

T155

189

T156

84

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4450

1

T76

35

T155

125

T156

56

auto[1]

3170

1

T76

25

T155

85

T156

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1			T76	2		T155	1		T156	1
all_values[0]	auto[0]	auto[0]	auto[1]	114	1			T155	5		T156	2		T53	6
all_values[0]	auto[0]	auto[1]	auto[0]	12	1			T76	2		T61	1		T299	1
all_values[0]	auto[0]	auto[1]	auto[1]	117	1			T155	3		T156	1		T61	2
all_values[0]	auto[1]	auto[0]	auto[1]	134	1			T155	2		T156	3		T61	3
all_values[0]	auto[1]	auto[1]	auto[1]	102	1			T155	3		T61	2		T53	2
all_values[1]	auto[0]	auto[0]	auto[0]	40	1			T266	1		T300	1		T301	2
all_values[1]	auto[0]	auto[0]	auto[1]	112	1			T76	1		T155	6		T156	2
all_values[1]	auto[0]	auto[1]	auto[0]	30	1			T53	2		T132	2		T300	2
all_values[1]	auto[0]	auto[1]	auto[1]	135	1			T76	1		T155	3		T156	2
all_values[1]	auto[1]	auto[0]	auto[1]	100	1			T76	2		T155	3		T156	2
all_values[1]	auto[1]	auto[1]	auto[1]	91	1			T155	2		T156	1		T61	4
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T156	1		T125	2		T302	3
all_values[2]	auto[0]	auto[0]	auto[1]	122	1			T155	4		T156	1		T61	5
all_values[2]	auto[0]	auto[1]	auto[0]	29	1			T156	3		T125	2		T49	1
all_values[2]	auto[0]	auto[1]	auto[1]	103	1			T76	2		T155	2		T61	3
all_values[2]	auto[1]	auto[0]	auto[1]	119	1			T76	1		T155	3		T61	1
all_values[2]	auto[1]	auto[1]	auto[1]	96	1			T76	1		T155	5		T156	2
all_values[3]	auto[0]	auto[0]	auto[0]	50	1			T155	1		T156	1		T266	1
all_values[3]	auto[0]	auto[0]	auto[1]	107	1			T155	3		T156	1		T61	4
all_values[3]	auto[0]	auto[1]	auto[0]	33	1			T53	8		T125	1		T300	2
all_values[3]	auto[0]	auto[1]	auto[1]	115	1			T76	1		T155	4		T156	1
all_values[3]	auto[1]	auto[0]	auto[1]	122	1			T76	1		T155	3		T156	3
all_values[3]	auto[1]	auto[1]	auto[1]	81	1			T76	2		T155	3		T156	1
all_values[4]	auto[0]	auto[0]	auto[0]	49	1			T156	3		T61	2		T266	1
all_values[4]	auto[0]	auto[0]	auto[1]	133	1			T76	1		T155	4		T156	2
all_values[4]	auto[0]	auto[1]	auto[0]	24	1			T132	1		T125	1		T303	1
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T76	2		T155	3		T61	2
all_values[4]	auto[1]	auto[0]	auto[1]	114	1			T76	1		T155	4		T156	2
all_values[4]	auto[1]	auto[1]	auto[1]	91	1			T155	3		T61	5		T266	2
all_values[5]	auto[0]	auto[0]	auto[0]	44	1			T156	1		T53	1		T300	2
all_values[5]	auto[0]	auto[0]	auto[1]	107	1			T76	1		T155	2		T156	1
all_values[5]	auto[0]	auto[1]	auto[0]	29	1			T300	1		T49	1		T108	2
all_values[5]	auto[0]	auto[1]	auto[1]	103	1			T155	6		T61	3		T266	2
all_values[5]	auto[1]	auto[0]	auto[1]	132	1			T76	3		T155	3		T61	4
all_values[5]	auto[1]	auto[1]	auto[1]	93	1			T155	3		T156	5		T61	1
all_values[6]	auto[0]	auto[0]	auto[0]	48	1			T76	1		T155	1		T156	3
all_values[6]	auto[0]	auto[0]	auto[1]	118	1			T76	1		T155	3		T156	2
all_values[6]	auto[0]	auto[1]	auto[0]	25	1			T132	1		T302	1		T126	1
all_values[6]	auto[0]	auto[1]	auto[1]	105	1			T155	4		T61	1		T266	2
all_values[6]	auto[1]	auto[0]	auto[1]	109	1			T155	4		T61	3		T266	1
all_values[6]	auto[1]	auto[1]	auto[1]	103	1			T76	2		T155	2		T156	2
all_values[7]	auto[0]	auto[0]	auto[0]	55	1			T76	2		T155	5		T156	1
all_values[7]	auto[0]	auto[0]	auto[1]	128	1			T155	2		T156	1		T61	3
all_values[7]	auto[0]	auto[1]	auto[0]	41	1			T76	2		T155	4		T266	2
all_values[7]	auto[0]	auto[1]	auto[1]	101	1			T155	2		T156	2		T61	3
all_values[7]	auto[1]	auto[0]	auto[1]	110	1			T156	3		T61	5		T53	2
all_values[7]	auto[1]	auto[1]	auto[1]	73	1			T155	1		T53	2		T300	1
all_values[8]	auto[0]	auto[0]	auto[0]	42	1			T155	2		T156	1		T61	1
all_values[8]	auto[0]	auto[0]	auto[1]	109	1			T76	1		T155	3		T61	4
all_values[8]	auto[0]	auto[1]	auto[0]	24	1			T155	1		T156	2		T132	1
all_values[8]	auto[0]	auto[1]	auto[1]	110	1			T76	1		T155	2		T156	2
all_values[8]	auto[1]	auto[0]	auto[1]	116	1			T76	2		T155	2		T61	1
all_values[8]	auto[1]	auto[1]	auto[1]	107	1			T155	4		T156	2		T61	2
all_values[9]	auto[0]	auto[0]	auto[0]	49	1			T156	1		T266	1		T132	1
all_values[9]	auto[0]	auto[0]	auto[1]	109	1			T155	4		T61	3		T53	4
all_values[9]	auto[0]	auto[1]	auto[0]	25	1			T53	1		T132	1		T302	4
all_values[9]	auto[0]	auto[1]	auto[1]	102	1			T76	2		T155	4		T156	2
all_values[9]	auto[1]	auto[0]	auto[1]	126	1			T76	1		T155	5		T156	1
all_values[9]	auto[1]	auto[1]	auto[1]	97	1			T76	1		T155	1		T156	3
all_values[10]	auto[0]	auto[0]	auto[0]	46	1			T156	1		T266	1		T51	1
all_values[10]	auto[0]	auto[0]	auto[1]	110	1			T155	4		T61	4		T266	1
all_values[10]	auto[0]	auto[1]	auto[0]	31	1			T155	3		T266	1		T132	1
all_values[10]	auto[0]	auto[1]	auto[1]	102	1			T76	1		T155	2		T156	2
all_values[10]	auto[1]	auto[0]	auto[1]	120	1			T76	3		T155	1		T156	3
all_values[10]	auto[1]	auto[1]	auto[1]	99	1			T155	4		T156	1		T61	1
all_values[11]	auto[0]	auto[0]	auto[0]	50	1			T76	4		T156	1		T51	1
all_values[11]	auto[0]	auto[0]	auto[1]	115	1			T155	4		T156	1		T61	3
all_values[11]	auto[0]	auto[1]	auto[0]	24	1			T132	2		T49	1		T108	1
all_values[11]	auto[0]	auto[1]	auto[1]	108	1			T155	3		T156	1		T61	3
all_values[11]	auto[1]	auto[0]	auto[1]	97	1			T155	4		T156	2		T61	1
all_values[11]	auto[1]	auto[1]	auto[1]	114	1			T155	3		T156	2		T61	4
all_values[12]	auto[0]	auto[0]	auto[0]	28	1			T156	1		T61	1		T125	1
all_values[12]	auto[0]	auto[0]	auto[1]	126	1			T76	1		T155	2		T156	3
all_values[12]	auto[0]	auto[1]	auto[0]	31	1			T155	2		T53	1		T125	3
all_values[12]	auto[0]	auto[1]	auto[1]	102	1			T76	2		T155	3		T61	3
all_values[12]	auto[1]	auto[0]	auto[1]	126	1			T76	1		T155	5		T156	3
all_values[12]	auto[1]	auto[1]	auto[1]	95	1			T155	2		T53	4		T132	4
all_values[13]	auto[0]	auto[0]	auto[0]	38	1			T61	2		T125	1		T51	1
all_values[13]	auto[0]	auto[0]	auto[1]	122	1			T76	2		T155	2		T156	3
all_values[13]	auto[0]	auto[1]	auto[0]	42	1			T53	2		T132	1		T125	3
all_values[13]	auto[0]	auto[1]	auto[1]	106	1			T155	6		T156	1		T53	3
all_values[13]	auto[1]	auto[0]	auto[1]	117	1			T76	2		T155	2		T156	1
all_values[13]	auto[1]	auto[1]	auto[1]	83	1			T155	4		T156	2		T61	2
all_values[14]	auto[0]	auto[0]	auto[0]	49	1			T76	1		T155	1		T125	4
all_values[14]	auto[0]	auto[0]	auto[1]	126	1			T155	6		T156	1		T61	2
all_values[14]	auto[0]	auto[1]	auto[0]	23	1			T53	1		T125	2		T304	2
all_values[14]	auto[0]	auto[1]	auto[1]	107	1			T76	1		T155	3		T156	1
all_values[14]	auto[1]	auto[0]	auto[1]	103	1			T155	3		T156	3		T61	4
all_values[14]	auto[1]	auto[1]	auto[1]	100	1			T76	2		T155	1		T156	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal