Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	917787	1			T1	2		T3	343		T4	2
all_values[1]	917787	1			T1	2		T3	343		T4	2
all_values[2]	917787	1			T1	2		T3	343		T4	2
all_values[3]	917787	1			T1	2		T3	343		T4	2
all_values[4]	917787	1			T1	2		T3	343		T4	2
all_values[5]	917787	1			T1	2		T3	343		T4	2
all_values[6]	917787	1			T1	2		T3	343		T4	2
all_values[7]	917787	1			T1	2		T3	343		T4	2
all_values[8]	917787	1			T1	2		T3	343		T4	2
all_values[9]	917787	1			T1	2		T3	343		T4	2
all_values[10]	917787	1			T1	2		T3	343		T4	2
all_values[11]	917787	1			T1	2		T3	343		T4	2
all_values[12]	917787	1			T1	2		T3	343		T4	2
all_values[13]	917787	1			T1	2		T3	343		T4	2
all_values[14]	917787	1			T1	2		T3	343		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11294891

1

T1

30

T3

4408

T4

26

auto[1]

2471914

1

T3

737

T4

4

T5

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10927855

1

T1

30

T3

5145

T4

30

auto[1]

2838950

1

T158

93213

T50

36869

T52

259

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92684	1			T1	2		T3	11		T6	1
all_values[0]	auto[0]	auto[1]	11886	1			T158	49		T50	1616		T52	5
all_values[0]	auto[1]	auto[0]	629011	1			T3	332		T4	2		T5	3
all_values[0]	auto[1]	auto[1]	184206	1			T158	7122		T50	841		T52	11
all_values[1]	auto[0]	auto[0]	721404	1			T1	2		T3	343		T4	2
all_values[1]	auto[0]	auto[1]	195735	1			T158	7167		T50	2452		T52	14
all_values[1]	auto[1]	auto[0]	266	1			T187	2		T269	1		T270	1
all_values[1]	auto[1]	auto[1]	382	1			T158	4		T50	7		T52	4
all_values[2]	auto[0]	auto[0]	721611	1			T1	2		T3	343		T4	2
all_values[2]	auto[0]	auto[1]	195914	1			T158	7165		T50	2450		T52	15
all_values[2]	auto[1]	auto[0]	50	1			T18	1		T265	1		T271	1
all_values[2]	auto[1]	auto[1]	212	1			T158	5		T50	8		T52	3
all_values[3]	auto[0]	auto[0]	738941	1			T1	2		T3	343		T4	2
all_values[3]	auto[0]	auto[1]	178618	1			T158	7163		T50	2450		T52	12
all_values[3]	auto[1]	auto[1]	228	1			T158	6		T50	6		T52	5
all_values[4]	auto[0]	auto[0]	721668	1			T1	2		T3	343		T4	2
all_values[4]	auto[0]	auto[1]	195912	1			T158	7165		T50	2451		T52	14
all_values[4]	auto[1]	auto[0]	9	1			T45	1		T272	1		T273	1
all_values[4]	auto[1]	auto[1]	198	1			T158	1		T50	8		T52	1
all_values[5]	auto[0]	auto[0]	728153	1			T1	2		T3	343		T4	2
all_values[5]	auto[0]	auto[1]	189409	1			T158	7166		T50	2448		T52	15
all_values[5]	auto[1]	auto[1]	225	1			T158	5		T50	10		T52	1
all_values[6]	auto[0]	auto[0]	721655	1			T1	2		T3	343		T4	2
all_values[6]	auto[0]	auto[1]	195900	1			T158	7167		T50	2454		T52	16
all_values[6]	auto[1]	auto[1]	232	1			T158	4		T50	5		T52	2
all_values[7]	auto[0]	auto[0]	694566	1			T1	2		T3	307		T4	2
all_values[7]	auto[0]	auto[1]	192695	1			T158	7095		T50	2437		T52	11
all_values[7]	auto[1]	auto[0]	27079	1			T3	36		T6	1		T7	30
all_values[7]	auto[1]	auto[1]	3447	1			T158	76		T50	22		T52	7
all_values[8]	auto[0]	auto[0]	754391	1			T1	2		T3	343		T4	2
all_values[8]	auto[0]	auto[1]	163180	1			T158	7165		T50	2449		T52	13
all_values[8]	auto[1]	auto[1]	216	1			T158	6		T50	10		T52	5
all_values[9]	auto[0]	auto[0]	179521	1			T1	2		T3	314		T4	2
all_values[9]	auto[0]	auto[1]	27462	1			T158	1638		T50	2442		T52	14
all_values[9]	auto[1]	auto[0]	542172	1			T3	29		T5	1		T6	1
all_values[9]	auto[1]	auto[1]	168632	1			T158	5532		T50	17		T52	4
all_values[10]	auto[0]	auto[0]	721693	1			T1	2		T3	343		T4	2
all_values[10]	auto[0]	auto[1]	195889	1			T158	7166		T50	2454		T52	15
all_values[10]	auto[1]	auto[1]	205	1			T158	4		T50	5		T52	3
all_values[11]	auto[0]	auto[0]	2776	1			T1	2		T3	3		T6	1
all_values[11]	auto[0]	auto[1]	560	1			T50	35		T52	7		T47	12
all_values[11]	auto[1]	auto[0]	726046	1			T3	340		T4	2		T5	3
all_values[11]	auto[1]	auto[1]	188405	1			T50	2423		T52	11		T108	5
all_values[12]	auto[0]	auto[0]	721640	1			T1	2		T3	343		T4	2
all_values[12]	auto[0]	auto[1]	195932	1			T158	7167		T50	2451		T52	15
all_values[12]	auto[1]	auto[0]	13	1			T18	1		T274	1		T275	1
all_values[12]	auto[1]	auto[1]	202	1			T158	4		T50	5		T52	2
all_values[13]	auto[0]	auto[0]	753693	1			T1	2		T3	343		T4	2
all_values[13]	auto[0]	auto[1]	163859	1			T158	7165		T50	2448		T52	15
all_values[13]	auto[1]	auto[1]	235	1			T158	6		T50	9		T52	2
all_values[14]	auto[0]	auto[0]	728813	1			T1	2		T3	343		T4	2
all_values[14]	auto[0]	auto[1]	188731	1			T50	2450		T52	13		T108	2
all_values[14]	auto[1]	auto[1]	243	1			T50	6		T52	4		T108	2