Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	917787	1			T1	2		T3	343		T4	2
all_pins[1]	917787	1			T1	2		T3	343		T4	2
all_pins[2]	917787	1			T1	2		T3	343		T4	2
all_pins[3]	917787	1			T1	2		T3	343		T4	2
all_pins[4]	917787	1			T1	2		T3	343		T4	2
all_pins[5]	917787	1			T1	2		T3	343		T4	2
all_pins[6]	917787	1			T1	2		T3	343		T4	2
all_pins[7]	917787	1			T1	2		T3	343		T4	2
all_pins[8]	917787	1			T1	2		T3	343		T4	2
all_pins[9]	917787	1			T1	2		T3	343		T4	2
all_pins[10]	917787	1			T1	2		T3	343		T4	2
all_pins[11]	917787	1			T1	2		T3	343		T4	2
all_pins[12]	917787	1			T1	2		T3	343		T4	2
all_pins[13]	917787	1			T1	2		T3	343		T4	2
all_pins[14]	917787	1			T1	2		T3	343		T4	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11300646	1			T1	30		T3	4406		T4	26
values[0x1]	2466159	1			T3	739		T4	4		T5	7
transitions[0x0=>0x1]	2465194	1			T3	739		T4	4		T5	7
transitions[0x1=>0x0]	2464045	1			T3	738		T4	3		T5	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	108099	1			T1	2		T3	11		T6	1
all_pins[0]	values[0x1]	809688	1			T3	332		T4	2		T5	3
all_pins[0]	transitions[0x0=>0x1]	809114	1			T3	332		T4	2		T5	3
all_pins[0]	transitions[0x1=>0x0]	70	1			T158	2		T50	2		T52	1
all_pins[1]	values[0x0]	917143	1			T1	2		T3	343		T4	2
all_pins[1]	values[0x1]	644	1			T187	3		T158	2		T50	2
all_pins[1]	transitions[0x0=>0x1]	624	1			T187	3		T158	2		T50	2
all_pins[1]	transitions[0x1=>0x0]	128	1			T18	1		T265	1		T158	1
all_pins[2]	values[0x0]	917639	1			T1	2		T3	343		T4	2
all_pins[2]	values[0x1]	148	1			T18	1		T265	1		T158	1
all_pins[2]	transitions[0x0=>0x1]	129	1			T18	1		T265	1		T158	1
all_pins[2]	transitions[0x1=>0x0]	95	1			T158	3		T50	1		T52	3
all_pins[3]	values[0x0]	917673	1			T1	2		T3	343		T4	2
all_pins[3]	values[0x1]	114	1			T158	3		T50	1		T52	4
all_pins[3]	transitions[0x0=>0x1]	99	1			T158	3		T52	4		T47	1
all_pins[3]	transitions[0x1=>0x0]	83	1			T158	1		T45	1		T50	5
all_pins[4]	values[0x0]	917689	1			T1	2		T3	343		T4	2
all_pins[4]	values[0x1]	98	1			T158	1		T45	1		T50	6
all_pins[4]	transitions[0x0=>0x1]	78	1			T158	1		T45	1		T50	3
all_pins[4]	transitions[0x1=>0x0]	97	1			T158	4		T50	4		T108	1
all_pins[5]	values[0x0]	917670	1			T1	2		T3	343		T4	2
all_pins[5]	values[0x1]	117	1			T158	4		T50	7		T108	1
all_pins[5]	transitions[0x0=>0x1]	95	1			T158	4		T50	5		T108	1
all_pins[5]	transitions[0x1=>0x0]	75	1			T158	1		T50	2		T52	1
all_pins[6]	values[0x0]	917690	1			T1	2		T3	343		T4	2
all_pins[6]	values[0x1]	97	1			T158	1		T50	4		T52	1
all_pins[6]	transitions[0x0=>0x1]	67	1			T158	1		T50	4		T52	1
all_pins[6]	transitions[0x1=>0x0]	33370	1			T3	38		T6	1		T7	31
all_pins[7]	values[0x0]	884387	1			T1	2		T3	305		T4	2
all_pins[7]	values[0x1]	33400	1			T3	38		T6	1		T7	31
all_pins[7]	transitions[0x0=>0x1]	33369	1			T3	38		T6	1		T7	31
all_pins[7]	transitions[0x1=>0x0]	85	1			T158	2		T50	5		T52	1
all_pins[8]	values[0x0]	917671	1			T1	2		T3	343		T4	2
all_pins[8]	values[0x1]	116	1			T158	2		T50	7		T52	2
all_pins[8]	transitions[0x0=>0x1]	95	1			T158	2		T50	7		T52	2
all_pins[8]	transitions[0x1=>0x0]	710695	1			T3	29		T5	1		T6	1
all_pins[9]	values[0x0]	207071	1			T1	2		T3	314		T4	2
all_pins[9]	values[0x1]	710716	1			T3	29		T5	1		T6	1
all_pins[9]	transitions[0x0=>0x1]	710691	1			T3	29		T5	1		T6	1
all_pins[9]	transitions[0x1=>0x0]	71	1			T158	1		T50	3		T52	1
all_pins[10]	values[0x0]	917691	1			T1	2		T3	343		T4	2
all_pins[10]	values[0x1]	96	1			T158	2		T50	3		T52	1
all_pins[10]	transitions[0x0=>0x1]	71	1			T158	1		T50	2		T52	1
all_pins[10]	transitions[0x1=>0x0]	910532	1			T3	340		T4	2		T5	3
all_pins[11]	values[0x0]	7230	1			T1	2		T3	3		T6	1
all_pins[11]	values[0x1]	910557	1			T3	340		T4	2		T5	3
all_pins[11]	transitions[0x0=>0x1]	910508	1			T3	340		T4	2		T5	3
all_pins[11]	transitions[0x1=>0x0]	74	1			T158	1		T50	2		T52	1
all_pins[12]	values[0x0]	917664	1			T1	2		T3	343		T4	2
all_pins[12]	values[0x1]	123	1			T18	1		T158	3		T50	3
all_pins[12]	transitions[0x0=>0x1]	97	1			T18	1		T158	1		T50	2
all_pins[12]	transitions[0x1=>0x0]	98	1			T158	2		T50	4		T52	1
all_pins[13]	values[0x0]	917663	1			T1	2		T3	343		T4	2
all_pins[13]	values[0x1]	124	1			T158	4		T50	5		T52	1
all_pins[13]	transitions[0x0=>0x1]	91	1			T158	4		T50	2		T52	1
all_pins[13]	transitions[0x1=>0x0]	88	1			T50	3		T52	1		T110	3
all_pins[14]	values[0x0]	917666	1			T1	2		T3	343		T4	2
all_pins[14]	values[0x1]	121	1			T50	6		T52	1		T47	2
all_pins[14]	transitions[0x0=>0x1]	66	1			T50	5		T52	1		T110	3
all_pins[14]	transitions[0x1=>0x0]	808484	1			T3	331		T4	1		T5	2