Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	490	1			T158	8		T50	14		T52	7
all_values[1]	490	1			T158	8		T50	14		T52	7
all_values[2]	490	1			T158	8		T50	14		T52	7
all_values[3]	490	1			T158	8		T50	14		T52	7
all_values[4]	490	1			T158	8		T50	14		T52	7
all_values[5]	490	1			T158	8		T50	14		T52	7
all_values[6]	490	1			T158	8		T50	14		T52	7
all_values[7]	490	1			T158	8		T50	14		T52	7
all_values[8]	490	1			T158	8		T50	14		T52	7
all_values[9]	490	1			T158	8		T50	14		T52	7
all_values[10]	490	1			T158	8		T50	14		T52	7
all_values[11]	490	1			T158	8		T50	14		T52	7
all_values[12]	490	1			T158	8		T50	14		T52	7
all_values[13]	490	1			T158	8		T50	14		T52	7
all_values[14]	490	1			T158	8		T50	14		T52	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3925

1

T158

60

T50

100

T52

56

auto[1]

3425

1

T158

60

T50

110

T52

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T158

25

T50

16

T52

11

auto[1]

6250

1

T158

95

T50

194

T52

94

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4342

1

T158

80

T50

122

T52

62

auto[1]

3008

1

T158

40

T50

88

T52

43

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	53	1			T52	2		T108	1		T82	2
all_values[0]	auto[0]	auto[0]	auto[1]	112	1			T158	4		T50	1		T52	2
all_values[0]	auto[0]	auto[1]	auto[0]	43	1			T50	2		T108	1		T110	2
all_values[0]	auto[0]	auto[1]	auto[1]	99	1			T158	2		T50	7		T52	1
all_values[0]	auto[1]	auto[0]	auto[1]	96	1			T158	1		T50	1		T52	1
all_values[0]	auto[1]	auto[1]	auto[1]	87	1			T158	1		T50	3		T52	1
all_values[1]	auto[0]	auto[0]	auto[0]	46	1			T47	1		T286	1		T125	2
all_values[1]	auto[0]	auto[0]	auto[1]	133	1			T158	1		T50	4		T52	3
all_values[1]	auto[0]	auto[1]	auto[0]	28	1			T110	2		T82	1		T286	4
all_values[1]	auto[0]	auto[1]	auto[1]	88	1			T158	3		T50	3		T108	1
all_values[1]	auto[1]	auto[0]	auto[1]	114	1			T158	1		T50	4		T52	2
all_values[1]	auto[1]	auto[1]	auto[1]	81	1			T158	3		T50	3		T52	2
all_values[2]	auto[0]	auto[0]	auto[0]	40	1			T50	1		T47	2		T110	2
all_values[2]	auto[0]	auto[0]	auto[1]	114	1			T158	2		T50	4		T52	2
all_values[2]	auto[0]	auto[1]	auto[0]	30	1			T158	1		T110	2		T286	3
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T50	1		T52	2		T108	1
all_values[2]	auto[1]	auto[0]	auto[1]	119	1			T158	3		T50	4		T52	1
all_values[2]	auto[1]	auto[1]	auto[1]	93	1			T158	2		T50	4		T52	2
all_values[3]	auto[0]	auto[0]	auto[0]	52	1			T158	1		T50	1		T52	1
all_values[3]	auto[0]	auto[0]	auto[1]	106	1			T158	1		T50	5		T52	1
all_values[3]	auto[0]	auto[1]	auto[0]	29	1			T158	1		T50	2		T286	1
all_values[3]	auto[0]	auto[1]	auto[1]	96	1			T158	2		T50	1		T52	2
all_values[3]	auto[1]	auto[0]	auto[1]	112	1			T158	2		T50	3		T52	1
all_values[3]	auto[1]	auto[1]	auto[1]	95	1			T158	1		T50	2		T52	2
all_values[4]	auto[0]	auto[0]	auto[0]	49	1			T158	1		T52	2		T82	1
all_values[4]	auto[0]	auto[0]	auto[1]	114	1			T50	2		T52	1		T108	1
all_values[4]	auto[0]	auto[1]	auto[0]	33	1			T158	3		T52	1		T108	1
all_values[4]	auto[0]	auto[1]	auto[1]	96	1			T158	3		T50	4		T52	2
all_values[4]	auto[1]	auto[0]	auto[1]	109	1			T158	1		T50	4		T108	1
all_values[4]	auto[1]	auto[1]	auto[1]	89	1			T50	4		T52	1		T108	1
all_values[5]	auto[0]	auto[0]	auto[0]	50	1			T52	2		T77	1		T61	1
all_values[5]	auto[0]	auto[0]	auto[1]	110	1			T158	1		T50	4		T52	2
all_values[5]	auto[0]	auto[1]	auto[0]	44	1			T50	1		T108	1		T47	2
all_values[5]	auto[0]	auto[1]	auto[1]	92	1			T158	4		T50	2		T110	2
all_values[5]	auto[1]	auto[0]	auto[1]	99	1			T158	1		T50	5		T52	2
all_values[5]	auto[1]	auto[1]	auto[1]	95	1			T158	2		T50	2		T52	1
all_values[6]	auto[0]	auto[0]	auto[0]	31	1			T287	1		T82	1		T78	1
all_values[6]	auto[0]	auto[0]	auto[1]	133	1			T158	4		T50	3		T52	1
all_values[6]	auto[0]	auto[1]	auto[0]	29	1			T47	1		T125	1		T78	1
all_values[6]	auto[0]	auto[1]	auto[1]	109	1			T158	2		T50	7		T52	2
all_values[6]	auto[1]	auto[0]	auto[1]	104	1			T158	1		T50	1		T52	1
all_values[6]	auto[1]	auto[1]	auto[1]	84	1			T158	1		T50	3		T52	3
all_values[7]	auto[0]	auto[0]	auto[0]	28	1			T110	3		T77	1		T126	1
all_values[7]	auto[0]	auto[0]	auto[1]	119	1			T158	7		T50	3		T52	2
all_values[7]	auto[0]	auto[1]	auto[0]	25	1			T82	1		T61	1		T125	2
all_values[7]	auto[0]	auto[1]	auto[1]	106	1			T50	2		T52	3		T108	1
all_values[7]	auto[1]	auto[0]	auto[1]	114	1			T50	5		T52	1		T108	1
all_values[7]	auto[1]	auto[1]	auto[1]	98	1			T158	1		T50	4		T52	1
all_values[8]	auto[0]	auto[0]	auto[0]	44	1			T108	1		T77	1		T288	2
all_values[8]	auto[0]	auto[0]	auto[1]	103	1			T158	3		T50	3		T52	2
all_values[8]	auto[0]	auto[1]	auto[0]	31	1			T108	1		T287	1		T286	1
all_values[8]	auto[0]	auto[1]	auto[1]	120	1			T158	1		T50	5		T47	4
all_values[8]	auto[1]	auto[0]	auto[1]	92	1			T158	1		T50	4		T52	3
all_values[8]	auto[1]	auto[1]	auto[1]	100	1			T158	3		T50	2		T52	2
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T82	2		T289	1		T290	1
all_values[9]	auto[0]	auto[0]	auto[1]	108	1			T158	2		T50	6		T52	1
all_values[9]	auto[0]	auto[1]	auto[0]	41	1			T158	1		T108	1		T47	2
all_values[9]	auto[0]	auto[1]	auto[1]	104	1			T158	3		T50	1		T52	4
all_values[9]	auto[1]	auto[0]	auto[1]	115	1			T158	1		T50	5		T52	1
all_values[9]	auto[1]	auto[1]	auto[1]	90	1			T158	1		T50	2		T52	1
all_values[10]	auto[0]	auto[0]	auto[0]	50	1			T108	1		T47	5		T125	1
all_values[10]	auto[0]	auto[0]	auto[1]	102	1			T158	2		T50	7		T52	3
all_values[10]	auto[0]	auto[1]	auto[0]	30	1			T158	1		T108	1		T47	3
all_values[10]	auto[0]	auto[1]	auto[1]	103	1			T158	1		T50	2		T52	1
all_values[10]	auto[1]	auto[0]	auto[1]	119	1			T158	2		T50	2		T52	2
all_values[10]	auto[1]	auto[1]	auto[1]	86	1			T158	2		T50	3		T52	1
all_values[11]	auto[0]	auto[0]	auto[0]	38	1			T158	4		T82	1		T125	1
all_values[11]	auto[0]	auto[0]	auto[1]	125	1			T50	5		T52	1		T108	2
all_values[11]	auto[0]	auto[1]	auto[0]	28	1			T158	4		T50	1		T108	1
all_values[11]	auto[0]	auto[1]	auto[1]	100	1			T50	5		T52	4		T47	3
all_values[11]	auto[1]	auto[0]	auto[1]	120	1			T50	1		T108	1		T47	4
all_values[11]	auto[1]	auto[1]	auto[1]	79	1			T50	2		T52	2		T47	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1			T50	1		T110	2		T82	1
all_values[12]	auto[0]	auto[0]	auto[1]	108	1			T158	4		T50	2		T52	3
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T50	2		T52	1		T47	2
all_values[12]	auto[0]	auto[1]	auto[1]	120	1			T50	4		T52	1		T47	3
all_values[12]	auto[1]	auto[0]	auto[1]	93	1			T50	2		T52	2		T108	1
all_values[12]	auto[1]	auto[1]	auto[1]	109	1			T158	4		T50	3		T108	2
all_values[13]	auto[0]	auto[0]	auto[0]	30	1			T52	1		T82	1		T286	2
all_values[13]	auto[0]	auto[0]	auto[1]	103	1			T158	1		T50	3		T47	5
all_values[13]	auto[0]	auto[1]	auto[0]	48	1			T50	2		T108	2		T110	1
all_values[13]	auto[0]	auto[1]	auto[1]	107	1			T158	2		T50	4		T52	4
all_values[13]	auto[1]	auto[0]	auto[1]	95	1			T158	1		T50	1		T52	1
all_values[13]	auto[1]	auto[1]	auto[1]	107	1			T158	4		T50	4		T52	1
all_values[14]	auto[0]	auto[0]	auto[0]	31	1			T158	7		T52	1		T77	1
all_values[14]	auto[0]	auto[0]	auto[1]	115	1			T50	2		T52	1		T108	1
all_values[14]	auto[0]	auto[1]	auto[0]	27	1			T158	1		T50	3		T108	2
all_values[14]	auto[0]	auto[1]	auto[1]	103	1			T50	4		T47	1		T110	1
all_values[14]	auto[1]	auto[0]	auto[1]	114	1			T50	1		T52	4		T47	1
all_values[14]	auto[1]	auto[1]	auto[1]	100	1			T50	4		T52	1		T108	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal