Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	917005	1			T1	5297		T2	2		T3	1
all_values[1]	917005	1			T1	5297		T2	2		T3	1
all_values[2]	917005	1			T1	5297		T2	2		T3	1
all_values[3]	917005	1			T1	5297		T2	2		T3	1
all_values[4]	917005	1			T1	5297		T2	2		T3	1
all_values[5]	917005	1			T1	5297		T2	2		T3	1
all_values[6]	917005	1			T1	5297		T2	2		T3	1
all_values[7]	917005	1			T1	5297		T2	2		T3	1
all_values[8]	917005	1			T1	5297		T2	2		T3	1
all_values[9]	917005	1			T1	5297		T2	2		T3	1
all_values[10]	917005	1			T1	5297		T2	2		T3	1
all_values[11]	917005	1			T1	5297		T2	2		T3	1
all_values[12]	917005	1			T1	5297		T2	2		T3	1
all_values[13]	917005	1			T1	5297		T2	2		T3	1
all_values[14]	917005	1			T1	5297		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11252088

1

T1

71874

T2

26

T3

15

auto[1]

2502987

1

T1

7581

T2

4

T4

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11719079

1

T1

79455

T2

30

T3

15

auto[1]

2035996

1

T9

432

T46

63927

T45

364910

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	92039	1			T1	3784		T3	1		T5	1
all_values[0]	auto[0]	auto[1]	9978	1			T9	13		T46	61		T45	232
all_values[0]	auto[1]	auto[0]	719089	1			T1	1513		T2	2		T4	3
all_values[0]	auto[1]	auto[1]	95899	1			T9	15		T46	4201		T45	24096
all_values[1]	auto[0]	auto[0]	791603	1			T1	5297		T2	2		T3	1
all_values[1]	auto[0]	auto[1]	124718	1			T9	23		T46	4259		T45	24318
all_values[1]	auto[1]	auto[0]	430	1			T32	1		T33	1		T140	17
all_values[1]	auto[1]	auto[1]	254	1			T9	7		T46	2		T45	8
all_values[2]	auto[0]	auto[0]	775589	1			T1	5297		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	141118	1			T9	24		T46	4259		T45	24321
all_values[2]	auto[1]	auto[0]	51	1			T80	1		T81	1		T138	1
all_values[2]	auto[1]	auto[1]	247	1			T9	6		T46	3		T45	6
all_values[3]	auto[0]	auto[0]	790126	1			T1	5297		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	126645	1			T9	22		T46	4258		T45	24318
all_values[3]	auto[1]	auto[1]	234	1			T9	7		T46	4		T45	9
all_values[4]	auto[0]	auto[0]	778652	1			T1	5297		T2	2		T3	1
all_values[4]	auto[0]	auto[1]	138092	1			T9	21		T46	4258		T45	24319
all_values[4]	auto[1]	auto[0]	22	1			T38	2		T263	1		T264	2
all_values[4]	auto[1]	auto[1]	239	1			T9	7		T46	3		T45	5
all_values[5]	auto[0]	auto[0]	775654	1			T1	5297		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	141061	1			T9	20		T46	4259		T45	24321
all_values[5]	auto[1]	auto[1]	290	1			T9	9		T46	3		T45	6
all_values[6]	auto[0]	auto[0]	775889	1			T1	5297		T2	2		T3	1
all_values[6]	auto[0]	auto[1]	140885	1			T9	21		T46	4260		T45	24328
all_values[6]	auto[1]	auto[1]	231	1			T9	9		T46	2		T47	4
all_values[7]	auto[0]	auto[0]	749710	1			T1	4498		T2	2		T3	1
all_values[7]	auto[0]	auto[1]	136629	1			T9	20		T46	4102		T45	24085
all_values[7]	auto[1]	auto[0]	25964	1			T1	799		T5	1		T8	20
all_values[7]	auto[1]	auto[1]	4702	1			T9	7		T46	160		T45	242
all_values[8]	auto[0]	auto[0]	775691	1			T1	5297		T2	2		T3	1
all_values[8]	auto[0]	auto[1]	141077	1			T9	22		T46	4258		T45	24322
all_values[8]	auto[1]	auto[1]	237	1			T9	8		T46	3		T45	6
all_values[9]	auto[0]	auto[0]	156255	1			T1	5291		T2	2		T3	1
all_values[9]	auto[0]	auto[1]	20123	1			T9	20		T46	118		T45	717
all_values[9]	auto[1]	auto[0]	619407	1			T1	6		T4	1		T5	1
all_values[9]	auto[1]	auto[1]	121220	1			T9	7		T46	4144		T45	23611
all_values[10]	auto[0]	auto[0]	775682	1			T1	5297		T2	2		T3	1
all_values[10]	auto[0]	auto[1]	141107	1			T9	25		T46	4259		T45	24323
all_values[10]	auto[1]	auto[1]	216	1			T9	4		T46	3		T45	5
all_values[11]	auto[0]	auto[0]	2859	1			T1	34		T3	1		T5	1
all_values[11]	auto[0]	auto[1]	646	1			T9	14		T46	6		T45	48
all_values[11]	auto[1]	auto[0]	773840	1			T1	5263		T2	2		T4	3
all_values[11]	auto[1]	auto[1]	139660	1			T9	16		T46	4256		T45	24280
all_values[12]	auto[0]	auto[0]	788985	1			T1	5297		T2	2		T3	1
all_values[12]	auto[0]	auto[1]	127776	1			T9	23		T46	4258		T45	24319
all_values[12]	auto[1]	auto[0]	16	1			T138	1		T265	1		T266	1
all_values[12]	auto[1]	auto[1]	228	1			T9	5		T46	4		T45	9
all_values[13]	auto[0]	auto[0]	775854	1			T1	5297		T2	2		T3	1
all_values[13]	auto[0]	auto[1]	140895	1			T9	19		T46	4258		T45	24320
all_values[13]	auto[1]	auto[1]	256	1			T9	11		T46	4		T45	8
all_values[14]	auto[0]	auto[0]	775672	1			T1	5297		T2	2		T3	1
all_values[14]	auto[0]	auto[1]	141078	1			T9	22		T46	4258		T45	24326
all_values[14]	auto[1]	auto[1]	255	1			T9	5		T46	4		T45	2