Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	917005	1			T1	5297		T2	2		T3	1
all_pins[1]	917005	1			T1	5297		T2	2		T3	1
all_pins[2]	917005	1			T1	5297		T2	2		T3	1
all_pins[3]	917005	1			T1	5297		T2	2		T3	1
all_pins[4]	917005	1			T1	5297		T2	2		T3	1
all_pins[5]	917005	1			T1	5297		T2	2		T3	1
all_pins[6]	917005	1			T1	5297		T2	2		T3	1
all_pins[7]	917005	1			T1	5297		T2	2		T3	1
all_pins[8]	917005	1			T1	5297		T2	2		T3	1
all_pins[9]	917005	1			T1	5297		T2	2		T3	1
all_pins[10]	917005	1			T1	5297		T2	2		T3	1
all_pins[11]	917005	1			T1	5297		T2	2		T3	1
all_pins[12]	917005	1			T1	5297		T2	2		T3	1
all_pins[13]	917005	1			T1	5297		T2	2		T3	1
all_pins[14]	917005	1			T1	5297		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11257655	1			T1	71873		T2	26		T3	15
values[0x1]	2497420	1			T1	7582		T2	4		T4	7
transitions[0x0=>0x1]	2496366	1			T1	7582		T2	4		T4	7
transitions[0x1=>0x0]	2495166	1			T1	7582		T2	3		T4	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	105534	1			T1	3784		T3	1		T5	1
all_pins[0]	values[0x1]	811471	1			T1	1513		T2	2		T4	3
all_pins[0]	transitions[0x0=>0x1]	810865	1			T1	1513		T2	2		T4	3
all_pins[0]	transitions[0x1=>0x0]	93	1			T9	3		T46	1		T45	2
all_pins[1]	values[0x0]	916306	1			T1	5297		T2	2		T3	1
all_pins[1]	values[0x1]	699	1			T9	4		T46	1		T32	1
all_pins[1]	transitions[0x0=>0x1]	664	1			T9	3		T32	1		T33	1
all_pins[1]	transitions[0x1=>0x0]	137	1			T9	3		T80	1		T81	1
all_pins[2]	values[0x0]	916833	1			T1	5297		T2	2		T3	1
all_pins[2]	values[0x1]	172	1			T9	4		T46	1		T80	1
all_pins[2]	transitions[0x0=>0x1]	148	1			T9	3		T80	1		T81	1
all_pins[2]	transitions[0x1=>0x0]	76	1			T9	2		T46	2		T280	2
all_pins[3]	values[0x0]	916905	1			T1	5297		T2	2		T3	1
all_pins[3]	values[0x1]	100	1			T9	3		T46	3		T45	1
all_pins[3]	transitions[0x0=>0x1]	76	1			T9	1		T46	2		T45	1
all_pins[3]	transitions[0x1=>0x0]	111	1			T9	1		T38	2		T45	4
all_pins[4]	values[0x0]	916870	1			T1	5297		T2	2		T3	1
all_pins[4]	values[0x1]	135	1			T9	3		T46	1		T38	2
all_pins[4]	transitions[0x0=>0x1]	111	1			T9	2		T46	1		T38	2
all_pins[4]	transitions[0x1=>0x0]	123	1			T9	6		T46	3		T45	1
all_pins[5]	values[0x0]	916858	1			T1	5297		T2	2		T3	1
all_pins[5]	values[0x1]	147	1			T9	7		T46	3		T45	1
all_pins[5]	transitions[0x0=>0x1]	109	1			T9	4		T46	2		T45	1
all_pins[5]	transitions[0x1=>0x0]	80	1			T9	3		T46	1		T47	3
all_pins[6]	values[0x0]	916887	1			T1	5297		T2	2		T3	1
all_pins[6]	values[0x1]	118	1			T9	6		T46	2		T47	3
all_pins[6]	transitions[0x0=>0x1]	90	1			T9	2		T46	1		T47	3
all_pins[6]	transitions[0x1=>0x0]	33783	1			T1	800		T5	1		T8	20
all_pins[7]	values[0x0]	883194	1			T1	4497		T2	2		T3	1
all_pins[7]	values[0x1]	33811	1			T1	800		T5	1		T8	20
all_pins[7]	transitions[0x0=>0x1]	33775	1			T1	800		T5	1		T8	20
all_pins[7]	transitions[0x1=>0x0]	96	1			T9	1		T46	1		T45	4
all_pins[8]	values[0x0]	916873	1			T1	5297		T2	2		T3	1
all_pins[8]	values[0x1]	132	1			T9	3		T46	3		T45	4
all_pins[8]	transitions[0x0=>0x1]	102	1			T9	1		T46	3		T45	2
all_pins[8]	transitions[0x1=>0x0]	740539	1			T1	6		T4	1		T5	1
all_pins[9]	values[0x0]	176436	1			T1	5291		T2	2		T3	1
all_pins[9]	values[0x1]	740569	1			T1	6		T4	1		T5	1
all_pins[9]	transitions[0x0=>0x1]	740547	1			T1	6		T4	1		T5	1
all_pins[9]	transitions[0x1=>0x0]	89	1			T9	1		T46	1		T45	1
all_pins[10]	values[0x0]	916894	1			T1	5297		T2	2		T3	1
all_pins[10]	values[0x1]	111	1			T9	1		T46	1		T45	2
all_pins[10]	transitions[0x0=>0x1]	75	1			T9	1		T46	1		T45	1
all_pins[10]	transitions[0x1=>0x0]	909512	1			T1	5263		T2	2		T4	3
all_pins[11]	values[0x0]	7457	1			T1	34		T3	1		T5	1
all_pins[11]	values[0x1]	909548	1			T1	5263		T2	2		T4	3
all_pins[11]	transitions[0x0=>0x1]	909498	1			T1	5263		T2	2		T4	3
all_pins[11]	transitions[0x1=>0x0]	84	1			T46	1		T45	2		T281	1
all_pins[12]	values[0x0]	916871	1			T1	5297		T2	2		T3	1
all_pins[12]	values[0x1]	134	1			T9	2		T46	3		T138	1
all_pins[12]	transitions[0x0=>0x1]	114	1			T9	1		T46	3		T138	1
all_pins[12]	transitions[0x1=>0x0]	115	1			T9	5		T46	1		T45	4
all_pins[13]	values[0x0]	916870	1			T1	5297		T2	2		T3	1
all_pins[13]	values[0x1]	135	1			T9	6		T46	1		T45	5
all_pins[13]	transitions[0x0=>0x1]	105	1			T9	5		T46	1		T45	5
all_pins[13]	transitions[0x1=>0x0]	108	1			T46	1		T45	1		T47	1
all_pins[14]	values[0x0]	916867	1			T1	5297		T2	2		T3	1
all_pins[14]	values[0x1]	138	1			T9	1		T46	1		T45	1
all_pins[14]	transitions[0x0=>0x1]	87	1			T46	1		T45	1		T247	3
all_pins[14]	transitions[0x1=>0x0]	810220	1			T1	1513		T2	1		T4	2