Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	553	1			T9	14		T46	7		T45	14
all_values[1]	553	1			T9	14		T46	7		T45	14
all_values[2]	553	1			T9	14		T46	7		T45	14
all_values[3]	553	1			T9	14		T46	7		T45	14
all_values[4]	553	1			T9	14		T46	7		T45	14
all_values[5]	553	1			T9	14		T46	7		T45	14
all_values[6]	553	1			T9	14		T46	7		T45	14
all_values[7]	553	1			T9	14		T46	7		T45	14
all_values[8]	553	1			T9	14		T46	7		T45	14
all_values[9]	553	1			T9	14		T46	7		T45	14
all_values[10]	553	1			T9	14		T46	7		T45	14
all_values[11]	553	1			T9	14		T46	7		T45	14
all_values[12]	553	1			T9	14		T46	7		T45	14
all_values[13]	553	1			T9	14		T46	7		T45	14
all_values[14]	553	1			T9	14		T46	7		T45	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4281

1

T9

98

T46

60

T45

124

auto[1]

4014

1

T9

112

T46

45

T45

86

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1189

1

T9

18

T46

3

T45

10

auto[1]

7106

1

T9

192

T46

102

T45

200

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4898

1

T9

121

T46

55

T45

123

auto[1]

3397

1

T9

89

T46

50

T45

87

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	50	1			T9	1		T281	4		T280	1
all_values[0]	auto[0]	auto[0]	auto[1]	123	1			T9	3		T46	1		T45	7
all_values[0]	auto[0]	auto[1]	auto[0]	32	1			T9	1		T47	1		T282	2
all_values[0]	auto[0]	auto[1]	auto[1]	126	1			T9	3		T46	1		T45	3
all_values[0]	auto[1]	auto[0]	auto[1]	110	1			T9	3		T46	3		T45	2
all_values[0]	auto[1]	auto[1]	auto[1]	112	1			T9	3		T46	2		T45	2
all_values[1]	auto[0]	auto[0]	auto[0]	43	1			T46	1		T45	1		T115	1
all_values[1]	auto[0]	auto[0]	auto[1]	113	1			T9	4		T46	1		T45	4
all_values[1]	auto[0]	auto[1]	auto[0]	48	1			T45	1		T247	2		T282	4
all_values[1]	auto[0]	auto[1]	auto[1]	117	1			T9	3		T46	3		T45	2
all_values[1]	auto[1]	auto[0]	auto[1]	115	1			T9	2		T46	1		T45	4
all_values[1]	auto[1]	auto[1]	auto[1]	117	1			T9	5		T46	1		T45	2
all_values[2]	auto[0]	auto[0]	auto[0]	43	1			T45	1		T47	2		T50	1
all_values[2]	auto[0]	auto[0]	auto[1]	118	1			T9	5		T46	2		T45	4
all_values[2]	auto[0]	auto[1]	auto[0]	15	1			T282	1		T50	1		T283	2
all_values[2]	auto[0]	auto[1]	auto[1]	130	1			T9	3		T46	2		T45	3
all_values[2]	auto[1]	auto[0]	auto[1]	146	1			T9	4		T46	2		T45	3
all_values[2]	auto[1]	auto[1]	auto[1]	101	1			T9	2		T46	1		T45	3
all_values[3]	auto[0]	auto[0]	auto[0]	51	1			T45	1		T50	7		T101	2
all_values[3]	auto[0]	auto[0]	auto[1]	147	1			T9	3		T46	3		T45	6
all_values[3]	auto[0]	auto[1]	auto[0]	20	1			T9	1		T282	1		T115	1
all_values[3]	auto[0]	auto[1]	auto[1]	121	1			T9	6		T46	1		T45	1
all_values[3]	auto[1]	auto[0]	auto[1]	128	1			T9	2		T46	1		T45	3
all_values[3]	auto[1]	auto[1]	auto[1]	86	1			T9	2		T46	2		T45	3
all_values[4]	auto[0]	auto[0]	auto[0]	49	1			T9	1		T46	1		T45	3
all_values[4]	auto[0]	auto[0]	auto[1]	114	1			T9	3		T46	2		T45	3
all_values[4]	auto[0]	auto[1]	auto[0]	35	1			T9	1		T45	1		T47	1
all_values[4]	auto[0]	auto[1]	auto[1]	116	1			T9	2		T46	1		T45	2
all_values[4]	auto[1]	auto[0]	auto[1]	129	1			T9	5		T46	2		T45	1
all_values[4]	auto[1]	auto[1]	auto[1]	110	1			T9	2		T46	1		T45	4
all_values[5]	auto[0]	auto[0]	auto[0]	35	1			T50	1		T284	1		T285	1
all_values[5]	auto[0]	auto[0]	auto[1]	116	1			T9	2		T46	2		T45	6
all_values[5]	auto[0]	auto[1]	auto[0]	33	1			T9	1		T45	1		T47	1
all_values[5]	auto[0]	auto[1]	auto[1]	132	1			T9	7		T46	2		T281	2
all_values[5]	auto[1]	auto[0]	auto[1]	126	1			T9	1		T46	1		T45	5
all_values[5]	auto[1]	auto[1]	auto[1]	111	1			T9	3		T46	2		T45	2
all_values[6]	auto[0]	auto[0]	auto[0]	66	1			T280	1		T247	3		T282	1
all_values[6]	auto[0]	auto[0]	auto[1]	96	1			T46	1		T45	2		T281	1
all_values[6]	auto[0]	auto[1]	auto[0]	33	1			T282	1		T283	1		T101	1
all_values[6]	auto[0]	auto[1]	auto[1]	130	1			T9	6		T46	1		T45	5
all_values[6]	auto[1]	auto[0]	auto[1]	122	1			T9	1		T46	3		T45	5
all_values[6]	auto[1]	auto[1]	auto[1]	106	1			T9	7		T46	2		T45	2
all_values[7]	auto[0]	auto[0]	auto[0]	45	1			T9	1		T247	1		T115	1
all_values[7]	auto[0]	auto[0]	auto[1]	122	1			T9	4		T46	2		T45	6
all_values[7]	auto[0]	auto[1]	auto[0]	42	1			T9	2		T45	1		T47	2
all_values[7]	auto[0]	auto[1]	auto[1]	123	1			T9	4		T46	1		T45	2
all_values[7]	auto[1]	auto[0]	auto[1]	112	1			T9	1		T46	2		T45	4
all_values[7]	auto[1]	auto[1]	auto[1]	109	1			T9	2		T46	2		T45	1
all_values[8]	auto[0]	auto[0]	auto[0]	52	1			T46	1		T282	1		T101	1
all_values[8]	auto[0]	auto[0]	auto[1]	107	1			T9	2		T46	3		T45	3
all_values[8]	auto[0]	auto[1]	auto[0]	38	1			T282	1		T284	2		T67	2
all_values[8]	auto[0]	auto[1]	auto[1]	126	1			T9	2		T45	5		T280	1
all_values[8]	auto[1]	auto[0]	auto[1]	117	1			T9	5		T45	3		T47	3
all_values[8]	auto[1]	auto[1]	auto[1]	113	1			T9	5		T46	3		T45	3
all_values[9]	auto[0]	auto[0]	auto[0]	47	1			T9	1		T281	3		T115	2
all_values[9]	auto[0]	auto[0]	auto[1]	129	1			T9	6		T46	3		T45	2
all_values[9]	auto[0]	auto[1]	auto[0]	26	1			T9	2		T281	1		T102	1
all_values[9]	auto[0]	auto[1]	auto[1]	132	1			T9	1		T46	2		T45	6
all_values[9]	auto[1]	auto[0]	auto[1]	116	1			T9	3		T46	2		T45	5
all_values[9]	auto[1]	auto[1]	auto[1]	103	1			T9	1		T45	1		T47	1
all_values[10]	auto[0]	auto[0]	auto[0]	45	1			T281	3		T280	1		T115	2
all_values[10]	auto[0]	auto[0]	auto[1]	123	1			T9	5		T46	2		T45	4
all_values[10]	auto[0]	auto[1]	auto[0]	47	1			T9	1		T281	1		T280	1
all_values[10]	auto[0]	auto[1]	auto[1]	122	1			T9	4		T46	2		T45	5
all_values[10]	auto[1]	auto[0]	auto[1]	119	1			T9	3		T46	2		T45	4
all_values[10]	auto[1]	auto[1]	auto[1]	97	1			T9	1		T46	1		T45	1
all_values[11]	auto[0]	auto[0]	auto[0]	40	1			T281	1		T49	1		T279	1
all_values[11]	auto[0]	auto[0]	auto[1]	123	1			T9	3		T46	4		T45	7
all_values[11]	auto[0]	auto[1]	auto[0]	38	1			T247	2		T282	2		T279	3
all_values[11]	auto[0]	auto[1]	auto[1]	138	1			T9	4		T45	2		T47	3
all_values[11]	auto[1]	auto[0]	auto[1]	121	1			T9	5		T46	1		T45	2
all_values[11]	auto[1]	auto[1]	auto[1]	93	1			T9	2		T46	2		T45	3
all_values[12]	auto[0]	auto[0]	auto[0]	37	1			T281	1		T282	1		T49	1
all_values[12]	auto[0]	auto[0]	auto[1]	120	1			T9	4		T46	2		T45	4
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T9	2		T282	3		T49	1
all_values[12]	auto[0]	auto[1]	auto[1]	139	1			T9	3		T46	1		T45	1
all_values[12]	auto[1]	auto[0]	auto[1]	125	1			T9	4		T46	2		T45	5
all_values[12]	auto[1]	auto[1]	auto[1]	103	1			T9	1		T46	2		T45	4
all_values[13]	auto[0]	auto[0]	auto[0]	31	1			T47	1		T281	1		T280	1
all_values[13]	auto[0]	auto[0]	auto[1]	109	1			T9	2		T46	1		T45	2
all_values[13]	auto[0]	auto[1]	auto[0]	33	1			T281	3		T280	1		T282	1
all_values[13]	auto[0]	auto[1]	auto[1]	151	1			T9	4		T46	2		T45	7
all_values[13]	auto[1]	auto[0]	auto[1]	128	1			T9	2		T46	2		T45	3
all_values[13]	auto[1]	auto[1]	auto[1]	101	1			T9	6		T46	2		T45	2
all_values[14]	auto[0]	auto[0]	auto[0]	47	1			T9	1		T115	1		T50	1
all_values[14]	auto[0]	auto[0]	auto[1]	113	1			T9	2		T46	2		T45	5
all_values[14]	auto[0]	auto[1]	auto[0]	39	1			T9	2		T115	2		T279	1
all_values[14]	auto[0]	auto[1]	auto[1]	133	1			T9	3		T46	2		T45	4
all_values[14]	auto[1]	auto[0]	auto[1]	113	1			T9	4		T46	2		T45	4
all_values[14]	auto[1]	auto[1]	auto[1]	108	1			T9	2		T46	1		T45	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal