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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.72 96.51 89.73 97.22 69.05 93.48 98.44 90.63


Total test records in report: 1645
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T1546 /workspace/coverage/cover_reg_top/37.i2c_intr_test.2626276054 Jul 02 08:03:13 AM PDT 24 Jul 02 08:03:28 AM PDT 24 32144771 ps
T1547 /workspace/coverage/cover_reg_top/33.i2c_intr_test.1165468483 Jul 02 08:03:19 AM PDT 24 Jul 02 08:03:33 AM PDT 24 18727014 ps
T1548 /workspace/coverage/cover_reg_top/45.i2c_intr_test.773641071 Jul 02 08:03:17 AM PDT 24 Jul 02 08:03:31 AM PDT 24 18011927 ps
T211 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3853696363 Jul 02 08:03:07 AM PDT 24 Jul 02 08:03:23 AM PDT 24 35408886 ps
T92 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4081387063 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:21 AM PDT 24 29604212 ps
T216 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2271892648 Jul 02 08:03:10 AM PDT 24 Jul 02 08:03:25 AM PDT 24 19081467 ps
T1549 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3873521827 Jul 02 08:03:04 AM PDT 24 Jul 02 08:03:21 AM PDT 24 52418523 ps
T1550 /workspace/coverage/cover_reg_top/31.i2c_intr_test.2604280016 Jul 02 08:03:11 AM PDT 24 Jul 02 08:03:26 AM PDT 24 53807828 ps
T1551 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.235539577 Jul 02 08:02:54 AM PDT 24 Jul 02 08:03:14 AM PDT 24 99195882 ps
T1552 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1373258781 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:21 AM PDT 24 80589223 ps
T1553 /workspace/coverage/cover_reg_top/36.i2c_intr_test.1486472056 Jul 02 08:03:16 AM PDT 24 Jul 02 08:03:32 AM PDT 24 29543965 ps
T191 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1144147564 Jul 02 08:03:06 AM PDT 24 Jul 02 08:03:22 AM PDT 24 66391445 ps
T236 /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.510295261 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:20 AM PDT 24 28032534 ps
T93 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2960324122 Jul 02 08:03:14 AM PDT 24 Jul 02 08:03:29 AM PDT 24 80599002 ps
T212 /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.809246593 Jul 02 08:03:06 AM PDT 24 Jul 02 08:03:22 AM PDT 24 30148914 ps
T94 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.741650104 Jul 02 08:03:00 AM PDT 24 Jul 02 08:03:18 AM PDT 24 303169045 ps
T188 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3770398002 Jul 02 08:02:58 AM PDT 24 Jul 02 08:03:17 AM PDT 24 99092768 ps
T1554 /workspace/coverage/cover_reg_top/21.i2c_intr_test.1693126174 Jul 02 08:03:13 AM PDT 24 Jul 02 08:03:27 AM PDT 24 17687523 ps
T213 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.659079281 Jul 02 08:02:48 AM PDT 24 Jul 02 08:03:06 AM PDT 24 32815416 ps
T214 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.139116458 Jul 02 08:03:14 AM PDT 24 Jul 02 08:03:29 AM PDT 24 38055382 ps
T1555 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2480941868 Jul 02 08:02:50 AM PDT 24 Jul 02 08:03:09 AM PDT 24 61427084 ps
T189 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.927656238 Jul 02 08:02:58 AM PDT 24 Jul 02 08:03:17 AM PDT 24 95834318 ps
T1556 /workspace/coverage/cover_reg_top/16.i2c_intr_test.1649891623 Jul 02 08:03:09 AM PDT 24 Jul 02 08:03:23 AM PDT 24 29791157 ps
T1557 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1690998967 Jul 02 08:03:02 AM PDT 24 Jul 02 08:03:18 AM PDT 24 56858982 ps
T1558 /workspace/coverage/cover_reg_top/0.i2c_intr_test.1767467280 Jul 02 08:02:41 AM PDT 24 Jul 02 08:02:58 AM PDT 24 15426030 ps
T1559 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2575499094 Jul 02 08:03:01 AM PDT 24 Jul 02 08:03:18 AM PDT 24 33266774 ps
T197 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2012193513 Jul 02 08:02:46 AM PDT 24 Jul 02 08:03:04 AM PDT 24 65835571 ps
T1560 /workspace/coverage/cover_reg_top/46.i2c_intr_test.212722036 Jul 02 08:03:13 AM PDT 24 Jul 02 08:03:27 AM PDT 24 22763826 ps
T267 /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1873995365 Jul 02 08:03:10 AM PDT 24 Jul 02 08:03:26 AM PDT 24 138457971 ps
T1561 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3266354046 Jul 02 08:03:12 AM PDT 24 Jul 02 08:03:27 AM PDT 24 43849216 ps
T1562 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2274462666 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:21 AM PDT 24 19227383 ps
T1563 /workspace/coverage/cover_reg_top/32.i2c_intr_test.360187555 Jul 02 08:03:15 AM PDT 24 Jul 02 08:03:29 AM PDT 24 30789981 ps
T1564 /workspace/coverage/cover_reg_top/49.i2c_intr_test.2020589644 Jul 02 08:03:16 AM PDT 24 Jul 02 08:03:30 AM PDT 24 67387773 ps
T217 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4085694914 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:21 AM PDT 24 23821542 ps
T95 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3206881693 Jul 02 08:02:57 AM PDT 24 Jul 02 08:03:17 AM PDT 24 1273802987 ps
T1565 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1804555241 Jul 02 08:02:58 AM PDT 24 Jul 02 08:03:16 AM PDT 24 339781872 ps
T1566 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1547598859 Jul 02 08:02:51 AM PDT 24 Jul 02 08:03:10 AM PDT 24 18830501 ps
T1567 /workspace/coverage/cover_reg_top/8.i2c_intr_test.3702267303 Jul 02 08:03:10 AM PDT 24 Jul 02 08:03:25 AM PDT 24 52980064 ps
T195 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.744526655 Jul 02 08:02:59 AM PDT 24 Jul 02 08:03:18 AM PDT 24 130710272 ps
T1568 /workspace/coverage/cover_reg_top/47.i2c_intr_test.1924460508 Jul 02 08:03:20 AM PDT 24 Jul 02 08:03:34 AM PDT 24 21108469 ps
T1569 /workspace/coverage/cover_reg_top/44.i2c_intr_test.1939072250 Jul 02 08:03:20 AM PDT 24 Jul 02 08:03:34 AM PDT 24 17082337 ps
T96 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2183103570 Jul 02 08:03:07 AM PDT 24 Jul 02 08:03:22 AM PDT 24 356314767 ps
T1570 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.129126278 Jul 02 08:03:01 AM PDT 24 Jul 02 08:03:19 AM PDT 24 68848277 ps
T97 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3256896874 Jul 02 08:02:53 AM PDT 24 Jul 02 08:03:12 AM PDT 24 116259748 ps
T203 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1655397910 Jul 02 08:03:00 AM PDT 24 Jul 02 08:03:18 AM PDT 24 103273178 ps
T205 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1940241680 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:22 AM PDT 24 439040979 ps
T218 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2123937808 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:21 AM PDT 24 59952303 ps
T1571 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2972361996 Jul 02 08:02:50 AM PDT 24 Jul 02 08:03:10 AM PDT 24 88588238 ps
T201 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3167446894 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:21 AM PDT 24 489778304 ps
T1572 /workspace/coverage/cover_reg_top/39.i2c_intr_test.3620981413 Jul 02 08:03:11 AM PDT 24 Jul 02 08:03:27 AM PDT 24 36136985 ps
T1573 /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2188454817 Jul 02 08:02:55 AM PDT 24 Jul 02 08:03:14 AM PDT 24 51430810 ps
T114 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2170385704 Jul 02 08:02:56 AM PDT 24 Jul 02 08:03:14 AM PDT 24 41793374 ps
T198 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1803999275 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:21 AM PDT 24 84373651 ps
T192 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2633435285 Jul 02 08:02:56 AM PDT 24 Jul 02 08:03:16 AM PDT 24 684722814 ps
T1574 /workspace/coverage/cover_reg_top/42.i2c_intr_test.307550606 Jul 02 08:03:15 AM PDT 24 Jul 02 08:03:29 AM PDT 24 32007218 ps
T1575 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4268812530 Jul 02 08:03:09 AM PDT 24 Jul 02 08:03:26 AM PDT 24 69492988 ps
T199 /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1245671612 Jul 02 08:02:45 AM PDT 24 Jul 02 08:03:04 AM PDT 24 121503643 ps
T1576 /workspace/coverage/cover_reg_top/14.i2c_intr_test.909158064 Jul 02 08:03:10 AM PDT 24 Jul 02 08:03:25 AM PDT 24 15093759 ps
T1577 /workspace/coverage/cover_reg_top/43.i2c_intr_test.4046688342 Jul 02 08:03:14 AM PDT 24 Jul 02 08:03:29 AM PDT 24 15827833 ps
T1578 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2278553090 Jul 02 08:02:51 AM PDT 24 Jul 02 08:03:10 AM PDT 24 24461344 ps
T204 /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.343829958 Jul 02 08:03:06 AM PDT 24 Jul 02 08:03:23 AM PDT 24 147069315 ps
T219 /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3567621026 Jul 02 08:02:50 AM PDT 24 Jul 02 08:03:13 AM PDT 24 2593107840 ps
T1579 /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3318883561 Jul 02 08:03:01 AM PDT 24 Jul 02 08:03:18 AM PDT 24 61400805 ps
T1580 /workspace/coverage/cover_reg_top/24.i2c_intr_test.809585162 Jul 02 08:03:15 AM PDT 24 Jul 02 08:03:29 AM PDT 24 32464496 ps
T220 /workspace/coverage/cover_reg_top/18.i2c_csr_rw.325721833 Jul 02 08:03:14 AM PDT 24 Jul 02 08:03:28 AM PDT 24 70297108 ps
T200 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.570956156 Jul 02 08:02:46 AM PDT 24 Jul 02 08:03:04 AM PDT 24 152784185 ps
T1581 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2360192767 Jul 02 08:03:15 AM PDT 24 Jul 02 08:03:29 AM PDT 24 18354734 ps
T221 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2030745528 Jul 02 08:03:06 AM PDT 24 Jul 02 08:03:22 AM PDT 24 45053739 ps
T1582 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1414888875 Jul 02 08:02:59 AM PDT 24 Jul 02 08:03:16 AM PDT 24 18838072 ps
T222 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2072693682 Jul 02 08:02:50 AM PDT 24 Jul 02 08:03:09 AM PDT 24 17804348 ps
T1583 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2783722595 Jul 02 08:02:49 AM PDT 24 Jul 02 08:03:07 AM PDT 24 29106707 ps
T1584 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1015906219 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:21 AM PDT 24 191660068 ps
T1585 /workspace/coverage/cover_reg_top/25.i2c_intr_test.3991482563 Jul 02 08:03:12 AM PDT 24 Jul 02 08:03:27 AM PDT 24 186875961 ps
T224 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.959398110 Jul 02 08:02:48 AM PDT 24 Jul 02 08:03:10 AM PDT 24 1865059524 ps
T1586 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.726031038 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:21 AM PDT 24 24088762 ps
T1587 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2236602632 Jul 02 08:03:00 AM PDT 24 Jul 02 08:03:17 AM PDT 24 195605761 ps
T1588 /workspace/coverage/cover_reg_top/1.i2c_intr_test.1328129264 Jul 02 08:02:52 AM PDT 24 Jul 02 08:03:11 AM PDT 24 45382314 ps
T1589 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1020208919 Jul 02 08:03:10 AM PDT 24 Jul 02 08:03:27 AM PDT 24 409398246 ps
T1590 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.610760395 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:20 AM PDT 24 59789005 ps
T1591 /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.926693660 Jul 02 08:03:00 AM PDT 24 Jul 02 08:03:17 AM PDT 24 44190681 ps
T1592 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4076577810 Jul 02 08:03:00 AM PDT 24 Jul 02 08:03:18 AM PDT 24 134161061 ps
T1593 /workspace/coverage/cover_reg_top/30.i2c_intr_test.577212626 Jul 02 08:03:13 AM PDT 24 Jul 02 08:03:27 AM PDT 24 37888407 ps
T202 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4126435177 Jul 02 08:02:41 AM PDT 24 Jul 02 08:02:59 AM PDT 24 415165193 ps
T1594 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1669172311 Jul 02 08:02:50 AM PDT 24 Jul 02 08:03:09 AM PDT 24 198120257 ps
T1595 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1082730796 Jul 02 08:03:01 AM PDT 24 Jul 02 08:03:18 AM PDT 24 172528700 ps
T1596 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.498464089 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:21 AM PDT 24 248785871 ps
T1597 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4252021685 Jul 02 08:02:53 AM PDT 24 Jul 02 08:03:12 AM PDT 24 18468761 ps
T1598 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1703965333 Jul 02 08:03:12 AM PDT 24 Jul 02 08:03:27 AM PDT 24 52885301 ps
T223 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3054709978 Jul 02 08:02:52 AM PDT 24 Jul 02 08:03:12 AM PDT 24 64367739 ps
T1599 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1385689473 Jul 02 08:03:15 AM PDT 24 Jul 02 08:03:29 AM PDT 24 20374572 ps
T227 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.290559980 Jul 02 08:02:44 AM PDT 24 Jul 02 08:03:03 AM PDT 24 94747508 ps
T1600 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1255712433 Jul 02 08:02:49 AM PDT 24 Jul 02 08:03:09 AM PDT 24 217800371 ps
T1601 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3509725758 Jul 02 08:02:57 AM PDT 24 Jul 02 08:03:16 AM PDT 24 37157030 ps
T225 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.780235992 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:19 AM PDT 24 66635461 ps
T1602 /workspace/coverage/cover_reg_top/40.i2c_intr_test.3117773950 Jul 02 08:03:13 AM PDT 24 Jul 02 08:03:28 AM PDT 24 16966609 ps
T1603 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2559656564 Jul 02 08:03:13 AM PDT 24 Jul 02 08:03:29 AM PDT 24 115810451 ps
T1604 /workspace/coverage/cover_reg_top/15.i2c_intr_test.1661523071 Jul 02 08:03:12 AM PDT 24 Jul 02 08:03:26 AM PDT 24 23585635 ps
T1605 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1976614779 Jul 02 08:03:07 AM PDT 24 Jul 02 08:03:23 AM PDT 24 96205785 ps
T226 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1425901131 Jul 02 08:02:47 AM PDT 24 Jul 02 08:03:05 AM PDT 24 18310570 ps
T1606 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4063550139 Jul 02 08:03:16 AM PDT 24 Jul 02 08:03:33 AM PDT 24 34536096 ps
T1607 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1440126827 Jul 02 08:03:02 AM PDT 24 Jul 02 08:03:20 AM PDT 24 560498757 ps
T1608 /workspace/coverage/cover_reg_top/17.i2c_intr_test.843512658 Jul 02 08:03:10 AM PDT 24 Jul 02 08:03:25 AM PDT 24 33015024 ps
T1609 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2846488794 Jul 02 08:03:01 AM PDT 24 Jul 02 08:03:20 AM PDT 24 76804904 ps
T1610 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3905962572 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:20 AM PDT 24 36221506 ps
T1611 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1931186629 Jul 02 08:03:10 AM PDT 24 Jul 02 08:03:25 AM PDT 24 81029849 ps
T1612 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1685749089 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:20 AM PDT 24 30543534 ps
T1613 /workspace/coverage/cover_reg_top/6.i2c_intr_test.411441613 Jul 02 08:02:51 AM PDT 24 Jul 02 08:03:10 AM PDT 24 51856790 ps
T1614 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.741067945 Jul 02 08:03:09 AM PDT 24 Jul 02 08:03:23 AM PDT 24 161346352 ps
T1615 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.550341048 Jul 02 08:03:06 AM PDT 24 Jul 02 08:03:24 AM PDT 24 402460392 ps
T1616 /workspace/coverage/cover_reg_top/35.i2c_intr_test.3492476099 Jul 02 08:03:16 AM PDT 24 Jul 02 08:03:32 AM PDT 24 23709294 ps
T1617 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3629751346 Jul 02 08:02:48 AM PDT 24 Jul 02 08:03:06 AM PDT 24 191816178 ps
T1618 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2426961545 Jul 02 08:02:48 AM PDT 24 Jul 02 08:03:07 AM PDT 24 67920629 ps
T1619 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2328278897 Jul 02 08:03:15 AM PDT 24 Jul 02 08:03:29 AM PDT 24 55656836 ps
T1620 /workspace/coverage/cover_reg_top/2.i2c_intr_test.998333144 Jul 02 08:02:49 AM PDT 24 Jul 02 08:03:07 AM PDT 24 43866185 ps
T1621 /workspace/coverage/cover_reg_top/9.i2c_intr_test.2832319876 Jul 02 08:03:02 AM PDT 24 Jul 02 08:03:18 AM PDT 24 37541896 ps
T1622 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.296918740 Jul 02 08:02:56 AM PDT 24 Jul 02 08:03:14 AM PDT 24 227339487 ps
T1623 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1296907807 Jul 02 08:02:52 AM PDT 24 Jul 02 08:03:16 AM PDT 24 362760258 ps
T1624 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.696204964 Jul 02 08:02:45 AM PDT 24 Jul 02 08:03:04 AM PDT 24 29814417 ps
T193 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1480180981 Jul 02 08:03:13 AM PDT 24 Jul 02 08:03:28 AM PDT 24 147893670 ps
T1625 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3445825185 Jul 02 08:03:11 AM PDT 24 Jul 02 08:03:26 AM PDT 24 27010271 ps
T1626 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1100162773 Jul 02 08:03:11 AM PDT 24 Jul 02 08:03:27 AM PDT 24 712109191 ps
T1627 /workspace/coverage/cover_reg_top/34.i2c_intr_test.292078123 Jul 02 08:03:11 AM PDT 24 Jul 02 08:03:26 AM PDT 24 54086513 ps
T1628 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1767803092 Jul 02 08:03:06 AM PDT 24 Jul 02 08:03:22 AM PDT 24 42711620 ps
T1629 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3947676440 Jul 02 08:02:52 AM PDT 24 Jul 02 08:03:11 AM PDT 24 23134707 ps
T1630 /workspace/coverage/cover_reg_top/11.i2c_intr_test.523905607 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:20 AM PDT 24 51567363 ps
T1631 /workspace/coverage/cover_reg_top/38.i2c_intr_test.410337190 Jul 02 08:03:14 AM PDT 24 Jul 02 08:03:28 AM PDT 24 17488399 ps
T1632 /workspace/coverage/cover_reg_top/22.i2c_intr_test.4001563913 Jul 02 08:03:13 AM PDT 24 Jul 02 08:03:27 AM PDT 24 16852953 ps
T1633 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2003529840 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:21 AM PDT 24 544716898 ps
T194 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4220465410 Jul 02 08:03:15 AM PDT 24 Jul 02 08:03:30 AM PDT 24 255615312 ps
T228 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3010246134 Jul 02 08:02:58 AM PDT 24 Jul 02 08:03:16 AM PDT 24 28035011 ps
T1634 /workspace/coverage/cover_reg_top/26.i2c_intr_test.2238950315 Jul 02 08:03:14 AM PDT 24 Jul 02 08:03:28 AM PDT 24 16046994 ps
T1635 /workspace/coverage/cover_reg_top/10.i2c_intr_test.4032256629 Jul 02 08:02:58 AM PDT 24 Jul 02 08:03:16 AM PDT 24 17945634 ps
T1636 /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3290621896 Jul 02 08:03:03 AM PDT 24 Jul 02 08:03:20 AM PDT 24 192910934 ps
T1637 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2395411716 Jul 02 08:02:46 AM PDT 24 Jul 02 08:03:03 AM PDT 24 15786985 ps
T1638 /workspace/coverage/cover_reg_top/3.i2c_intr_test.3469610433 Jul 02 08:02:55 AM PDT 24 Jul 02 08:03:14 AM PDT 24 41352423 ps
T1639 /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3889693542 Jul 02 08:03:11 AM PDT 24 Jul 02 08:03:26 AM PDT 24 449275749 ps
T1640 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1318343245 Jul 02 08:02:58 AM PDT 24 Jul 02 08:03:17 AM PDT 24 235428459 ps
T1641 /workspace/coverage/cover_reg_top/28.i2c_intr_test.3038722791 Jul 02 08:03:15 AM PDT 24 Jul 02 08:03:29 AM PDT 24 15317174 ps
T1642 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4222337381 Jul 02 08:03:05 AM PDT 24 Jul 02 08:03:21 AM PDT 24 49643367 ps
T1643 /workspace/coverage/cover_reg_top/4.i2c_intr_test.3455740472 Jul 02 08:02:58 AM PDT 24 Jul 02 08:03:16 AM PDT 24 17603115 ps
T229 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3867503869 Jul 02 08:02:51 AM PDT 24 Jul 02 08:03:09 AM PDT 24 26611762 ps
T1644 /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3136350815 Jul 02 08:03:01 AM PDT 24 Jul 02 08:03:19 AM PDT 24 201449873 ps
T196 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3773062379 Jul 02 08:02:56 AM PDT 24 Jul 02 08:03:15 AM PDT 24 66039483 ps
T1645 /workspace/coverage/cover_reg_top/23.i2c_intr_test.394123923 Jul 02 08:03:09 AM PDT 24 Jul 02 08:03:25 AM PDT 24 108589784 ps
T230 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3146301967 Jul 02 08:03:01 AM PDT 24 Jul 02 08:03:17 AM PDT 24 44855315 ps

Test location /workspace/coverage/default/34.i2c_host_stress_all.1013586423
Short name T9
Test name
Test status
Simulation time 7609895376 ps
CPU time 211.63 seconds
Started Jul 02 08:12:41 AM PDT 24
Finished Jul 02 08:16:14 AM PDT 24
Peak memory 922844 kb
Host smart-7941ff1f-5b38-4564-a7db-79b7135f50bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013586423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.1013586423
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.383659881
Short name T27
Test name
Test status
Simulation time 4991455805 ps
CPU time 6.47 seconds
Started Jul 02 08:13:11 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 204968 kb
Host smart-e4fa2d85-723c-4089-87aa-1c1deb90857f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383659881 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.383659881
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.2122620854
Short name T15
Test name
Test status
Simulation time 2375610552 ps
CPU time 12.03 seconds
Started Jul 02 08:08:55 AM PDT 24
Finished Jul 02 08:09:13 AM PDT 24
Peak memory 213528 kb
Host smart-2788710f-4a67-4977-9493-8c4e829327a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122620854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.2122620854
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2644922767
Short name T90
Test name
Test status
Simulation time 588785527 ps
CPU time 2.06 seconds
Started Jul 02 08:03:02 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204580 kb
Host smart-b152e9c5-dca2-4f92-b942-0ac4b58afc66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644922767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2644922767
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1285553761
Short name T17
Test name
Test status
Simulation time 44551457182 ps
CPU time 268.27 seconds
Started Jul 02 08:10:26 AM PDT 24
Finished Jul 02 08:14:57 AM PDT 24
Peak memory 3028072 kb
Host smart-8c12534e-80da-41c7-8492-dca352eee99c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285553761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1285553761
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_host_override.2988199856
Short name T130
Test name
Test status
Simulation time 20584533 ps
CPU time 0.67 seconds
Started Jul 02 08:09:22 AM PDT 24
Finished Jul 02 08:09:25 AM PDT 24
Peak memory 204504 kb
Host smart-52046387-835a-42a9-acab-49d7bd6475b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988199856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2988199856
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.870038241
Short name T38
Test name
Test status
Simulation time 2418020219 ps
CPU time 7.57 seconds
Started Jul 02 08:13:01 AM PDT 24
Finished Jul 02 08:13:10 AM PDT 24
Peak memory 204884 kb
Host smart-d210279a-ba47-4c20-891b-58185e6053ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870038241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.870038241
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.111305662
Short name T50
Test name
Test status
Simulation time 120893099903 ps
CPU time 1719.21 seconds
Started Jul 02 08:12:07 AM PDT 24
Finished Jul 02 08:40:49 AM PDT 24
Peak memory 2743588 kb
Host smart-6f082bc5-c250-4fa6-ae8a-08500be12370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111305662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.111305662
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.2496825460
Short name T175
Test name
Test status
Simulation time 197507791 ps
CPU time 0.82 seconds
Started Jul 02 08:09:08 AM PDT 24
Finished Jul 02 08:09:12 AM PDT 24
Peak memory 222204 kb
Host smart-3e05e69f-256a-4446-9f34-67daecc9c845
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496825460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.2496825460
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.1209594157
Short name T145
Test name
Test status
Simulation time 439472305 ps
CPU time 1.38 seconds
Started Jul 02 08:11:50 AM PDT 24
Finished Jul 02 08:11:53 AM PDT 24
Peak memory 204788 kb
Host smart-7e82a42e-b253-4e8f-8132-007c0750771a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209594157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.1209594157
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.2058891257
Short name T174
Test name
Test status
Simulation time 117607828 ps
CPU time 2.48 seconds
Started Jul 02 08:02:53 AM PDT 24
Finished Jul 02 08:03:13 AM PDT 24
Peak memory 204504 kb
Host smart-837ff83e-b329-4bf3-abd8-e7c1a9975d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058891257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.2058891257
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.4204267389
Short name T88
Test name
Test status
Simulation time 194047467 ps
CPU time 0.86 seconds
Started Jul 02 08:03:00 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 204384 kb
Host smart-28294407-a1b6-44c5-a673-2a4564f53215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204267389 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.4204267389
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.927981748
Short name T281
Test name
Test status
Simulation time 11428801613 ps
CPU time 720.26 seconds
Started Jul 02 08:11:04 AM PDT 24
Finished Jul 02 08:23:07 AM PDT 24
Peak memory 1743588 kb
Host smart-400f42a0-8a1a-4e99-8fea-e2f5bbd86a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927981748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.927981748
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.2692951822
Short name T19
Test name
Test status
Simulation time 295022451 ps
CPU time 4.17 seconds
Started Jul 02 08:12:57 AM PDT 24
Finished Jul 02 08:13:02 AM PDT 24
Peak memory 204836 kb
Host smart-8c8dc712-dd18-4266-bf79-89c867b65790
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692951822 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.2692951822
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1199618369
Short name T11
Test name
Test status
Simulation time 1007857939 ps
CPU time 4.75 seconds
Started Jul 02 08:10:13 AM PDT 24
Finished Jul 02 08:10:20 AM PDT 24
Peak memory 213032 kb
Host smart-f4173bba-773a-47c4-aae3-cfdb17b4afaf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199618369 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1199618369
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.2302221647
Short name T67
Test name
Test status
Simulation time 25280586189 ps
CPU time 200.2 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:12:22 AM PDT 24
Peak memory 1321560 kb
Host smart-34080c4e-d5c3-4420-b18b-306216633d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302221647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.2302221647
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.620041045
Short name T52
Test name
Test status
Simulation time 109342086 ps
CPU time 1.11 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:12:28 AM PDT 24
Peak memory 204668 kb
Host smart-32fde696-c5d1-4b6b-8a08-b1d123115962
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620041045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_fm
t.620041045
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.1136720466
Short name T164
Test name
Test status
Simulation time 2892869391 ps
CPU time 11.03 seconds
Started Jul 02 08:11:45 AM PDT 24
Finished Jul 02 08:11:57 AM PDT 24
Peak memory 204836 kb
Host smart-bbc319b3-8b33-412c-bee8-69c117767f6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136720466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.1136720466
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.589927803
Short name T35
Test name
Test status
Simulation time 21930104223 ps
CPU time 847.67 seconds
Started Jul 02 08:14:28 AM PDT 24
Finished Jul 02 08:28:37 AM PDT 24
Peak memory 1049348 kb
Host smart-e0e785de-f371-4456-a170-9f973b3f988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589927803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.589927803
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_alert_test.1924178390
Short name T7
Test name
Test status
Simulation time 19872541 ps
CPU time 0.64 seconds
Started Jul 02 08:12:29 AM PDT 24
Finished Jul 02 08:12:32 AM PDT 24
Peak memory 204468 kb
Host smart-87cfc2f9-e341-4117-85c7-5daa650dbc6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924178390 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.1924178390
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.217639250
Short name T32
Test name
Test status
Simulation time 25245187217 ps
CPU time 105.72 seconds
Started Jul 02 08:11:53 AM PDT 24
Finished Jul 02 08:13:40 AM PDT 24
Peak memory 464312 kb
Host smart-a75bc11b-92e3-4c3e-a9a7-7e59c84aaef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217639250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.217639250
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.4246000559
Short name T49
Test name
Test status
Simulation time 36430285017 ps
CPU time 289.01 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:17:56 AM PDT 24
Peak memory 1654756 kb
Host smart-ef946b60-61ec-4adc-9db3-527a989f1fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246000559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.4246000559
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.804598685
Short name T241
Test name
Test status
Simulation time 512191512 ps
CPU time 7.36 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:09:09 AM PDT 24
Peak memory 204804 kb
Host smart-7099b802-7b8c-427e-a3c8-8e45bf679561
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804598685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.804598685
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_stress_all.1863762308
Short name T69
Test name
Test status
Simulation time 89264874371 ps
CPU time 2266.85 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:51:17 AM PDT 24
Peak memory 3142616 kb
Host smart-46d69037-6f75-4775-8344-5c06a1360267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863762308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stress_all.1863762308
Directory /workspace/40.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.4148267932
Short name T206
Test name
Test status
Simulation time 10532888221 ps
CPU time 68.83 seconds
Started Jul 02 08:09:32 AM PDT 24
Finished Jul 02 08:10:45 AM PDT 24
Peak memory 464128 kb
Host smart-e83f44ab-18ed-4a57-a7e3-2c24d33a0dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148267932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.4148267932
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.1220329081
Short name T176
Test name
Test status
Simulation time 44342768 ps
CPU time 0.95 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:09:03 AM PDT 24
Peak memory 222204 kb
Host smart-a5400d89-8f82-47f4-afc5-4efbaafee5d1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220329081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.1220329081
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3167446894
Short name T201
Test name
Test status
Simulation time 489778304 ps
CPU time 2.22 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204504 kb
Host smart-195003dc-48de-40a4-81b6-c9cdc6b60d1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167446894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3167446894
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.3926786431
Short name T271
Test name
Test status
Simulation time 56951247308 ps
CPU time 661.43 seconds
Started Jul 02 08:10:12 AM PDT 24
Finished Jul 02 08:21:16 AM PDT 24
Peak memory 3240988 kb
Host smart-f64ab52a-2522-4ecd-bf69-821d37767564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926786431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.3926786431
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.2672004964
Short name T611
Test name
Test status
Simulation time 380763009 ps
CPU time 0.93 seconds
Started Jul 02 08:10:04 AM PDT 24
Finished Jul 02 08:10:06 AM PDT 24
Peak memory 204440 kb
Host smart-6ca2af59-74b1-4fac-89b8-e1e125cf6985
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672004964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.2672004964
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.2907813938
Short name T34
Test name
Test status
Simulation time 3873170652 ps
CPU time 45.94 seconds
Started Jul 02 08:10:14 AM PDT 24
Finished Jul 02 08:11:03 AM PDT 24
Peak memory 311032 kb
Host smart-5d97a9a5-decb-47e9-a82b-003616d68e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907813938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.2907813938
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.3715804807
Short name T246
Test name
Test status
Simulation time 349865901 ps
CPU time 1.1 seconds
Started Jul 02 08:10:12 AM PDT 24
Finished Jul 02 08:10:15 AM PDT 24
Peak memory 204428 kb
Host smart-9bba7971-2869-458c-8222-8092f47a6dc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715804807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.3715804807
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.3230382224
Short name T238
Test name
Test status
Simulation time 133399940 ps
CPU time 0.86 seconds
Started Jul 02 08:10:47 AM PDT 24
Finished Jul 02 08:10:53 AM PDT 24
Peak memory 204608 kb
Host smart-46b68015-cd44-4378-ad83-54d5779848d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230382224 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.3230382224
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.1527588020
Short name T265
Test name
Test status
Simulation time 580519749 ps
CPU time 2.81 seconds
Started Jul 02 08:09:09 AM PDT 24
Finished Jul 02 08:09:15 AM PDT 24
Peak memory 204820 kb
Host smart-0869ac6b-8428-414c-ae91-e110853e0856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527588020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.1527588020
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.332154685
Short name T269
Test name
Test status
Simulation time 3003210219 ps
CPU time 2.92 seconds
Started Jul 02 08:09:09 AM PDT 24
Finished Jul 02 08:09:14 AM PDT 24
Peak memory 204832 kb
Host smart-bb26680a-f78e-4ad0-98e7-7033de1bbaf8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332154685 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.i2c_target_hrst.332154685
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_host_override.847114354
Short name T251
Test name
Test status
Simulation time 48670042 ps
CPU time 0.65 seconds
Started Jul 02 08:11:14 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 204480 kb
Host smart-a4d2907d-74d2-45c7-b568-62bdae70e347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847114354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.847114354
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.4104432475
Short name T4
Test name
Test status
Simulation time 35225703318 ps
CPU time 206.5 seconds
Started Jul 02 08:13:48 AM PDT 24
Finished Jul 02 08:17:16 AM PDT 24
Peak memory 1800648 kb
Host smart-b61da05d-49d0-4001-8d63-9ccfb05bf484
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104432475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.4104432475
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3774496854
Short name T58
Test name
Test status
Simulation time 1378203587 ps
CPU time 22.53 seconds
Started Jul 02 08:11:32 AM PDT 24
Finished Jul 02 08:11:56 AM PDT 24
Peak memory 350736 kb
Host smart-04813312-42eb-4d74-9d53-a1671c084eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774496854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3774496854
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.698900810
Short name T1305
Test name
Test status
Simulation time 212048120 ps
CPU time 1.32 seconds
Started Jul 02 08:10:14 AM PDT 24
Finished Jul 02 08:10:18 AM PDT 24
Peak memory 204632 kb
Host smart-c2a0a519-aba8-4d23-a1c1-d9e7b36a8866
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698900810 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.698900810
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.3770398002
Short name T188
Test name
Test status
Simulation time 99092768 ps
CPU time 1.51 seconds
Started Jul 02 08:02:58 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 204564 kb
Host smart-09099335-d85f-458a-b885-d4c1235739be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770398002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.3770398002
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.3435664136
Short name T47
Test name
Test status
Simulation time 16969843738 ps
CPU time 670.81 seconds
Started Jul 02 08:10:20 AM PDT 24
Finished Jul 02 08:21:32 AM PDT 24
Peak memory 1468812 kb
Host smart-e21e0768-54c2-43ce-99ad-4a82d043681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435664136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.3435664136
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.487060780
Short name T272
Test name
Test status
Simulation time 15356002159 ps
CPU time 15.65 seconds
Started Jul 02 08:11:40 AM PDT 24
Finished Jul 02 08:11:59 AM PDT 24
Peak memory 217912 kb
Host smart-78b1c2a7-8577-4091-a735-396846a534fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487060780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.487060780
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.1867618568
Short name T289
Test name
Test status
Simulation time 6487932921 ps
CPU time 17.55 seconds
Started Jul 02 08:13:49 AM PDT 24
Finished Jul 02 08:14:08 AM PDT 24
Peak memory 204896 kb
Host smart-7345edeb-6fd8-4545-a92d-6cfa1308cb74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867618568 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_ta
rget_smoke.1867618568
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.744526655
Short name T195
Test name
Test status
Simulation time 130710272 ps
CPU time 2.18 seconds
Started Jul 02 08:02:59 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204452 kb
Host smart-25178a73-7229-4f9b-be08-a110d9a3b510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744526655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.744526655
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.1245671612
Short name T199
Test name
Test status
Simulation time 121503643 ps
CPU time 2.24 seconds
Started Jul 02 08:02:45 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 204712 kb
Host smart-62f2facd-8604-485c-9daa-fc9756363bab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245671612 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.1245671612
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1575363695
Short name T190
Test name
Test status
Simulation time 47872867 ps
CPU time 2.37 seconds
Started Jul 02 08:02:46 AM PDT 24
Finished Jul 02 08:03:05 AM PDT 24
Peak memory 204632 kb
Host smart-dab255cd-8d8c-46fa-9c17-3e67c0c6a98c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575363695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1575363695
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2633435285
Short name T192
Test name
Test status
Simulation time 684722814 ps
CPU time 2.26 seconds
Started Jul 02 08:02:56 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 204448 kb
Host smart-6fd763df-cbc1-4794-8335-17dd991c10a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633435285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2633435285
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.484088462
Short name T446
Test name
Test status
Simulation time 512600918 ps
CPU time 8.92 seconds
Started Jul 02 08:10:39 AM PDT 24
Finished Jul 02 08:10:50 AM PDT 24
Peak memory 231364 kb
Host smart-48694dad-5d2c-4903-9f52-19320c4fb6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484088462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.484088462
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3296985416
Short name T63
Test name
Test status
Simulation time 3590727186 ps
CPU time 43.16 seconds
Started Jul 02 08:12:58 AM PDT 24
Finished Jul 02 08:13:43 AM PDT 24
Peak memory 519736 kb
Host smart-a0a55fd2-b178-4f75-ae81-df25db1458c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296985416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3296985416
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.290559980
Short name T227
Test name
Test status
Simulation time 94747508 ps
CPU time 1.92 seconds
Started Jul 02 08:02:44 AM PDT 24
Finished Jul 02 08:03:03 AM PDT 24
Peak memory 204492 kb
Host smart-878c68e8-961e-49f4-8f61-e8369856e9e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290559980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.290559980
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.3567621026
Short name T219
Test name
Test status
Simulation time 2593107840 ps
CPU time 5.15 seconds
Started Jul 02 08:02:50 AM PDT 24
Finished Jul 02 08:03:13 AM PDT 24
Peak memory 204588 kb
Host smart-2419a9bb-adb4-47ce-a23b-2a44bf0dcf6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567621026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.3567621026
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2395411716
Short name T1637
Test name
Test status
Simulation time 15786985 ps
CPU time 0.8 seconds
Started Jul 02 08:02:46 AM PDT 24
Finished Jul 02 08:03:03 AM PDT 24
Peak memory 204416 kb
Host smart-d3dee4f0-d94d-46cf-aa8e-db76ef86c94d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395411716 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2395411716
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.3847550038
Short name T91
Test name
Test status
Simulation time 28510583 ps
CPU time 0.86 seconds
Started Jul 02 08:02:58 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 204460 kb
Host smart-e3610d40-d10a-4e8b-bde2-61e51e68694d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847550038 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.3847550038
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.1425901131
Short name T226
Test name
Test status
Simulation time 18310570 ps
CPU time 0.77 seconds
Started Jul 02 08:02:47 AM PDT 24
Finished Jul 02 08:03:05 AM PDT 24
Peak memory 204424 kb
Host smart-a42cc168-b67d-4f8c-92aa-244242312d59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425901131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.1425901131
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.1767467280
Short name T1558
Test name
Test status
Simulation time 15426030 ps
CPU time 0.65 seconds
Started Jul 02 08:02:41 AM PDT 24
Finished Jul 02 08:02:58 AM PDT 24
Peak memory 204320 kb
Host smart-36433e30-9d50-470a-b96e-d94c4484a77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767467280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.1767467280
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3256896874
Short name T97
Test name
Test status
Simulation time 116259748 ps
CPU time 1.15 seconds
Started Jul 02 08:02:53 AM PDT 24
Finished Jul 02 08:03:12 AM PDT 24
Peak memory 204584 kb
Host smart-8a1b8805-79ae-45ea-9bf0-4aff669f613d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256896874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3256896874
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.570956156
Short name T200
Test name
Test status
Simulation time 152784185 ps
CPU time 1.38 seconds
Started Jul 02 08:02:46 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 204584 kb
Host smart-a8a2f7af-999c-40b3-a819-7cb712f86632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570956156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.570956156
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.235539577
Short name T1551
Test name
Test status
Simulation time 99195882 ps
CPU time 1.83 seconds
Started Jul 02 08:02:54 AM PDT 24
Finished Jul 02 08:03:14 AM PDT 24
Peak memory 204576 kb
Host smart-cbd7326a-15ec-4baa-a2d9-e4f2f76e9cad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235539577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.235539577
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.1255712433
Short name T1600
Test name
Test status
Simulation time 217800371 ps
CPU time 2.53 seconds
Started Jul 02 08:02:49 AM PDT 24
Finished Jul 02 08:03:09 AM PDT 24
Peak memory 204476 kb
Host smart-5b7f53d6-9271-4e40-892d-bdd59a36b581
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255712433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.1255712433
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.4085694914
Short name T217
Test name
Test status
Simulation time 23821542 ps
CPU time 0.75 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204424 kb
Host smart-31be39bf-66ae-4d8e-b4ff-b3c196d3528f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085694914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.4085694914
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.696204964
Short name T1624
Test name
Test status
Simulation time 29814417 ps
CPU time 1.34 seconds
Started Jul 02 08:02:45 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 220968 kb
Host smart-5b50a7a7-b8e7-446c-a479-43d2e527ccd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696204964 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.696204964
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.1547598859
Short name T1566
Test name
Test status
Simulation time 18830501 ps
CPU time 0.74 seconds
Started Jul 02 08:02:51 AM PDT 24
Finished Jul 02 08:03:10 AM PDT 24
Peak memory 204456 kb
Host smart-d6d0367b-17f7-41fd-92e0-970811d7e5e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547598859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.1547598859
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.1328129264
Short name T1588
Test name
Test status
Simulation time 45382314 ps
CPU time 0.66 seconds
Started Jul 02 08:02:52 AM PDT 24
Finished Jul 02 08:03:11 AM PDT 24
Peak memory 204360 kb
Host smart-9ab3d327-caf8-4383-bfdb-84adad91ca3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328129264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.1328129264
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2480941868
Short name T1555
Test name
Test status
Simulation time 61427084 ps
CPU time 0.89 seconds
Started Jul 02 08:02:50 AM PDT 24
Finished Jul 02 08:03:09 AM PDT 24
Peak memory 204436 kb
Host smart-279afe42-465b-4d24-8e01-87b1da2aec3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480941868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.2480941868
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.2972361996
Short name T1571
Test name
Test status
Simulation time 88588238 ps
CPU time 2.15 seconds
Started Jul 02 08:02:50 AM PDT 24
Finished Jul 02 08:03:10 AM PDT 24
Peak memory 204624 kb
Host smart-3a4ec227-7316-4504-ab8b-cc0bbff610c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972361996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.2972361996
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.726031038
Short name T1586
Test name
Test status
Simulation time 24088762 ps
CPU time 0.91 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204392 kb
Host smart-49843121-44da-46b4-8bc1-1e7f39209fb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726031038 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.726031038
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.780235992
Short name T225
Test name
Test status
Simulation time 66635461 ps
CPU time 0.73 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:19 AM PDT 24
Peak memory 204400 kb
Host smart-7e4a3108-33b4-4d3b-9e30-b01d2251624a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780235992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.780235992
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.4032256629
Short name T1635
Test name
Test status
Simulation time 17945634 ps
CPU time 0.71 seconds
Started Jul 02 08:02:58 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 204332 kb
Host smart-b7ac96fe-281d-4dfb-abfe-27c49820288d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032256629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.4032256629
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.498464089
Short name T1596
Test name
Test status
Simulation time 248785871 ps
CPU time 1.16 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204604 kb
Host smart-ddede67c-b85a-4c73-b5d2-1357ec4a2934
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498464089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_ou
tstanding.498464089
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1318343245
Short name T1640
Test name
Test status
Simulation time 235428459 ps
CPU time 2.19 seconds
Started Jul 02 08:02:58 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 204504 kb
Host smart-13f87c3c-9df7-43b6-84e5-e299989fb2d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318343245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1318343245
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.3290621896
Short name T1636
Test name
Test status
Simulation time 192910934 ps
CPU time 0.83 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204512 kb
Host smart-4d76a52d-fb97-4ca8-8358-382f178dca60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290621896 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.3290621896
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.2123937808
Short name T218
Test name
Test status
Simulation time 59952303 ps
CPU time 0.72 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204468 kb
Host smart-abaab53a-a298-4c27-b499-3edff9f83a38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123937808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.2123937808
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.523905607
Short name T1630
Test name
Test status
Simulation time 51567363 ps
CPU time 0.74 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204360 kb
Host smart-fc04a7de-6f44-4ddb-87a6-6f9e24ac2013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523905607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.523905607
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.1144147564
Short name T191
Test name
Test status
Simulation time 66391445 ps
CPU time 1.08 seconds
Started Jul 02 08:03:06 AM PDT 24
Finished Jul 02 08:03:22 AM PDT 24
Peak memory 204644 kb
Host smart-c6138fa6-6439-45c3-9d51-acb82b1a4b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144147564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.1144147564
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.741650104
Short name T94
Test name
Test status
Simulation time 303169045 ps
CPU time 1.45 seconds
Started Jul 02 08:03:00 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204532 kb
Host smart-ffd2ae34-843e-4851-ac72-403a5446a6f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741650104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.741650104
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1655397910
Short name T203
Test name
Test status
Simulation time 103273178 ps
CPU time 1.29 seconds
Started Jul 02 08:03:00 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 220180 kb
Host smart-b4a373f5-874e-404d-9ec4-f43421e57c67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655397910 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1655397910
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.3146301967
Short name T230
Test name
Test status
Simulation time 44855315 ps
CPU time 0.76 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 204452 kb
Host smart-ae5ccf81-ce00-4e35-b395-2b2b748497d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146301967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.3146301967
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.1937639498
Short name T1540
Test name
Test status
Simulation time 27682066 ps
CPU time 0.68 seconds
Started Jul 02 08:03:09 AM PDT 24
Finished Jul 02 08:03:25 AM PDT 24
Peak memory 204368 kb
Host smart-802d0624-194a-467c-adfb-9b4699d45ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937639498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.1937639498
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.2274607468
Short name T235
Test name
Test status
Simulation time 32109951 ps
CPU time 0.85 seconds
Started Jul 02 08:03:16 AM PDT 24
Finished Jul 02 08:03:30 AM PDT 24
Peak memory 204396 kb
Host smart-e2913e51-47d1-4094-9acd-b03563324cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274607468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.2274607468
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.1015906219
Short name T1584
Test name
Test status
Simulation time 191660068 ps
CPU time 2.25 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204548 kb
Host smart-3d2a2724-b416-4c1b-8545-6e0e1bbc5dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015906219 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.1015906219
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.1976614779
Short name T1605
Test name
Test status
Simulation time 96205785 ps
CPU time 1.47 seconds
Started Jul 02 08:03:07 AM PDT 24
Finished Jul 02 08:03:23 AM PDT 24
Peak memory 204588 kb
Host smart-6dea3e4a-a314-4ef4-b6b9-450448510abc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976614779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.1976614779
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.3509725758
Short name T1601
Test name
Test status
Simulation time 37157030 ps
CPU time 1.53 seconds
Started Jul 02 08:02:57 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 212936 kb
Host smart-a6edc41f-be24-45cf-ad47-e69d6d50da5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509725758 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.3509725758
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.1931186629
Short name T1611
Test name
Test status
Simulation time 81029849 ps
CPU time 0.74 seconds
Started Jul 02 08:03:10 AM PDT 24
Finished Jul 02 08:03:25 AM PDT 24
Peak memory 204424 kb
Host smart-c6bc2f96-b363-4abe-a793-87cbfa0ea8d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931186629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.1931186629
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.2644075836
Short name T1544
Test name
Test status
Simulation time 29893776 ps
CPU time 0.63 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204312 kb
Host smart-0098b6d9-48d5-4a81-a74a-ad2a512ed014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644075836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.2644075836
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1082730796
Short name T1595
Test name
Test status
Simulation time 172528700 ps
CPU time 0.83 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204648 kb
Host smart-2b8fa5b8-1fba-4573-94ec-440924774393
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082730796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1082730796
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.1685749089
Short name T1612
Test name
Test status
Simulation time 30543534 ps
CPU time 1.6 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204580 kb
Host smart-2b38c6ae-573e-4d3e-b67d-32c139816880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685749089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.1685749089
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.3445825185
Short name T1625
Test name
Test status
Simulation time 27010271 ps
CPU time 1.17 seconds
Started Jul 02 08:03:11 AM PDT 24
Finished Jul 02 08:03:26 AM PDT 24
Peak memory 204628 kb
Host smart-7e3e9113-6a65-4722-8b86-560a194801d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445825185 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.3445825185
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.2271892648
Short name T216
Test name
Test status
Simulation time 19081467 ps
CPU time 0.78 seconds
Started Jul 02 08:03:10 AM PDT 24
Finished Jul 02 08:03:25 AM PDT 24
Peak memory 204436 kb
Host smart-06eef6da-6e83-4b8f-950d-9d4c8fe7bc42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271892648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.2271892648
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.909158064
Short name T1576
Test name
Test status
Simulation time 15093759 ps
CPU time 0.65 seconds
Started Jul 02 08:03:10 AM PDT 24
Finished Jul 02 08:03:25 AM PDT 24
Peak memory 204360 kb
Host smart-7b991b1e-71dc-4637-b1e3-d26a5042a615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909158064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.909158064
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2815714529
Short name T233
Test name
Test status
Simulation time 36163245 ps
CPU time 1.06 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204484 kb
Host smart-691edfa1-f015-47c5-b283-004e6d3b07bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815714529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2815714529
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3097612340
Short name T173
Test name
Test status
Simulation time 58727909 ps
CPU time 1.4 seconds
Started Jul 02 08:03:04 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204572 kb
Host smart-a3f46719-5391-4562-b260-ee69d8290fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097612340 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3097612340
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.3136350815
Short name T1644
Test name
Test status
Simulation time 201449873 ps
CPU time 1.06 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:19 AM PDT 24
Peak memory 220196 kb
Host smart-983ea4e2-aac2-4f0f-b3d6-e76a0332ffbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136350815 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.3136350815
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.2274462666
Short name T1562
Test name
Test status
Simulation time 19227383 ps
CPU time 0.77 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204360 kb
Host smart-8ea7ba9b-2358-4670-99e3-c9d4590aac20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274462666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.2274462666
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.1661523071
Short name T1604
Test name
Test status
Simulation time 23585635 ps
CPU time 0.64 seconds
Started Jul 02 08:03:12 AM PDT 24
Finished Jul 02 08:03:26 AM PDT 24
Peak memory 204328 kb
Host smart-4ae5bca9-7d98-4850-89b0-d24d0193d309
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661523071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.1661523071
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_same_csr_outstanding.926693660
Short name T1591
Test name
Test status
Simulation time 44190681 ps
CPU time 0.87 seconds
Started Jul 02 08:03:00 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 204396 kb
Host smart-e63b1174-dc74-40a3-b32e-f24942c825a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926693660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_same_csr_ou
tstanding.926693660
Directory /workspace/15.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.1767803092
Short name T1628
Test name
Test status
Simulation time 42711620 ps
CPU time 1.3 seconds
Started Jul 02 08:03:06 AM PDT 24
Finished Jul 02 08:03:22 AM PDT 24
Peak memory 204560 kb
Host smart-07da1de1-7d87-4ffe-a677-83a560d58b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767803092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.1767803092
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.1873995365
Short name T267
Test name
Test status
Simulation time 138457971 ps
CPU time 1.33 seconds
Started Jul 02 08:03:10 AM PDT 24
Finished Jul 02 08:03:26 AM PDT 24
Peak memory 204472 kb
Host smart-381cc06a-21da-4cc9-b206-39b46b75c2db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873995365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.1873995365
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.3853696363
Short name T211
Test name
Test status
Simulation time 35408886 ps
CPU time 1 seconds
Started Jul 02 08:03:07 AM PDT 24
Finished Jul 02 08:03:23 AM PDT 24
Peak memory 204496 kb
Host smart-297e16dd-0989-48e7-8fcb-d44f61c2ec6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853696363 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.3853696363
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.1373258781
Short name T1552
Test name
Test status
Simulation time 80589223 ps
CPU time 0.72 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204388 kb
Host smart-475f58f8-3f1d-4bbb-bead-d69dd08573a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373258781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.1373258781
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.1649891623
Short name T1556
Test name
Test status
Simulation time 29791157 ps
CPU time 0.73 seconds
Started Jul 02 08:03:09 AM PDT 24
Finished Jul 02 08:03:23 AM PDT 24
Peak memory 204308 kb
Host smart-ef627d0c-d2fd-4c1e-afe0-28e48faf7691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649891623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.1649891623
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.3889693542
Short name T1639
Test name
Test status
Simulation time 449275749 ps
CPU time 1.12 seconds
Started Jul 02 08:03:11 AM PDT 24
Finished Jul 02 08:03:26 AM PDT 24
Peak memory 204516 kb
Host smart-512c0fd8-f727-4b37-a466-f63dfebc15df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889693542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.3889693542
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1100162773
Short name T1626
Test name
Test status
Simulation time 712109191 ps
CPU time 2.08 seconds
Started Jul 02 08:03:11 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204600 kb
Host smart-6464dfb8-9ab5-492b-8e5c-0ac853aeae37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100162773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1100162773
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1803999275
Short name T198
Test name
Test status
Simulation time 84373651 ps
CPU time 2.08 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204536 kb
Host smart-9f2a75b6-1a41-4559-ba37-0ccd0ab8f677
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803999275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1803999275
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.809246593
Short name T212
Test name
Test status
Simulation time 30148914 ps
CPU time 1.41 seconds
Started Jul 02 08:03:06 AM PDT 24
Finished Jul 02 08:03:22 AM PDT 24
Peak memory 212800 kb
Host smart-982c276a-98f2-4310-aea1-551ccef52a83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809246593 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.809246593
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.2030745528
Short name T221
Test name
Test status
Simulation time 45053739 ps
CPU time 0.8 seconds
Started Jul 02 08:03:06 AM PDT 24
Finished Jul 02 08:03:22 AM PDT 24
Peak memory 204380 kb
Host smart-bceaf39b-86fe-481f-b292-fbd27ca7d75a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030745528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.2030745528
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.843512658
Short name T1608
Test name
Test status
Simulation time 33015024 ps
CPU time 0.7 seconds
Started Jul 02 08:03:10 AM PDT 24
Finished Jul 02 08:03:25 AM PDT 24
Peak memory 204356 kb
Host smart-94ea6cb0-b927-4d35-9aed-02ed847ac042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843512658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.843512658
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.741067945
Short name T1614
Test name
Test status
Simulation time 161346352 ps
CPU time 0.88 seconds
Started Jul 02 08:03:09 AM PDT 24
Finished Jul 02 08:03:23 AM PDT 24
Peak memory 204384 kb
Host smart-859d0791-524a-4944-a26b-8c8a02d21e9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741067945 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_ou
tstanding.741067945
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.2003529840
Short name T1633
Test name
Test status
Simulation time 544716898 ps
CPU time 2.02 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204636 kb
Host smart-e0d276e5-a48d-47c0-8bac-f589beb7d973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003529840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.2003529840
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.343829958
Short name T204
Test name
Test status
Simulation time 147069315 ps
CPU time 1.46 seconds
Started Jul 02 08:03:06 AM PDT 24
Finished Jul 02 08:03:23 AM PDT 24
Peak memory 204504 kb
Host smart-09979171-2fdd-49cb-b57d-b52bbf38309a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343829958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.343829958
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.4063550139
Short name T1606
Test name
Test status
Simulation time 34536096 ps
CPU time 1.5 seconds
Started Jul 02 08:03:16 AM PDT 24
Finished Jul 02 08:03:33 AM PDT 24
Peak memory 204620 kb
Host smart-14ab5731-e464-4c64-bd4e-103e0c8bf714
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063550139 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.4063550139
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.325721833
Short name T220
Test name
Test status
Simulation time 70297108 ps
CPU time 0.74 seconds
Started Jul 02 08:03:14 AM PDT 24
Finished Jul 02 08:03:28 AM PDT 24
Peak memory 204432 kb
Host smart-937903d2-7d04-47a0-962b-e38c9ff4ad3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325721833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.325721833
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1703965333
Short name T1598
Test name
Test status
Simulation time 52885301 ps
CPU time 0.67 seconds
Started Jul 02 08:03:12 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204372 kb
Host smart-90c54539-6b9a-46a1-aa50-0e59e0802803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703965333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1703965333
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.1627675584
Short name T232
Test name
Test status
Simulation time 21852102 ps
CPU time 0.87 seconds
Started Jul 02 08:03:11 AM PDT 24
Finished Jul 02 08:03:26 AM PDT 24
Peak memory 204384 kb
Host smart-2d2756dd-ae54-4af4-bb13-a5826e8e3309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627675584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.1627675584
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.2559656564
Short name T1603
Test name
Test status
Simulation time 115810451 ps
CPU time 2.6 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 212764 kb
Host smart-16517c5b-f5e5-41cf-8342-e3dec6a4980c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559656564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.2559656564
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.1480180981
Short name T193
Test name
Test status
Simulation time 147893670 ps
CPU time 2.24 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:28 AM PDT 24
Peak memory 204540 kb
Host smart-d1d7d727-c1ff-4bd5-a3e4-bf64a909c6b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480180981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.1480180981
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2960324122
Short name T93
Test name
Test status
Simulation time 80599002 ps
CPU time 0.84 seconds
Started Jul 02 08:03:14 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204452 kb
Host smart-7461383e-2123-4134-ad9b-2cefa434ec09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960324122 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2960324122
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.2027860814
Short name T234
Test name
Test status
Simulation time 81565921 ps
CPU time 0.65 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204424 kb
Host smart-bd5c7989-2685-49d6-b9a0-05017472a011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027860814 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.2027860814
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1385689473
Short name T1599
Test name
Test status
Simulation time 20374572 ps
CPU time 0.69 seconds
Started Jul 02 08:03:15 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204340 kb
Host smart-fc4648ef-c39d-405d-84f0-278d5f7b6e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385689473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1385689473
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.3989808991
Short name T231
Test name
Test status
Simulation time 111780932 ps
CPU time 0.92 seconds
Started Jul 02 08:03:18 AM PDT 24
Finished Jul 02 08:03:33 AM PDT 24
Peak memory 204392 kb
Host smart-33d824ec-b795-43c9-b543-db9f16ea5642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989808991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.3989808991
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.139116458
Short name T214
Test name
Test status
Simulation time 38055382 ps
CPU time 1.15 seconds
Started Jul 02 08:03:14 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204632 kb
Host smart-a0618030-fd23-4e69-8c6f-64987a288702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139116458 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.139116458
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.4220465410
Short name T194
Test name
Test status
Simulation time 255615312 ps
CPU time 1.44 seconds
Started Jul 02 08:03:15 AM PDT 24
Finished Jul 02 08:03:30 AM PDT 24
Peak memory 204520 kb
Host smart-d58fe814-c088-4dc1-bdb8-21caee48546d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220465410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.4220465410
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.1669172311
Short name T1594
Test name
Test status
Simulation time 198120257 ps
CPU time 1.25 seconds
Started Jul 02 08:02:50 AM PDT 24
Finished Jul 02 08:03:09 AM PDT 24
Peak memory 204528 kb
Host smart-9fb38d0b-b933-4a38-93c6-196d7504a369
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669172311 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.1669172311
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.959398110
Short name T224
Test name
Test status
Simulation time 1865059524 ps
CPU time 4.8 seconds
Started Jul 02 08:02:48 AM PDT 24
Finished Jul 02 08:03:10 AM PDT 24
Peak memory 204444 kb
Host smart-d36d057a-368f-4b3d-b238-952168fe5fde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959398110 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.959398110
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.2072693682
Short name T222
Test name
Test status
Simulation time 17804348 ps
CPU time 0.65 seconds
Started Jul 02 08:02:50 AM PDT 24
Finished Jul 02 08:03:09 AM PDT 24
Peak memory 204432 kb
Host smart-6e9a993f-866f-4d18-aa6d-d48c681d29e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072693682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.2072693682
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.3629751346
Short name T1617
Test name
Test status
Simulation time 191816178 ps
CPU time 0.99 seconds
Started Jul 02 08:02:48 AM PDT 24
Finished Jul 02 08:03:06 AM PDT 24
Peak memory 204484 kb
Host smart-19eb08ca-06d8-4320-8aad-6249e6684ede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629751346 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.3629751346
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3947676440
Short name T1629
Test name
Test status
Simulation time 23134707 ps
CPU time 0.68 seconds
Started Jul 02 08:02:52 AM PDT 24
Finished Jul 02 08:03:11 AM PDT 24
Peak memory 204416 kb
Host smart-43336686-9cbe-413f-82bf-c6ad3e366bcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947676440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3947676440
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.998333144
Short name T1620
Test name
Test status
Simulation time 43866185 ps
CPU time 0.65 seconds
Started Jul 02 08:02:49 AM PDT 24
Finished Jul 02 08:03:07 AM PDT 24
Peak memory 204324 kb
Host smart-514c312a-69ba-486b-b5c1-378835f0f59f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998333144 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.998333144
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1804555241
Short name T1565
Test name
Test status
Simulation time 339781872 ps
CPU time 0.81 seconds
Started Jul 02 08:02:58 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 204432 kb
Host smart-7a32a0ed-5f91-4efd-a1b8-4633dcee5d32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804555241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.1804555241
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.4126435177
Short name T202
Test name
Test status
Simulation time 415165193 ps
CPU time 1.39 seconds
Started Jul 02 08:02:41 AM PDT 24
Finished Jul 02 08:02:59 AM PDT 24
Peak memory 204520 kb
Host smart-4980bd5f-306b-4a60-ab24-c9a22d32d5f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126435177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.4126435177
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3266354046
Short name T1561
Test name
Test status
Simulation time 43849216 ps
CPU time 0.69 seconds
Started Jul 02 08:03:12 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204336 kb
Host smart-daa80ca6-fc4d-4e90-8680-7275e227ce1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266354046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3266354046
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.1693126174
Short name T1554
Test name
Test status
Simulation time 17687523 ps
CPU time 0.65 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204324 kb
Host smart-f5b151a2-aa9f-49a8-b782-6b6808d75750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693126174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.1693126174
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4001563913
Short name T1632
Test name
Test status
Simulation time 16852953 ps
CPU time 0.71 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204336 kb
Host smart-b48f3d31-d2fc-4fe2-93af-89af6558094c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001563913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4001563913
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.394123923
Short name T1645
Test name
Test status
Simulation time 108589784 ps
CPU time 0.66 seconds
Started Jul 02 08:03:09 AM PDT 24
Finished Jul 02 08:03:25 AM PDT 24
Peak memory 204356 kb
Host smart-6bef63a5-ae43-48bd-99bd-770886b07757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394123923 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.394123923
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.809585162
Short name T1580
Test name
Test status
Simulation time 32464496 ps
CPU time 0.75 seconds
Started Jul 02 08:03:15 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204356 kb
Host smart-a4d61549-8f0c-4835-9ea7-0186dd2cda85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809585162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.809585162
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.3991482563
Short name T1585
Test name
Test status
Simulation time 186875961 ps
CPU time 0.71 seconds
Started Jul 02 08:03:12 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204260 kb
Host smart-695da5d0-f473-4167-b25d-57a2efe1f07c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991482563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.3991482563
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.2238950315
Short name T1634
Test name
Test status
Simulation time 16046994 ps
CPU time 0.69 seconds
Started Jul 02 08:03:14 AM PDT 24
Finished Jul 02 08:03:28 AM PDT 24
Peak memory 204360 kb
Host smart-263c5d09-87be-4648-b8b4-c3eb066a0b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238950315 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.2238950315
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2328278897
Short name T1619
Test name
Test status
Simulation time 55656836 ps
CPU time 0.65 seconds
Started Jul 02 08:03:15 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204340 kb
Host smart-3e93b6d3-9f6d-4b4d-89f3-939e99eabf28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328278897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2328278897
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.3038722791
Short name T1641
Test name
Test status
Simulation time 15317174 ps
CPU time 0.63 seconds
Started Jul 02 08:03:15 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204288 kb
Host smart-0dcce634-c4ce-4f6a-bb0d-2b8915e5f439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038722791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.3038722791
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.3113677227
Short name T1541
Test name
Test status
Simulation time 40959949 ps
CPU time 0.67 seconds
Started Jul 02 08:03:17 AM PDT 24
Finished Jul 02 08:03:31 AM PDT 24
Peak memory 204376 kb
Host smart-2b778053-1e15-47ec-88f7-287f9c2c3fbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113677227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.3113677227
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.693389912
Short name T141
Test name
Test status
Simulation time 84929499 ps
CPU time 1.24 seconds
Started Jul 02 08:02:46 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 204564 kb
Host smart-50171f7b-bfc8-468d-8812-bf970a81dd16
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693389912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.693389912
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.550341048
Short name T1615
Test name
Test status
Simulation time 402460392 ps
CPU time 2.86 seconds
Started Jul 02 08:03:06 AM PDT 24
Finished Jul 02 08:03:24 AM PDT 24
Peak memory 204572 kb
Host smart-398b0052-d7f0-4d12-a84d-4ab8ef33b5a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550341048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.550341048
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.3873521827
Short name T1549
Test name
Test status
Simulation time 52418523 ps
CPU time 0.68 seconds
Started Jul 02 08:03:04 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204420 kb
Host smart-dca83722-ce6e-42bd-adec-a0f8738e74fe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873521827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.3873521827
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.659079281
Short name T213
Test name
Test status
Simulation time 32815416 ps
CPU time 0.8 seconds
Started Jul 02 08:02:48 AM PDT 24
Finished Jul 02 08:03:06 AM PDT 24
Peak memory 204512 kb
Host smart-21f82ed9-9b67-4a38-a513-d6252bf08416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659079281 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.659079281
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3010246134
Short name T228
Test name
Test status
Simulation time 28035011 ps
CPU time 0.77 seconds
Started Jul 02 08:02:58 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 204456 kb
Host smart-c8e574b9-838b-4b67-836a-8a5d09dd5967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010246134 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3010246134
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.3469610433
Short name T1638
Test name
Test status
Simulation time 41352423 ps
CPU time 0.64 seconds
Started Jul 02 08:02:55 AM PDT 24
Finished Jul 02 08:03:14 AM PDT 24
Peak memory 204360 kb
Host smart-2d964277-dea7-4b98-bc60-b072e84cac9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469610433 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.3469610433
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.2188454817
Short name T1573
Test name
Test status
Simulation time 51430810 ps
CPU time 1.14 seconds
Started Jul 02 08:02:55 AM PDT 24
Finished Jul 02 08:03:14 AM PDT 24
Peak memory 204508 kb
Host smart-e5b4819a-c943-489e-b893-19256c531df4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188454817 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.2188454817
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.2783722595
Short name T1583
Test name
Test status
Simulation time 29106707 ps
CPU time 1.36 seconds
Started Jul 02 08:02:49 AM PDT 24
Finished Jul 02 08:03:07 AM PDT 24
Peak memory 204568 kb
Host smart-f0d655ce-71bf-4e1c-b68e-d72cdf7bfb9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783722595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.2783722595
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.577212626
Short name T1593
Test name
Test status
Simulation time 37888407 ps
CPU time 0.62 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204284 kb
Host smart-9f37d671-e722-4716-bbbd-517d707584b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577212626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.577212626
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.2604280016
Short name T1550
Test name
Test status
Simulation time 53807828 ps
CPU time 0.66 seconds
Started Jul 02 08:03:11 AM PDT 24
Finished Jul 02 08:03:26 AM PDT 24
Peak memory 204336 kb
Host smart-3ba304ff-ae62-4284-a2d4-66dff327a0d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604280016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.2604280016
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.360187555
Short name T1563
Test name
Test status
Simulation time 30789981 ps
CPU time 0.7 seconds
Started Jul 02 08:03:15 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204324 kb
Host smart-5974f40b-58bd-4754-9515-c3a47d390d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360187555 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.360187555
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.1165468483
Short name T1547
Test name
Test status
Simulation time 18727014 ps
CPU time 0.65 seconds
Started Jul 02 08:03:19 AM PDT 24
Finished Jul 02 08:03:33 AM PDT 24
Peak memory 204348 kb
Host smart-6c0fd013-7f0f-46b4-8bb3-4145afeeee58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165468483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.1165468483
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.292078123
Short name T1627
Test name
Test status
Simulation time 54086513 ps
CPU time 0.66 seconds
Started Jul 02 08:03:11 AM PDT 24
Finished Jul 02 08:03:26 AM PDT 24
Peak memory 204320 kb
Host smart-b1edb832-29d9-43a4-be70-908c33d9527b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292078123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.292078123
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.3492476099
Short name T1616
Test name
Test status
Simulation time 23709294 ps
CPU time 0.67 seconds
Started Jul 02 08:03:16 AM PDT 24
Finished Jul 02 08:03:32 AM PDT 24
Peak memory 204536 kb
Host smart-c4f09dd6-4b97-4084-b703-ffa904f2f8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492476099 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.3492476099
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.1486472056
Short name T1553
Test name
Test status
Simulation time 29543965 ps
CPU time 0.67 seconds
Started Jul 02 08:03:16 AM PDT 24
Finished Jul 02 08:03:32 AM PDT 24
Peak memory 204248 kb
Host smart-a1fb00d2-54cb-4bab-b71d-94829705d2f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486472056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.1486472056
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.2626276054
Short name T1546
Test name
Test status
Simulation time 32144771 ps
CPU time 0.64 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:28 AM PDT 24
Peak memory 204344 kb
Host smart-2081fbb3-38d1-416c-a4e0-e3de197072bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626276054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.2626276054
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.410337190
Short name T1631
Test name
Test status
Simulation time 17488399 ps
CPU time 0.65 seconds
Started Jul 02 08:03:14 AM PDT 24
Finished Jul 02 08:03:28 AM PDT 24
Peak memory 204244 kb
Host smart-a09d72a7-7d97-412c-bb46-75536dac2c37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410337190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.410337190
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.3620981413
Short name T1572
Test name
Test status
Simulation time 36136985 ps
CPU time 0.64 seconds
Started Jul 02 08:03:11 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204368 kb
Host smart-f7bc0e4e-e300-4e89-bfce-7e9dfd8373fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620981413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.3620981413
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.3054709978
Short name T223
Test name
Test status
Simulation time 64367739 ps
CPU time 1.21 seconds
Started Jul 02 08:02:52 AM PDT 24
Finished Jul 02 08:03:12 AM PDT 24
Peak memory 204480 kb
Host smart-93d0e4c8-ca04-48ab-973b-60a814ebb264
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054709978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.3054709978
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.1296907807
Short name T1623
Test name
Test status
Simulation time 362760258 ps
CPU time 4.97 seconds
Started Jul 02 08:02:52 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 204492 kb
Host smart-bfa4542f-ea72-4b44-bc86-960bb21dcad9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296907807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.1296907807
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.4252021685
Short name T1597
Test name
Test status
Simulation time 18468761 ps
CPU time 0.75 seconds
Started Jul 02 08:02:53 AM PDT 24
Finished Jul 02 08:03:12 AM PDT 24
Peak memory 204428 kb
Host smart-96299e27-bcb8-4191-9d5e-b752fb8e44d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252021685 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.4252021685
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.296918740
Short name T1622
Test name
Test status
Simulation time 227339487 ps
CPU time 0.95 seconds
Started Jul 02 08:02:56 AM PDT 24
Finished Jul 02 08:03:14 AM PDT 24
Peak memory 204436 kb
Host smart-8f6534f2-2f09-4aa9-9b3d-34f466ad1726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296918740 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.296918740
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.3867503869
Short name T229
Test name
Test status
Simulation time 26611762 ps
CPU time 0.81 seconds
Started Jul 02 08:02:51 AM PDT 24
Finished Jul 02 08:03:09 AM PDT 24
Peak memory 204412 kb
Host smart-10d576d8-bab2-47cf-971c-ba1ae35edea5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867503869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.3867503869
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.3455740472
Short name T1643
Test name
Test status
Simulation time 17603115 ps
CPU time 0.67 seconds
Started Jul 02 08:02:58 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 204376 kb
Host smart-d98e8077-b0f6-43e9-9158-15584a02ffdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455740472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.3455740472
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4222337381
Short name T1642
Test name
Test status
Simulation time 49643367 ps
CPU time 1.17 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204548 kb
Host smart-4906602e-b7a8-4156-be9d-9102f8eda86c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222337381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.4222337381
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2846488794
Short name T1609
Test name
Test status
Simulation time 76804904 ps
CPU time 2.04 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204624 kb
Host smart-955c04ca-64e5-4893-9310-0404a6061c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846488794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2846488794
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.927656238
Short name T189
Test name
Test status
Simulation time 95834318 ps
CPU time 1.37 seconds
Started Jul 02 08:02:58 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 204548 kb
Host smart-588a54fe-fb6a-497c-9b24-8cabf87976ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927656238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.927656238
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.3117773950
Short name T1602
Test name
Test status
Simulation time 16966609 ps
CPU time 0.66 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:28 AM PDT 24
Peak memory 204364 kb
Host smart-e7fef0ef-b5bd-4ce5-afde-b61222619110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117773950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.3117773950
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2360192767
Short name T1581
Test name
Test status
Simulation time 18354734 ps
CPU time 0.68 seconds
Started Jul 02 08:03:15 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204368 kb
Host smart-963dab2c-f678-491b-aacb-10773cde1391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360192767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2360192767
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.307550606
Short name T1574
Test name
Test status
Simulation time 32007218 ps
CPU time 0.69 seconds
Started Jul 02 08:03:15 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204380 kb
Host smart-b8129ef3-a3a9-467a-bc59-73ef06ebc219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307550606 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.307550606
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.4046688342
Short name T1577
Test name
Test status
Simulation time 15827833 ps
CPU time 0.78 seconds
Started Jul 02 08:03:14 AM PDT 24
Finished Jul 02 08:03:29 AM PDT 24
Peak memory 204348 kb
Host smart-fae2b5bd-9863-4f25-8431-78425736cc16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046688342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.4046688342
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.1939072250
Short name T1569
Test name
Test status
Simulation time 17082337 ps
CPU time 0.68 seconds
Started Jul 02 08:03:20 AM PDT 24
Finished Jul 02 08:03:34 AM PDT 24
Peak memory 204308 kb
Host smart-f691ab27-b578-44ba-84a2-ad50ec81a63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939072250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.1939072250
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.773641071
Short name T1548
Test name
Test status
Simulation time 18011927 ps
CPU time 0.66 seconds
Started Jul 02 08:03:17 AM PDT 24
Finished Jul 02 08:03:31 AM PDT 24
Peak memory 204356 kb
Host smart-5c59928f-2ebe-49f6-bcff-6dde708f36d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773641071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.773641071
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.212722036
Short name T1560
Test name
Test status
Simulation time 22763826 ps
CPU time 0.69 seconds
Started Jul 02 08:03:13 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204348 kb
Host smart-0cba00ef-9ea2-4389-82ff-59eb8142b743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212722036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.212722036
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.1924460508
Short name T1568
Test name
Test status
Simulation time 21108469 ps
CPU time 0.67 seconds
Started Jul 02 08:03:20 AM PDT 24
Finished Jul 02 08:03:34 AM PDT 24
Peak memory 204360 kb
Host smart-187249b3-1ab2-43ab-a8b1-c57ee71b7d14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924460508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.1924460508
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2048518448
Short name T1542
Test name
Test status
Simulation time 17817728 ps
CPU time 0.68 seconds
Started Jul 02 08:03:19 AM PDT 24
Finished Jul 02 08:03:33 AM PDT 24
Peak memory 204360 kb
Host smart-9b72c567-05b5-4d3a-908a-21801f283048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048518448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2048518448
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.2020589644
Short name T1564
Test name
Test status
Simulation time 67387773 ps
CPU time 0.67 seconds
Started Jul 02 08:03:16 AM PDT 24
Finished Jul 02 08:03:30 AM PDT 24
Peak memory 204304 kb
Host smart-1d4cb2ba-ad45-454d-a26d-81c907c1869a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020589644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.2020589644
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4076577810
Short name T1592
Test name
Test status
Simulation time 134161061 ps
CPU time 0.84 seconds
Started Jul 02 08:03:00 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204480 kb
Host smart-692fa858-f154-48ea-8947-85fa58b32138
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076577810 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.4076577810
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.4081387063
Short name T92
Test name
Test status
Simulation time 29604212 ps
CPU time 0.8 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204428 kb
Host smart-fde90732-32fa-4e5d-ae74-0b04d1d7352d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081387063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.4081387063
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.1605156190
Short name T1545
Test name
Test status
Simulation time 44923164 ps
CPU time 0.68 seconds
Started Jul 02 08:02:51 AM PDT 24
Finished Jul 02 08:03:10 AM PDT 24
Peak memory 204368 kb
Host smart-ea5e69e7-5ce8-470f-ab45-b73b8f3c7c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605156190 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.1605156190
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2183103570
Short name T96
Test name
Test status
Simulation time 356314767 ps
CPU time 1.12 seconds
Started Jul 02 08:03:07 AM PDT 24
Finished Jul 02 08:03:22 AM PDT 24
Peak memory 204604 kb
Host smart-4fe3dc3f-bad8-48c2-94e9-7fe2b4f8ca82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183103570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2183103570
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.1440126827
Short name T1607
Test name
Test status
Simulation time 560498757 ps
CPU time 2.84 seconds
Started Jul 02 08:03:02 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204604 kb
Host smart-e19d116f-e293-4c66-a129-d43f5485ee6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440126827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.1440126827
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.2012193513
Short name T197
Test name
Test status
Simulation time 65835571 ps
CPU time 1.36 seconds
Started Jul 02 08:02:46 AM PDT 24
Finished Jul 02 08:03:04 AM PDT 24
Peak memory 204504 kb
Host smart-7449662a-c619-4535-bed3-b9c820f2c50a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012193513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.2012193513
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2426961545
Short name T1618
Test name
Test status
Simulation time 67920629 ps
CPU time 0.94 seconds
Started Jul 02 08:02:48 AM PDT 24
Finished Jul 02 08:03:07 AM PDT 24
Peak memory 204520 kb
Host smart-94705b65-1720-4651-aa8f-3d6ebbf8a481
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426961545 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.2426961545
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.2236602632
Short name T1587
Test name
Test status
Simulation time 195605761 ps
CPU time 0.77 seconds
Started Jul 02 08:03:00 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 204408 kb
Host smart-e832b6c5-e0f1-4583-99d4-03808d17bd1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236602632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.2236602632
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.411441613
Short name T1613
Test name
Test status
Simulation time 51856790 ps
CPU time 0.65 seconds
Started Jul 02 08:02:51 AM PDT 24
Finished Jul 02 08:03:10 AM PDT 24
Peak memory 204368 kb
Host smart-83dc4a3d-3561-4656-8233-0b7e83e00d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411441613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.411441613
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1690998967
Short name T1557
Test name
Test status
Simulation time 56858982 ps
CPU time 0.79 seconds
Started Jul 02 08:03:02 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204452 kb
Host smart-c582e34a-f49e-4200-a952-6779e5d73002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690998967 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.1690998967
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.1020208919
Short name T1589
Test name
Test status
Simulation time 409398246 ps
CPU time 2.48 seconds
Started Jul 02 08:03:10 AM PDT 24
Finished Jul 02 08:03:27 AM PDT 24
Peak memory 204664 kb
Host smart-0720e6ae-770b-4929-a0a1-5f6d951433ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020208919 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.1020208919
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.3773062379
Short name T196
Test name
Test status
Simulation time 66039483 ps
CPU time 1.45 seconds
Started Jul 02 08:02:56 AM PDT 24
Finished Jul 02 08:03:15 AM PDT 24
Peak memory 204508 kb
Host smart-afc56fe2-4941-4ff7-ad0b-2a9cc858e1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773062379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.3773062379
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.2575499094
Short name T1559
Test name
Test status
Simulation time 33266774 ps
CPU time 0.92 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204520 kb
Host smart-6d9bc522-27f3-4689-aa16-d1e2d93b48f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575499094 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.2575499094
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.738038177
Short name T1543
Test name
Test status
Simulation time 16219173 ps
CPU time 0.65 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204332 kb
Host smart-371bcf5b-8de3-4c10-b72b-245620758a6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738038177 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.738038177
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3318883561
Short name T1579
Test name
Test status
Simulation time 61400805 ps
CPU time 0.91 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204648 kb
Host smart-4b280aec-b64b-4e4f-bfc1-d90ff51296f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318883561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3318883561
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.129126278
Short name T1570
Test name
Test status
Simulation time 68848277 ps
CPU time 1.68 seconds
Started Jul 02 08:03:01 AM PDT 24
Finished Jul 02 08:03:19 AM PDT 24
Peak memory 204544 kb
Host smart-0a6015be-4413-44e9-8d41-e6dc2a0a99f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129126278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.129126278
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.1940241680
Short name T205
Test name
Test status
Simulation time 439040979 ps
CPU time 2.15 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:22 AM PDT 24
Peak memory 204532 kb
Host smart-5d47ebc0-1449-4bfe-b3b4-8ed63c3f7330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940241680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.1940241680
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.2170385704
Short name T114
Test name
Test status
Simulation time 41793374 ps
CPU time 1.05 seconds
Started Jul 02 08:02:56 AM PDT 24
Finished Jul 02 08:03:14 AM PDT 24
Peak memory 204420 kb
Host smart-10780db6-4e52-4938-8ad8-4e35695f1068
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170385704 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.2170385704
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.610760395
Short name T1590
Test name
Test status
Simulation time 59789005 ps
CPU time 0.78 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204460 kb
Host smart-0985fc55-5721-45fb-8615-fa6091de4e84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610760395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.610760395
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.3702267303
Short name T1567
Test name
Test status
Simulation time 52980064 ps
CPU time 0.68 seconds
Started Jul 02 08:03:10 AM PDT 24
Finished Jul 02 08:03:25 AM PDT 24
Peak memory 204244 kb
Host smart-68783bfc-1287-4e9b-8f53-5554a695a656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702267303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.3702267303
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2724841406
Short name T89
Test name
Test status
Simulation time 128998191 ps
CPU time 1.23 seconds
Started Jul 02 08:03:05 AM PDT 24
Finished Jul 02 08:03:21 AM PDT 24
Peak memory 204504 kb
Host smart-dcd3d1a5-8945-4d9a-af81-5f992d7cd96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724841406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2724841406
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.2278553090
Short name T1578
Test name
Test status
Simulation time 24461344 ps
CPU time 1.29 seconds
Started Jul 02 08:02:51 AM PDT 24
Finished Jul 02 08:03:10 AM PDT 24
Peak memory 204620 kb
Host smart-1c66ed86-ea30-4fe6-a9cf-3502a2232f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278553090 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.2278553090
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.3206881693
Short name T95
Test name
Test status
Simulation time 1273802987 ps
CPU time 2.38 seconds
Started Jul 02 08:02:57 AM PDT 24
Finished Jul 02 08:03:17 AM PDT 24
Peak memory 204564 kb
Host smart-3c043429-a82f-4b29-9612-56b11888a56d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206881693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.3206881693
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.3905962572
Short name T1610
Test name
Test status
Simulation time 36221506 ps
CPU time 0.93 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204456 kb
Host smart-1539c62c-717f-4dc1-809f-84d5012a0f41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905962572 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.3905962572
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.1414888875
Short name T1582
Test name
Test status
Simulation time 18838072 ps
CPU time 0.7 seconds
Started Jul 02 08:02:59 AM PDT 24
Finished Jul 02 08:03:16 AM PDT 24
Peak memory 204344 kb
Host smart-60575f8c-6cb5-4970-b09b-3b890cf8138c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414888875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.1414888875
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.2832319876
Short name T1621
Test name
Test status
Simulation time 37541896 ps
CPU time 0.7 seconds
Started Jul 02 08:03:02 AM PDT 24
Finished Jul 02 08:03:18 AM PDT 24
Peak memory 204316 kb
Host smart-0494429a-7fc3-4072-b03d-60d49e11d12b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832319876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.2832319876
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.510295261
Short name T236
Test name
Test status
Simulation time 28032534 ps
CPU time 1.17 seconds
Started Jul 02 08:03:03 AM PDT 24
Finished Jul 02 08:03:20 AM PDT 24
Peak memory 204500 kb
Host smart-eb9b06a7-1389-49f3-b553-2cee45766dcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510295261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_out
standing.510295261
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4268812530
Short name T1575
Test name
Test status
Simulation time 69492988 ps
CPU time 1.71 seconds
Started Jul 02 08:03:09 AM PDT 24
Finished Jul 02 08:03:26 AM PDT 24
Peak memory 204444 kb
Host smart-8e01e1ca-92b2-450d-8bfa-2c2d38cfb22a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268812530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.4268812530
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/0.i2c_alert_test.3674477472
Short name T1285
Test name
Test status
Simulation time 27716098 ps
CPU time 0.64 seconds
Started Jul 02 08:08:56 AM PDT 24
Finished Jul 02 08:09:02 AM PDT 24
Peak memory 204476 kb
Host smart-8f117b31-00ff-43a8-8816-75f5cb7c6413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674477472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.3674477472
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.59141273
Short name T43
Test name
Test status
Simulation time 365432946 ps
CPU time 1.38 seconds
Started Jul 02 08:08:54 AM PDT 24
Finished Jul 02 08:09:00 AM PDT 24
Peak memory 221212 kb
Host smart-4f4707c0-4643-4c1c-9e7f-8c3eee3e29e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59141273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.59141273
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.894537540
Short name T398
Test name
Test status
Simulation time 4985618393 ps
CPU time 8.93 seconds
Started Jul 02 08:08:53 AM PDT 24
Finished Jul 02 08:09:06 AM PDT 24
Peak memory 290040 kb
Host smart-e93915ff-1775-4aea-968d-7d62bbf9d289
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894537540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.894537540
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.3358447375
Short name T70
Test name
Test status
Simulation time 2224277495 ps
CPU time 150.03 seconds
Started Jul 02 08:08:52 AM PDT 24
Finished Jul 02 08:11:27 AM PDT 24
Peak memory 733968 kb
Host smart-29027b83-6802-4d5f-93d0-66a1f16f9a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358447375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.3358447375
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.3017973615
Short name T1028
Test name
Test status
Simulation time 3144643844 ps
CPU time 51.64 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:09:54 AM PDT 24
Peak memory 589776 kb
Host smart-aa036341-1f6f-441b-b72a-d57606b3dfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017973615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.3017973615
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.3640834439
Short name T585
Test name
Test status
Simulation time 75538326 ps
CPU time 0.89 seconds
Started Jul 02 08:08:54 AM PDT 24
Finished Jul 02 08:09:00 AM PDT 24
Peak memory 204432 kb
Host smart-28d65eb8-8d6d-4fad-adba-fee52d3359f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640834439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fm
t.3640834439
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.532320269
Short name T1219
Test name
Test status
Simulation time 5181600600 ps
CPU time 154.3 seconds
Started Jul 02 08:08:53 AM PDT 24
Finished Jul 02 08:11:33 AM PDT 24
Peak memory 1473168 kb
Host smart-6029cbaa-ba51-44ec-bb1f-15342ca86032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532320269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.532320269
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.3432823056
Short name T1424
Test name
Test status
Simulation time 2954476280 ps
CPU time 7.9 seconds
Started Jul 02 08:08:56 AM PDT 24
Finished Jul 02 08:09:08 AM PDT 24
Peak memory 204844 kb
Host smart-0d41bcd6-b2c6-4ad7-bed5-3c4ba486588f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432823056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.3432823056
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.536296957
Short name T1512
Test name
Test status
Simulation time 20514559040 ps
CPU time 76.76 seconds
Started Jul 02 08:08:58 AM PDT 24
Finished Jul 02 08:10:20 AM PDT 24
Peak memory 313808 kb
Host smart-6a15048a-eb4a-47fd-becd-a8ae7db861e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536296957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.536296957
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.3950660584
Short name T614
Test name
Test status
Simulation time 26275450 ps
CPU time 0.73 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:08:55 AM PDT 24
Peak memory 204476 kb
Host smart-22e3947c-13c9-4fc8-af0a-edcd23fdea6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950660584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.3950660584
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.1708404556
Short name T37
Test name
Test status
Simulation time 7073411110 ps
CPU time 73.55 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:10:15 AM PDT 24
Peak memory 214152 kb
Host smart-1d3dbd07-4e2d-4c79-ad30-2f4d3db228d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708404556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.1708404556
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.1496757368
Short name T1415
Test name
Test status
Simulation time 87079008 ps
CPU time 2.17 seconds
Started Jul 02 08:08:50 AM PDT 24
Finished Jul 02 08:08:56 AM PDT 24
Peak memory 229176 kb
Host smart-215e90c3-84d2-4998-bfa3-6b4520612f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496757368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.1496757368
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.289417956
Short name T1047
Test name
Test status
Simulation time 7885261993 ps
CPU time 79.6 seconds
Started Jul 02 08:08:51 AM PDT 24
Finished Jul 02 08:10:16 AM PDT 24
Peak memory 294312 kb
Host smart-96155162-57f9-4d85-a40d-92a332b7040e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289417956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.289417956
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.1904281382
Short name T594
Test name
Test status
Simulation time 2979201270 ps
CPU time 12.56 seconds
Started Jul 02 08:08:52 AM PDT 24
Finished Jul 02 08:09:10 AM PDT 24
Peak memory 218120 kb
Host smart-b1a86fb2-8649-4f0f-b050-03d71563d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904281382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.1904281382
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.1880853422
Short name T1428
Test name
Test status
Simulation time 6071888192 ps
CPU time 4.85 seconds
Started Jul 02 08:08:59 AM PDT 24
Finished Jul 02 08:09:08 AM PDT 24
Peak memory 213152 kb
Host smart-b16bdc01-dbb4-4157-a6af-1243e1088e9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880853422 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.1880853422
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2777291188
Short name T779
Test name
Test status
Simulation time 243727038 ps
CPU time 0.88 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:09:03 AM PDT 24
Peak memory 204580 kb
Host smart-447f7aef-f1f6-4c3d-8469-c7c9216ecebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777291188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2777291188
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.818421481
Short name T1168
Test name
Test status
Simulation time 246600430 ps
CPU time 1.45 seconds
Started Jul 02 08:08:59 AM PDT 24
Finished Jul 02 08:09:05 AM PDT 24
Peak memory 204612 kb
Host smart-ce09d674-4659-44f1-a599-35fd0a0391b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818421481 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.818421481
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.502123556
Short name T771
Test name
Test status
Simulation time 887047140 ps
CPU time 2.18 seconds
Started Jul 02 08:08:55 AM PDT 24
Finished Jul 02 08:09:02 AM PDT 24
Peak memory 204708 kb
Host smart-16363546-5b03-4257-97dd-bb6aa69a6fdd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502123556 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.502123556
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.383038162
Short name T298
Test name
Test status
Simulation time 1685603557 ps
CPU time 1.11 seconds
Started Jul 02 08:08:58 AM PDT 24
Finished Jul 02 08:09:03 AM PDT 24
Peak memory 204600 kb
Host smart-18072e2e-0393-49b2-94e0-5bdd1cd71af7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383038162 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.383038162
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.2904490216
Short name T900
Test name
Test status
Simulation time 381590319 ps
CPU time 3.76 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:09:06 AM PDT 24
Peak memory 204792 kb
Host smart-93c2a0c2-586c-4249-b8bc-693fb820b21b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904490216 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.2904490216
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.1171966596
Short name T1035
Test name
Test status
Simulation time 778486965 ps
CPU time 4.51 seconds
Started Jul 02 08:08:58 AM PDT 24
Finished Jul 02 08:09:08 AM PDT 24
Peak memory 217516 kb
Host smart-6207004e-8c7c-40e1-a3d7-75857a3d543b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171966596 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.1171966596
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.829610123
Short name T1251
Test name
Test status
Simulation time 13649060797 ps
CPU time 37.15 seconds
Started Jul 02 08:08:59 AM PDT 24
Finished Jul 02 08:09:41 AM PDT 24
Peak memory 974712 kb
Host smart-14cd2c98-7c6b-4ca4-81f0-a58458fe0dc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829610123 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.829610123
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.2812143464
Short name T644
Test name
Test status
Simulation time 1681858193 ps
CPU time 14.42 seconds
Started Jul 02 08:08:59 AM PDT 24
Finished Jul 02 08:09:18 AM PDT 24
Peak memory 204684 kb
Host smart-57041936-90b0-4c5b-a96b-abcfebeac75f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812143464 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.2812143464
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.1015812101
Short name T791
Test name
Test status
Simulation time 4532248918 ps
CPU time 30.96 seconds
Started Jul 02 08:08:56 AM PDT 24
Finished Jul 02 08:09:32 AM PDT 24
Peak memory 204940 kb
Host smart-45e60635-5766-465d-8999-0576d8a0862a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015812101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_rd.1015812101
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.2539151330
Short name T1260
Test name
Test status
Simulation time 16888369720 ps
CPU time 30.15 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:09:35 AM PDT 24
Peak memory 204896 kb
Host smart-af28f0ad-3d03-41ce-b154-22c9f2411f2c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539151330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.2539151330
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.511881841
Short name T28
Test name
Test status
Simulation time 2324035223 ps
CPU time 6.75 seconds
Started Jul 02 08:08:55 AM PDT 24
Finished Jul 02 08:09:07 AM PDT 24
Peak memory 204908 kb
Host smart-6d86d1a9-f978-4b17-8814-837b40e1b537
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511881841 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_timeout.511881841
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.2236766774
Short name T960
Test name
Test status
Simulation time 427615624 ps
CPU time 6 seconds
Started Jul 02 08:08:55 AM PDT 24
Finished Jul 02 08:09:07 AM PDT 24
Peak memory 204796 kb
Host smart-c4c2b9da-b1cb-4c07-8397-8fa41593c25b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236766774 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.2236766774
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.4274100553
Short name T1364
Test name
Test status
Simulation time 24428367 ps
CPU time 0.62 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:09:05 AM PDT 24
Peak memory 204464 kb
Host smart-c63d4549-62ae-4297-b67b-cc7093a870a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274100553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.4274100553
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.3434285098
Short name T762
Test name
Test status
Simulation time 390711136 ps
CPU time 3.48 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:09:08 AM PDT 24
Peak memory 213092 kb
Host smart-8a2ed5f5-3c84-452a-a3a2-77803698f7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434285098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.3434285098
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.456681128
Short name T784
Test name
Test status
Simulation time 2783744425 ps
CPU time 13.21 seconds
Started Jul 02 08:08:55 AM PDT 24
Finished Jul 02 08:09:13 AM PDT 24
Peak memory 363544 kb
Host smart-7a8621d6-db91-4b63-9076-3b6da63b9b1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456681128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.456681128
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.490934960
Short name T1038
Test name
Test status
Simulation time 5935207440 ps
CPU time 91.79 seconds
Started Jul 02 08:08:58 AM PDT 24
Finished Jul 02 08:10:35 AM PDT 24
Peak memory 788792 kb
Host smart-7ce6f6ca-990b-4771-bb05-5bb95fb846b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490934960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.490934960
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.22851367
Short name T355
Test name
Test status
Simulation time 2008321888 ps
CPU time 67.43 seconds
Started Jul 02 08:08:58 AM PDT 24
Finished Jul 02 08:10:10 AM PDT 24
Peak memory 701180 kb
Host smart-2f567d3c-2f04-414a-bd17-ba7c8b57c9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22851367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.22851367
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.3326943911
Short name T1349
Test name
Test status
Simulation time 153566186 ps
CPU time 1.1 seconds
Started Jul 02 08:08:56 AM PDT 24
Finished Jul 02 08:09:02 AM PDT 24
Peak memory 204664 kb
Host smart-0e388930-908c-4fa4-997f-f072cfaec0e2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326943911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.3326943911
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.451969719
Short name T1178
Test name
Test status
Simulation time 272050912 ps
CPU time 4.01 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:09:06 AM PDT 24
Peak memory 227604 kb
Host smart-77b1169b-3a30-460e-8543-3b2fccbd3567
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451969719 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.451969719
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.1587252088
Short name T361
Test name
Test status
Simulation time 7950167024 ps
CPU time 111.98 seconds
Started Jul 02 08:08:55 AM PDT 24
Finished Jul 02 08:10:53 AM PDT 24
Peak memory 1122104 kb
Host smart-431d030c-004b-4514-9bc4-c00a32aece60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587252088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.1587252088
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.66362654
Short name T1118
Test name
Test status
Simulation time 2295917869 ps
CPU time 6.97 seconds
Started Jul 02 08:09:02 AM PDT 24
Finished Jul 02 08:09:13 AM PDT 24
Peak memory 204848 kb
Host smart-9c680410-6f98-4e2e-a1bd-e70c0d52f9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66362654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.66362654
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.4249630756
Short name T974
Test name
Test status
Simulation time 6223555625 ps
CPU time 79.76 seconds
Started Jul 02 08:09:02 AM PDT 24
Finished Jul 02 08:10:25 AM PDT 24
Peak memory 398744 kb
Host smart-c80bf81f-8a99-491a-8526-c9c290f22286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249630756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.4249630756
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/1.i2c_host_override.2876396181
Short name T132
Test name
Test status
Simulation time 19470789 ps
CPU time 0.71 seconds
Started Jul 02 08:08:58 AM PDT 24
Finished Jul 02 08:09:04 AM PDT 24
Peak memory 204500 kb
Host smart-3e4e52a7-c8d1-48fb-9625-afe404b98a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876396181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.2876396181
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf.1541596220
Short name T948
Test name
Test status
Simulation time 6855247819 ps
CPU time 41.7 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:09:43 AM PDT 24
Peak memory 204948 kb
Host smart-c2e0cbd6-bb53-4f4a-bee2-c27610a5509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541596220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.1541596220
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.2172277316
Short name T804
Test name
Test status
Simulation time 333278532 ps
CPU time 3.14 seconds
Started Jul 02 08:08:57 AM PDT 24
Finished Jul 02 08:09:05 AM PDT 24
Peak memory 217292 kb
Host smart-1bae9f94-92ab-456c-b73c-135199b52e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172277316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.2172277316
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.1897074649
Short name T1079
Test name
Test status
Simulation time 7316253521 ps
CPU time 84.28 seconds
Started Jul 02 08:08:59 AM PDT 24
Finished Jul 02 08:10:28 AM PDT 24
Peak memory 349564 kb
Host smart-c38f32c9-30c3-489d-98c2-4c22c997eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897074649 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.1897074649
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.3753291060
Short name T898
Test name
Test status
Simulation time 599487668 ps
CPU time 26.25 seconds
Started Jul 02 08:09:03 AM PDT 24
Finished Jul 02 08:09:33 AM PDT 24
Peak memory 212484 kb
Host smart-c38484fa-f999-4257-bed6-74bcd0a5355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753291060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.3753291060
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.3334823148
Short name T178
Test name
Test status
Simulation time 78024916 ps
CPU time 0.89 seconds
Started Jul 02 08:09:02 AM PDT 24
Finished Jul 02 08:09:07 AM PDT 24
Peak memory 222212 kb
Host smart-7e52fd32-6dc2-4bb5-b888-391225f60407
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334823148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.3334823148
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.3954004344
Short name T470
Test name
Test status
Simulation time 2205566198 ps
CPU time 3.12 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:09:09 AM PDT 24
Peak memory 204884 kb
Host smart-b5269b1d-6138-428a-8b86-430f96c8bceb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954004344 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.3954004344
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.3554315988
Short name T1218
Test name
Test status
Simulation time 934571855 ps
CPU time 1.48 seconds
Started Jul 02 08:09:05 AM PDT 24
Finished Jul 02 08:09:10 AM PDT 24
Peak memory 207260 kb
Host smart-23367661-6908-4f23-9840-27b917db3594
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554315988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.3554315988
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.727190895
Short name T1184
Test name
Test status
Simulation time 208719827 ps
CPU time 1.29 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:09:07 AM PDT 24
Peak memory 204712 kb
Host smart-8ef9eae5-efa8-4a60-ba9d-dee5eecca2c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727190895 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.i2c_target_fifo_reset_tx.727190895
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.217131892
Short name T1339
Test name
Test status
Simulation time 636014360 ps
CPU time 3.29 seconds
Started Jul 02 08:09:04 AM PDT 24
Finished Jul 02 08:09:10 AM PDT 24
Peak memory 204792 kb
Host smart-50918279-0ed3-4f3b-a190-8fb214f54164
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217131892 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.217131892
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.734926692
Short name T1198
Test name
Test status
Simulation time 436679766 ps
CPU time 1.09 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:09:07 AM PDT 24
Peak memory 204568 kb
Host smart-895797a3-0ff2-4dbc-b08b-929d9d861ada
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734926692 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.734926692
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.4091346508
Short name T14
Test name
Test status
Simulation time 10890700999 ps
CPU time 10.18 seconds
Started Jul 02 08:09:03 AM PDT 24
Finished Jul 02 08:09:16 AM PDT 24
Peak memory 213596 kb
Host smart-e2eec418-65fc-48f1-b308-4eb6eda3d2e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091346508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.4091346508
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3539886770
Short name T1409
Test name
Test status
Simulation time 1149562120 ps
CPU time 3.94 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:09:09 AM PDT 24
Peak memory 204764 kb
Host smart-5d4e1a0c-0fe6-43ec-9e6d-d8257ad0bb7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539886770 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3539886770
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2253024166
Short name T1381
Test name
Test status
Simulation time 1861655433 ps
CPU time 4.89 seconds
Started Jul 02 08:09:00 AM PDT 24
Finished Jul 02 08:09:09 AM PDT 24
Peak memory 204772 kb
Host smart-1117842c-d530-4ce1-889f-3ec07ea80dcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253024166 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2253024166
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.3129115520
Short name T1176
Test name
Test status
Simulation time 10735151119 ps
CPU time 15.1 seconds
Started Jul 02 08:09:04 AM PDT 24
Finished Jul 02 08:09:22 AM PDT 24
Peak memory 548240 kb
Host smart-3ac15408-1f0a-4e4d-b2d9-2db3e101780d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129115520 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.3129115520
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.1672672773
Short name T1385
Test name
Test status
Simulation time 3522545860 ps
CPU time 20.11 seconds
Started Jul 02 08:09:03 AM PDT 24
Finished Jul 02 08:09:27 AM PDT 24
Peak memory 204076 kb
Host smart-cc9da2ee-252d-4404-910c-8e906762baea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672672773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_tar
get_smoke.1672672773
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.1269490563
Short name T1122
Test name
Test status
Simulation time 3651765397 ps
CPU time 81.03 seconds
Started Jul 02 08:09:05 AM PDT 24
Finished Jul 02 08:10:29 AM PDT 24
Peak memory 210252 kb
Host smart-1fc071f9-21cd-4ed0-920e-c48dc70b7dcb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269490563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.1269490563
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.2994661751
Short name T987
Test name
Test status
Simulation time 35724452001 ps
CPU time 77.03 seconds
Started Jul 02 08:08:59 AM PDT 24
Finished Jul 02 08:10:20 AM PDT 24
Peak memory 1183432 kb
Host smart-27f70df8-5226-429e-a928-5ea0b5ea15ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994661751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.2994661751
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.1035015447
Short name T511
Test name
Test status
Simulation time 32979657330 ps
CPU time 77.18 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:10:22 AM PDT 24
Peak memory 842360 kb
Host smart-f5e4d03d-a5e2-43aa-bf2c-6273e07ca6b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035015447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.1035015447
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.3722846323
Short name T1532
Test name
Test status
Simulation time 2911289559 ps
CPU time 7.38 seconds
Started Jul 02 08:09:04 AM PDT 24
Finished Jul 02 08:09:15 AM PDT 24
Peak memory 204852 kb
Host smart-61f6e568-6ce5-42f9-9455-6e9b5ba3f059
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722846323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.3722846323
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.1657835047
Short name T942
Test name
Test status
Simulation time 405197367 ps
CPU time 5.47 seconds
Started Jul 02 08:09:05 AM PDT 24
Finished Jul 02 08:09:14 AM PDT 24
Peak memory 204788 kb
Host smart-b9531d81-1cd1-4439-9fe3-edb3a7cd1e90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657835047 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.1657835047
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.435112528
Short name T1137
Test name
Test status
Simulation time 19502740 ps
CPU time 0.71 seconds
Started Jul 02 08:09:59 AM PDT 24
Finished Jul 02 08:10:02 AM PDT 24
Peak memory 204460 kb
Host smart-c3c15d79-0600-49e8-9230-539687d5a495
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435112528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.435112528
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.254523130
Short name T1383
Test name
Test status
Simulation time 126853712 ps
CPU time 3.99 seconds
Started Jul 02 08:09:53 AM PDT 24
Finished Jul 02 08:09:59 AM PDT 24
Peak memory 213132 kb
Host smart-5a54d848-7f23-4cc4-b621-f16df0c198ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254523130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.254523130
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.1178894236
Short name T1199
Test name
Test status
Simulation time 404652891 ps
CPU time 7.2 seconds
Started Jul 02 08:09:51 AM PDT 24
Finished Jul 02 08:10:00 AM PDT 24
Peak memory 293084 kb
Host smart-0f11555c-1143-493f-abb8-8cb09c6792ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178894236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.1178894236
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.2890127987
Short name T1365
Test name
Test status
Simulation time 11636099729 ps
CPU time 212.23 seconds
Started Jul 02 08:09:54 AM PDT 24
Finished Jul 02 08:13:28 AM PDT 24
Peak memory 900896 kb
Host smart-779a10a3-a6ab-4d4f-b5e4-c87047e12778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890127987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.2890127987
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.690302074
Short name T152
Test name
Test status
Simulation time 9246340786 ps
CPU time 158.07 seconds
Started Jul 02 08:09:53 AM PDT 24
Finished Jul 02 08:12:32 AM PDT 24
Peak memory 736264 kb
Host smart-b78e6634-cf49-4b18-9647-feef0902cb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690302074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.690302074
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.1444671779
Short name T540
Test name
Test status
Simulation time 101946752 ps
CPU time 1.1 seconds
Started Jul 02 08:09:50 AM PDT 24
Finished Jul 02 08:09:53 AM PDT 24
Peak memory 204664 kb
Host smart-ef1367b6-9454-4217-8c9c-52c043d36bf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444671779 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_f
mt.1444671779
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.1433239837
Short name T983
Test name
Test status
Simulation time 462598438 ps
CPU time 2.77 seconds
Started Jul 02 08:09:50 AM PDT 24
Finished Jul 02 08:09:55 AM PDT 24
Peak memory 204824 kb
Host smart-4ed992de-1f3e-4e41-a3cd-abcfe71755f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433239837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.1433239837
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.3329444207
Short name T607
Test name
Test status
Simulation time 22702265993 ps
CPU time 330.73 seconds
Started Jul 02 08:09:52 AM PDT 24
Finished Jul 02 08:15:25 AM PDT 24
Peak memory 1294512 kb
Host smart-9810645c-299d-4af3-80da-de28d6f706a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329444207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.3329444207
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.1317880143
Short name T1115
Test name
Test status
Simulation time 627905878 ps
CPU time 8.49 seconds
Started Jul 02 08:09:56 AM PDT 24
Finished Jul 02 08:10:06 AM PDT 24
Peak memory 204700 kb
Host smart-e4c5607a-77c7-4b7a-a436-bc6017137899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317880143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.1317880143
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.2173984741
Short name T438
Test name
Test status
Simulation time 5362218185 ps
CPU time 45.47 seconds
Started Jul 02 08:09:58 AM PDT 24
Finished Jul 02 08:10:46 AM PDT 24
Peak memory 401344 kb
Host smart-3a76ef91-a40a-4448-adb7-ceeecbb6fa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173984741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.2173984741
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.3531438245
Short name T683
Test name
Test status
Simulation time 16940927 ps
CPU time 0.62 seconds
Started Jul 02 08:09:49 AM PDT 24
Finished Jul 02 08:09:52 AM PDT 24
Peak memory 204508 kb
Host smart-e7d8caa6-14dc-429f-abcb-c6255e2fe203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531438245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.3531438245
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.2050839180
Short name T36
Test name
Test status
Simulation time 7600472468 ps
CPU time 300.32 seconds
Started Jul 02 08:09:51 AM PDT 24
Finished Jul 02 08:14:54 AM PDT 24
Peak memory 380584 kb
Host smart-50c88a83-ba4d-4f67-b161-b4f62b1634f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050839180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.2050839180
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.3998657658
Short name T951
Test name
Test status
Simulation time 218747707 ps
CPU time 2.88 seconds
Started Jul 02 08:09:50 AM PDT 24
Finished Jul 02 08:09:55 AM PDT 24
Peak memory 212916 kb
Host smart-ae9ea72c-9828-4bb1-abb6-d41f6abfa160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998657658 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.3998657658
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.775018894
Short name T1499
Test name
Test status
Simulation time 2001367293 ps
CPU time 40.55 seconds
Started Jul 02 08:09:57 AM PDT 24
Finished Jul 02 08:10:39 AM PDT 24
Peak memory 400380 kb
Host smart-f1c5faad-08d5-4e61-9cfa-dbff54d0a040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775018894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.775018894
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.3199364625
Short name T120
Test name
Test status
Simulation time 36622884933 ps
CPU time 636.96 seconds
Started Jul 02 08:09:52 AM PDT 24
Finished Jul 02 08:20:31 AM PDT 24
Peak memory 2176848 kb
Host smart-29c8f03c-68c7-42f8-b5ca-756753d1e322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199364625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.3199364625
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.1335236684
Short name T443
Test name
Test status
Simulation time 840841349 ps
CPU time 6.18 seconds
Started Jul 02 08:09:50 AM PDT 24
Finished Jul 02 08:09:59 AM PDT 24
Peak memory 212988 kb
Host smart-26faaced-7575-42b8-80bf-a011447bf436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335236684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.1335236684
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.3577324786
Short name T789
Test name
Test status
Simulation time 875267371 ps
CPU time 4.46 seconds
Started Jul 02 08:09:59 AM PDT 24
Finished Jul 02 08:10:06 AM PDT 24
Peak memory 204844 kb
Host smart-b3d50d28-4206-4afa-a654-8eac430e2dbc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577324786 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.3577324786
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3197787895
Short name T1278
Test name
Test status
Simulation time 621725786 ps
CPU time 1.22 seconds
Started Jul 02 08:09:58 AM PDT 24
Finished Jul 02 08:10:01 AM PDT 24
Peak memory 204796 kb
Host smart-c9491d07-6776-41fc-b878-fe22c71c2eb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197787895 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3197787895
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.3202240645
Short name T615
Test name
Test status
Simulation time 277176883 ps
CPU time 0.9 seconds
Started Jul 02 08:09:55 AM PDT 24
Finished Jul 02 08:09:58 AM PDT 24
Peak memory 204604 kb
Host smart-e906fdc6-7746-41da-a039-d0cb775098be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202240645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.3202240645
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.89663785
Short name T296
Test name
Test status
Simulation time 249399592 ps
CPU time 1.6 seconds
Started Jul 02 08:09:58 AM PDT 24
Finished Jul 02 08:10:02 AM PDT 24
Peak memory 204608 kb
Host smart-7a65d1b1-d038-45f3-a4c7-b06b7619a823
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89663785 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.89663785
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.3448222560
Short name T958
Test name
Test status
Simulation time 278997366 ps
CPU time 1.21 seconds
Started Jul 02 08:09:58 AM PDT 24
Finished Jul 02 08:10:01 AM PDT 24
Peak memory 204608 kb
Host smart-a274fe8d-bdaa-4ec1-b7bc-e987e979f495
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448222560 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.3448222560
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.3953500407
Short name T290
Test name
Test status
Simulation time 1440140753 ps
CPU time 3.71 seconds
Started Jul 02 08:09:57 AM PDT 24
Finished Jul 02 08:10:02 AM PDT 24
Peak memory 204860 kb
Host smart-bd73c3b4-3675-41bc-8712-f987d354c76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953500407 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_hrst.3953500407
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.508933140
Short name T407
Test name
Test status
Simulation time 532056319 ps
CPU time 3.15 seconds
Started Jul 02 08:09:55 AM PDT 24
Finished Jul 02 08:10:00 AM PDT 24
Peak memory 204744 kb
Host smart-6ef0e962-245c-4953-a5f9-fce992bc9481
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508933140 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 10.i2c_target_intr_smoke.508933140
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.644987512
Short name T728
Test name
Test status
Simulation time 8256185058 ps
CPU time 21.17 seconds
Started Jul 02 08:09:59 AM PDT 24
Finished Jul 02 08:10:22 AM PDT 24
Peak memory 431728 kb
Host smart-0c0dafc8-a809-49c7-8f02-bc33c9b58eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644987512 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.644987512
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1488811692
Short name T522
Test name
Test status
Simulation time 2165209375 ps
CPU time 5.6 seconds
Started Jul 02 08:09:52 AM PDT 24
Finished Jul 02 08:10:00 AM PDT 24
Peak memory 204880 kb
Host smart-c941bcab-ab97-4903-ab92-6f6afc270b2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488811692 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1488811692
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.4015241614
Short name T1120
Test name
Test status
Simulation time 734263163 ps
CPU time 30.65 seconds
Started Jul 02 08:09:59 AM PDT 24
Finished Jul 02 08:10:31 AM PDT 24
Peak memory 204716 kb
Host smart-2eb564c5-5d8f-4ac1-8d2f-ea769f37ae31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015241614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_rd.4015241614
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.3459526251
Short name T773
Test name
Test status
Simulation time 49188286197 ps
CPU time 366.02 seconds
Started Jul 02 08:09:54 AM PDT 24
Finished Jul 02 08:16:02 AM PDT 24
Peak memory 3760048 kb
Host smart-61733e04-4a9e-42a0-90e1-667d885c5f62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459526251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2
c_target_stress_wr.3459526251
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.1665500915
Short name T410
Test name
Test status
Simulation time 13658332504 ps
CPU time 48.79 seconds
Started Jul 02 08:09:57 AM PDT 24
Finished Jul 02 08:10:48 AM PDT 24
Peak memory 709220 kb
Host smart-c2b3ef49-56e4-4738-87ea-760bab392460
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665500915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.1665500915
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.2975032988
Short name T287
Test name
Test status
Simulation time 2443774057 ps
CPU time 6.15 seconds
Started Jul 02 08:09:56 AM PDT 24
Finished Jul 02 08:10:04 AM PDT 24
Peak memory 204800 kb
Host smart-40e76ef3-236a-4809-8390-3e77cc655ba7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975032988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.2975032988
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.3354272218
Short name T20
Test name
Test status
Simulation time 177177628 ps
CPU time 2.29 seconds
Started Jul 02 08:09:58 AM PDT 24
Finished Jul 02 08:10:03 AM PDT 24
Peak memory 204788 kb
Host smart-da7c5930-369b-4b13-bdf8-0415b5468a2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354272218 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.3354272218
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.141435501
Short name T1077
Test name
Test status
Simulation time 17746861 ps
CPU time 0.65 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:10:09 AM PDT 24
Peak memory 204404 kb
Host smart-7513d076-4e71-469d-a0c2-e1f31ebc4ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141435501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.141435501
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.335757271
Short name T1241
Test name
Test status
Simulation time 2364395285 ps
CPU time 1.91 seconds
Started Jul 02 08:10:04 AM PDT 24
Finished Jul 02 08:10:08 AM PDT 24
Peak memory 213164 kb
Host smart-e5da1e8c-c324-43de-ae46-38f1d31793d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335757271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.335757271
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.2616575404
Short name T782
Test name
Test status
Simulation time 1185868584 ps
CPU time 5.63 seconds
Started Jul 02 08:10:05 AM PDT 24
Finished Jul 02 08:10:12 AM PDT 24
Peak memory 264664 kb
Host smart-ceca9caa-03c3-4019-965b-edb1408ad561
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616575404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_emp
ty.2616575404
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1165710184
Short name T76
Test name
Test status
Simulation time 3837911506 ps
CPU time 66.58 seconds
Started Jul 02 08:10:05 AM PDT 24
Finished Jul 02 08:11:13 AM PDT 24
Peak memory 654196 kb
Host smart-4d0214d9-4446-429d-86f8-93ff5e43f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165710184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1165710184
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.928951482
Short name T664
Test name
Test status
Simulation time 2189637985 ps
CPU time 77.07 seconds
Started Jul 02 08:09:58 AM PDT 24
Finished Jul 02 08:11:17 AM PDT 24
Peak memory 735048 kb
Host smart-1c966cd2-aa25-468b-8916-dff0d16ec9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928951482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.928951482
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.3917286451
Short name T304
Test name
Test status
Simulation time 173757674 ps
CPU time 4.56 seconds
Started Jul 02 08:10:02 AM PDT 24
Finished Jul 02 08:10:08 AM PDT 24
Peak memory 231528 kb
Host smart-81af4269-cbde-4aa3-8fe5-17adee4f0321
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917286451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.3917286451
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.4124308861
Short name T430
Test name
Test status
Simulation time 15560908840 ps
CPU time 107.7 seconds
Started Jul 02 08:09:58 AM PDT 24
Finished Jul 02 08:11:48 AM PDT 24
Peak memory 1138992 kb
Host smart-df082bc4-eabf-4fff-8122-e03b09518619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124308861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.4124308861
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.4256177299
Short name T1281
Test name
Test status
Simulation time 1020205516 ps
CPU time 20.72 seconds
Started Jul 02 08:10:02 AM PDT 24
Finished Jul 02 08:10:24 AM PDT 24
Peak memory 204812 kb
Host smart-bb988ede-80c6-4846-83a6-0c68c4263186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256177299 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.4256177299
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.3871723063
Short name T1023
Test name
Test status
Simulation time 1095796409 ps
CPU time 16.05 seconds
Started Jul 02 08:10:06 AM PDT 24
Finished Jul 02 08:10:23 AM PDT 24
Peak memory 279916 kb
Host smart-0ccd4b41-854a-45b6-866e-ea80e54e87ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871723063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.3871723063
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2755666750
Short name T535
Test name
Test status
Simulation time 52851820 ps
CPU time 0.68 seconds
Started Jul 02 08:09:57 AM PDT 24
Finished Jul 02 08:09:59 AM PDT 24
Peak memory 204512 kb
Host smart-5c6dbb8c-5e7d-4e96-bdf4-2275d77830b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755666750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2755666750
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.1483457671
Short name T600
Test name
Test status
Simulation time 7758795468 ps
CPU time 457.74 seconds
Started Jul 02 08:10:02 AM PDT 24
Finished Jul 02 08:17:41 AM PDT 24
Peak memory 1378236 kb
Host smart-f1a78765-dca7-4b2c-9567-5b47115a62f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483457671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.1483457671
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.1267790058
Short name T530
Test name
Test status
Simulation time 177902649 ps
CPU time 1.05 seconds
Started Jul 02 08:10:03 AM PDT 24
Finished Jul 02 08:10:05 AM PDT 24
Peak memory 204504 kb
Host smart-034dfdb7-5c8e-464b-8371-6a423b574bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267790058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.1267790058
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.971517877
Short name T481
Test name
Test status
Simulation time 4835849779 ps
CPU time 74.62 seconds
Started Jul 02 08:09:59 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 328128 kb
Host smart-adf33a7b-f8bf-4ad9-aceb-5c37707ecdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971517877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.971517877
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.3149505755
Short name T692
Test name
Test status
Simulation time 15779359734 ps
CPU time 91.56 seconds
Started Jul 02 08:10:03 AM PDT 24
Finished Jul 02 08:11:37 AM PDT 24
Peak memory 474596 kb
Host smart-b588cbad-0c51-4b55-928a-e1d2a6d0112a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149505755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.3149505755
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.2467002559
Short name T437
Test name
Test status
Simulation time 553618542 ps
CPU time 25.36 seconds
Started Jul 02 08:10:04 AM PDT 24
Finished Jul 02 08:10:31 AM PDT 24
Peak memory 213016 kb
Host smart-4574c15c-8143-4964-a054-0aa8fe3e0842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467002559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.2467002559
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.591537474
Short name T621
Test name
Test status
Simulation time 2371253777 ps
CPU time 3 seconds
Started Jul 02 08:10:04 AM PDT 24
Finished Jul 02 08:10:08 AM PDT 24
Peak memory 204856 kb
Host smart-0f0cda1f-c0d8-413e-852c-26d33a2862da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591537474 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.591537474
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3704291165
Short name T504
Test name
Test status
Simulation time 699528461 ps
CPU time 1.34 seconds
Started Jul 02 08:10:03 AM PDT 24
Finished Jul 02 08:10:06 AM PDT 24
Peak memory 205028 kb
Host smart-e02c16b7-2d1a-4e67-a6f0-1adf306a6c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704291165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3704291165
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1598448282
Short name T1315
Test name
Test status
Simulation time 1662487083 ps
CPU time 1.25 seconds
Started Jul 02 08:10:09 AM PDT 24
Finished Jul 02 08:10:13 AM PDT 24
Peak memory 205192 kb
Host smart-3e8ce7d9-dfff-4316-8d86-60ccbb30eb1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598448282 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1598448282
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.2530082068
Short name T538
Test name
Test status
Simulation time 1242483163 ps
CPU time 1.94 seconds
Started Jul 02 08:10:04 AM PDT 24
Finished Jul 02 08:10:07 AM PDT 24
Peak memory 204792 kb
Host smart-4d11cc2a-1ba1-4abd-85f8-c6777c616c07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530082068 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.2530082068
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.1342707478
Short name T1014
Test name
Test status
Simulation time 119828084 ps
CPU time 1.21 seconds
Started Jul 02 08:10:02 AM PDT 24
Finished Jul 02 08:10:04 AM PDT 24
Peak memory 204576 kb
Host smart-dda52e85-9b67-4c08-aac1-ff2c58e46ef5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342707478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.1342707478
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3172469294
Short name T1061
Test name
Test status
Simulation time 1416857720 ps
CPU time 6.73 seconds
Started Jul 02 08:10:02 AM PDT 24
Finished Jul 02 08:10:10 AM PDT 24
Peak memory 204852 kb
Host smart-df2c1e8f-a79d-4d40-8f06-4431dd2c9966
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172469294 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3172469294
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.4095127502
Short name T954
Test name
Test status
Simulation time 9129749973 ps
CPU time 6.73 seconds
Started Jul 02 08:10:04 AM PDT 24
Finished Jul 02 08:10:12 AM PDT 24
Peak memory 204960 kb
Host smart-38db3c0f-497b-47f9-870e-91562b671c0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095127502 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.4095127502
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.4170946107
Short name T160
Test name
Test status
Simulation time 478865600 ps
CPU time 7.61 seconds
Started Jul 02 08:10:02 AM PDT 24
Finished Jul 02 08:10:11 AM PDT 24
Peak memory 204720 kb
Host smart-df98ead6-a095-4fdf-8393-d1d79d8dd685
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170946107 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.4170946107
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2202087478
Short name T1444
Test name
Test status
Simulation time 9565290730 ps
CPU time 31.84 seconds
Started Jul 02 08:10:09 AM PDT 24
Finished Jul 02 08:10:43 AM PDT 24
Peak memory 229620 kb
Host smart-f60ec5ef-eb2c-4c53-84a9-2a1b59877f90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202087478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2202087478
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.274093262
Short name T259
Test name
Test status
Simulation time 51294121528 ps
CPU time 1292.2 seconds
Started Jul 02 08:10:09 AM PDT 24
Finished Jul 02 08:31:44 AM PDT 24
Peak memory 7922976 kb
Host smart-d26eed58-c595-4471-9566-9f9b6bab7d48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274093262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c
_target_stress_wr.274093262
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.2671142196
Short name T814
Test name
Test status
Simulation time 14556719391 ps
CPU time 80.32 seconds
Started Jul 02 08:10:09 AM PDT 24
Finished Jul 02 08:11:32 AM PDT 24
Peak memory 939552 kb
Host smart-95fef7a2-c588-4290-959f-22b6417fb6ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671142196 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.2671142196
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1823125405
Short name T572
Test name
Test status
Simulation time 22888847024 ps
CPU time 7.22 seconds
Started Jul 02 08:10:02 AM PDT 24
Finished Jul 02 08:10:10 AM PDT 24
Peak memory 213344 kb
Host smart-c09abf05-f55c-4d55-ae0d-85d876fb48a3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823125405 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1823125405
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.1790115524
Short name T337
Test name
Test status
Simulation time 93713694 ps
CPU time 1.98 seconds
Started Jul 02 08:10:07 AM PDT 24
Finished Jul 02 08:10:09 AM PDT 24
Peak memory 204836 kb
Host smart-865463f5-4ea8-4483-a5d8-14553c159e2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790115524 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.1790115524
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/12.i2c_alert_test.1151514104
Short name T154
Test name
Test status
Simulation time 17950865 ps
CPU time 0.64 seconds
Started Jul 02 08:10:13 AM PDT 24
Finished Jul 02 08:10:16 AM PDT 24
Peak memory 204464 kb
Host smart-e3212ac0-11d8-4c71-9ec2-0636b7dbe994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151514104 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.1151514104
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.3225881215
Short name T1223
Test name
Test status
Simulation time 167137518 ps
CPU time 1.68 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:10:13 AM PDT 24
Peak memory 221144 kb
Host smart-3b9a3ccf-e641-4e50-a3b2-e77d27148bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225881215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.3225881215
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2607323339
Short name T83
Test name
Test status
Simulation time 1153079918 ps
CPU time 14.92 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:10:26 AM PDT 24
Peak memory 262840 kb
Host smart-0b992cff-c0cc-42bd-92b1-3bcb4ccfd266
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607323339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2607323339
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.2531261317
Short name T1351
Test name
Test status
Simulation time 7024579943 ps
CPU time 49.47 seconds
Started Jul 02 08:10:07 AM PDT 24
Finished Jul 02 08:10:58 AM PDT 24
Peak memory 387300 kb
Host smart-209193a5-44ea-42e1-86fa-d93d54409853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531261317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.2531261317
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.3322796594
Short name T837
Test name
Test status
Simulation time 2175247547 ps
CPU time 159.24 seconds
Started Jul 02 08:10:10 AM PDT 24
Finished Jul 02 08:12:52 AM PDT 24
Peak memory 744256 kb
Host smart-a12be264-c924-43fd-851c-cce5e0e2a9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322796594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.3322796594
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.2003755247
Short name T919
Test name
Test status
Simulation time 94596476 ps
CPU time 0.84 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:10:09 AM PDT 24
Peak memory 204440 kb
Host smart-21c1961b-ad9c-45a2-9e4b-c011abbfed17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003755247 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.2003755247
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.2087340446
Short name T747
Test name
Test status
Simulation time 453699408 ps
CPU time 6.06 seconds
Started Jul 02 08:10:11 AM PDT 24
Finished Jul 02 08:10:19 AM PDT 24
Peak memory 204728 kb
Host smart-b404ed11-0c59-4d5b-bf34-fe2acbebc218
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087340446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.2087340446
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.1826794791
Short name T103
Test name
Test status
Simulation time 10895444795 ps
CPU time 148.01 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:12:37 AM PDT 24
Peak memory 1532760 kb
Host smart-6f7d7b3c-43db-4b8a-815d-44348eb58472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826794791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.1826794791
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.193681072
Short name T254
Test name
Test status
Simulation time 3902508002 ps
CPU time 8.39 seconds
Started Jul 02 08:10:14 AM PDT 24
Finished Jul 02 08:10:25 AM PDT 24
Peak memory 204892 kb
Host smart-48c66d90-870d-4f72-9c5a-d8e01e5e134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193681072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.193681072
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_override.1589677982
Short name T836
Test name
Test status
Simulation time 16661971 ps
CPU time 0.68 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:10:10 AM PDT 24
Peak memory 204528 kb
Host smart-c3916b94-94bd-4152-b071-fe2f53ffdfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589677982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.1589677982
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.4251339044
Short name T1298
Test name
Test status
Simulation time 2894053650 ps
CPU time 73.29 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:11:22 AM PDT 24
Peak memory 476360 kb
Host smart-9007585e-1cb6-4c55-88c2-a31025edc742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251339044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.4251339044
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.310981136
Short name T336
Test name
Test status
Simulation time 2653926810 ps
CPU time 10.97 seconds
Started Jul 02 08:10:07 AM PDT 24
Finished Jul 02 08:10:19 AM PDT 24
Peak memory 213276 kb
Host smart-eb76361f-730c-4f65-8314-86f7a156c259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310981136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.310981136
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.3887961775
Short name T643
Test name
Test status
Simulation time 1264476054 ps
CPU time 55.02 seconds
Started Jul 02 08:10:11 AM PDT 24
Finished Jul 02 08:11:09 AM PDT 24
Peak memory 252552 kb
Host smart-aa1db7ff-1643-4184-9d0e-83ea076fb0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887961775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.3887961775
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.2899937733
Short name T408
Test name
Test status
Simulation time 3331056184 ps
CPU time 36.96 seconds
Started Jul 02 08:10:09 AM PDT 24
Finished Jul 02 08:10:48 AM PDT 24
Peak memory 213072 kb
Host smart-be978add-5bb2-4e56-85bf-ad9b53db8677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899937733 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.2899937733
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.3657371092
Short name T1234
Test name
Test status
Simulation time 1561816249 ps
CPU time 1.31 seconds
Started Jul 02 08:10:14 AM PDT 24
Finished Jul 02 08:10:18 AM PDT 24
Peak memory 204808 kb
Host smart-4dddce49-1aa9-4cc8-be87-98cd446479ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657371092 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.3657371092
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.3654119716
Short name T367
Test name
Test status
Simulation time 602707047 ps
CPU time 1.86 seconds
Started Jul 02 08:10:12 AM PDT 24
Finished Jul 02 08:10:16 AM PDT 24
Peak memory 204684 kb
Host smart-a2fbbc59-8d4a-4704-b0be-7e41b9fc513b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654119716 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.3654119716
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.3263677080
Short name T636
Test name
Test status
Simulation time 497511439 ps
CPU time 1.08 seconds
Started Jul 02 08:10:14 AM PDT 24
Finished Jul 02 08:10:17 AM PDT 24
Peak memory 204608 kb
Host smart-04856bc6-2f35-455d-9b06-84f5d9301431
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263677080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.3263677080
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_hrst.207682493
Short name T1519
Test name
Test status
Simulation time 449299500 ps
CPU time 3.2 seconds
Started Jul 02 08:10:14 AM PDT 24
Finished Jul 02 08:10:20 AM PDT 24
Peak memory 204760 kb
Host smart-a9a33dad-a355-49de-8df0-21773c7f7cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207682493 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.i2c_target_hrst.207682493
Directory /workspace/12.i2c_target_hrst/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.756271569
Short name T505
Test name
Test status
Simulation time 1768460740 ps
CPU time 7.14 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:10:17 AM PDT 24
Peak memory 213024 kb
Host smart-946f5ab7-3183-4275-8303-4926e9871c16
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756271569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.756271569
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.2676917935
Short name T1425
Test name
Test status
Simulation time 10134297706 ps
CPU time 42.12 seconds
Started Jul 02 08:10:11 AM PDT 24
Finished Jul 02 08:10:56 AM PDT 24
Peak memory 847348 kb
Host smart-50470b23-ccd2-4e6a-b8ec-b5bf8af30c89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676917935 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.2676917935
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.3054570871
Short name T889
Test name
Test status
Simulation time 5649668633 ps
CPU time 14.71 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:10:25 AM PDT 24
Peak memory 204944 kb
Host smart-56d8d71c-9180-4972-83d2-47a45b061116
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054570871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.3054570871
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.618609329
Short name T1326
Test name
Test status
Simulation time 1640570754 ps
CPU time 28.14 seconds
Started Jul 02 08:10:12 AM PDT 24
Finished Jul 02 08:10:43 AM PDT 24
Peak memory 236416 kb
Host smart-dc70d081-b16a-4f56-9c08-3b08d4c19081
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618609329 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c
_target_stress_rd.618609329
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.3346882122
Short name T359
Test name
Test status
Simulation time 37021012628 ps
CPU time 61.77 seconds
Started Jul 02 08:10:11 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 1058812 kb
Host smart-0ee3dd06-25b1-42b5-8d1a-562c55942fde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346882122 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.3346882122
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.4148579621
Short name T350
Test name
Test status
Simulation time 4664156430 ps
CPU time 18.68 seconds
Started Jul 02 08:10:08 AM PDT 24
Finished Jul 02 08:10:29 AM PDT 24
Peak memory 402368 kb
Host smart-fe6c97c9-add4-4a9b-8196-b1be6f9ab178
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148579621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_
target_stretch.4148579621
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.2109464621
Short name T1116
Test name
Test status
Simulation time 6604099767 ps
CPU time 6.84 seconds
Started Jul 02 08:10:09 AM PDT 24
Finished Jul 02 08:10:18 AM PDT 24
Peak memory 220904 kb
Host smart-bb4d95c6-714e-471c-97ae-cd3278a9b51f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109464621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.2109464621
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.1453453111
Short name T1406
Test name
Test status
Simulation time 564588545 ps
CPU time 7.32 seconds
Started Jul 02 08:10:11 AM PDT 24
Finished Jul 02 08:10:21 AM PDT 24
Peak memory 204692 kb
Host smart-b6b01884-ad65-4fba-8707-e3012b8d36aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453453111 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.1453453111
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_alert_test.3667239675
Short name T1373
Test name
Test status
Simulation time 15504190 ps
CPU time 0.64 seconds
Started Jul 02 08:10:20 AM PDT 24
Finished Jul 02 08:10:22 AM PDT 24
Peak memory 204460 kb
Host smart-bb103634-349d-405f-afe8-29bb5f7a4246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667239675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.3667239675
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.905127094
Short name T581
Test name
Test status
Simulation time 233412567 ps
CPU time 8.54 seconds
Started Jul 02 08:10:20 AM PDT 24
Finished Jul 02 08:10:30 AM PDT 24
Peak memory 213704 kb
Host smart-7b397178-905f-4443-90b3-0a5300401750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905127094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.905127094
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.1015479123
Short name T1445
Test name
Test status
Simulation time 2382717063 ps
CPU time 14.93 seconds
Started Jul 02 08:10:15 AM PDT 24
Finished Jul 02 08:10:32 AM PDT 24
Peak memory 351348 kb
Host smart-c0eb34fa-cb5c-4b60-bc4a-b64ff39e4c14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015479123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_emp
ty.1015479123
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.1772492949
Short name T1413
Test name
Test status
Simulation time 3461734472 ps
CPU time 55.68 seconds
Started Jul 02 08:10:14 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 581856 kb
Host smart-0550384b-aa4f-4533-99f2-649063f91128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772492949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.1772492949
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.1424033544
Short name T559
Test name
Test status
Simulation time 9715918705 ps
CPU time 65.39 seconds
Started Jul 02 08:10:15 AM PDT 24
Finished Jul 02 08:11:22 AM PDT 24
Peak memory 497480 kb
Host smart-b75500eb-d826-49dc-b21b-b6cbd2359e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424033544 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.1424033544
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1637640664
Short name T755
Test name
Test status
Simulation time 281397413 ps
CPU time 3.71 seconds
Started Jul 02 08:10:13 AM PDT 24
Finished Jul 02 08:10:19 AM PDT 24
Peak memory 227624 kb
Host smart-bc4d0ecb-4d03-48b8-8672-997bda4d5240
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637640664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1637640664
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2714990490
Short name T678
Test name
Test status
Simulation time 34602499691 ps
CPU time 135.56 seconds
Started Jul 02 08:10:15 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 1278444 kb
Host smart-e9516d4c-bbd8-481c-9467-d76299b6fe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714990490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2714990490
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.1566096881
Short name T1245
Test name
Test status
Simulation time 363863279 ps
CPU time 15.25 seconds
Started Jul 02 08:10:21 AM PDT 24
Finished Jul 02 08:10:38 AM PDT 24
Peak memory 204792 kb
Host smart-712ed5b3-26e7-42ad-8156-a599604415c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566096881 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.1566096881
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.3668034690
Short name T1213
Test name
Test status
Simulation time 3021174096 ps
CPU time 28.4 seconds
Started Jul 02 08:10:22 AM PDT 24
Finished Jul 02 08:10:52 AM PDT 24
Peak memory 342964 kb
Host smart-d0c30334-e897-4a6b-a7ee-998c794ff204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668034690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.3668034690
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/13.i2c_host_override.1763408442
Short name T1461
Test name
Test status
Simulation time 17740322 ps
CPU time 0.72 seconds
Started Jul 02 08:10:15 AM PDT 24
Finished Jul 02 08:10:18 AM PDT 24
Peak memory 204536 kb
Host smart-0fec66a8-f043-47f1-b102-38fc0ad7b08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763408442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.1763408442
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.307471175
Short name T488
Test name
Test status
Simulation time 26842941444 ps
CPU time 369.64 seconds
Started Jul 02 08:10:15 AM PDT 24
Finished Jul 02 08:16:27 AM PDT 24
Peak memory 252372 kb
Host smart-fe5afdc0-5734-4707-9cb6-7b9fa453a3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307471175 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.307471175
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.531276112
Short name T1384
Test name
Test status
Simulation time 320609859 ps
CPU time 4.25 seconds
Started Jul 02 08:10:21 AM PDT 24
Finished Jul 02 08:10:27 AM PDT 24
Peak memory 236684 kb
Host smart-21f370f5-d991-4758-9e75-3af7118266c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531276112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.531276112
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1489524297
Short name T640
Test name
Test status
Simulation time 1714815247 ps
CPU time 79.89 seconds
Started Jul 02 08:10:13 AM PDT 24
Finished Jul 02 08:11:35 AM PDT 24
Peak memory 349204 kb
Host smart-e8602e87-a93a-46f0-92d6-506b03ce193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489524297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1489524297
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.3589047744
Short name T750
Test name
Test status
Simulation time 2364100150 ps
CPU time 14.91 seconds
Started Jul 02 08:10:18 AM PDT 24
Finished Jul 02 08:10:34 AM PDT 24
Peak memory 229288 kb
Host smart-2f6e4090-b42a-4885-8552-344d8f22d499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589047744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.3589047744
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.544988069
Short name T973
Test name
Test status
Simulation time 419359854 ps
CPU time 2.65 seconds
Started Jul 02 08:10:20 AM PDT 24
Finished Jul 02 08:10:24 AM PDT 24
Peak memory 204844 kb
Host smart-588a3bf2-85fd-4f14-b97a-ca0d058e2331
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544988069 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.544988069
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1923217650
Short name T1270
Test name
Test status
Simulation time 194610124 ps
CPU time 1.23 seconds
Started Jul 02 08:10:21 AM PDT 24
Finished Jul 02 08:10:24 AM PDT 24
Peak memory 204632 kb
Host smart-25fb6958-3256-4b54-a4d3-788bc0cb48c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923217650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1923217650
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.3228548767
Short name T721
Test name
Test status
Simulation time 356203417 ps
CPU time 1.36 seconds
Started Jul 02 08:10:21 AM PDT 24
Finished Jul 02 08:10:24 AM PDT 24
Peak memory 204824 kb
Host smart-92d07b0f-3e09-4464-afb7-bd636ff96464
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228548767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.i2c_target_fifo_reset_tx.3228548767
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.2572094597
Short name T471
Test name
Test status
Simulation time 232708896 ps
CPU time 1.51 seconds
Started Jul 02 08:10:22 AM PDT 24
Finished Jul 02 08:10:25 AM PDT 24
Peak memory 204556 kb
Host smart-e5dbc221-e2f9-4f2b-8fe3-8b1a727d3932
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572094597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.2572094597
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.3009501589
Short name T969
Test name
Test status
Simulation time 397748668 ps
CPU time 1.05 seconds
Started Jul 02 08:10:22 AM PDT 24
Finished Jul 02 08:10:24 AM PDT 24
Peak memory 204624 kb
Host smart-37998e2c-8f47-47f4-b35c-31eaa8e76ffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009501589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.3009501589
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.953533887
Short name T634
Test name
Test status
Simulation time 697942537 ps
CPU time 4.18 seconds
Started Jul 02 08:10:20 AM PDT 24
Finished Jul 02 08:10:25 AM PDT 24
Peak memory 204812 kb
Host smart-bd4654d8-a988-49a7-87f6-c911bcb301fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953533887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 13.i2c_target_intr_smoke.953533887
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.3404460470
Short name T1371
Test name
Test status
Simulation time 18439397702 ps
CPU time 94.71 seconds
Started Jul 02 08:10:22 AM PDT 24
Finished Jul 02 08:11:58 AM PDT 24
Peak memory 1355748 kb
Host smart-d8b45153-60d4-4c4b-ba5f-bae3f4a4645e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404460470 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.3404460470
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.3395999762
Short name T525
Test name
Test status
Simulation time 6333718765 ps
CPU time 15.35 seconds
Started Jul 02 08:10:21 AM PDT 24
Finished Jul 02 08:10:37 AM PDT 24
Peak memory 204888 kb
Host smart-4dfcd236-2f49-475e-a2c0-4a3b9971a5ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395999762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.3395999762
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.973920087
Short name T550
Test name
Test status
Simulation time 5258914345 ps
CPU time 31.33 seconds
Started Jul 02 08:10:23 AM PDT 24
Finished Jul 02 08:10:55 AM PDT 24
Peak memory 204944 kb
Host smart-c84c2a16-e0d2-4f30-85c8-be07218565f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973920087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c
_target_stress_rd.973920087
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1311586271
Short name T24
Test name
Test status
Simulation time 48143598531 ps
CPU time 121.06 seconds
Started Jul 02 08:10:21 AM PDT 24
Finished Jul 02 08:12:24 AM PDT 24
Peak memory 1780552 kb
Host smart-47fd099a-2fb9-4927-9990-c03e7d967291
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311586271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1311586271
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.3415313966
Short name T590
Test name
Test status
Simulation time 5221184519 ps
CPU time 24.62 seconds
Started Jul 02 08:10:20 AM PDT 24
Finished Jul 02 08:10:46 AM PDT 24
Peak memory 433236 kb
Host smart-4a729ac4-53dc-403f-b766-2eb22319088b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415313966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_
target_stretch.3415313966
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1563536861
Short name T1507
Test name
Test status
Simulation time 4596631774 ps
CPU time 7.1 seconds
Started Jul 02 08:10:21 AM PDT 24
Finished Jul 02 08:10:30 AM PDT 24
Peak memory 221196 kb
Host smart-b0c50f4c-5197-4de8-8550-14401c80638c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563536861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1563536861
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.1120378754
Short name T181
Test name
Test status
Simulation time 588689207 ps
CPU time 8.56 seconds
Started Jul 02 08:10:24 AM PDT 24
Finished Jul 02 08:10:34 AM PDT 24
Peak memory 204804 kb
Host smart-3a143962-4e82-4715-8078-9658e855202f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120378754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.1120378754
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.1759347948
Short name T786
Test name
Test status
Simulation time 16419044 ps
CPU time 0.63 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:45 AM PDT 24
Peak memory 204496 kb
Host smart-a80bdf37-b702-4a6f-a5c8-85c1dba75e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759347948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.1759347948
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.2146674541
Short name T48
Test name
Test status
Simulation time 723957390 ps
CPU time 2.8 seconds
Started Jul 02 08:10:24 AM PDT 24
Finished Jul 02 08:10:27 AM PDT 24
Peak memory 213072 kb
Host smart-f7052206-1d13-4b33-bb41-e07f9e4eb32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146674541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.2146674541
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2292136176
Short name T972
Test name
Test status
Simulation time 290019948 ps
CPU time 14.24 seconds
Started Jul 02 08:10:27 AM PDT 24
Finished Jul 02 08:10:43 AM PDT 24
Peak memory 260540 kb
Host smart-b0dc4c87-b819-45d1-8555-637320227077
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292136176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2292136176
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.403844071
Short name T1524
Test name
Test status
Simulation time 20088479971 ps
CPU time 86.96 seconds
Started Jul 02 08:10:27 AM PDT 24
Finished Jul 02 08:11:56 AM PDT 24
Peak memory 814096 kb
Host smart-3db16cfc-8efc-489f-8efb-2adc48be5580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403844071 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.403844071
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.3547044476
Short name T668
Test name
Test status
Simulation time 1954029017 ps
CPU time 57.95 seconds
Started Jul 02 08:10:27 AM PDT 24
Finished Jul 02 08:11:27 AM PDT 24
Peak memory 682256 kb
Host smart-5bca33f8-4c64-4f58-aac7-26aab47f5338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547044476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.3547044476
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.482118205
Short name T774
Test name
Test status
Simulation time 134336378 ps
CPU time 1.1 seconds
Started Jul 02 08:10:24 AM PDT 24
Finished Jul 02 08:10:27 AM PDT 24
Peak memory 204416 kb
Host smart-82317777-3805-45e2-b8c6-95162d62cc7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482118205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_fm
t.482118205
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2801439541
Short name T901
Test name
Test status
Simulation time 668578899 ps
CPU time 4.35 seconds
Started Jul 02 08:10:28 AM PDT 24
Finished Jul 02 08:10:34 AM PDT 24
Peak memory 204780 kb
Host smart-46e7d6f4-7651-4a43-9984-1ea4f8432ced
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801439541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2801439541
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.2743063502
Short name T1356
Test name
Test status
Simulation time 9860713504 ps
CPU time 99.28 seconds
Started Jul 02 08:10:21 AM PDT 24
Finished Jul 02 08:12:02 AM PDT 24
Peak memory 1064636 kb
Host smart-3d211025-2e15-4dbc-ae62-84a046175830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743063502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.2743063502
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.213590660
Short name T680
Test name
Test status
Simulation time 2777403782 ps
CPU time 4.22 seconds
Started Jul 02 08:10:26 AM PDT 24
Finished Jul 02 08:10:32 AM PDT 24
Peak memory 204904 kb
Host smart-7e29e5d3-1850-408c-9b8e-050662973f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213590660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.213590660
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.1785752275
Short name T686
Test name
Test status
Simulation time 1935104370 ps
CPU time 35.66 seconds
Started Jul 02 08:10:24 AM PDT 24
Finished Jul 02 08:11:01 AM PDT 24
Peak memory 342472 kb
Host smart-9a350314-4958-47f9-858b-8edacbaa4b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785752275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.1785752275
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3209557407
Short name T1334
Test name
Test status
Simulation time 80961640 ps
CPU time 0.68 seconds
Started Jul 02 08:10:24 AM PDT 24
Finished Jul 02 08:10:27 AM PDT 24
Peak memory 204520 kb
Host smart-e19c19f0-4e6e-4a11-a773-62a26d61c88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209557407 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3209557407
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.4117483892
Short name T512
Test name
Test status
Simulation time 6708658375 ps
CPU time 21.32 seconds
Started Jul 02 08:10:24 AM PDT 24
Finished Jul 02 08:10:47 AM PDT 24
Peak memory 213184 kb
Host smart-16443e71-dfb9-45c0-a614-39dbc38598be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117483892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.4117483892
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.3978265993
Short name T1171
Test name
Test status
Simulation time 3094474583 ps
CPU time 8.34 seconds
Started Jul 02 08:10:25 AM PDT 24
Finished Jul 02 08:10:35 AM PDT 24
Peak memory 301432 kb
Host smart-18417d93-5b44-4fc4-9066-e82c72129b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978265993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.3978265993
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.691001235
Short name T813
Test name
Test status
Simulation time 1937397724 ps
CPU time 35.17 seconds
Started Jul 02 08:10:22 AM PDT 24
Finished Jul 02 08:10:58 AM PDT 24
Peak memory 350004 kb
Host smart-c03049ce-94f6-4082-b811-eb8163bc7414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691001235 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.691001235
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stress_all.3243380024
Short name T1454
Test name
Test status
Simulation time 5155426465 ps
CPU time 110.65 seconds
Started Jul 02 08:10:26 AM PDT 24
Finished Jul 02 08:12:18 AM PDT 24
Peak memory 855848 kb
Host smart-9b0c9d24-7843-4793-8116-276537dc5779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243380024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stress_all.3243380024
Directory /workspace/14.i2c_host_stress_all/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.800455372
Short name T591
Test name
Test status
Simulation time 1959980941 ps
CPU time 8.93 seconds
Started Jul 02 08:10:26 AM PDT 24
Finished Jul 02 08:10:36 AM PDT 24
Peak memory 212996 kb
Host smart-997877cc-1e34-4f71-83db-b21831d45928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800455372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.800455372
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.341430794
Short name T1072
Test name
Test status
Simulation time 2200668608 ps
CPU time 4.61 seconds
Started Jul 02 08:10:26 AM PDT 24
Finished Jul 02 08:10:32 AM PDT 24
Peak memory 213116 kb
Host smart-31384f09-551a-4619-9b19-fdbfe8e86312
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341430794 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.341430794
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2368610376
Short name T732
Test name
Test status
Simulation time 652875016 ps
CPU time 1.04 seconds
Started Jul 02 08:10:25 AM PDT 24
Finished Jul 02 08:10:28 AM PDT 24
Peak memory 204596 kb
Host smart-141e3b3a-3cac-44d7-92ca-16acfa05d5fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368610376 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2368610376
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.1307004775
Short name T360
Test name
Test status
Simulation time 1110408097 ps
CPU time 1.32 seconds
Started Jul 02 08:10:26 AM PDT 24
Finished Jul 02 08:10:28 AM PDT 24
Peak memory 204800 kb
Host smart-dc353e1a-62d9-4e03-9586-e68365e17cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307004775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.i2c_target_fifo_reset_tx.1307004775
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.3193735683
Short name T947
Test name
Test status
Simulation time 449601203 ps
CPU time 2.3 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:46 AM PDT 24
Peak memory 204784 kb
Host smart-2932f688-9f67-4edf-ae3d-99ce84419a3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193735683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.3193735683
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.375515116
Short name T1018
Test name
Test status
Simulation time 101460374 ps
CPU time 0.77 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:45 AM PDT 24
Peak memory 204612 kb
Host smart-9b052e99-98bf-4544-9868-59665fd46739
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375515116 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.375515116
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.321730054
Short name T516
Test name
Test status
Simulation time 342005251 ps
CPU time 2.78 seconds
Started Jul 02 08:10:26 AM PDT 24
Finished Jul 02 08:10:31 AM PDT 24
Peak memory 204828 kb
Host smart-5f4cda5e-7e46-4a9e-a7db-8c175ff74d2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321730054 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.i2c_target_hrst.321730054
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.297499421
Short name T932
Test name
Test status
Simulation time 1180704939 ps
CPU time 6.03 seconds
Started Jul 02 08:10:28 AM PDT 24
Finished Jul 02 08:10:36 AM PDT 24
Peak memory 204784 kb
Host smart-6c5cf4aa-66e3-4219-aeb1-319757ba12ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297499421 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.297499421
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.1279815068
Short name T1229
Test name
Test status
Simulation time 5385671238 ps
CPU time 6.77 seconds
Started Jul 02 08:10:24 AM PDT 24
Finished Jul 02 08:10:32 AM PDT 24
Peak memory 204932 kb
Host smart-a9ec69d5-7076-4048-8704-b89d5c18bfb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279815068 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.1279815068
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.2161809020
Short name T1447
Test name
Test status
Simulation time 2698207089 ps
CPU time 24.49 seconds
Started Jul 02 08:10:25 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 204900 kb
Host smart-de574d6c-d200-4e06-8d0b-bcc74e32d2d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161809020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_ta
rget_smoke.2161809020
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.3879033936
Short name T662
Test name
Test status
Simulation time 457209276 ps
CPU time 8.25 seconds
Started Jul 02 08:10:28 AM PDT 24
Finished Jul 02 08:10:38 AM PDT 24
Peak memory 204812 kb
Host smart-d678bd3e-5a50-462c-97d1-91faa535cba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879033936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_rd.3879033936
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.2279232084
Short name T1181
Test name
Test status
Simulation time 25507550591 ps
CPU time 1466.08 seconds
Started Jul 02 08:10:27 AM PDT 24
Finished Jul 02 08:34:56 AM PDT 24
Peak memory 5988912 kb
Host smart-2cbf7c78-b172-4ba8-904a-45681f3db51e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279232084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.2279232084
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.2106902764
Short name T764
Test name
Test status
Simulation time 2643224454 ps
CPU time 7.89 seconds
Started Jul 02 08:10:25 AM PDT 24
Finished Jul 02 08:10:34 AM PDT 24
Peak memory 221132 kb
Host smart-20eb0b8e-13c0-4729-8ffb-bbe78cd555f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106902764 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.2106902764
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.2827141476
Short name T326
Test name
Test status
Simulation time 89769267 ps
CPU time 2.01 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:46 AM PDT 24
Peak memory 204844 kb
Host smart-485779c2-3f39-45ee-9ef2-231f1f8c3eb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827141476 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.2827141476
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.584881443
Short name T1108
Test name
Test status
Simulation time 17903349 ps
CPU time 0.66 seconds
Started Jul 02 08:10:37 AM PDT 24
Finished Jul 02 08:10:40 AM PDT 24
Peak memory 204448 kb
Host smart-f9dbd4fb-8096-4b4f-8883-7229eb638046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584881443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.584881443
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.3368064759
Short name T642
Test name
Test status
Simulation time 1649327044 ps
CPU time 4.34 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:50 AM PDT 24
Peak memory 234976 kb
Host smart-c6679f09-4633-4e39-80ac-4fbf8ad5fb16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368064759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.3368064759
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.3313822928
Short name T997
Test name
Test status
Simulation time 527938995 ps
CPU time 5.59 seconds
Started Jul 02 08:10:37 AM PDT 24
Finished Jul 02 08:10:45 AM PDT 24
Peak memory 262748 kb
Host smart-4cfaeb59-f11d-4ac6-a8ef-ce990f25a858
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313822928 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.3313822928
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.661257901
Short name T1520
Test name
Test status
Simulation time 12306345803 ps
CPU time 54.35 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:11:40 AM PDT 24
Peak memory 476724 kb
Host smart-df5ce623-0602-47a1-93b4-6c77d0064bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661257901 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.661257901
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.2417388585
Short name T1006
Test name
Test status
Simulation time 30313429548 ps
CPU time 67.61 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:11:53 AM PDT 24
Peak memory 645800 kb
Host smart-5742c409-0c32-4e1e-b302-b6aae7d5806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417388585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.2417388585
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1744170567
Short name T593
Test name
Test status
Simulation time 118745451 ps
CPU time 0.98 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:10:43 AM PDT 24
Peak memory 204444 kb
Host smart-283b93dd-a56e-4f79-a380-c559a7650ee0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744170567 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1744170567
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.1128863983
Short name T1437
Test name
Test status
Simulation time 157498088 ps
CPU time 9.04 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 232660 kb
Host smart-87cbb694-4962-4a58-be2f-3c9bf9a35751
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128863983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx
.1128863983
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.2476726211
Short name T1446
Test name
Test status
Simulation time 4100961408 ps
CPU time 285.01 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:15:29 AM PDT 24
Peak memory 1228388 kb
Host smart-d2bb93ca-ce5f-40c3-be4c-fc1450b660e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476726211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.2476726211
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1458103312
Short name T533
Test name
Test status
Simulation time 1758879057 ps
CPU time 5.13 seconds
Started Jul 02 08:10:44 AM PDT 24
Finished Jul 02 08:10:52 AM PDT 24
Peak memory 204796 kb
Host smart-5c0f9e08-e67b-4ace-806b-9f0561cb89c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458103312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1458103312
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_mode_toggle.4062119426
Short name T952
Test name
Test status
Simulation time 1627386596 ps
CPU time 34.95 seconds
Started Jul 02 08:10:35 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 433044 kb
Host smart-f43cba41-c741-43d1-97f4-84be0e5347d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062119426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_mode_toggle.4062119426
Directory /workspace/15.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/15.i2c_host_override.3744909246
Short name T659
Test name
Test status
Simulation time 371869765 ps
CPU time 0.7 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:45 AM PDT 24
Peak memory 204460 kb
Host smart-e26f6048-d43f-4df8-a6c6-4ea21935a4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744909246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.3744909246
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.1975269061
Short name T946
Test name
Test status
Simulation time 3094185685 ps
CPU time 61.44 seconds
Started Jul 02 08:10:43 AM PDT 24
Finished Jul 02 08:11:48 AM PDT 24
Peak memory 220744 kb
Host smart-09efcf2c-1725-489c-a674-e3c9ff0301d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975269061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.1975269061
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.2757862699
Short name T685
Test name
Test status
Simulation time 52323911 ps
CPU time 1.52 seconds
Started Jul 02 08:10:36 AM PDT 24
Finished Jul 02 08:10:39 AM PDT 24
Peak memory 213244 kb
Host smart-259f4000-6be3-4117-8cca-c91ca85f12ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757862699 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.2757862699
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.1806193454
Short name T588
Test name
Test status
Simulation time 1672129768 ps
CPU time 32.99 seconds
Started Jul 02 08:10:38 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 376580 kb
Host smart-387c2b53-83de-436c-86cc-c4d7efc2c283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806193454 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.1806193454
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.2828496661
Short name T1076
Test name
Test status
Simulation time 2149819917 ps
CPU time 11.21 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:55 AM PDT 24
Peak memory 221116 kb
Host smart-71f69588-5d56-46bb-ae9e-de2f6bfce8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828496661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.2828496661
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.2381582034
Short name T560
Test name
Test status
Simulation time 1628447368 ps
CPU time 2.57 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:48 AM PDT 24
Peak memory 204832 kb
Host smart-84277edb-d1dc-4957-adab-7c6df9fab869
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381582034 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.2381582034
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.3936242149
Short name T716
Test name
Test status
Simulation time 230980496 ps
CPU time 1.5 seconds
Started Jul 02 08:10:39 AM PDT 24
Finished Jul 02 08:10:42 AM PDT 24
Peak memory 204824 kb
Host smart-50a7b1be-316e-4c38-aefe-c50e3d6db802
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936242149 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_fifo_reset_acq.3936242149
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.2266039655
Short name T1414
Test name
Test status
Simulation time 452376710 ps
CPU time 1.47 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:47 AM PDT 24
Peak memory 204768 kb
Host smart-bedb72a0-e16c-45b2-a4f1-5d3f3d559a44
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266039655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_fifo_reset_tx.2266039655
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.910253073
Short name T672
Test name
Test status
Simulation time 1085653971 ps
CPU time 3.03 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:49 AM PDT 24
Peak memory 204688 kb
Host smart-32b0db29-4dca-4ab4-87cc-c3008cc512ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910253073 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.910253073
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.3497156239
Short name T1471
Test name
Test status
Simulation time 183664230 ps
CPU time 1.42 seconds
Started Jul 02 08:10:43 AM PDT 24
Finished Jul 02 08:10:48 AM PDT 24
Peak memory 204520 kb
Host smart-3b3ce5f6-3597-47a3-b0f8-f95d6eafe8c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497156239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.3497156239
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.2182843892
Short name T1456
Test name
Test status
Simulation time 842273323 ps
CPU time 4.88 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 210400 kb
Host smart-438460b7-4678-4731-ba5d-3c82de91f18e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182843892 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_intr_smoke.2182843892
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.2328703319
Short name T1262
Test name
Test status
Simulation time 6570740246 ps
CPU time 7.09 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:52 AM PDT 24
Peak memory 361468 kb
Host smart-eea5e871-54be-4d29-a634-28ae31fe3de8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328703319 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.2328703319
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.3787867049
Short name T1043
Test name
Test status
Simulation time 1978584314 ps
CPU time 13.41 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:59 AM PDT 24
Peak memory 204768 kb
Host smart-df34efb0-2b6d-4eb6-9c63-37960a5dca47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787867049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.3787867049
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.1562115131
Short name T981
Test name
Test status
Simulation time 1598859106 ps
CPU time 27.48 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:11:09 AM PDT 24
Peak memory 221288 kb
Host smart-51242782-0637-429f-9108-f5b814887773
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562115131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.1562115131
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1221476405
Short name T839
Test name
Test status
Simulation time 22057179965 ps
CPU time 37.09 seconds
Started Jul 02 08:10:36 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 569516 kb
Host smart-028ea247-d650-4c4b-98b3-102bc1d5b9f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221476405 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1221476405
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.913617556
Short name T210
Test name
Test status
Simulation time 12617595378 ps
CPU time 76.23 seconds
Started Jul 02 08:10:39 AM PDT 24
Finished Jul 02 08:11:57 AM PDT 24
Peak memory 843860 kb
Host smart-41c700c8-385b-4612-adef-38d3d2c78c5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913617556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_t
arget_stretch.913617556
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.386947883
Short name T393
Test name
Test status
Simulation time 6650494907 ps
CPU time 7 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:10:49 AM PDT 24
Peak memory 218752 kb
Host smart-980848f3-609b-47a7-b78a-a7d291a14ec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386947883 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 15.i2c_target_timeout.386947883
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.269639399
Short name T1190
Test name
Test status
Simulation time 69286428 ps
CPU time 1.54 seconds
Started Jul 02 08:10:35 AM PDT 24
Finished Jul 02 08:10:38 AM PDT 24
Peak memory 205024 kb
Host smart-bec8e3bf-0106-4d27-8895-bd59acf0757c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269639399 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.269639399
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1308513048
Short name T1207
Test name
Test status
Simulation time 42271526 ps
CPU time 0.61 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:45 AM PDT 24
Peak memory 204416 kb
Host smart-6bd349fc-d3de-40ae-9dad-cedac745fb3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308513048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1308513048
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.329559149
Short name T880
Test name
Test status
Simulation time 1509846614 ps
CPU time 18.98 seconds
Started Jul 02 08:10:37 AM PDT 24
Finished Jul 02 08:10:57 AM PDT 24
Peak memory 284508 kb
Host smart-7399070f-b88f-45bc-aa7c-b12c2a6dd9dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329559149 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.329559149
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.1340750860
Short name T150
Test name
Test status
Simulation time 9370494567 ps
CPU time 176.18 seconds
Started Jul 02 08:10:38 AM PDT 24
Finished Jul 02 08:13:35 AM PDT 24
Peak memory 765856 kb
Host smart-8326d103-0357-4f82-a247-a72ffa89548d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340750860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.1340750860
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.1800265216
Short name T799
Test name
Test status
Simulation time 10566991088 ps
CPU time 165.47 seconds
Started Jul 02 08:10:39 AM PDT 24
Finished Jul 02 08:13:26 AM PDT 24
Peak memory 726808 kb
Host smart-f10c36a3-d01f-4588-a6ab-24c0f57dbaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800265216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.1800265216
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.2563376395
Short name T894
Test name
Test status
Simulation time 78290328 ps
CPU time 0.76 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:10:43 AM PDT 24
Peak memory 204468 kb
Host smart-bebc381d-07d6-4d83-b7ed-edc6ceca4efb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563376395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.2563376395
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.1245810743
Short name T149
Test name
Test status
Simulation time 881256672 ps
CPU time 5.15 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:50 AM PDT 24
Peak memory 204852 kb
Host smart-08093ae9-7f48-4d21-9316-09176c6f3e7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245810743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.1245810743
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.4016188773
Short name T603
Test name
Test status
Simulation time 10403810386 ps
CPU time 162.97 seconds
Started Jul 02 08:10:36 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 1367688 kb
Host smart-9b756510-fd50-4498-a1cf-c3ea25fe5f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016188773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.4016188773
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.2831586643
Short name T1046
Test name
Test status
Simulation time 287347752 ps
CPU time 4.35 seconds
Started Jul 02 08:10:43 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 204736 kb
Host smart-41decdf4-8869-4a26-8421-4768a78a2750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831586643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.2831586643
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.158043502
Short name T261
Test name
Test status
Simulation time 1299876565 ps
CPU time 54.66 seconds
Started Jul 02 08:10:45 AM PDT 24
Finished Jul 02 08:11:43 AM PDT 24
Peak memory 334224 kb
Host smart-1b2a7ea5-1f3e-4c7d-ba4f-3cd63cc5c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158043502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.158043502
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_override.1577145953
Short name T1288
Test name
Test status
Simulation time 32540567 ps
CPU time 0.69 seconds
Started Jul 02 08:10:39 AM PDT 24
Finished Jul 02 08:10:42 AM PDT 24
Peak memory 203480 kb
Host smart-bbaf0c0a-a318-40ff-a636-327e23447d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577145953 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.1577145953
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/16.i2c_host_perf.4203783824
Short name T1523
Test name
Test status
Simulation time 7790148767 ps
CPU time 21.68 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:11:06 AM PDT 24
Peak memory 220484 kb
Host smart-4bccc82d-4883-45f2-909e-38f6e2d076ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203783824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.4203783824
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.548003713
Short name T1290
Test name
Test status
Simulation time 289585316 ps
CPU time 3.78 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:10:45 AM PDT 24
Peak memory 205300 kb
Host smart-4f2d34ab-086c-4c6b-905c-01a82bed636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548003713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.548003713
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1774901377
Short name T292
Test name
Test status
Simulation time 4334296314 ps
CPU time 46.52 seconds
Started Jul 02 08:10:35 AM PDT 24
Finished Jul 02 08:11:23 AM PDT 24
Peak memory 248172 kb
Host smart-80d03830-f989-4e18-9d01-eed9eb2872cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774901377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1774901377
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.327421747
Short name T279
Test name
Test status
Simulation time 66402748899 ps
CPU time 526 seconds
Started Jul 02 08:10:38 AM PDT 24
Finished Jul 02 08:19:26 AM PDT 24
Peak memory 1476776 kb
Host smart-6ce9b3cb-9597-4798-8222-1aceeb63d122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327421747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.327421747
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.2277272559
Short name T557
Test name
Test status
Simulation time 1077355922 ps
CPU time 40.7 seconds
Started Jul 02 08:10:43 AM PDT 24
Finished Jul 02 08:11:27 AM PDT 24
Peak memory 212988 kb
Host smart-ccaf9912-2b4b-4057-b59e-0acaa8686a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277272559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.2277272559
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.640563909
Short name T22
Test name
Test status
Simulation time 2783040713 ps
CPU time 3.68 seconds
Started Jul 02 08:10:43 AM PDT 24
Finished Jul 02 08:10:50 AM PDT 24
Peak memory 213036 kb
Host smart-3bd7390a-11c7-4ad8-ade9-6a0ab8ced98c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640563909 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.640563909
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.4060269831
Short name T862
Test name
Test status
Simulation time 186843863 ps
CPU time 1.16 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:47 AM PDT 24
Peak memory 204580 kb
Host smart-e9af3e73-04c4-47f3-a5e7-3d3acd3ff024
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060269831 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.4060269831
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.4290644438
Short name T168
Test name
Test status
Simulation time 145648076 ps
CPU time 0.85 seconds
Started Jul 02 08:10:38 AM PDT 24
Finished Jul 02 08:10:41 AM PDT 24
Peak memory 204568 kb
Host smart-f6858bc8-0406-48a6-91b3-de02802a4204
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290644438 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.4290644438
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.3100326909
Short name T1195
Test name
Test status
Simulation time 2829431720 ps
CPU time 2.45 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:10:44 AM PDT 24
Peak memory 204840 kb
Host smart-0523c0fd-738e-4960-8396-de70c8921645
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100326909 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.3100326909
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.1149760679
Short name T859
Test name
Test status
Simulation time 77631586 ps
CPU time 0.9 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:46 AM PDT 24
Peak memory 204532 kb
Host smart-1fa7775c-b6de-4b36-9dc1-68dd7481290e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149760679 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.1149760679
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.3234457178
Short name T1387
Test name
Test status
Simulation time 1106531347 ps
CPU time 6.6 seconds
Started Jul 02 08:10:39 AM PDT 24
Finished Jul 02 08:10:48 AM PDT 24
Peak memory 212100 kb
Host smart-caf780eb-3408-42cc-a7f2-237d18bd3a2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234457178 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.3234457178
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.1115084466
Short name T1317
Test name
Test status
Simulation time 21244751474 ps
CPU time 46.59 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:11:32 AM PDT 24
Peak memory 777464 kb
Host smart-47102a8b-8e71-462e-bb7c-8e3a36c1c022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115084466 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.1115084466
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.889057267
Short name T163
Test name
Test status
Simulation time 789352998 ps
CPU time 28.93 seconds
Started Jul 02 08:10:40 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 204788 kb
Host smart-8c239fee-3e15-41d3-8a1f-ec6327b0d37f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889057267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.889057267
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.659303972
Short name T1099
Test name
Test status
Simulation time 732864535 ps
CPU time 11.88 seconds
Started Jul 02 08:10:37 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 210024 kb
Host smart-cef859f4-3781-4832-90ac-4028f96b61d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659303972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c
_target_stress_rd.659303972
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.3700601303
Short name T638
Test name
Test status
Simulation time 15110838263 ps
CPU time 9.43 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:55 AM PDT 24
Peak memory 204928 kb
Host smart-72c1ae01-b11f-414f-880c-ea05e42b003f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700601303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.3700601303
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.1764484180
Short name T1286
Test name
Test status
Simulation time 18613433583 ps
CPU time 2505.84 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:52:31 AM PDT 24
Peak memory 4487260 kb
Host smart-b2d726fe-70aa-4176-ba04-8a5d4e663047
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764484180 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.1764484180
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.432407270
Short name T450
Test name
Test status
Simulation time 4520582956 ps
CPU time 6.38 seconds
Started Jul 02 08:10:41 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 213084 kb
Host smart-0fb4e4c2-888d-48f8-adc7-0e2d125a6cf2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432407270 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_timeout.432407270
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.835130070
Short name T21
Test name
Test status
Simulation time 1170522943 ps
CPU time 14.3 seconds
Started Jul 02 08:10:44 AM PDT 24
Finished Jul 02 08:11:01 AM PDT 24
Peak memory 204708 kb
Host smart-d77efcc8-0c34-4a1a-9f72-1c688bced2ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835130070 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.835130070
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.933179074
Short name T584
Test name
Test status
Simulation time 16823178 ps
CPU time 0.63 seconds
Started Jul 02 08:10:48 AM PDT 24
Finished Jul 02 08:10:53 AM PDT 24
Peak memory 204436 kb
Host smart-b8f6aac3-8a73-4600-94e5-d8cf32ac471f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933179074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.933179074
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.653821511
Short name T850
Test name
Test status
Simulation time 127255783 ps
CPU time 1.93 seconds
Started Jul 02 08:10:47 AM PDT 24
Finished Jul 02 08:10:52 AM PDT 24
Peak memory 215912 kb
Host smart-b7ce263f-bb5b-43b1-98ed-a3e157abfb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653821511 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.653821511
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.2406343123
Short name T770
Test name
Test status
Simulation time 632498992 ps
CPU time 6.93 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:53 AM PDT 24
Peak memory 267428 kb
Host smart-f652bb6d-6c45-41be-91ee-128c7d81d44b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406343123 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_emp
ty.2406343123
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.2142925327
Short name T531
Test name
Test status
Simulation time 2179263904 ps
CPU time 151.69 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:13:17 AM PDT 24
Peak memory 735628 kb
Host smart-5bfa849f-7247-4e3e-b500-126c12a5392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142925327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.2142925327
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.2356433992
Short name T778
Test name
Test status
Simulation time 2813901985 ps
CPU time 79.19 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 845168 kb
Host smart-3e8e55b3-2fcd-446e-950e-b728e4962d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356433992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.2356433992
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.4056242472
Short name T391
Test name
Test status
Simulation time 453543392 ps
CPU time 1.04 seconds
Started Jul 02 08:10:46 AM PDT 24
Finished Jul 02 08:10:49 AM PDT 24
Peak memory 204416 kb
Host smart-bc09fdb3-ec18-4618-9511-306acd4b5ef8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056242472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.4056242472
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.1058450878
Short name T733
Test name
Test status
Simulation time 495754778 ps
CPU time 2.69 seconds
Started Jul 02 08:10:45 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 204772 kb
Host smart-ad275ba0-b0e1-45b0-b6fa-0b645cbeb63d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058450878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.1058450878
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.432572885
Short name T1350
Test name
Test status
Simulation time 10274460159 ps
CPU time 106.63 seconds
Started Jul 02 08:10:43 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 1097672 kb
Host smart-5e0d33b6-c8bb-4731-b9cb-b8e7a1bd4916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432572885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.432572885
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.2535089452
Short name T1188
Test name
Test status
Simulation time 1400240760 ps
CPU time 6.04 seconds
Started Jul 02 08:10:48 AM PDT 24
Finished Jul 02 08:10:58 AM PDT 24
Peak memory 204752 kb
Host smart-7178a183-13ad-4981-9f41-d37c85fabb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535089452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.2535089452
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2713150292
Short name T823
Test name
Test status
Simulation time 1762208808 ps
CPU time 27.14 seconds
Started Jul 02 08:10:47 AM PDT 24
Finished Jul 02 08:11:18 AM PDT 24
Peak memory 263228 kb
Host smart-bb8f6d98-753c-465c-8b94-9d3a73fb74b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713150292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2713150292
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.2883718705
Short name T312
Test name
Test status
Simulation time 83377699 ps
CPU time 0.64 seconds
Started Jul 02 08:10:45 AM PDT 24
Finished Jul 02 08:10:48 AM PDT 24
Peak memory 204516 kb
Host smart-fef44738-1641-43e0-840a-cb4499994286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883718705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.2883718705
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.1779126082
Short name T979
Test name
Test status
Simulation time 682254961 ps
CPU time 7.24 seconds
Started Jul 02 08:10:42 AM PDT 24
Finished Jul 02 08:10:53 AM PDT 24
Peak memory 213724 kb
Host smart-8b73b62d-92ec-4b64-9bc7-72030f464407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779126082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.1779126082
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.510228813
Short name T167
Test name
Test status
Simulation time 171434737 ps
CPU time 1.18 seconds
Started Jul 02 08:10:45 AM PDT 24
Finished Jul 02 08:10:49 AM PDT 24
Peak memory 212948 kb
Host smart-14b410a7-817f-484b-b234-6f0a3f5decfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510228813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.510228813
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.1483408053
Short name T299
Test name
Test status
Simulation time 1627059004 ps
CPU time 30.17 seconds
Started Jul 02 08:10:43 AM PDT 24
Finished Jul 02 08:11:17 AM PDT 24
Peak memory 354112 kb
Host smart-147aef0c-4db3-4a62-841b-b694078366e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483408053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.1483408053
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stress_all.321330556
Short name T738
Test name
Test status
Simulation time 27516993516 ps
CPU time 129.51 seconds
Started Jul 02 08:10:52 AM PDT 24
Finished Jul 02 08:13:05 AM PDT 24
Peak memory 705680 kb
Host smart-6d9a0409-fe3d-41ee-9001-503f3b16a666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321330556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stress_all.321330556
Directory /workspace/17.i2c_host_stress_all/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2443537251
Short name T796
Test name
Test status
Simulation time 646149289 ps
CPU time 10.47 seconds
Started Jul 02 08:10:49 AM PDT 24
Finished Jul 02 08:11:04 AM PDT 24
Peak memory 215492 kb
Host smart-72c5b89b-3ccb-41ae-982f-14e27523ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443537251 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2443537251
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3846165727
Short name T856
Test name
Test status
Simulation time 819858500 ps
CPU time 4.26 seconds
Started Jul 02 08:10:47 AM PDT 24
Finished Jul 02 08:10:55 AM PDT 24
Peak memory 204832 kb
Host smart-f4f8f287-21aa-4917-b982-191f96362e3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846165727 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3846165727
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.3258519921
Short name T1408
Test name
Test status
Simulation time 143043744 ps
CPU time 1.05 seconds
Started Jul 02 08:10:49 AM PDT 24
Finished Jul 02 08:10:55 AM PDT 24
Peak memory 204504 kb
Host smart-c3cb63b6-fa54-496a-a0bf-6e549d629727
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258519921 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.i2c_target_fifo_reset_tx.3258519921
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.1286497823
Short name T80
Test name
Test status
Simulation time 810125214 ps
CPU time 2.46 seconds
Started Jul 02 08:10:47 AM PDT 24
Finished Jul 02 08:10:53 AM PDT 24
Peak memory 204760 kb
Host smart-25bc2497-f400-4daf-bee2-76eb30e249c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286497823 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.1286497823
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.2846693472
Short name T445
Test name
Test status
Simulation time 156127802 ps
CPU time 1.36 seconds
Started Jul 02 08:10:47 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 204492 kb
Host smart-51337beb-3ca7-4582-90f5-b460fdcb5547
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846693472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.2846693472
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.1360604029
Short name T1403
Test name
Test status
Simulation time 847444325 ps
CPU time 3.29 seconds
Started Jul 02 08:10:51 AM PDT 24
Finished Jul 02 08:10:58 AM PDT 24
Peak memory 204712 kb
Host smart-e2d9b58c-22e6-4cf7-9416-52b1279f6a92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360604029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 17.i2c_target_hrst.1360604029
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2892195503
Short name T1060
Test name
Test status
Simulation time 1234636272 ps
CPU time 4.22 seconds
Started Jul 02 08:10:47 AM PDT 24
Finished Jul 02 08:10:54 AM PDT 24
Peak memory 213028 kb
Host smart-6edb46ac-6281-4932-a36b-a54ae22d0f72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892195503 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2892195503
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2504890253
Short name T543
Test name
Test status
Simulation time 7746001066 ps
CPU time 7.24 seconds
Started Jul 02 08:10:48 AM PDT 24
Finished Jul 02 08:11:00 AM PDT 24
Peak memory 204912 kb
Host smart-5952e40c-8792-4280-b059-4b014a7260a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504890253 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2504890253
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.2309965212
Short name T1224
Test name
Test status
Simulation time 3752074345 ps
CPU time 13.18 seconds
Started Jul 02 08:10:47 AM PDT 24
Finished Jul 02 08:11:04 AM PDT 24
Peak memory 204872 kb
Host smart-d3b13db2-3e7c-42df-bce6-23c3f0e4b15f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309965212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.2309965212
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2198302490
Short name T679
Test name
Test status
Simulation time 1901562207 ps
CPU time 40.41 seconds
Started Jul 02 08:10:48 AM PDT 24
Finished Jul 02 08:11:33 AM PDT 24
Peak memory 204856 kb
Host smart-d5d5d397-f975-4866-9f60-6e5dbba4b851
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198302490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2198302490
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.279676139
Short name T818
Test name
Test status
Simulation time 54426801258 ps
CPU time 31.07 seconds
Started Jul 02 08:10:48 AM PDT 24
Finished Jul 02 08:11:23 AM PDT 24
Peak memory 676704 kb
Host smart-fd28c37f-23a9-49b2-a9ff-9e3703ed819b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279676139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c
_target_stress_wr.279676139
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.3711763259
Short name T629
Test name
Test status
Simulation time 19483201918 ps
CPU time 186.98 seconds
Started Jul 02 08:10:49 AM PDT 24
Finished Jul 02 08:14:01 AM PDT 24
Peak memory 832020 kb
Host smart-3aabf938-3ca0-4e50-891e-7a9be33ce528
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711763259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.3711763259
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.3046978454
Short name T760
Test name
Test status
Simulation time 1439588842 ps
CPU time 7.25 seconds
Started Jul 02 08:10:50 AM PDT 24
Finished Jul 02 08:11:01 AM PDT 24
Peak memory 219488 kb
Host smart-3e471dfb-d0a2-4a23-88c0-33a2502cab78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046978454 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.3046978454
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.1284793880
Short name T670
Test name
Test status
Simulation time 397108547 ps
CPU time 5.55 seconds
Started Jul 02 08:10:49 AM PDT 24
Finished Jul 02 08:10:59 AM PDT 24
Peak memory 213016 kb
Host smart-ad86d3c2-cda6-4129-be03-c1e60b2b6123
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284793880 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.1284793880
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.589858891
Short name T1240
Test name
Test status
Simulation time 45608000 ps
CPU time 0.66 seconds
Started Jul 02 08:10:59 AM PDT 24
Finished Jul 02 08:11:03 AM PDT 24
Peak memory 204440 kb
Host smart-3c4648f0-887e-4a59-9e0b-2fec01d95cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589858891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.589858891
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.4008945096
Short name T626
Test name
Test status
Simulation time 136886952 ps
CPU time 1.35 seconds
Started Jul 02 08:10:55 AM PDT 24
Finished Jul 02 08:10:59 AM PDT 24
Peak memory 213368 kb
Host smart-3656705a-2d73-4722-8b20-bb6f3b19b54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008945096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.4008945096
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.2029176121
Short name T709
Test name
Test status
Simulation time 1137651215 ps
CPU time 6.33 seconds
Started Jul 02 08:10:54 AM PDT 24
Finished Jul 02 08:11:03 AM PDT 24
Peak memory 261920 kb
Host smart-b659867c-8877-4c71-a9bb-e46660fbb05a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029176121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_emp
ty.2029176121
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.1297878416
Short name T1393
Test name
Test status
Simulation time 4652242660 ps
CPU time 82.48 seconds
Started Jul 02 08:10:52 AM PDT 24
Finished Jul 02 08:12:18 AM PDT 24
Peak memory 775612 kb
Host smart-84cf1d7d-d20e-441d-9296-c22ab6fd1d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297878416 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.1297878416
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.713763856
Short name T541
Test name
Test status
Simulation time 2824476528 ps
CPU time 85.39 seconds
Started Jul 02 08:10:51 AM PDT 24
Finished Jul 02 08:12:21 AM PDT 24
Peak memory 846904 kb
Host smart-8eefe904-e868-4bd1-9049-3404f6c4ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713763856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.713763856
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.4128800879
Short name T245
Test name
Test status
Simulation time 284811169 ps
CPU time 1.2 seconds
Started Jul 02 08:10:48 AM PDT 24
Finished Jul 02 08:10:53 AM PDT 24
Peak memory 204624 kb
Host smart-0189a41b-911f-4bfa-843c-c4bcc4059076
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128800879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.4128800879
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.1274771562
Short name T717
Test name
Test status
Simulation time 194084775 ps
CPU time 4.53 seconds
Started Jul 02 08:10:52 AM PDT 24
Finished Jul 02 08:11:00 AM PDT 24
Peak memory 204776 kb
Host smart-4f00c350-4a79-4d05-9de7-43f14ece022b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274771562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.1274771562
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1761819239
Short name T1098
Test name
Test status
Simulation time 3986992624 ps
CPU time 94.78 seconds
Started Jul 02 08:10:49 AM PDT 24
Finished Jul 02 08:12:29 AM PDT 24
Peak memory 1196876 kb
Host smart-8060c00b-2ec6-47fa-9409-35d148f81ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761819239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1761819239
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.1819448257
Short name T1124
Test name
Test status
Simulation time 1016770210 ps
CPU time 3.95 seconds
Started Jul 02 08:10:57 AM PDT 24
Finished Jul 02 08:11:04 AM PDT 24
Peak memory 204880 kb
Host smart-84932cfc-9126-452b-9903-9d82c9833834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819448257 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.1819448257
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.716292829
Short name T1004
Test name
Test status
Simulation time 1761979265 ps
CPU time 26.75 seconds
Started Jul 02 08:10:54 AM PDT 24
Finished Jul 02 08:11:24 AM PDT 24
Peak memory 332672 kb
Host smart-aaf10768-a712-4fce-88da-cf892d4b5ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716292829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.716292829
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.2024970615
Short name T1142
Test name
Test status
Simulation time 27296906 ps
CPU time 0.68 seconds
Started Jul 02 08:10:52 AM PDT 24
Finished Jul 02 08:10:56 AM PDT 24
Peak memory 204540 kb
Host smart-f5eebf8d-c529-476e-aeb9-aadd9724c535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024970615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.2024970615
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.2378554448
Short name T897
Test name
Test status
Simulation time 2613266397 ps
CPU time 44.21 seconds
Started Jul 02 08:10:55 AM PDT 24
Finished Jul 02 08:11:42 AM PDT 24
Peak memory 388312 kb
Host smart-6029d8eb-030b-46e3-bcfd-da5b7d8408a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378554448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.2378554448
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.2652965743
Short name T1348
Test name
Test status
Simulation time 231611046 ps
CPU time 3.75 seconds
Started Jul 02 08:10:52 AM PDT 24
Finished Jul 02 08:10:59 AM PDT 24
Peak memory 212896 kb
Host smart-49441911-4349-4e9a-8bef-8685e5e14b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652965743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.2652965743
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.3051156151
Short name T797
Test name
Test status
Simulation time 1922987784 ps
CPU time 34.91 seconds
Started Jul 02 08:10:50 AM PDT 24
Finished Jul 02 08:11:29 AM PDT 24
Peak memory 299368 kb
Host smart-a3901ef7-4b01-464f-9953-b939ba7ebc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051156151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.3051156151
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.1405354825
Short name T521
Test name
Test status
Simulation time 4003461313 ps
CPU time 18.25 seconds
Started Jul 02 08:10:54 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 219736 kb
Host smart-2cdc30ad-5ce0-4748-936c-2708c5cab971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405354825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.1405354825
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.1608922773
Short name T1361
Test name
Test status
Simulation time 722350598 ps
CPU time 3.69 seconds
Started Jul 02 08:10:55 AM PDT 24
Finished Jul 02 08:11:02 AM PDT 24
Peak memory 212964 kb
Host smart-e7914caa-988f-4797-8758-e3a00be2b44c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608922773 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.1608922773
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.3519696265
Short name T1075
Test name
Test status
Simulation time 473576594 ps
CPU time 0.83 seconds
Started Jul 02 08:10:54 AM PDT 24
Finished Jul 02 08:10:58 AM PDT 24
Peak memory 204596 kb
Host smart-ff6fefde-560c-414e-b8a9-16070f90d6d4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519696265 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_fifo_reset_acq.3519696265
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.4026497767
Short name T1490
Test name
Test status
Simulation time 181117794 ps
CPU time 1.11 seconds
Started Jul 02 08:10:54 AM PDT 24
Finished Jul 02 08:10:58 AM PDT 24
Peak memory 204576 kb
Host smart-3b382aa8-6105-4383-b00e-1dfe31f9ac95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026497767 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.4026497767
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.2587316662
Short name T647
Test name
Test status
Simulation time 1176029223 ps
CPU time 2.84 seconds
Started Jul 02 08:10:59 AM PDT 24
Finished Jul 02 08:11:05 AM PDT 24
Peak memory 204840 kb
Host smart-edb5ffc8-3212-4d03-b58e-5712a14b7c24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587316662 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.2587316662
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.3829414353
Short name T458
Test name
Test status
Simulation time 153086895 ps
CPU time 1.27 seconds
Started Jul 02 08:10:58 AM PDT 24
Finished Jul 02 08:11:03 AM PDT 24
Peak memory 204576 kb
Host smart-c8b83967-ef87-4a14-8d12-1c25f0712756
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829414353 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.3829414353
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.4227999300
Short name T501
Test name
Test status
Simulation time 300520964 ps
CPU time 2.88 seconds
Started Jul 02 08:10:55 AM PDT 24
Finished Jul 02 08:11:02 AM PDT 24
Peak memory 204788 kb
Host smart-798bde9e-e97c-47fb-85ed-a365b526c4cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227999300 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.4227999300
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.4084896086
Short name T923
Test name
Test status
Simulation time 2885485412 ps
CPU time 3.72 seconds
Started Jul 02 08:10:53 AM PDT 24
Finished Jul 02 08:11:00 AM PDT 24
Peak memory 204808 kb
Host smart-55be4da5-d961-4999-9e3e-1305634619b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084896086 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.i2c_target_intr_smoke.4084896086
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.567615211
Short name T1412
Test name
Test status
Simulation time 2667389961 ps
CPU time 6.06 seconds
Started Jul 02 08:10:54 AM PDT 24
Finished Jul 02 08:11:03 AM PDT 24
Peak memory 204868 kb
Host smart-65322831-ad2d-4846-b5be-88316170b621
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567615211 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.567615211
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.597006061
Short name T963
Test name
Test status
Simulation time 10117723955 ps
CPU time 21.43 seconds
Started Jul 02 08:10:54 AM PDT 24
Finished Jul 02 08:11:19 AM PDT 24
Peak memory 204948 kb
Host smart-01709c6c-3993-4ff9-9b11-fd1ecd71bc0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597006061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_tar
get_smoke.597006061
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.699851188
Short name T515
Test name
Test status
Simulation time 1101584951 ps
CPU time 16.19 seconds
Started Jul 02 08:10:53 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 218220 kb
Host smart-6717cc2d-6d4a-42d4-99b7-665286e67ff1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699851188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.699851188
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.887047277
Short name T1390
Test name
Test status
Simulation time 29032591253 ps
CPU time 188.6 seconds
Started Jul 02 08:10:53 AM PDT 24
Finished Jul 02 08:14:05 AM PDT 24
Peak memory 2427492 kb
Host smart-bae54d58-4ce4-44e1-a5c5-872cf9ffcdd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887047277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_wr.887047277
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1110308694
Short name T310
Test name
Test status
Simulation time 18459503412 ps
CPU time 1999.93 seconds
Started Jul 02 08:10:55 AM PDT 24
Finished Jul 02 08:44:18 AM PDT 24
Peak memory 4040068 kb
Host smart-7ce1a65c-f5a3-4e30-b9e6-c895ec4bfd0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110308694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1110308694
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.3229097179
Short name T1036
Test name
Test status
Simulation time 5888225091 ps
CPU time 7.02 seconds
Started Jul 02 08:10:55 AM PDT 24
Finished Jul 02 08:11:05 AM PDT 24
Peak memory 213164 kb
Host smart-bb17048c-7d27-4bff-be64-d75d7677f36b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229097179 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.3229097179
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.3752182238
Short name T737
Test name
Test status
Simulation time 81947186 ps
CPU time 1.95 seconds
Started Jul 02 08:10:58 AM PDT 24
Finished Jul 02 08:11:04 AM PDT 24
Peak memory 204844 kb
Host smart-d4cbf47c-c3f2-4e2d-ac3f-3c2b365d5aed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752182238 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.3752182238
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.1493556765
Short name T637
Test name
Test status
Simulation time 14971932 ps
CPU time 0.62 seconds
Started Jul 02 08:11:07 AM PDT 24
Finished Jul 02 08:11:08 AM PDT 24
Peak memory 204464 kb
Host smart-c76aa5a0-f690-4316-bb1a-7af8c8c1c619
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493556765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.1493556765
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.4150782011
Short name T1232
Test name
Test status
Simulation time 117049713 ps
CPU time 2.09 seconds
Started Jul 02 08:11:00 AM PDT 24
Finished Jul 02 08:11:05 AM PDT 24
Peak memory 213112 kb
Host smart-598923ac-97a5-4e60-be56-8d587c93380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150782011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.4150782011
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.717149385
Short name T1294
Test name
Test status
Simulation time 1070854851 ps
CPU time 5.09 seconds
Started Jul 02 08:11:01 AM PDT 24
Finished Jul 02 08:11:09 AM PDT 24
Peak memory 222684 kb
Host smart-4632d850-5d03-428b-9093-7fb6c724a53a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717149385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_empt
y.717149385
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.4006573076
Short name T902
Test name
Test status
Simulation time 3012537676 ps
CPU time 229.35 seconds
Started Jul 02 08:11:00 AM PDT 24
Finished Jul 02 08:14:52 AM PDT 24
Peak memory 942352 kb
Host smart-f41261c7-af3b-4807-9e0e-d8c7429e787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006573076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.4006573076
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2787801760
Short name T1165
Test name
Test status
Simulation time 1735579755 ps
CPU time 46.76 seconds
Started Jul 02 08:10:56 AM PDT 24
Finished Jul 02 08:11:47 AM PDT 24
Peak memory 552912 kb
Host smart-ccc3b8a8-f56f-4941-8355-39e63a4c0fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787801760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2787801760
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.2020645809
Short name T627
Test name
Test status
Simulation time 107018616 ps
CPU time 0.85 seconds
Started Jul 02 08:10:57 AM PDT 24
Finished Jul 02 08:11:01 AM PDT 24
Peak memory 204464 kb
Host smart-54875e41-efd4-44ce-8b51-bdce084d97ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020645809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.2020645809
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.878839995
Short name T749
Test name
Test status
Simulation time 183344050 ps
CPU time 4.56 seconds
Started Jul 02 08:10:59 AM PDT 24
Finished Jul 02 08:11:06 AM PDT 24
Peak memory 204816 kb
Host smart-4cfe817e-26a5-40a6-ade1-f9a10cc509ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878839995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
878839995
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.3581083842
Short name T1333
Test name
Test status
Simulation time 9221594251 ps
CPU time 123.96 seconds
Started Jul 02 08:10:59 AM PDT 24
Finished Jul 02 08:13:06 AM PDT 24
Peak memory 1334676 kb
Host smart-cc603d08-d9ed-4d3e-b791-0ab2321ff538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581083842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.3581083842
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.2800979603
Short name T1093
Test name
Test status
Simulation time 645602175 ps
CPU time 12.44 seconds
Started Jul 02 08:11:03 AM PDT 24
Finished Jul 02 08:11:17 AM PDT 24
Peak memory 204856 kb
Host smart-cff2eafa-d1df-43da-8d9d-e887763ad7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800979603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.2800979603
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.2605900766
Short name T719
Test name
Test status
Simulation time 6247235036 ps
CPU time 24.03 seconds
Started Jul 02 08:11:03 AM PDT 24
Finished Jul 02 08:11:29 AM PDT 24
Peak memory 352836 kb
Host smart-c4bb20a5-8d23-4acd-a348-dcc3ffbaa7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605900766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.2605900766
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.3228883423
Short name T707
Test name
Test status
Simulation time 84938419 ps
CPU time 0.67 seconds
Started Jul 02 08:10:58 AM PDT 24
Finished Jul 02 08:11:02 AM PDT 24
Peak memory 204536 kb
Host smart-de1dea2f-f399-49e6-8cc4-3e95006669d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228883423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.3228883423
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.4082471171
Short name T215
Test name
Test status
Simulation time 2309664151 ps
CPU time 7.62 seconds
Started Jul 02 08:10:58 AM PDT 24
Finished Jul 02 08:11:09 AM PDT 24
Peak memory 231484 kb
Host smart-863e0151-cac9-4740-8946-335e90615bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082471171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.4082471171
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.3217047835
Short name T725
Test name
Test status
Simulation time 317841863 ps
CPU time 1.83 seconds
Started Jul 02 08:11:00 AM PDT 24
Finished Jul 02 08:11:05 AM PDT 24
Peak memory 204908 kb
Host smart-fe6466aa-7d92-4b65-b416-5b41f7d1fc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217047835 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.3217047835
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.1441855229
Short name T1268
Test name
Test status
Simulation time 9419093431 ps
CPU time 16.05 seconds
Started Jul 02 08:11:00 AM PDT 24
Finished Jul 02 08:11:19 AM PDT 24
Peak memory 260712 kb
Host smart-8a7b5163-d2a7-4f9e-a9af-0fef7f4f9177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441855229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.1441855229
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.3606840620
Short name T282
Test name
Test status
Simulation time 38797202459 ps
CPU time 789.66 seconds
Started Jul 02 08:10:59 AM PDT 24
Finished Jul 02 08:24:12 AM PDT 24
Peak memory 1329940 kb
Host smart-661aae73-176a-4acc-90ec-69c7435f11f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606840620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.3606840620
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.602787885
Short name T1031
Test name
Test status
Simulation time 1865116726 ps
CPU time 17.58 seconds
Started Jul 02 08:10:58 AM PDT 24
Finished Jul 02 08:11:19 AM PDT 24
Peak memory 229352 kb
Host smart-a73ad6fd-63cc-41fa-912d-7e69670ce6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602787885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.602787885
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.168411266
Short name T1187
Test name
Test status
Simulation time 481492982 ps
CPU time 3.11 seconds
Started Jul 02 08:11:04 AM PDT 24
Finished Jul 02 08:11:08 AM PDT 24
Peak memory 204816 kb
Host smart-fc18cb9b-395d-4bc7-a580-bccff5ede78a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168411266 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.168411266
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.178977928
Short name T491
Test name
Test status
Simulation time 304962343 ps
CPU time 1.28 seconds
Started Jul 02 08:11:03 AM PDT 24
Finished Jul 02 08:11:06 AM PDT 24
Peak memory 204608 kb
Host smart-75fde332-9fc8-471f-aed4-5da83d6aecc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178977928 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.178977928
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.1442946752
Short name T1088
Test name
Test status
Simulation time 614639298 ps
CPU time 1.11 seconds
Started Jul 02 08:11:03 AM PDT 24
Finished Jul 02 08:11:06 AM PDT 24
Peak memory 204620 kb
Host smart-83730753-0500-48d4-bc8d-729ffe9396d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442946752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.1442946752
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.3208616589
Short name T1316
Test name
Test status
Simulation time 810934528 ps
CPU time 2.46 seconds
Started Jul 02 08:11:09 AM PDT 24
Finished Jul 02 08:11:13 AM PDT 24
Peak memory 205068 kb
Host smart-276d76dd-cc4f-42df-957a-d1dc9f19647d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208616589 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.3208616589
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.2125670801
Short name T833
Test name
Test status
Simulation time 112398553 ps
CPU time 1.19 seconds
Started Jul 02 08:11:03 AM PDT 24
Finished Jul 02 08:11:06 AM PDT 24
Peak memory 204572 kb
Host smart-bdcc9bc2-72e8-4d87-a124-8cd892c73463
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125670801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.2125670801
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.797910952
Short name T509
Test name
Test status
Simulation time 1585272313 ps
CPU time 8.52 seconds
Started Jul 02 08:10:58 AM PDT 24
Finished Jul 02 08:11:10 AM PDT 24
Peak memory 212976 kb
Host smart-e9a01a62-fd1d-4305-b610-e174c3070818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797910952 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.797910952
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3379321661
Short name T895
Test name
Test status
Simulation time 17973043998 ps
CPU time 265.06 seconds
Started Jul 02 08:11:06 AM PDT 24
Finished Jul 02 08:15:33 AM PDT 24
Peak memory 2927260 kb
Host smart-aad91f86-5ec2-4829-9313-2e1260cf6522
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379321661 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3379321661
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.626142302
Short name T1015
Test name
Test status
Simulation time 1029266330 ps
CPU time 25.54 seconds
Started Jul 02 08:10:58 AM PDT 24
Finished Jul 02 08:11:27 AM PDT 24
Peak memory 204684 kb
Host smart-685baa08-2020-44cd-837a-25f9989cfe5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626142302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_tar
get_smoke.626142302
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.4046816637
Short name T1003
Test name
Test status
Simulation time 1068407703 ps
CPU time 42.5 seconds
Started Jul 02 08:10:58 AM PDT 24
Finished Jul 02 08:11:44 AM PDT 24
Peak memory 204776 kb
Host smart-dcead271-0a25-4540-92a3-a4feb3baba45
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046816637 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_rd.4046816637
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.2954305642
Short name T1497
Test name
Test status
Simulation time 47598213938 ps
CPU time 122.53 seconds
Started Jul 02 08:10:59 AM PDT 24
Finished Jul 02 08:13:04 AM PDT 24
Peak memory 1804832 kb
Host smart-74484e66-f1a2-480d-9bda-ebfead72853f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954305642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.2954305642
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.3793704367
Short name T1259
Test name
Test status
Simulation time 17433108791 ps
CPU time 963.54 seconds
Started Jul 02 08:11:01 AM PDT 24
Finished Jul 02 08:27:07 AM PDT 24
Peak memory 4324212 kb
Host smart-36e8fa96-d651-4847-9ce9-6223017c829d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793704367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_
target_stretch.3793704367
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.605563893
Short name T1258
Test name
Test status
Simulation time 2775286654 ps
CPU time 7.98 seconds
Started Jul 02 08:11:05 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 220752 kb
Host smart-8ea216b3-a249-47f9-b02b-2da648056248
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605563893 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 19.i2c_target_timeout.605563893
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.1425099741
Short name T985
Test name
Test status
Simulation time 145333121 ps
CPU time 2.94 seconds
Started Jul 02 08:11:05 AM PDT 24
Finished Jul 02 08:11:09 AM PDT 24
Peak memory 204784 kb
Host smart-c5e834d7-7294-40c6-91ef-81f41a250fb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425099741 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.1425099741
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.1183838285
Short name T373
Test name
Test status
Simulation time 18430739 ps
CPU time 0.67 seconds
Started Jul 02 08:09:07 AM PDT 24
Finished Jul 02 08:09:11 AM PDT 24
Peak memory 204448 kb
Host smart-8f7efe3b-0998-4b69-bb7d-0e4920ac2f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183838285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1183838285
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3239542018
Short name T1482
Test name
Test status
Simulation time 172108349 ps
CPU time 7.72 seconds
Started Jul 02 08:09:09 AM PDT 24
Finished Jul 02 08:09:20 AM PDT 24
Peak memory 236828 kb
Host smart-b0172a4d-91d0-4865-86f6-3b87a1f50bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239542018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3239542018
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2374826741
Short name T108
Test name
Test status
Simulation time 272010082 ps
CPU time 5.04 seconds
Started Jul 02 08:09:04 AM PDT 24
Finished Jul 02 08:09:13 AM PDT 24
Peak memory 255520 kb
Host smart-92099476-c97c-44c7-8948-4e593ced5081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374826741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2374826741
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.3105603895
Short name T1336
Test name
Test status
Simulation time 4408612127 ps
CPU time 64.02 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:10:09 AM PDT 24
Peak memory 646292 kb
Host smart-2df0b98e-1219-4810-89f4-2b47415f5cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105603895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.3105603895
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3066918439
Short name T658
Test name
Test status
Simulation time 7927611682 ps
CPU time 147.34 seconds
Started Jul 02 08:09:04 AM PDT 24
Finished Jul 02 08:11:35 AM PDT 24
Peak memory 698384 kb
Host smart-4c74b27e-e3b8-4cfd-ad9f-12570aad1a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066918439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3066918439
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.613931746
Short name T1214
Test name
Test status
Simulation time 1534947905 ps
CPU time 0.96 seconds
Started Jul 02 08:09:03 AM PDT 24
Finished Jul 02 08:09:07 AM PDT 24
Peak memory 204476 kb
Host smart-aaac7af8-619b-4625-85e1-dbc4a14ac294
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613931746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fmt
.613931746
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.876976049
Short name T723
Test name
Test status
Simulation time 166246454 ps
CPU time 7.18 seconds
Started Jul 02 08:09:04 AM PDT 24
Finished Jul 02 08:09:14 AM PDT 24
Peak memory 204792 kb
Host smart-e08ff1a4-2363-4901-8036-192a8f07d211
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876976049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.876976049
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.3515359391
Short name T1292
Test name
Test status
Simulation time 10155987295 ps
CPU time 158.78 seconds
Started Jul 02 08:09:01 AM PDT 24
Finished Jul 02 08:11:44 AM PDT 24
Peak memory 1500160 kb
Host smart-29666edf-937e-47ac-a923-a1eed1a1ab7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515359391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.3515359391
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.1829058318
Short name T1377
Test name
Test status
Simulation time 415112343 ps
CPU time 15.6 seconds
Started Jul 02 08:09:06 AM PDT 24
Finished Jul 02 08:09:25 AM PDT 24
Peak memory 204808 kb
Host smart-64a5aa4d-40f6-4b61-85f4-1c9ac4421945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829058318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.1829058318
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.2758942285
Short name T865
Test name
Test status
Simulation time 32073592862 ps
CPU time 91.14 seconds
Started Jul 02 08:09:08 AM PDT 24
Finished Jul 02 08:10:42 AM PDT 24
Peak memory 399968 kb
Host smart-beaf2a81-2802-4133-9627-6021953efb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758942285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.2758942285
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.2083863897
Short name T82
Test name
Test status
Simulation time 89325597 ps
CPU time 0.68 seconds
Started Jul 02 08:09:04 AM PDT 24
Finished Jul 02 08:09:08 AM PDT 24
Peak memory 204432 kb
Host smart-c295ca8d-eb7f-49a6-87c2-6b7443a5139d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083863897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.2083863897
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.779683873
Short name T1196
Test name
Test status
Simulation time 75280134375 ps
CPU time 1816.01 seconds
Started Jul 02 08:09:03 AM PDT 24
Finished Jul 02 08:39:23 AM PDT 24
Peak memory 2644632 kb
Host smart-bff6a669-1721-4716-8de2-4e70dfd6ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779683873 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.779683873
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.3767938538
Short name T493
Test name
Test status
Simulation time 218313779 ps
CPU time 2.91 seconds
Started Jul 02 08:09:02 AM PDT 24
Finished Jul 02 08:09:09 AM PDT 24
Peak memory 204708 kb
Host smart-7c85987f-7801-42b8-8dec-e6cabf1bd76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767938538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.3767938538
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.1305628000
Short name T496
Test name
Test status
Simulation time 1937115437 ps
CPU time 41.57 seconds
Started Jul 02 08:09:04 AM PDT 24
Finished Jul 02 08:09:48 AM PDT 24
Peak memory 380088 kb
Host smart-e31b07cc-b45b-42a0-8fc5-c869ac5f23db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305628000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1305628000
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.3892344584
Short name T46
Test name
Test status
Simulation time 9702233956 ps
CPU time 389.34 seconds
Started Jul 02 08:09:06 AM PDT 24
Finished Jul 02 08:15:39 AM PDT 24
Peak memory 1726344 kb
Host smart-6d5ed6d6-e23f-4893-8c31-b6a3ad62b37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892344584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.3892344584
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.3097405139
Short name T922
Test name
Test status
Simulation time 503081724 ps
CPU time 22.11 seconds
Started Jul 02 08:09:05 AM PDT 24
Finished Jul 02 08:09:30 AM PDT 24
Peak memory 212952 kb
Host smart-dd05f337-b62c-4de8-b037-148668e81fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097405139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.3097405139
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1351002560
Short name T419
Test name
Test status
Simulation time 537108050 ps
CPU time 3.21 seconds
Started Jul 02 08:09:06 AM PDT 24
Finished Jul 02 08:09:12 AM PDT 24
Peak memory 205060 kb
Host smart-4e26611e-6c68-4e6b-8344-0b076ca691ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351002560 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1351002560
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.1369550813
Short name T1183
Test name
Test status
Simulation time 490620148 ps
CPU time 1.07 seconds
Started Jul 02 08:09:08 AM PDT 24
Finished Jul 02 08:09:12 AM PDT 24
Peak memory 212984 kb
Host smart-526c568b-4db1-41f5-af75-9e0ddbcb4872
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369550813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_fifo_reset_acq.1369550813
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.3528695749
Short name T73
Test name
Test status
Simulation time 722042373 ps
CPU time 1.15 seconds
Started Jul 02 08:09:06 AM PDT 24
Finished Jul 02 08:09:10 AM PDT 24
Peak memory 204612 kb
Host smart-01050386-9acc-4c04-a190-271cc8e0200f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528695749 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_tx.3528695749
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.1495548157
Short name T975
Test name
Test status
Simulation time 136120091 ps
CPU time 1.32 seconds
Started Jul 02 08:09:05 AM PDT 24
Finished Jul 02 08:09:09 AM PDT 24
Peak memory 204624 kb
Host smart-e9d9394b-b708-4676-929f-4cbed6639a10
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495548157 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.1495548157
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.2745372341
Short name T1366
Test name
Test status
Simulation time 3322584492 ps
CPU time 4.71 seconds
Started Jul 02 08:09:10 AM PDT 24
Finished Jul 02 08:09:18 AM PDT 24
Peak memory 204864 kb
Host smart-4b0165ec-c847-46b0-a1bb-d0a0b7e35ae2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745372341 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.2745372341
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.2550412034
Short name T1358
Test name
Test status
Simulation time 21950223766 ps
CPU time 55.96 seconds
Started Jul 02 08:09:09 AM PDT 24
Finished Jul 02 08:10:08 AM PDT 24
Peak memory 1199208 kb
Host smart-8d6e5317-59e6-4a82-9907-b50b178a2a05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550412034 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.2550412034
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.887503897
Short name T1025
Test name
Test status
Simulation time 3453073261 ps
CPU time 15.43 seconds
Started Jul 02 08:09:08 AM PDT 24
Finished Jul 02 08:09:26 AM PDT 24
Peak memory 204852 kb
Host smart-60fd2716-96e6-4510-9184-6f491a815459
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887503897 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_targ
et_smoke.887503897
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.672198207
Short name T870
Test name
Test status
Simulation time 1103542656 ps
CPU time 10.21 seconds
Started Jul 02 08:09:06 AM PDT 24
Finished Jul 02 08:09:19 AM PDT 24
Peak memory 206264 kb
Host smart-6f92fcf8-fc69-4343-a344-0b9335e272ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672198207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_
target_stress_rd.672198207
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.2766981026
Short name T485
Test name
Test status
Simulation time 52618482214 ps
CPU time 1041.96 seconds
Started Jul 02 08:09:07 AM PDT 24
Finished Jul 02 08:26:32 AM PDT 24
Peak memory 7384008 kb
Host smart-a0459470-f398-4fd7-9db0-a5ed661455b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766981026 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.2766981026
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3462766478
Short name T562
Test name
Test status
Simulation time 34677076911 ps
CPU time 260.93 seconds
Started Jul 02 08:09:10 AM PDT 24
Finished Jul 02 08:13:33 AM PDT 24
Peak memory 1986928 kb
Host smart-e9d2cd16-1803-4b39-8de4-1674db043081
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462766478 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3462766478
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.1085259772
Short name T1058
Test name
Test status
Simulation time 2828534966 ps
CPU time 7.78 seconds
Started Jul 02 08:09:06 AM PDT 24
Finished Jul 02 08:09:17 AM PDT 24
Peak memory 216944 kb
Host smart-8fa4acb3-101a-46b7-aa70-b1b5d363d94f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085259772 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.1085259772
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.448378243
Short name T343
Test name
Test status
Simulation time 35871783 ps
CPU time 1 seconds
Started Jul 02 08:09:06 AM PDT 24
Finished Jul 02 08:09:10 AM PDT 24
Peak memory 204800 kb
Host smart-09ce121d-0b2e-4600-a360-571b2a6e8267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448378243 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.448378243
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.3043985324
Short name T710
Test name
Test status
Simulation time 18268687 ps
CPU time 0.64 seconds
Started Jul 02 08:11:13 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 204432 kb
Host smart-d6c9804b-6d36-433a-a2a0-ec3972ad4358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043985324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.3043985324
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2234613151
Short name T1310
Test name
Test status
Simulation time 193456136 ps
CPU time 1.43 seconds
Started Jul 02 08:11:05 AM PDT 24
Finished Jul 02 08:11:08 AM PDT 24
Peak memory 213132 kb
Host smart-d1c3c7b4-9ba2-4807-b3e5-a1153e983325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234613151 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2234613151
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.2999848522
Short name T661
Test name
Test status
Simulation time 233114310 ps
CPU time 11.48 seconds
Started Jul 02 08:11:04 AM PDT 24
Finished Jul 02 08:11:18 AM PDT 24
Peak memory 247724 kb
Host smart-92c3f947-8d54-4ecc-a28a-984d49a028f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999848522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.2999848522
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.225298722
Short name T681
Test name
Test status
Simulation time 1485574554 ps
CPU time 47.84 seconds
Started Jul 02 08:11:04 AM PDT 24
Finished Jul 02 08:11:54 AM PDT 24
Peak memory 507500 kb
Host smart-6fe5f42f-aa1b-483d-b9ce-c4817eb5b664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225298722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.225298722
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2597642974
Short name T675
Test name
Test status
Simulation time 1812186211 ps
CPU time 126.59 seconds
Started Jul 02 08:11:04 AM PDT 24
Finished Jul 02 08:13:12 AM PDT 24
Peak memory 624784 kb
Host smart-021bd1e8-2b8f-4fc6-8b76-8eecc480ab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597642974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2597642974
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.3470446451
Short name T545
Test name
Test status
Simulation time 147735054 ps
CPU time 0.99 seconds
Started Jul 02 08:11:07 AM PDT 24
Finished Jul 02 08:11:09 AM PDT 24
Peak memory 204464 kb
Host smart-18729277-a5cb-4b04-b548-0d0ce341b061
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470446451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_f
mt.3470446451
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.4042535864
Short name T1059
Test name
Test status
Simulation time 289026281 ps
CPU time 4.3 seconds
Started Jul 02 08:11:03 AM PDT 24
Finished Jul 02 08:11:09 AM PDT 24
Peak memory 228056 kb
Host smart-dc83287f-ef0e-4b8a-8122-d2e900a93142
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042535864 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx
.4042535864
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.1333822759
Short name T1085
Test name
Test status
Simulation time 4735495680 ps
CPU time 141.81 seconds
Started Jul 02 08:11:06 AM PDT 24
Finished Jul 02 08:13:29 AM PDT 24
Peak memory 1363292 kb
Host smart-345021e9-e882-4364-9ed2-32ac0a702ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333822759 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.1333822759
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.88386990
Short name T564
Test name
Test status
Simulation time 608403802 ps
CPU time 9.74 seconds
Started Jul 02 08:11:09 AM PDT 24
Finished Jul 02 08:11:20 AM PDT 24
Peak memory 204748 kb
Host smart-c6567a33-14b7-4a47-a5e7-0a3421cf5d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88386990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.88386990
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.689225043
Short name T936
Test name
Test status
Simulation time 8618167197 ps
CPU time 29.16 seconds
Started Jul 02 08:11:10 AM PDT 24
Finished Jul 02 08:11:40 AM PDT 24
Peak memory 340520 kb
Host smart-3be33a36-d0fb-45a7-8d6d-223ec7b8e10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689225043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.689225043
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.2868233178
Short name T1344
Test name
Test status
Simulation time 16222560 ps
CPU time 0.66 seconds
Started Jul 02 08:11:06 AM PDT 24
Finished Jul 02 08:11:08 AM PDT 24
Peak memory 204504 kb
Host smart-1db9ba33-8826-441e-afbb-9ff81be2b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868233178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.2868233178
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.1732852885
Short name T306
Test name
Test status
Simulation time 3026110087 ps
CPU time 41.93 seconds
Started Jul 02 08:11:05 AM PDT 24
Finished Jul 02 08:11:49 AM PDT 24
Peak memory 225364 kb
Host smart-068ac3af-56b7-4472-a9ba-6ae6c67214f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732852885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.1732852885
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.3760139856
Short name T348
Test name
Test status
Simulation time 62392388 ps
CPU time 2.98 seconds
Started Jul 02 08:11:04 AM PDT 24
Finished Jul 02 08:11:09 AM PDT 24
Peak memory 222508 kb
Host smart-4032d56e-a336-4499-a636-705821f860a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760139856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.3760139856
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.3073494924
Short name T1012
Test name
Test status
Simulation time 1493568759 ps
CPU time 30.33 seconds
Started Jul 02 08:11:02 AM PDT 24
Finished Jul 02 08:11:34 AM PDT 24
Peak memory 338676 kb
Host smart-adad3cf3-66d6-477d-b537-ad87a92b8ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073494924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.3073494924
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.4090749694
Short name T464
Test name
Test status
Simulation time 3968073669 ps
CPU time 16.88 seconds
Started Jul 02 08:11:08 AM PDT 24
Finished Jul 02 08:11:25 AM PDT 24
Peak memory 229764 kb
Host smart-4055f997-ed46-4489-a8cb-7d820fad2f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090749694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.4090749694
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.2452904629
Short name T1206
Test name
Test status
Simulation time 3748939886 ps
CPU time 4.42 seconds
Started Jul 02 08:11:09 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 213128 kb
Host smart-5ebe2a1e-87e5-47a9-8992-c5a3a2e1a39b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452904629 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.2452904629
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.700669264
Short name T920
Test name
Test status
Simulation time 569295797 ps
CPU time 1.19 seconds
Started Jul 02 08:11:08 AM PDT 24
Finished Jul 02 08:11:11 AM PDT 24
Peak memory 204572 kb
Host smart-eeeb7258-2fa6-425b-b36d-53fa63835aa2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700669264 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_acq.700669264
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3362430251
Short name T1011
Test name
Test status
Simulation time 129457175 ps
CPU time 0.97 seconds
Started Jul 02 08:11:09 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 204576 kb
Host smart-6842ab70-dab2-4830-9aff-6ac885f1e775
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362430251 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3362430251
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.3416901571
Short name T138
Test name
Test status
Simulation time 2378937097 ps
CPU time 3.07 seconds
Started Jul 02 08:11:13 AM PDT 24
Finished Jul 02 08:11:17 AM PDT 24
Peak memory 204888 kb
Host smart-d032a5f6-fee0-4a33-a8ff-319074d7daaa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416901571 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.3416901571
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.3825689207
Short name T489
Test name
Test status
Simulation time 688162045 ps
CPU time 0.81 seconds
Started Jul 02 08:11:10 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 204616 kb
Host smart-e6dd8e31-fe9b-48d6-8a1f-88d489ede9f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825689207 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.3825689207
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.552033732
Short name T1335
Test name
Test status
Simulation time 876430488 ps
CPU time 3.53 seconds
Started Jul 02 08:11:10 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 204804 kb
Host smart-4b7077ca-3226-4095-a5bc-a09df356cd39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552033732 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.i2c_target_hrst.552033732
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.1160562853
Short name T1143
Test name
Test status
Simulation time 2525442989 ps
CPU time 6.83 seconds
Started Jul 02 08:11:09 AM PDT 24
Finished Jul 02 08:11:17 AM PDT 24
Peak memory 219148 kb
Host smart-f1de38f4-8ec9-4d2d-b2ff-0a31cd99cdd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160562853 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.1160562853
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2701566528
Short name T967
Test name
Test status
Simulation time 21751409349 ps
CPU time 69.6 seconds
Started Jul 02 08:11:11 AM PDT 24
Finished Jul 02 08:12:21 AM PDT 24
Peak memory 944700 kb
Host smart-4f927efe-147f-4a4c-bcd3-a32f4fbdbda7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701566528 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2701566528
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.616957910
Short name T165
Test name
Test status
Simulation time 2087567694 ps
CPU time 35.54 seconds
Started Jul 02 08:11:13 AM PDT 24
Finished Jul 02 08:11:50 AM PDT 24
Peak memory 204848 kb
Host smart-f54909a7-322b-4f1d-85f9-3fab13c3c9fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616957910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_tar
get_smoke.616957910
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2047517595
Short name T1104
Test name
Test status
Simulation time 4671706609 ps
CPU time 48.14 seconds
Started Jul 02 08:11:09 AM PDT 24
Finished Jul 02 08:11:59 AM PDT 24
Peak memory 205104 kb
Host smart-2fb5cf45-f015-408e-8148-f180b4980954
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047517595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2047517595
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.258754654
Short name T677
Test name
Test status
Simulation time 40429892581 ps
CPU time 73.25 seconds
Started Jul 02 08:11:11 AM PDT 24
Finished Jul 02 08:12:25 AM PDT 24
Peak memory 1265448 kb
Host smart-2deeee03-a3e2-4548-9337-f02a0127e321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258754654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c
_target_stress_wr.258754654
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.306408802
Short name T911
Test name
Test status
Simulation time 3254010796 ps
CPU time 77.3 seconds
Started Jul 02 08:11:09 AM PDT 24
Finished Jul 02 08:12:27 AM PDT 24
Peak memory 520052 kb
Host smart-0ceb4740-57a2-4396-9699-434d920f66ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306408802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.306408802
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.1187283916
Short name T1508
Test name
Test status
Simulation time 3856923888 ps
CPU time 7.38 seconds
Started Jul 02 08:11:10 AM PDT 24
Finished Jul 02 08:11:18 AM PDT 24
Peak memory 220480 kb
Host smart-3b0cbb43-7c62-439e-9dc1-5e4fd1e65b1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187283916 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 20.i2c_target_timeout.1187283916
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.2099331304
Short name T561
Test name
Test status
Simulation time 168402008 ps
CPU time 3.32 seconds
Started Jul 02 08:11:09 AM PDT 24
Finished Jul 02 08:11:14 AM PDT 24
Peak memory 204836 kb
Host smart-a5293d9b-a5ec-4bbe-88f1-d074d58aa111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099331304 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.2099331304
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2642144475
Short name T1105
Test name
Test status
Simulation time 35594840 ps
CPU time 0.67 seconds
Started Jul 02 08:11:23 AM PDT 24
Finished Jul 02 08:11:24 AM PDT 24
Peak memory 204472 kb
Host smart-6cfd7c64-b90d-4b2c-a9ba-83827b29a826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642144475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2642144475
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3275492449
Short name T356
Test name
Test status
Simulation time 579831338 ps
CPU time 4.35 seconds
Started Jul 02 08:11:15 AM PDT 24
Finished Jul 02 08:11:21 AM PDT 24
Peak memory 225416 kb
Host smart-0b470cbc-20e8-4da1-9269-590eb2b2f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275492449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3275492449
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1742312600
Short name T1325
Test name
Test status
Simulation time 1860209860 ps
CPU time 24.02 seconds
Started Jul 02 08:11:16 AM PDT 24
Finished Jul 02 08:11:41 AM PDT 24
Peak memory 304900 kb
Host smart-ba38facf-acf7-42d6-a99d-571f14d05cb1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742312600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.1742312600
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.3536108490
Short name T1536
Test name
Test status
Simulation time 2695712390 ps
CPU time 105.18 seconds
Started Jul 02 08:11:13 AM PDT 24
Finished Jul 02 08:12:59 AM PDT 24
Peak memory 865908 kb
Host smart-438d93f7-ce2a-42fa-b228-cdbc3e74f0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536108490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.3536108490
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.2924424799
Short name T1037
Test name
Test status
Simulation time 1912414726 ps
CPU time 118.58 seconds
Started Jul 02 08:11:13 AM PDT 24
Finished Jul 02 08:13:13 AM PDT 24
Peak memory 589688 kb
Host smart-91756a9e-6174-4983-9b88-264e8f5c49ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924424799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.2924424799
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.3324254914
Short name T906
Test name
Test status
Simulation time 250699634 ps
CPU time 1 seconds
Started Jul 02 08:11:13 AM PDT 24
Finished Jul 02 08:11:15 AM PDT 24
Peak memory 204448 kb
Host smart-9e99c071-eabc-4f3f-9655-f7a8639e2e26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324254914 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.3324254914
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.3372758956
Short name T891
Test name
Test status
Simulation time 538321291 ps
CPU time 8.01 seconds
Started Jul 02 08:11:13 AM PDT 24
Finished Jul 02 08:11:23 AM PDT 24
Peak memory 204808 kb
Host smart-6a323cc8-52e5-4209-99c8-337652a6ba7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372758956 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx
.3372758956
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.4116243863
Short name T772
Test name
Test status
Simulation time 4508578712 ps
CPU time 360.06 seconds
Started Jul 02 08:11:16 AM PDT 24
Finished Jul 02 08:17:17 AM PDT 24
Peak memory 1330388 kb
Host smart-a4452e20-699b-467e-80c2-1b9ec5a93c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116243863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.4116243863
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1985784125
Short name T456
Test name
Test status
Simulation time 2191339962 ps
CPU time 7.13 seconds
Started Jul 02 08:11:20 AM PDT 24
Finished Jul 02 08:11:29 AM PDT 24
Peak memory 204868 kb
Host smart-54059249-1739-44ce-9028-2324a937f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985784125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1985784125
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.4009216973
Short name T62
Test name
Test status
Simulation time 7399381414 ps
CPU time 43.32 seconds
Started Jul 02 08:11:19 AM PDT 24
Finished Jul 02 08:12:03 AM PDT 24
Peak memory 296892 kb
Host smart-c19ca78e-3fa7-48fb-b69e-a98335a65501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009216973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.4009216973
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2091171139
Short name T553
Test name
Test status
Simulation time 169519940 ps
CPU time 1.9 seconds
Started Jul 02 08:11:15 AM PDT 24
Finished Jul 02 08:11:18 AM PDT 24
Peak memory 214360 kb
Host smart-0ace6e73-3990-4793-b42d-280be22735a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091171139 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2091171139
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.1164373387
Short name T1417
Test name
Test status
Simulation time 2399464772 ps
CPU time 87.7 seconds
Started Jul 02 08:11:14 AM PDT 24
Finished Jul 02 08:12:43 AM PDT 24
Peak memory 223176 kb
Host smart-6a3e0406-dfa3-4738-9642-79101e5a78a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164373387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.1164373387
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.385095722
Short name T1379
Test name
Test status
Simulation time 8047947298 ps
CPU time 108.89 seconds
Started Jul 02 08:11:10 AM PDT 24
Finished Jul 02 08:13:00 AM PDT 24
Peak memory 455268 kb
Host smart-3bbf7302-abea-4652-99da-fd67aa5f756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385095722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.385095722
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.551685712
Short name T1
Test name
Test status
Simulation time 34325019265 ps
CPU time 1380.94 seconds
Started Jul 02 08:11:15 AM PDT 24
Finished Jul 02 08:34:18 AM PDT 24
Peak memory 3081412 kb
Host smart-0cfef4b7-2355-40dc-81b4-711a385f1d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551685712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.551685712
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.1863074142
Short name T1526
Test name
Test status
Simulation time 8543156291 ps
CPU time 17.35 seconds
Started Jul 02 08:11:15 AM PDT 24
Finished Jul 02 08:11:34 AM PDT 24
Peak memory 220500 kb
Host smart-a1ef9de1-8094-4efd-b947-5675c9cfb42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863074142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.1863074142
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.2984230537
Short name T1528
Test name
Test status
Simulation time 3924012775 ps
CPU time 3.22 seconds
Started Jul 02 08:11:22 AM PDT 24
Finished Jul 02 08:11:26 AM PDT 24
Peak memory 213076 kb
Host smart-88b57af4-f3c3-4403-8bf8-800c986cb98b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984230537 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.2984230537
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.2799493296
Short name T810
Test name
Test status
Simulation time 424693595 ps
CPU time 1.61 seconds
Started Jul 02 08:11:20 AM PDT 24
Finished Jul 02 08:11:23 AM PDT 24
Peak memory 211228 kb
Host smart-086fb5a3-9297-42e2-8b10-aaad54cd1adc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799493296 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.2799493296
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.3281936824
Short name T746
Test name
Test status
Simulation time 100111581 ps
CPU time 0.9 seconds
Started Jul 02 08:11:20 AM PDT 24
Finished Jul 02 08:11:22 AM PDT 24
Peak memory 204556 kb
Host smart-b36e1941-b702-4426-b51d-8b0b775c0c51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281936824 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_fifo_reset_tx.3281936824
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.4160679877
Short name T110
Test name
Test status
Simulation time 3004134393 ps
CPU time 2.29 seconds
Started Jul 02 08:11:21 AM PDT 24
Finished Jul 02 08:11:24 AM PDT 24
Peak memory 204900 kb
Host smart-52536ce4-324e-41d5-acbf-8ffbe2db5b37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160679877 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.4160679877
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.433253338
Short name T529
Test name
Test status
Simulation time 62702461 ps
CPU time 0.9 seconds
Started Jul 02 08:11:22 AM PDT 24
Finished Jul 02 08:11:24 AM PDT 24
Peak memory 204600 kb
Host smart-715b1f7d-b015-4bf0-a19e-8a8947300eff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433253338 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.433253338
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.53987320
Short name T676
Test name
Test status
Simulation time 838301461 ps
CPU time 4.65 seconds
Started Jul 02 08:11:21 AM PDT 24
Finished Jul 02 08:11:27 AM PDT 24
Peak memory 213032 kb
Host smart-a2005f7d-78d3-4284-9011-f7a2f7d000e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53987320 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_intr_smoke.53987320
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.4125678285
Short name T645
Test name
Test status
Simulation time 8909921987 ps
CPU time 12.62 seconds
Started Jul 02 08:11:23 AM PDT 24
Finished Jul 02 08:11:37 AM PDT 24
Peak memory 292764 kb
Host smart-27033215-9e0d-4d2d-8ad0-6972b50a0e48
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125678285 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.4125678285
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.1591883581
Short name T1450
Test name
Test status
Simulation time 939666518 ps
CPU time 13.72 seconds
Started Jul 02 08:11:15 AM PDT 24
Finished Jul 02 08:11:30 AM PDT 24
Peak memory 204668 kb
Host smart-6f51c2b5-576e-43f8-b4c2-e4d7806d40a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591883581 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_ta
rget_smoke.1591883581
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.2762672055
Short name T384
Test name
Test status
Simulation time 749357423 ps
CPU time 11.65 seconds
Started Jul 02 08:11:19 AM PDT 24
Finished Jul 02 08:11:32 AM PDT 24
Peak memory 209876 kb
Host smart-b579aff4-7812-4e22-a8f7-cb472c9663ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762672055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_rd.2762672055
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.4094424708
Short name T857
Test name
Test status
Simulation time 23500191402 ps
CPU time 15.28 seconds
Started Jul 02 08:11:14 AM PDT 24
Finished Jul 02 08:11:31 AM PDT 24
Peak memory 310308 kb
Host smart-52619c1c-c64a-4653-b3c1-08f72cd9ead7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094424708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.4094424708
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1542273836
Short name T26
Test name
Test status
Simulation time 4865639216 ps
CPU time 100.34 seconds
Started Jul 02 08:11:21 AM PDT 24
Finished Jul 02 08:13:02 AM PDT 24
Peak memory 634928 kb
Host smart-f49fc527-28dc-4cd2-95de-4f6621d2f17b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542273836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1542273836
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3140308832
Short name T1332
Test name
Test status
Simulation time 1551842673 ps
CPU time 7.59 seconds
Started Jul 02 08:11:20 AM PDT 24
Finished Jul 02 08:11:29 AM PDT 24
Peak memory 213252 kb
Host smart-9c15cf16-6169-4c1e-8d15-86f437819761
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140308832 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3140308832
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.2378731324
Short name T429
Test name
Test status
Simulation time 770334678 ps
CPU time 9.8 seconds
Started Jul 02 08:11:23 AM PDT 24
Finished Jul 02 08:11:33 AM PDT 24
Peak memory 204836 kb
Host smart-8c42d033-6433-4686-9857-bf97928e562e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378731324 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.2378731324
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.4049116308
Short name T978
Test name
Test status
Simulation time 69669977 ps
CPU time 0.58 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:11:41 AM PDT 24
Peak memory 204484 kb
Host smart-a6dfa2df-3fee-4057-bc36-08e88bbcf534
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049116308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.4049116308
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.3500539979
Short name T1522
Test name
Test status
Simulation time 283230176 ps
CPU time 2.12 seconds
Started Jul 02 08:11:37 AM PDT 24
Finished Jul 02 08:11:42 AM PDT 24
Peak memory 221256 kb
Host smart-fd5dee6b-f629-4151-90c0-5b40fa471f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500539979 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.3500539979
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1880271770
Short name T319
Test name
Test status
Simulation time 290643393 ps
CPU time 5.13 seconds
Started Jul 02 08:11:24 AM PDT 24
Finished Jul 02 08:11:30 AM PDT 24
Peak memory 238200 kb
Host smart-37137d81-beb1-47f1-b18c-f70295224809
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880271770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1880271770
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.2427189223
Short name T863
Test name
Test status
Simulation time 6186529187 ps
CPU time 103.71 seconds
Started Jul 02 08:11:19 AM PDT 24
Finished Jul 02 08:13:03 AM PDT 24
Peak memory 427112 kb
Host smart-90290170-59c2-46e2-bcbf-5ab6c0577a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427189223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.2427189223
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.1406749931
Short name T650
Test name
Test status
Simulation time 1591115592 ps
CPU time 98.71 seconds
Started Jul 02 08:11:19 AM PDT 24
Finished Jul 02 08:12:59 AM PDT 24
Peak memory 562032 kb
Host smart-075c9eef-8c1f-4c13-a279-746a447aaba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406749931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.1406749931
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.3205553049
Short name T993
Test name
Test status
Simulation time 255196482 ps
CPU time 1.17 seconds
Started Jul 02 08:11:21 AM PDT 24
Finished Jul 02 08:11:23 AM PDT 24
Peak memory 204404 kb
Host smart-e11ebf2a-6080-4b33-8a74-4cfa04c84fe4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205553049 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.3205553049
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.3149579002
Short name T1086
Test name
Test status
Simulation time 184761762 ps
CPU time 5.33 seconds
Started Jul 02 08:11:21 AM PDT 24
Finished Jul 02 08:11:28 AM PDT 24
Peak memory 236768 kb
Host smart-49fda40f-798f-460b-9b31-65454f43d7fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149579002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.3149579002
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.193858357
Short name T406
Test name
Test status
Simulation time 4672251580 ps
CPU time 323.13 seconds
Started Jul 02 08:11:20 AM PDT 24
Finished Jul 02 08:16:44 AM PDT 24
Peak memory 1335732 kb
Host smart-7f14b240-c0bd-4039-828e-fac04cf4f515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193858357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.193858357
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3091677369
Short name T694
Test name
Test status
Simulation time 507976175 ps
CPU time 7.6 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:11:34 AM PDT 24
Peak memory 204852 kb
Host smart-3bb4e496-0524-4305-9188-261308eee898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091677369 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3091677369
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.3381502879
Short name T1319
Test name
Test status
Simulation time 3205405954 ps
CPU time 34.54 seconds
Started Jul 02 08:11:37 AM PDT 24
Finished Jul 02 08:12:14 AM PDT 24
Peak memory 330156 kb
Host smart-1e2756bd-d4af-4663-af07-1428f804ee63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381502879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.3381502879
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.3938428241
Short name T253
Test name
Test status
Simulation time 39726285 ps
CPU time 0.65 seconds
Started Jul 02 08:11:22 AM PDT 24
Finished Jul 02 08:11:24 AM PDT 24
Peak memory 204520 kb
Host smart-3489b665-ea64-4aca-9455-9aadaa119e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938428241 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3938428241
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.104606895
Short name T624
Test name
Test status
Simulation time 9756584988 ps
CPU time 10.18 seconds
Started Jul 02 08:11:25 AM PDT 24
Finished Jul 02 08:11:36 AM PDT 24
Peak memory 204936 kb
Host smart-34a424cc-d39d-4c90-a455-5eb36936b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104606895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.104606895
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.2026473040
Short name T781
Test name
Test status
Simulation time 75155455 ps
CPU time 1.68 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:11:30 AM PDT 24
Peak memory 222628 kb
Host smart-ea7997fc-3d1d-4d58-bb6b-a89d6c172ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026473040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.2026473040
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.4268562240
Short name T1123
Test name
Test status
Simulation time 3445451888 ps
CPU time 29.64 seconds
Started Jul 02 08:11:20 AM PDT 24
Finished Jul 02 08:11:50 AM PDT 24
Peak memory 419976 kb
Host smart-0cca727f-1dc2-4afa-a9b0-296e722d28b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268562240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.4268562240
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.2591648131
Short name T101
Test name
Test status
Simulation time 60675197680 ps
CPU time 809.03 seconds
Started Jul 02 08:11:25 AM PDT 24
Finished Jul 02 08:24:55 AM PDT 24
Peak memory 3027880 kb
Host smart-9679e50d-f888-42ea-a7bf-8e4ab4e7ee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591648131 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.2591648131
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.3224345081
Short name T874
Test name
Test status
Simulation time 743392189 ps
CPU time 31.98 seconds
Started Jul 02 08:11:28 AM PDT 24
Finished Jul 02 08:12:01 AM PDT 24
Peak memory 213048 kb
Host smart-5445cb7e-18bb-4021-8a6e-588d00151e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224345081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.3224345081
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.2982710258
Short name T208
Test name
Test status
Simulation time 1698899589 ps
CPU time 2.74 seconds
Started Jul 02 08:11:25 AM PDT 24
Finished Jul 02 08:11:29 AM PDT 24
Peak memory 204876 kb
Host smart-2b55126d-dff5-4c72-af02-f279df3f52d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982710258 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.2982710258
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.3117616350
Short name T604
Test name
Test status
Simulation time 1049628439 ps
CPU time 1.16 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:11:29 AM PDT 24
Peak memory 212972 kb
Host smart-6c5f5389-c9f6-492e-ba2c-312645a39302
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117616350 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.3117616350
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.3576859769
Short name T1074
Test name
Test status
Simulation time 220765740 ps
CPU time 1.28 seconds
Started Jul 02 08:11:27 AM PDT 24
Finished Jul 02 08:11:29 AM PDT 24
Peak memory 204608 kb
Host smart-d36c1a8e-acdd-4d46-af9d-6b3f945b123a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576859769 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.3576859769
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.3275496373
Short name T1149
Test name
Test status
Simulation time 1575304663 ps
CPU time 2.27 seconds
Started Jul 02 08:11:37 AM PDT 24
Finished Jul 02 08:11:42 AM PDT 24
Peak memory 204820 kb
Host smart-7e322910-562e-4e52-83a7-264b08e4adce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275496373 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.3275496373
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.4245959381
Short name T1227
Test name
Test status
Simulation time 177985421 ps
CPU time 1.29 seconds
Started Jul 02 08:11:24 AM PDT 24
Finished Jul 02 08:11:26 AM PDT 24
Peak memory 204592 kb
Host smart-da95da5f-0233-4ccd-a8be-62f682a74e8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245959381 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.4245959381
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.2060223529
Short name T462
Test name
Test status
Simulation time 287081044 ps
CPU time 2.49 seconds
Started Jul 02 08:11:27 AM PDT 24
Finished Jul 02 08:11:31 AM PDT 24
Peak memory 204832 kb
Host smart-10953397-5c1c-47b5-b169-fdaf6883ad00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060223529 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 22.i2c_target_hrst.2060223529
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.4030390394
Short name T524
Test name
Test status
Simulation time 1146047300 ps
CPU time 6.52 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:11:47 AM PDT 24
Peak memory 221144 kb
Host smart-c371002f-a842-40d9-90a4-4243fe4dcbfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030390394 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.4030390394
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.2750510765
Short name T1063
Test name
Test status
Simulation time 12860697097 ps
CPU time 12.24 seconds
Started Jul 02 08:11:24 AM PDT 24
Finished Jul 02 08:11:37 AM PDT 24
Peak memory 357336 kb
Host smart-0f0b2bd9-d94e-4bd6-a55b-2d1ac013cb0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750510765 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.2750510765
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.527325077
Short name T927
Test name
Test status
Simulation time 3788869036 ps
CPU time 36.28 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:12:03 AM PDT 24
Peak memory 204792 kb
Host smart-455d3a07-b40a-4e83-8283-991f4b9d5ad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527325077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.527325077
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1752663732
Short name T1429
Test name
Test status
Simulation time 6680124551 ps
CPU time 16.5 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:11:44 AM PDT 24
Peak memory 212588 kb
Host smart-77f3cbef-2a7c-450c-b6b7-f417c58ba0eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752663732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1752663732
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.1914240844
Short name T146
Test name
Test status
Simulation time 24045774569 ps
CPU time 13.1 seconds
Started Jul 02 08:11:27 AM PDT 24
Finished Jul 02 08:11:41 AM PDT 24
Peak memory 237104 kb
Host smart-2b2b9299-befd-403a-9ab8-176d2c6a9258
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914240844 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_wr.1914240844
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.658336624
Short name T1527
Test name
Test status
Simulation time 13799100753 ps
CPU time 1557.28 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:37:38 AM PDT 24
Peak memory 3314496 kb
Host smart-26d4b9b4-182d-44fe-aacb-ab449ebee9ba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658336624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_t
arget_stretch.658336624
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.2874298292
Short name T64
Test name
Test status
Simulation time 4206435026 ps
CPU time 6.3 seconds
Started Jul 02 08:11:24 AM PDT 24
Finished Jul 02 08:11:31 AM PDT 24
Peak memory 218232 kb
Host smart-30f219e9-7c28-4191-b91c-b14b978e6bcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874298292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.2874298292
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.2540672896
Short name T858
Test name
Test status
Simulation time 51918861 ps
CPU time 1.23 seconds
Started Jul 02 08:11:27 AM PDT 24
Finished Jul 02 08:11:30 AM PDT 24
Peak memory 204856 kb
Host smart-9e0cfc51-686d-41ee-9746-82b32740327c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540672896 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.2540672896
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.701931584
Short name T508
Test name
Test status
Simulation time 18148330 ps
CPU time 0.64 seconds
Started Jul 02 08:11:32 AM PDT 24
Finished Jul 02 08:11:35 AM PDT 24
Peak memory 204436 kb
Host smart-1ad2c290-d28f-4a53-9a92-83bf89cabaf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701931584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.701931584
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.567257686
Short name T1398
Test name
Test status
Simulation time 366143462 ps
CPU time 1.94 seconds
Started Jul 02 08:11:34 AM PDT 24
Finished Jul 02 08:11:37 AM PDT 24
Peak memory 213172 kb
Host smart-7ceb9f70-3d91-49e2-9859-137a79316117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567257686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.567257686
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.2989247671
Short name T690
Test name
Test status
Simulation time 1492715065 ps
CPU time 7.47 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:11:35 AM PDT 24
Peak memory 289688 kb
Host smart-6505c258-2b59-49d0-9c55-1316cba00895
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989247671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.2989247671
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.4109458770
Short name T75
Test name
Test status
Simulation time 7727018925 ps
CPU time 59.69 seconds
Started Jul 02 08:11:37 AM PDT 24
Finished Jul 02 08:12:40 AM PDT 24
Peak memory 269324 kb
Host smart-bb40886f-cfa4-45ad-ad5b-30f0aadea999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109458770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.4109458770
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.1313096427
Short name T107
Test name
Test status
Simulation time 5434068416 ps
CPU time 76.18 seconds
Started Jul 02 08:11:27 AM PDT 24
Finished Jul 02 08:12:45 AM PDT 24
Peak memory 831356 kb
Host smart-19f0d505-a434-475f-8b34-d6168f38195c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313096427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.1313096427
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.1354089289
Short name T1067
Test name
Test status
Simulation time 134205609 ps
CPU time 0.93 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:11:41 AM PDT 24
Peak memory 204476 kb
Host smart-7f8edc5b-c788-4959-83e5-1fc9a303ce24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354089289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.1354089289
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.2884782971
Short name T702
Test name
Test status
Simulation time 258547288 ps
CPU time 6.91 seconds
Started Jul 02 08:11:25 AM PDT 24
Finished Jul 02 08:11:33 AM PDT 24
Peak memory 253196 kb
Host smart-e9477597-f88b-4b52-93cb-3b00c8348d05
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884782971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.2884782971
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.3460245328
Short name T551
Test name
Test status
Simulation time 13419676786 ps
CPU time 79.61 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:12:47 AM PDT 24
Peak memory 908552 kb
Host smart-c5d59f0d-fddf-4d35-b4bc-b4e186bacd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460245328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.3460245328
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.146141321
Short name T556
Test name
Test status
Simulation time 561212414 ps
CPU time 4.44 seconds
Started Jul 02 08:11:30 AM PDT 24
Finished Jul 02 08:11:36 AM PDT 24
Peak memory 204828 kb
Host smart-94608e05-a985-4bfb-a4aa-5b4e2ca56aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146141321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.146141321
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_override.3965041148
Short name T434
Test name
Test status
Simulation time 31559833 ps
CPU time 0.7 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:11:29 AM PDT 24
Peak memory 204492 kb
Host smart-9f975091-5a4c-4e1c-b0fd-2cc6d0f7890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965041148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.3965041148
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2754361208
Short name T984
Test name
Test status
Simulation time 52078689454 ps
CPU time 486.59 seconds
Started Jul 02 08:11:27 AM PDT 24
Finished Jul 02 08:19:35 AM PDT 24
Peak memory 213092 kb
Host smart-6a5ba6f5-25f9-47ff-a2f5-6e4fbe071dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754361208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2754361208
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.266060777
Short name T1153
Test name
Test status
Simulation time 654854357 ps
CPU time 2.82 seconds
Started Jul 02 08:11:37 AM PDT 24
Finished Jul 02 08:11:43 AM PDT 24
Peak memory 204752 kb
Host smart-dbb357a6-8554-4184-bfd8-ad7de14be641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266060777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.266060777
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1379830130
Short name T1170
Test name
Test status
Simulation time 22087068694 ps
CPU time 21.61 seconds
Started Jul 02 08:11:25 AM PDT 24
Finished Jul 02 08:11:47 AM PDT 24
Peak memory 304968 kb
Host smart-7185b1b2-9d7e-43b0-9a0c-98f1db365048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379830130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1379830130
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.2436054877
Short name T1303
Test name
Test status
Simulation time 3310100565 ps
CPU time 13.86 seconds
Started Jul 02 08:11:26 AM PDT 24
Finished Jul 02 08:11:41 AM PDT 24
Peak memory 221228 kb
Host smart-b9e731dd-0030-429a-bdbd-ac4d7aac7b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436054877 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.2436054877
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.3514577114
Short name T864
Test name
Test status
Simulation time 893079191 ps
CPU time 4.48 seconds
Started Jul 02 08:11:31 AM PDT 24
Finished Jul 02 08:11:37 AM PDT 24
Peak memory 213192 kb
Host smart-a6290143-6231-4c50-a770-53d03cab7f97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514577114 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.3514577114
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.276051922
Short name T395
Test name
Test status
Simulation time 431110347 ps
CPU time 1.61 seconds
Started Jul 02 08:11:34 AM PDT 24
Finished Jul 02 08:11:36 AM PDT 24
Peak memory 204844 kb
Host smart-ec35d975-2dd1-4a0e-8f9e-473d48194fc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276051922 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_acq.276051922
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.4131306618
Short name T706
Test name
Test status
Simulation time 2748672223 ps
CPU time 1.44 seconds
Started Jul 02 08:11:30 AM PDT 24
Finished Jul 02 08:11:32 AM PDT 24
Peak memory 206984 kb
Host smart-96e12e43-d1fe-4bb2-972a-a3398ca8cd51
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131306618 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.4131306618
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.2903881431
Short name T669
Test name
Test status
Simulation time 657897046 ps
CPU time 1.18 seconds
Started Jul 02 08:11:32 AM PDT 24
Finished Jul 02 08:11:35 AM PDT 24
Peak memory 204556 kb
Host smart-eae2917f-5851-46aa-a9fa-6860541af05c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903881431 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.2903881431
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.3097204910
Short name T596
Test name
Test status
Simulation time 531086010 ps
CPU time 1.29 seconds
Started Jul 02 08:11:31 AM PDT 24
Finished Jul 02 08:11:33 AM PDT 24
Peak memory 204588 kb
Host smart-933b26ff-ec96-45ec-81d7-bf0b8c9b8fa7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097204910 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.3097204910
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.4106673485
Short name T855
Test name
Test status
Simulation time 409883779 ps
CPU time 2.95 seconds
Started Jul 02 08:11:30 AM PDT 24
Finished Jul 02 08:11:35 AM PDT 24
Peak memory 204752 kb
Host smart-e5f16df5-51f3-48b1-ac7c-ee0518314ea4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106673485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.4106673485
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2561282283
Short name T578
Test name
Test status
Simulation time 655389605 ps
CPU time 3.77 seconds
Started Jul 02 08:11:32 AM PDT 24
Finished Jul 02 08:11:38 AM PDT 24
Peak memory 204804 kb
Host smart-d6fa65c9-69d6-4acd-a83a-37d65d48c6b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561282283 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2561282283
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.1297689290
Short name T1044
Test name
Test status
Simulation time 3762887200 ps
CPU time 5.01 seconds
Started Jul 02 08:11:32 AM PDT 24
Finished Jul 02 08:11:39 AM PDT 24
Peak memory 204820 kb
Host smart-8938482b-374b-4a65-bea8-e541c92c053d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297689290 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.1297689290
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.867380029
Short name T845
Test name
Test status
Simulation time 1762853764 ps
CPU time 9.73 seconds
Started Jul 02 08:11:33 AM PDT 24
Finished Jul 02 08:11:44 AM PDT 24
Peak memory 204812 kb
Host smart-f04c05aa-3f13-4938-bfd6-5b749b2ffa8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867380029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_tar
get_smoke.867380029
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.1924015969
Short name T1009
Test name
Test status
Simulation time 565128662 ps
CPU time 9.74 seconds
Started Jul 02 08:11:29 AM PDT 24
Finished Jul 02 08:11:40 AM PDT 24
Peak memory 206248 kb
Host smart-dfe72572-8b8f-413f-8810-def87df3fc0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924015969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_rd.1924015969
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.3606476854
Short name T18
Test name
Test status
Simulation time 23808255894 ps
CPU time 20.38 seconds
Started Jul 02 08:11:30 AM PDT 24
Finished Jul 02 08:11:52 AM PDT 24
Peak memory 356568 kb
Host smart-77aafd0c-35ac-4595-a38b-65b4d34ed41d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606476854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2
c_target_stress_wr.3606476854
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.2469138974
Short name T955
Test name
Test status
Simulation time 30015507932 ps
CPU time 1604.3 seconds
Started Jul 02 08:11:30 AM PDT 24
Finished Jul 02 08:38:16 AM PDT 24
Peak memory 3681632 kb
Host smart-e92ca42e-6790-4a9d-ae83-0b7b3bb0bf15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469138974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_
target_stretch.2469138974
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.3048186768
Short name T1209
Test name
Test status
Simulation time 1157585706 ps
CPU time 6.61 seconds
Started Jul 02 08:11:30 AM PDT 24
Finished Jul 02 08:11:37 AM PDT 24
Peak memory 218640 kb
Host smart-3a9d1daf-8989-493d-bce6-80e63dd4ee32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048186768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.3048186768
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.2038155143
Short name T986
Test name
Test status
Simulation time 80767718 ps
CPU time 1.78 seconds
Started Jul 02 08:11:30 AM PDT 24
Finished Jul 02 08:11:34 AM PDT 24
Peak memory 204816 kb
Host smart-f33fb765-d796-4b78-8e2f-0f0e703f8e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038155143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.2038155143
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.1921433427
Short name T1295
Test name
Test status
Simulation time 32014484 ps
CPU time 0.68 seconds
Started Jul 02 08:11:40 AM PDT 24
Finished Jul 02 08:11:43 AM PDT 24
Peak memory 204464 kb
Host smart-c4520d51-8a82-49a3-a7a6-3e4abb98a9ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921433427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.1921433427
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.797912924
Short name T601
Test name
Test status
Simulation time 206114869 ps
CPU time 1.66 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:11:42 AM PDT 24
Peak memory 213112 kb
Host smart-e325faf5-0d81-485a-95cd-2eac454149fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797912924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.797912924
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3609368467
Short name T1244
Test name
Test status
Simulation time 1280542429 ps
CPU time 16.8 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:11:58 AM PDT 24
Peak memory 270792 kb
Host smart-77a84fb7-f14b-47ad-8ad9-9078743657ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609368467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3609368467
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.181412064
Short name T730
Test name
Test status
Simulation time 11373895670 ps
CPU time 97.93 seconds
Started Jul 02 08:11:36 AM PDT 24
Finished Jul 02 08:13:17 AM PDT 24
Peak memory 824744 kb
Host smart-21098928-295a-4380-aa7c-68afdc9b927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181412064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.181412064
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.3431215949
Short name T654
Test name
Test status
Simulation time 2272581682 ps
CPU time 107.15 seconds
Started Jul 02 08:11:34 AM PDT 24
Finished Jul 02 08:13:23 AM PDT 24
Peak memory 581840 kb
Host smart-aa754195-53a6-46b2-97be-bca19108294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431215949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.3431215949
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.1378677136
Short name T477
Test name
Test status
Simulation time 357848844 ps
CPU time 1 seconds
Started Jul 02 08:11:28 AM PDT 24
Finished Jul 02 08:11:31 AM PDT 24
Peak memory 204400 kb
Host smart-e3a46973-b3d4-4772-9fcc-4ab6f6eb47f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378677136 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_f
mt.1378677136
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.1913424900
Short name T376
Test name
Test status
Simulation time 416686057 ps
CPU time 5.09 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:11:46 AM PDT 24
Peak memory 204820 kb
Host smart-57ec3729-2425-4442-a620-569744b6d4c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913424900 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx
.1913424900
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.2307419703
Short name T277
Test name
Test status
Simulation time 10654512797 ps
CPU time 166.43 seconds
Started Jul 02 08:11:30 AM PDT 24
Finished Jul 02 08:14:18 AM PDT 24
Peak memory 1592108 kb
Host smart-9b1232ad-9d57-4d1c-bda1-8c922d0ba781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307419703 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.2307419703
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.1002895689
Short name T1299
Test name
Test status
Simulation time 478695196 ps
CPU time 6.27 seconds
Started Jul 02 08:11:36 AM PDT 24
Finished Jul 02 08:11:45 AM PDT 24
Peak memory 204752 kb
Host smart-c8998ccf-d8cc-484b-8056-16f0d5f8b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002895689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.1002895689
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.541574878
Short name T455
Test name
Test status
Simulation time 2126383055 ps
CPU time 40.21 seconds
Started Jul 02 08:11:39 AM PDT 24
Finished Jul 02 08:12:22 AM PDT 24
Peak memory 479056 kb
Host smart-268a6c74-7f53-480a-8b38-28b13df6da56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541574878 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.541574878
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.1453181319
Short name T131
Test name
Test status
Simulation time 29013426 ps
CPU time 0.65 seconds
Started Jul 02 08:11:31 AM PDT 24
Finished Jul 02 08:11:33 AM PDT 24
Peak memory 204460 kb
Host smart-215b8d44-c148-49e7-918a-b220317c4ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453181319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.1453181319
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.49446830
Short name T453
Test name
Test status
Simulation time 7597587572 ps
CPU time 293.35 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:16:34 AM PDT 24
Peak memory 1925784 kb
Host smart-6056bfe8-fef2-40fe-a813-0b3d0e8d624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49446830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.49446830
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.65055975
Short name T708
Test name
Test status
Simulation time 131530179 ps
CPU time 1.13 seconds
Started Jul 02 08:11:35 AM PDT 24
Finished Jul 02 08:11:38 AM PDT 24
Peak memory 205596 kb
Host smart-96a88019-5d2b-4ba7-9393-4e0dd7b4bd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65055975 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.65055975
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.1897700020
Short name T866
Test name
Test status
Simulation time 3294722174 ps
CPU time 29.5 seconds
Started Jul 02 08:11:33 AM PDT 24
Finished Jul 02 08:12:04 AM PDT 24
Peak memory 289996 kb
Host smart-51313d6f-9758-4f8a-a7f7-ab6c1448b79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897700020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.1897700020
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.4120357597
Short name T119
Test name
Test status
Simulation time 21518714258 ps
CPU time 291.13 seconds
Started Jul 02 08:11:35 AM PDT 24
Finished Jul 02 08:16:28 AM PDT 24
Peak memory 1401968 kb
Host smart-e92c19c2-5082-41bb-806f-96e66156188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120357597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.4120357597
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.2919563376
Short name T879
Test name
Test status
Simulation time 691916427 ps
CPU time 9.71 seconds
Started Jul 02 08:11:39 AM PDT 24
Finished Jul 02 08:11:52 AM PDT 24
Peak memory 220800 kb
Host smart-a4b2f79a-c2e1-4d6d-8945-9d0d3603a34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919563376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.2919563376
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4273505575
Short name T1282
Test name
Test status
Simulation time 6816172557 ps
CPU time 3.54 seconds
Started Jul 02 08:11:39 AM PDT 24
Finished Jul 02 08:11:45 AM PDT 24
Peak memory 204884 kb
Host smart-0270f6c7-064d-4d6a-8a55-84b1263293b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273505575 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4273505575
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1204083709
Short name T1284
Test name
Test status
Simulation time 986017284 ps
CPU time 0.99 seconds
Started Jul 02 08:11:38 AM PDT 24
Finished Jul 02 08:11:42 AM PDT 24
Peak memory 204580 kb
Host smart-370f15d6-71c7-4482-aeea-194e302d3b95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204083709 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1204083709
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.2540876984
Short name T1026
Test name
Test status
Simulation time 184078165 ps
CPU time 0.81 seconds
Started Jul 02 08:11:37 AM PDT 24
Finished Jul 02 08:11:41 AM PDT 24
Peak memory 204596 kb
Host smart-0a6047ae-7755-41a6-9124-cb7fca605b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540876984 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_fifo_reset_tx.2540876984
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.2795964807
Short name T448
Test name
Test status
Simulation time 685486116 ps
CPU time 1.94 seconds
Started Jul 02 08:11:37 AM PDT 24
Finished Jul 02 08:11:42 AM PDT 24
Peak memory 204764 kb
Host smart-1c17a747-a02b-45a3-8cbf-2fb64dfdc0f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795964807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.2795964807
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.52529097
Short name T1421
Test name
Test status
Simulation time 256950727 ps
CPU time 1.14 seconds
Started Jul 02 08:11:40 AM PDT 24
Finished Jul 02 08:11:44 AM PDT 24
Peak memory 204552 kb
Host smart-e6940cb7-b5be-4d92-822c-433ed5bda4eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52529097 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.52529097
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1682693585
Short name T1235
Test name
Test status
Simulation time 2097637982 ps
CPU time 5.22 seconds
Started Jul 02 08:11:36 AM PDT 24
Finished Jul 02 08:11:44 AM PDT 24
Peak memory 215432 kb
Host smart-54311718-0c3c-4b05-aec6-9049260549c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682693585 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1682693585
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.95880471
Short name T876
Test name
Test status
Simulation time 9734286723 ps
CPU time 2.96 seconds
Started Jul 02 08:11:36 AM PDT 24
Finished Jul 02 08:11:42 AM PDT 24
Peak memory 204932 kb
Host smart-b28bd45a-0587-4472-afd7-f5c214dc0cdc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95880471 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.95880471
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2800105348
Short name T653
Test name
Test status
Simulation time 1472275714 ps
CPU time 17.15 seconds
Started Jul 02 08:11:35 AM PDT 24
Finished Jul 02 08:11:54 AM PDT 24
Peak memory 204828 kb
Host smart-9759e15d-c8f9-4403-8ed2-11011034718f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800105348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2800105348
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.2685622357
Short name T1483
Test name
Test status
Simulation time 1883876457 ps
CPU time 14.36 seconds
Started Jul 02 08:11:33 AM PDT 24
Finished Jul 02 08:11:49 AM PDT 24
Peak memory 212220 kb
Host smart-4dc8b7ab-cdd4-4630-b790-693c7a4e9bc7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685622357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_rd.2685622357
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.1417258419
Short name T1355
Test name
Test status
Simulation time 28210826575 ps
CPU time 24.55 seconds
Started Jul 02 08:11:37 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 592956 kb
Host smart-01030718-8fc1-437a-90e3-5376c4df63bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417258419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2
c_target_stress_wr.1417258419
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.3919466027
Short name T1280
Test name
Test status
Simulation time 33327506378 ps
CPU time 581.39 seconds
Started Jul 02 08:11:36 AM PDT 24
Finished Jul 02 08:21:21 AM PDT 24
Peak memory 3737704 kb
Host smart-7c91f975-2a8e-4516-96bc-64b8cf2f0661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919466027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.3919466027
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.2057697801
Short name T1388
Test name
Test status
Simulation time 1664020151 ps
CPU time 8.75 seconds
Started Jul 02 08:11:39 AM PDT 24
Finished Jul 02 08:11:51 AM PDT 24
Peak memory 221148 kb
Host smart-0e9e2918-b997-4a78-aa8a-aefcbbf3d89e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057697801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.2057697801
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.48426096
Short name T1211
Test name
Test status
Simulation time 229075983 ps
CPU time 3.33 seconds
Started Jul 02 08:11:42 AM PDT 24
Finished Jul 02 08:11:47 AM PDT 24
Peak memory 204832 kb
Host smart-af5df04e-4bf2-41e0-8046-efbe35148b3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48426096 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.48426096
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.143705728
Short name T1225
Test name
Test status
Simulation time 30030400 ps
CPU time 0.63 seconds
Started Jul 02 08:11:46 AM PDT 24
Finished Jul 02 08:11:48 AM PDT 24
Peak memory 204448 kb
Host smart-4d299a2d-7407-492b-8b8e-01ba90373423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143705728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.143705728
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_error_intr.336303802
Short name T1468
Test name
Test status
Simulation time 104617900 ps
CPU time 1.8 seconds
Started Jul 02 08:11:40 AM PDT 24
Finished Jul 02 08:11:44 AM PDT 24
Peak memory 213012 kb
Host smart-bca9c6f4-f9f6-4bb7-9816-de1c98a6d33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336303802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_error_intr.336303802
Directory /workspace/25.i2c_host_error_intr/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.2985877642
Short name T609
Test name
Test status
Simulation time 274002610 ps
CPU time 14.45 seconds
Started Jul 02 08:11:40 AM PDT 24
Finished Jul 02 08:11:58 AM PDT 24
Peak memory 262716 kb
Host smart-ed1fb5a2-f8cc-49be-a874-088ec033e872
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985877642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.2985877642
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.717569198
Short name T877
Test name
Test status
Simulation time 1728784562 ps
CPU time 49.31 seconds
Started Jul 02 08:11:42 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 631416 kb
Host smart-387857cd-de40-4eba-a345-11b645e66f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717569198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.717569198
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.4096636023
Short name T480
Test name
Test status
Simulation time 2754605745 ps
CPU time 65.7 seconds
Started Jul 02 08:11:41 AM PDT 24
Finished Jul 02 08:12:49 AM PDT 24
Peak memory 673376 kb
Host smart-69108a3e-e1f0-49a2-8052-db07ada61b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096636023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.4096636023
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.3435259686
Short name T1102
Test name
Test status
Simulation time 91711252 ps
CPU time 0.88 seconds
Started Jul 02 08:11:43 AM PDT 24
Finished Jul 02 08:11:46 AM PDT 24
Peak memory 204440 kb
Host smart-6b75474c-bbea-413e-873c-f0ca35169cf7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435259686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.3435259686
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.529628711
Short name T1347
Test name
Test status
Simulation time 356355890 ps
CPU time 4.72 seconds
Started Jul 02 08:11:40 AM PDT 24
Finished Jul 02 08:11:48 AM PDT 24
Peak memory 232904 kb
Host smart-7a735478-a55c-4dda-b9a3-6a30e0e18e2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529628711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.
529628711
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.3421572871
Short name T899
Test name
Test status
Simulation time 2664239458 ps
CPU time 60.5 seconds
Started Jul 02 08:11:41 AM PDT 24
Finished Jul 02 08:12:44 AM PDT 24
Peak memory 846824 kb
Host smart-abb54afd-7d41-4345-8024-216f10158a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421572871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.3421572871
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.3383590239
Short name T1040
Test name
Test status
Simulation time 542354897 ps
CPU time 8.23 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:11:58 AM PDT 24
Peak memory 204836 kb
Host smart-a2587a4e-5493-4bc2-9a6d-f1fcbb2bab4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383590239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.3383590239
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2369361683
Short name T744
Test name
Test status
Simulation time 2827304990 ps
CPU time 58.47 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:12:48 AM PDT 24
Peak memory 572244 kb
Host smart-73dcaed9-9360-4eba-8c61-84ee58fa7b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369361683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2369361683
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2290174253
Short name T137
Test name
Test status
Simulation time 37246846 ps
CPU time 0.67 seconds
Started Jul 02 08:11:41 AM PDT 24
Finished Jul 02 08:11:44 AM PDT 24
Peak memory 204512 kb
Host smart-4aa38991-b903-4786-8af3-f91823548d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290174253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2290174253
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.1666428638
Short name T595
Test name
Test status
Simulation time 12718648135 ps
CPU time 18.6 seconds
Started Jul 02 08:11:42 AM PDT 24
Finished Jul 02 08:12:03 AM PDT 24
Peak memory 204892 kb
Host smart-14f5ef38-9e1d-4084-a3f2-74a194e2cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666428638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.1666428638
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.1589124600
Short name T751
Test name
Test status
Simulation time 809610395 ps
CPU time 8.31 seconds
Started Jul 02 08:11:42 AM PDT 24
Finished Jul 02 08:11:52 AM PDT 24
Peak memory 204736 kb
Host smart-42c3e370-62f2-4268-a1d2-7804c9751cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589124600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1589124600
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.921822767
Short name T1101
Test name
Test status
Simulation time 2355318258 ps
CPU time 50.07 seconds
Started Jul 02 08:11:41 AM PDT 24
Finished Jul 02 08:12:34 AM PDT 24
Peak memory 294992 kb
Host smart-7dba9fb0-45f4-4508-a4e5-bd2675202414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921822767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.921822767
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.2465663072
Short name T105
Test name
Test status
Simulation time 54235950896 ps
CPU time 494.77 seconds
Started Jul 02 08:11:45 AM PDT 24
Finished Jul 02 08:20:00 AM PDT 24
Peak memory 2305232 kb
Host smart-4a4fb9be-f481-480b-8dbd-4cc1ce5bf1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465663072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.2465663072
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.792864339
Short name T583
Test name
Test status
Simulation time 1482012723 ps
CPU time 3.81 seconds
Started Jul 02 08:11:44 AM PDT 24
Finished Jul 02 08:11:49 AM PDT 24
Peak memory 213112 kb
Host smart-1aec9171-5dc7-41fb-b6c7-1b02ce12f8e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792864339 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.792864339
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.3446929997
Short name T155
Test name
Test status
Simulation time 349773501 ps
CPU time 1.35 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:11:50 AM PDT 24
Peak memory 204796 kb
Host smart-d72387d1-0c95-4dfb-b4ce-a1c6411667c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446929997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_fifo_reset_acq.3446929997
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.2535285210
Short name T610
Test name
Test status
Simulation time 200860428 ps
CPU time 1.25 seconds
Started Jul 02 08:11:44 AM PDT 24
Finished Jul 02 08:11:46 AM PDT 24
Peak memory 204760 kb
Host smart-b44b7d28-afd0-41b7-a28c-e959a84109a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535285210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.2535285210
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.2996861127
Short name T1352
Test name
Test status
Simulation time 819061195 ps
CPU time 1.56 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:11:49 AM PDT 24
Peak memory 204556 kb
Host smart-4c324758-f2ab-4b4e-8c14-b12aa9573bd5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996861127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.2996861127
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.2072756581
Short name T663
Test name
Test status
Simulation time 470935684 ps
CPU time 1.07 seconds
Started Jul 02 08:11:45 AM PDT 24
Finished Jul 02 08:11:47 AM PDT 24
Peak memory 204572 kb
Host smart-21ae4634-8565-4b86-9e32-09f385317cbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072756581 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.2072756581
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.907100168
Short name T777
Test name
Test status
Simulation time 537156995 ps
CPU time 3.49 seconds
Started Jul 02 08:11:40 AM PDT 24
Finished Jul 02 08:11:47 AM PDT 24
Peak memory 204832 kb
Host smart-1f84d80d-7527-48c7-9183-30078b4d7ec9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907100168 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 25.i2c_target_intr_smoke.907100168
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.3561467290
Short name T432
Test name
Test status
Simulation time 20235816961 ps
CPU time 24.04 seconds
Started Jul 02 08:11:45 AM PDT 24
Finished Jul 02 08:12:11 AM PDT 24
Peak memory 738388 kb
Host smart-0d66a600-70d4-4167-a866-e26c72c140ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561467290 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.3561467290
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.2531316268
Short name T924
Test name
Test status
Simulation time 4089009483 ps
CPU time 15.98 seconds
Started Jul 02 08:11:40 AM PDT 24
Finished Jul 02 08:11:59 AM PDT 24
Peak memory 204868 kb
Host smart-beba15ab-cb23-4058-ba62-352c310b78e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531316268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_ta
rget_smoke.2531316268
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.1143096868
Short name T1194
Test name
Test status
Simulation time 3093776260 ps
CPU time 33.51 seconds
Started Jul 02 08:11:42 AM PDT 24
Finished Jul 02 08:12:18 AM PDT 24
Peak memory 204868 kb
Host smart-fae9f452-b8a6-464a-b645-265028476c31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143096868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_rd.1143096868
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.3896047096
Short name T921
Test name
Test status
Simulation time 11541652826 ps
CPU time 2.93 seconds
Started Jul 02 08:11:42 AM PDT 24
Finished Jul 02 08:11:47 AM PDT 24
Peak memory 204844 kb
Host smart-4fc55cf9-1e30-4503-ab83-6da3c89e5ddc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896047096 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.3896047096
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.2568296582
Short name T1022
Test name
Test status
Simulation time 23027000484 ps
CPU time 244.71 seconds
Started Jul 02 08:11:42 AM PDT 24
Finished Jul 02 08:15:49 AM PDT 24
Peak memory 1891196 kb
Host smart-d2c85f37-c116-466e-8ea4-844704f0ef46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568296582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.2568296582
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.158280766
Short name T375
Test name
Test status
Simulation time 6382150056 ps
CPU time 8.26 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:11:57 AM PDT 24
Peak memory 213932 kb
Host smart-bf5f10f1-12a2-40f8-9daa-84425170b9dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158280766 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_timeout.158280766
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.3317266339
Short name T547
Test name
Test status
Simulation time 68577047 ps
CPU time 1.55 seconds
Started Jul 02 08:11:48 AM PDT 24
Finished Jul 02 08:11:52 AM PDT 24
Peak memory 204832 kb
Host smart-c4ad3139-2d37-4d8f-866c-4b95f80dc2cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317266339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.3317266339
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.175092246
Short name T939
Test name
Test status
Simulation time 43567119 ps
CPU time 0.62 seconds
Started Jul 02 08:11:52 AM PDT 24
Finished Jul 02 08:11:54 AM PDT 24
Peak memory 204420 kb
Host smart-5ef9388f-49ee-469f-baed-4395415a6273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175092246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.175092246
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.807386981
Short name T1054
Test name
Test status
Simulation time 505187109 ps
CPU time 2.39 seconds
Started Jul 02 08:11:50 AM PDT 24
Finished Jul 02 08:11:54 AM PDT 24
Peak memory 213096 kb
Host smart-01046ec6-16cf-486c-83c0-614373aa8e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807386981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.807386981
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1947269452
Short name T500
Test name
Test status
Simulation time 501633215 ps
CPU time 11.43 seconds
Started Jul 02 08:11:48 AM PDT 24
Finished Jul 02 08:12:02 AM PDT 24
Peak memory 236288 kb
Host smart-ccc709cf-5638-4e76-83de-fddd1f32ba4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947269452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1947269452
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.2995430351
Short name T1233
Test name
Test status
Simulation time 4115010024 ps
CPU time 66.85 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:12:56 AM PDT 24
Peak memory 646416 kb
Host smart-2b815322-d603-4da1-bf28-d7d311a00f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995430351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.2995430351
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.479411354
Short name T1410
Test name
Test status
Simulation time 6632587854 ps
CPU time 70.09 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:12:59 AM PDT 24
Peak memory 753748 kb
Host smart-992e3194-70ce-4a84-a19b-038a949dc293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479411354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.479411354
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.3509675328
Short name T622
Test name
Test status
Simulation time 588782953 ps
CPU time 1.06 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:11:49 AM PDT 24
Peak memory 204444 kb
Host smart-f1dbc078-28da-489d-b15f-015cc917d963
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509675328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_f
mt.3509675328
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.2229976938
Short name T1357
Test name
Test status
Simulation time 148387701 ps
CPU time 8.76 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:11:58 AM PDT 24
Peak memory 230684 kb
Host smart-155d52c0-083b-46d7-9b22-7cb42b5c9840
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229976938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.2229976938
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.315817807
Short name T106
Test name
Test status
Simulation time 11107098474 ps
CPU time 141.79 seconds
Started Jul 02 08:11:48 AM PDT 24
Finished Jul 02 08:14:12 AM PDT 24
Peak memory 1527800 kb
Host smart-bc9a1d79-a044-43ec-97a2-06e6c9525c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315817807 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.315817807
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.1323092328
Short name T519
Test name
Test status
Simulation time 442367056 ps
CPU time 5.34 seconds
Started Jul 02 08:11:52 AM PDT 24
Finished Jul 02 08:11:58 AM PDT 24
Peak memory 204816 kb
Host smart-7b470208-614b-454b-8097-d50bf6dca145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323092328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.1323092328
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_override.4033914991
Short name T959
Test name
Test status
Simulation time 26940841 ps
CPU time 0.71 seconds
Started Jul 02 08:11:46 AM PDT 24
Finished Jul 02 08:11:48 AM PDT 24
Peak memory 204476 kb
Host smart-841ffaa3-700e-489b-85b4-64bc81ddeee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033914991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.4033914991
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.49966984
Short name T930
Test name
Test status
Simulation time 1740452379 ps
CPU time 17.95 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:12:08 AM PDT 24
Peak memory 213044 kb
Host smart-0336a844-fa12-47ea-b298-b1f10153bc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49966984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.49966984
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.1770486244
Short name T944
Test name
Test status
Simulation time 2472628170 ps
CPU time 65.65 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:12:56 AM PDT 24
Peak memory 492468 kb
Host smart-0f1d6c56-7878-4baa-8ae0-e72d3f3a0100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770486244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.1770486244
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3603051597
Short name T1343
Test name
Test status
Simulation time 8354596752 ps
CPU time 38.7 seconds
Started Jul 02 08:11:47 AM PDT 24
Finished Jul 02 08:12:29 AM PDT 24
Peak memory 350508 kb
Host smart-e876120f-e073-4363-a47b-3d696a41a5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603051597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3603051597
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.3366548573
Short name T283
Test name
Test status
Simulation time 45694964298 ps
CPU time 499.42 seconds
Started Jul 02 08:11:49 AM PDT 24
Finished Jul 02 08:20:10 AM PDT 24
Peak memory 1791284 kb
Host smart-62a681ff-c2ee-47b0-8241-f8798f4423a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366548573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.3366548573
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.4047676627
Short name T713
Test name
Test status
Simulation time 527319357 ps
CPU time 22.41 seconds
Started Jul 02 08:11:48 AM PDT 24
Finished Jul 02 08:12:13 AM PDT 24
Peak memory 213036 kb
Host smart-47e5c16e-7266-431b-9ed6-b71e5b7b5d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047676627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.4047676627
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.4065468308
Short name T1392
Test name
Test status
Simulation time 2408391731 ps
CPU time 3.08 seconds
Started Jul 02 08:11:51 AM PDT 24
Finished Jul 02 08:11:55 AM PDT 24
Peak memory 205080 kb
Host smart-863259f6-4b32-4561-8d6d-6520e363367b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065468308 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.4065468308
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.341734305
Short name T1363
Test name
Test status
Simulation time 485947727 ps
CPU time 1.08 seconds
Started Jul 02 08:11:51 AM PDT 24
Finished Jul 02 08:11:54 AM PDT 24
Peak memory 214136 kb
Host smart-2c97bb49-e44a-43db-b4e9-53cfa639ab73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341734305 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.i2c_target_fifo_reset_tx.341734305
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.1038561656
Short name T860
Test name
Test status
Simulation time 1530443452 ps
CPU time 1.98 seconds
Started Jul 02 08:11:54 AM PDT 24
Finished Jul 02 08:11:57 AM PDT 24
Peak memory 204792 kb
Host smart-29326438-8f39-4839-99ae-74d6d13b6ce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038561656 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1038561656
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.2723934938
Short name T592
Test name
Test status
Simulation time 111161636 ps
CPU time 1.09 seconds
Started Jul 02 08:11:51 AM PDT 24
Finished Jul 02 08:11:54 AM PDT 24
Peak memory 204612 kb
Host smart-22c525b7-8944-457f-8cfa-8e82e12fd3d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723934938 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.2723934938
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_hrst.1995988752
Short name T718
Test name
Test status
Simulation time 475734011 ps
CPU time 3.67 seconds
Started Jul 02 08:11:50 AM PDT 24
Finished Jul 02 08:11:55 AM PDT 24
Peak memory 204808 kb
Host smart-c3d27a2f-2fee-49d0-984c-24e1093d9ecf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995988752 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 26.i2c_target_hrst.1995988752
Directory /workspace/26.i2c_target_hrst/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3719201897
Short name T849
Test name
Test status
Simulation time 5733574185 ps
CPU time 4.55 seconds
Started Jul 02 08:11:53 AM PDT 24
Finished Jul 02 08:11:59 AM PDT 24
Peak memory 213112 kb
Host smart-5788c3ce-5b50-4990-be63-790e643e8f76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719201897 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3719201897
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.1528095605
Short name T452
Test name
Test status
Simulation time 4211757901 ps
CPU time 19.66 seconds
Started Jul 02 08:11:50 AM PDT 24
Finished Jul 02 08:12:12 AM PDT 24
Peak memory 747952 kb
Host smart-76dda358-473e-4103-8bab-24f268e7cb13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528095605 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.1528095605
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.1297549843
Short name T1159
Test name
Test status
Simulation time 6878703369 ps
CPU time 33.5 seconds
Started Jul 02 08:11:52 AM PDT 24
Finished Jul 02 08:12:27 AM PDT 24
Peak memory 228548 kb
Host smart-7251c5e1-ac71-4cd9-a52b-23db65bf2766
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297549843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.1297549843
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.3665794460
Short name T507
Test name
Test status
Simulation time 30926233093 ps
CPU time 39.42 seconds
Started Jul 02 08:11:51 AM PDT 24
Finished Jul 02 08:12:31 AM PDT 24
Peak memory 781504 kb
Host smart-0335a35c-3075-449f-9869-e22f8512d282
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665794460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_wr.3665794460
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.2220014627
Short name T1192
Test name
Test status
Simulation time 7604360659 ps
CPU time 201.82 seconds
Started Jul 02 08:11:53 AM PDT 24
Finished Jul 02 08:15:16 AM PDT 24
Peak memory 1913404 kb
Host smart-f2f759da-8d52-4932-abc4-51913cb7b4db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220014627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.2220014627
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.1951784778
Short name T885
Test name
Test status
Simulation time 2212545133 ps
CPU time 6.91 seconds
Started Jul 02 08:11:53 AM PDT 24
Finished Jul 02 08:12:02 AM PDT 24
Peak memory 221008 kb
Host smart-b248339b-7edd-49d7-99b1-c84ebbeb7a5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951784778 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.1951784778
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.3492189683
Short name T1389
Test name
Test status
Simulation time 105854401 ps
CPU time 2.43 seconds
Started Jul 02 08:11:53 AM PDT 24
Finished Jul 02 08:11:57 AM PDT 24
Peak memory 204804 kb
Host smart-1d45314e-e686-4e51-95ee-cc8a7f888ade
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492189683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.3492189683
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.3133031891
Short name T1205
Test name
Test status
Simulation time 20741652 ps
CPU time 0.67 seconds
Started Jul 02 08:12:02 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 204464 kb
Host smart-8c7b429f-23e4-4c2d-8c8e-b6f88a924c82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133031891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.3133031891
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2041306755
Short name T1155
Test name
Test status
Simulation time 106607401 ps
CPU time 2.68 seconds
Started Jul 02 08:11:56 AM PDT 24
Finished Jul 02 08:12:00 AM PDT 24
Peak memory 212972 kb
Host smart-183d8059-ec50-4735-a245-6469fc43e74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041306755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2041306755
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.123635185
Short name T795
Test name
Test status
Simulation time 7237848717 ps
CPU time 11.4 seconds
Started Jul 02 08:11:56 AM PDT 24
Finished Jul 02 08:12:09 AM PDT 24
Peak memory 336432 kb
Host smart-d3a9881d-e9b3-44de-98bb-cdcdf42383c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123635185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_empt
y.123635185
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.1485114410
Short name T157
Test name
Test status
Simulation time 1660621562 ps
CPU time 109.42 seconds
Started Jul 02 08:11:55 AM PDT 24
Finished Jul 02 08:13:45 AM PDT 24
Peak memory 603768 kb
Host smart-4b1d56ee-7ecb-4c8d-a078-7649fdfd31df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485114410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.1485114410
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.4115005969
Short name T335
Test name
Test status
Simulation time 5948173485 ps
CPU time 66.92 seconds
Started Jul 02 08:11:57 AM PDT 24
Finished Jul 02 08:13:06 AM PDT 24
Peak memory 738328 kb
Host smart-53f9e6d1-f10e-4f7c-b891-5fc59eb6b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115005969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.4115005969
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.2979782717
Short name T802
Test name
Test status
Simulation time 161568129 ps
CPU time 1.31 seconds
Started Jul 02 08:11:57 AM PDT 24
Finished Jul 02 08:12:00 AM PDT 24
Peak memory 204644 kb
Host smart-a218a123-d603-4a56-8913-458e4966c15b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979782717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.2979782717
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3479904475
Short name T151
Test name
Test status
Simulation time 900935551 ps
CPU time 4.99 seconds
Started Jul 02 08:11:58 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 204800 kb
Host smart-6ebc8b8f-f382-4a88-bb4a-7e9e76627afa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479904475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3479904475
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.4009487355
Short name T1491
Test name
Test status
Simulation time 4184040308 ps
CPU time 98.22 seconds
Started Jul 02 08:11:51 AM PDT 24
Finished Jul 02 08:13:30 AM PDT 24
Peak memory 1246304 kb
Host smart-258d4df7-a2b2-4484-8192-09c26d4de0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009487355 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.4009487355
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.1632255481
Short name T264
Test name
Test status
Simulation time 7193780179 ps
CPU time 5.52 seconds
Started Jul 02 08:12:03 AM PDT 24
Finished Jul 02 08:12:12 AM PDT 24
Peak memory 205148 kb
Host smart-91a9bbc8-307f-47f3-92e9-99ed0061b680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632255481 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.1632255481
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.918308146
Short name T579
Test name
Test status
Simulation time 5330441744 ps
CPU time 26.83 seconds
Started Jul 02 08:12:04 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 355460 kb
Host smart-8818c8a9-53bf-46bb-b989-49933ebb24a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918308146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.918308146
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.4087627832
Short name T136
Test name
Test status
Simulation time 22324111 ps
CPU time 0.71 seconds
Started Jul 02 08:11:51 AM PDT 24
Finished Jul 02 08:11:53 AM PDT 24
Peak memory 204500 kb
Host smart-fd8adef7-1257-49c1-a35d-19767ed60803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087627832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.4087627832
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3100116468
Short name T122
Test name
Test status
Simulation time 871143367 ps
CPU time 15.76 seconds
Started Jul 02 08:11:58 AM PDT 24
Finished Jul 02 08:12:15 AM PDT 24
Peak memory 403988 kb
Host smart-a23e6ff6-ae5d-4b3e-847a-076476f0b028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100116468 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3100116468
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.2090702683
Short name T297
Test name
Test status
Simulation time 223479982 ps
CPU time 1.05 seconds
Started Jul 02 08:11:55 AM PDT 24
Finished Jul 02 08:11:57 AM PDT 24
Peak memory 204552 kb
Host smart-b1eca8c3-a845-4ee8-8388-60879a9a74eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090702683 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.2090702683
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.110088399
Short name T1420
Test name
Test status
Simulation time 2773991263 ps
CPU time 32.35 seconds
Started Jul 02 08:11:52 AM PDT 24
Finished Jul 02 08:12:26 AM PDT 24
Peak memory 348996 kb
Host smart-52ffda15-c895-4060-8e95-daa349beeb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110088399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.110088399
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.4047653176
Short name T544
Test name
Test status
Simulation time 36839484348 ps
CPU time 766.36 seconds
Started Jul 02 08:11:57 AM PDT 24
Finished Jul 02 08:24:45 AM PDT 24
Peak memory 1748656 kb
Host smart-9fce5108-c761-4ac8-886e-25077046ee90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047653176 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.4047653176
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.3041768425
Short name T1117
Test name
Test status
Simulation time 1155634290 ps
CPU time 21.01 seconds
Started Jul 02 08:11:57 AM PDT 24
Finished Jul 02 08:12:21 AM PDT 24
Peak memory 220684 kb
Host smart-4c4959fc-117a-4f81-9f55-b1e4bbaefbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041768425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.3041768425
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.3882846124
Short name T698
Test name
Test status
Simulation time 1094048338 ps
CPU time 5.18 seconds
Started Jul 02 08:12:03 AM PDT 24
Finished Jul 02 08:12:11 AM PDT 24
Peak memory 213648 kb
Host smart-5198708c-1087-4a64-b5bd-f5094d7cd278
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882846124 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.3882846124
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.204494565
Short name T817
Test name
Test status
Simulation time 972651696 ps
CPU time 1.38 seconds
Started Jul 02 08:11:56 AM PDT 24
Finished Jul 02 08:11:59 AM PDT 24
Peak memory 204792 kb
Host smart-01d04da7-9f36-4dc6-881d-e14fccd8b3a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204494565 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_acq.204494565
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3856885107
Short name T12
Test name
Test status
Simulation time 136267219 ps
CPU time 0.91 seconds
Started Jul 02 08:11:58 AM PDT 24
Finished Jul 02 08:12:01 AM PDT 24
Peak memory 204568 kb
Host smart-c5179171-3efa-4164-9cba-c4dd647d7c0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856885107 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3856885107
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.2441320318
Short name T788
Test name
Test status
Simulation time 896010496 ps
CPU time 2.66 seconds
Started Jul 02 08:12:01 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 204672 kb
Host smart-5c142359-f325-4757-a5c1-1ba7497ac1dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441320318 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.2441320318
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.3986511226
Short name T411
Test name
Test status
Simulation time 120792641 ps
CPU time 1.13 seconds
Started Jul 02 08:12:01 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 204588 kb
Host smart-3e7c56a5-e629-423f-989a-6163e4fba533
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986511226 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.3986511226
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_hrst.1391040924
Short name T1329
Test name
Test status
Simulation time 377396334 ps
CPU time 2.75 seconds
Started Jul 02 08:12:02 AM PDT 24
Finished Jul 02 08:12:07 AM PDT 24
Peak memory 204756 kb
Host smart-4d056d01-ed99-4803-992c-33ea5aa5e2b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391040924 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 27.i2c_target_hrst.1391040924
Directory /workspace/27.i2c_target_hrst/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.1859063193
Short name T440
Test name
Test status
Simulation time 1250614896 ps
CPU time 7.11 seconds
Started Jul 02 08:11:57 AM PDT 24
Finished Jul 02 08:12:06 AM PDT 24
Peak memory 213060 kb
Host smart-4b3415ef-616d-4568-892a-8d683a570aad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859063193 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.1859063193
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.873215872
Short name T701
Test name
Test status
Simulation time 22328399391 ps
CPU time 180.17 seconds
Started Jul 02 08:11:56 AM PDT 24
Finished Jul 02 08:14:58 AM PDT 24
Peak memory 1970328 kb
Host smart-068ae8b0-1b10-4963-b40a-5f52ba075d59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873215872 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.873215872
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.1679405974
Short name T1369
Test name
Test status
Simulation time 1251618690 ps
CPU time 12.52 seconds
Started Jul 02 08:11:58 AM PDT 24
Finished Jul 02 08:12:12 AM PDT 24
Peak memory 204796 kb
Host smart-55ddf920-b644-466c-a947-ad5295910afb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679405974 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.1679405974
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.3932413904
Short name T1306
Test name
Test status
Simulation time 1558005152 ps
CPU time 31.53 seconds
Started Jul 02 08:11:58 AM PDT 24
Finished Jul 02 08:12:31 AM PDT 24
Peak memory 204824 kb
Host smart-6f4bb251-b6d8-4d9b-90fa-e0b84200b602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932413904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_rd.3932413904
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.1447423330
Short name T180
Test name
Test status
Simulation time 28647125740 ps
CPU time 149.13 seconds
Started Jul 02 08:11:58 AM PDT 24
Finished Jul 02 08:14:29 AM PDT 24
Peak memory 2037780 kb
Host smart-f92eaf20-bdbf-47a1-8b14-bf291942c0d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447423330 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.1447423330
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.3780084410
Short name T605
Test name
Test status
Simulation time 19787099234 ps
CPU time 2529.04 seconds
Started Jul 02 08:11:58 AM PDT 24
Finished Jul 02 08:54:10 AM PDT 24
Peak memory 4388680 kb
Host smart-78d2b3b2-aa52-45d6-a15e-cdcf31890508
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780084410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.3780084410
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3629751861
Short name T1094
Test name
Test status
Simulation time 1310926286 ps
CPU time 7.73 seconds
Started Jul 02 08:11:56 AM PDT 24
Finished Jul 02 08:12:06 AM PDT 24
Peak memory 220188 kb
Host smart-9617a8a4-c837-4b6e-b386-8d7dd77c9269
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629751861 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3629751861
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.3644242301
Short name T962
Test name
Test status
Simulation time 1381573354 ps
CPU time 16.4 seconds
Started Jul 02 08:12:03 AM PDT 24
Finished Jul 02 08:12:22 AM PDT 24
Peak memory 204808 kb
Host smart-7d61cb2b-7b45-4bc1-a0af-803fd561c0fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644242301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3644242301
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2913838840
Short name T1267
Test name
Test status
Simulation time 15965215 ps
CPU time 0.64 seconds
Started Jul 02 08:12:09 AM PDT 24
Finished Jul 02 08:12:12 AM PDT 24
Peak memory 204452 kb
Host smart-fe19c5bc-7127-44f0-8bf7-361b1c2ccff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913838840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2913838840
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_error_intr.3521283859
Short name T896
Test name
Test status
Simulation time 227672529 ps
CPU time 1.27 seconds
Started Jul 02 08:12:04 AM PDT 24
Finished Jul 02 08:12:08 AM PDT 24
Peak memory 213096 kb
Host smart-c8a1b9e8-ad03-4b40-83e5-6ace2c49394c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521283859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_error_intr.3521283859
Directory /workspace/28.i2c_host_error_intr/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2777310851
Short name T412
Test name
Test status
Simulation time 1194979305 ps
CPU time 16.05 seconds
Started Jul 02 08:12:01 AM PDT 24
Finished Jul 02 08:12:19 AM PDT 24
Peak memory 268012 kb
Host smart-6857d039-4448-4663-9d6a-a31bdc493a17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777310851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2777310851
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.106683663
Short name T72
Test name
Test status
Simulation time 5262176744 ps
CPU time 79.11 seconds
Started Jul 02 08:12:01 AM PDT 24
Finished Jul 02 08:13:23 AM PDT 24
Peak memory 689276 kb
Host smart-a98e28c1-ea4a-4f21-b4de-d5ac62af3b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106683663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.106683663
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.2832560629
Short name T809
Test name
Test status
Simulation time 8474604053 ps
CPU time 154.43 seconds
Started Jul 02 08:12:01 AM PDT 24
Finished Jul 02 08:14:38 AM PDT 24
Peak memory 734136 kb
Host smart-e5701e69-58b4-4332-8d93-c5d511049e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832560629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.2832560629
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2905929484
Short name T961
Test name
Test status
Simulation time 427386203 ps
CPU time 0.95 seconds
Started Jul 02 08:12:02 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 204412 kb
Host smart-caad4457-c044-4698-94bb-7fd7c64b7f14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905929484 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2905929484
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.1800202776
Short name T427
Test name
Test status
Simulation time 622463600 ps
CPU time 8.87 seconds
Started Jul 02 08:12:03 AM PDT 24
Finished Jul 02 08:12:15 AM PDT 24
Peak memory 204776 kb
Host smart-8ba94c89-2401-4842-b140-9f3b7b115065
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800202776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx
.1800202776
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.2087428983
Short name T1066
Test name
Test status
Simulation time 9541528229 ps
CPU time 355.04 seconds
Started Jul 02 08:12:02 AM PDT 24
Finished Jul 02 08:17:59 AM PDT 24
Peak memory 1370788 kb
Host smart-b938ba1b-871e-48ed-8e82-8eeab98356ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087428983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.2087428983
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.3879575085
Short name T1331
Test name
Test status
Simulation time 232385405 ps
CPU time 9.98 seconds
Started Jul 02 08:12:07 AM PDT 24
Finished Jul 02 08:12:19 AM PDT 24
Peak memory 204868 kb
Host smart-3e056e46-c2b0-4e85-86be-66aa201a714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879575085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.3879575085
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.4283779536
Short name T1423
Test name
Test status
Simulation time 2040773066 ps
CPU time 30.3 seconds
Started Jul 02 08:12:08 AM PDT 24
Finished Jul 02 08:12:40 AM PDT 24
Peak memory 374724 kb
Host smart-dbd4e639-2a68-43d6-8de3-43cf53ab3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283779536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.4283779536
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.143747935
Short name T1516
Test name
Test status
Simulation time 45709653 ps
CPU time 0.68 seconds
Started Jul 02 08:12:01 AM PDT 24
Finished Jul 02 08:12:05 AM PDT 24
Peak memory 204492 kb
Host smart-73fb0888-48b7-45db-8edd-9dac309b804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143747935 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.143747935
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.3509188931
Short name T1138
Test name
Test status
Simulation time 5209529194 ps
CPU time 52.39 seconds
Started Jul 02 08:12:02 AM PDT 24
Finished Jul 02 08:12:58 AM PDT 24
Peak memory 205556 kb
Host smart-06dbf5fa-c478-4f2a-98dc-caf0c916bed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509188931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.3509188931
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.3346636342
Short name T700
Test name
Test status
Simulation time 83210703 ps
CPU time 3.88 seconds
Started Jul 02 08:12:02 AM PDT 24
Finished Jul 02 08:12:09 AM PDT 24
Peak memory 204648 kb
Host smart-96120ae4-5efa-4284-abbd-d103e042bf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346636342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3346636342
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.2888670601
Short name T385
Test name
Test status
Simulation time 1526251077 ps
CPU time 30.66 seconds
Started Jul 02 08:12:03 AM PDT 24
Finished Jul 02 08:12:36 AM PDT 24
Peak memory 388780 kb
Host smart-cc59ddda-df8d-4cd8-bd22-325e23838f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888670601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.2888670601
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.1389167298
Short name T99
Test name
Test status
Simulation time 127971767646 ps
CPU time 461.64 seconds
Started Jul 02 08:12:02 AM PDT 24
Finished Jul 02 08:19:47 AM PDT 24
Peak memory 2829112 kb
Host smart-44e21951-379b-43ec-adae-f92aa4f17379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389167298 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.1389167298
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.2592388248
Short name T275
Test name
Test status
Simulation time 1765793378 ps
CPU time 14.01 seconds
Started Jul 02 08:12:04 AM PDT 24
Finished Jul 02 08:12:21 AM PDT 24
Peak memory 221144 kb
Host smart-99836cf2-952b-403c-867f-9803a7e3cbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592388248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.2592388248
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.1438446906
Short name T1173
Test name
Test status
Simulation time 733898837 ps
CPU time 4.1 seconds
Started Jul 02 08:12:07 AM PDT 24
Finished Jul 02 08:12:13 AM PDT 24
Peak memory 204772 kb
Host smart-d4524679-8d4c-4986-adc8-930b47e00865
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438446906 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.1438446906
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.782761177
Short name T571
Test name
Test status
Simulation time 452080212 ps
CPU time 1.35 seconds
Started Jul 02 08:12:12 AM PDT 24
Finished Jul 02 08:12:16 AM PDT 24
Peak memory 219176 kb
Host smart-94358376-28cd-40cb-b1c6-6c65bbbc9eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782761177 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_acq.782761177
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.3476677008
Short name T976
Test name
Test status
Simulation time 341554348 ps
CPU time 1.31 seconds
Started Jul 02 08:12:12 AM PDT 24
Finished Jul 02 08:12:16 AM PDT 24
Peak memory 204800 kb
Host smart-bca52c8b-b9f1-4159-91a4-a86b6f804eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476677008 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 28.i2c_target_fifo_reset_tx.3476677008
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.2683932007
Short name T1041
Test name
Test status
Simulation time 922150504 ps
CPU time 2.98 seconds
Started Jul 02 08:12:07 AM PDT 24
Finished Jul 02 08:12:12 AM PDT 24
Peak memory 204820 kb
Host smart-77099173-c232-4aa1-8576-b9f5f032974c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683932007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.2683932007
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.3464336997
Short name T127
Test name
Test status
Simulation time 793325537 ps
CPU time 1.15 seconds
Started Jul 02 08:12:06 AM PDT 24
Finished Jul 02 08:12:09 AM PDT 24
Peak memory 204604 kb
Host smart-f3e53676-6036-4a45-99d0-8d034d36ceb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464336997 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.3464336997
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.1731305090
Short name T1479
Test name
Test status
Simulation time 1144720838 ps
CPU time 3.34 seconds
Started Jul 02 08:12:08 AM PDT 24
Finished Jul 02 08:12:13 AM PDT 24
Peak memory 204832 kb
Host smart-b432000f-a2ed-48f9-933f-a148c1944267
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731305090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.1731305090
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1618694403
Short name T291
Test name
Test status
Simulation time 5458394014 ps
CPU time 7.02 seconds
Started Jul 02 08:12:10 AM PDT 24
Finished Jul 02 08:12:20 AM PDT 24
Peak memory 218132 kb
Host smart-3251a252-b97f-462a-8ca5-512f89e4e025
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618694403 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1618694403
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.1343144046
Short name T1029
Test name
Test status
Simulation time 10243139574 ps
CPU time 4.07 seconds
Started Jul 02 08:12:11 AM PDT 24
Finished Jul 02 08:12:18 AM PDT 24
Peak memory 204928 kb
Host smart-3a2067cf-6e80-4b63-8d84-deff0e607060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343144046 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.1343144046
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.4241644530
Short name T1480
Test name
Test status
Simulation time 1503836546 ps
CPU time 12.89 seconds
Started Jul 02 08:12:07 AM PDT 24
Finished Jul 02 08:12:22 AM PDT 24
Peak memory 204828 kb
Host smart-ff1f04a4-482e-4f7e-ab26-0e5ceddd6643
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241644530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.4241644530
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.762420281
Short name T612
Test name
Test status
Simulation time 551689012 ps
CPU time 23.51 seconds
Started Jul 02 08:12:07 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 204828 kb
Host smart-02c465b5-cf91-44e7-b09c-94901136acdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762420281 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c
_target_stress_rd.762420281
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.1344287313
Short name T466
Test name
Test status
Simulation time 11433505955 ps
CPU time 6.78 seconds
Started Jul 02 08:12:04 AM PDT 24
Finished Jul 02 08:12:14 AM PDT 24
Peak memory 204864 kb
Host smart-bec4f671-2809-49dd-b135-69b78a0d4d8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344287313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.1344287313
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.2174752469
Short name T187
Test name
Test status
Simulation time 26110031985 ps
CPU time 392.84 seconds
Started Jul 02 08:12:08 AM PDT 24
Finished Jul 02 08:18:43 AM PDT 24
Peak memory 2949420 kb
Host smart-04a43b94-e2b8-4b10-a55d-bd81b511e762
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174752469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.2174752469
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.1907300153
Short name T602
Test name
Test status
Simulation time 17380542353 ps
CPU time 7.33 seconds
Started Jul 02 08:12:06 AM PDT 24
Finished Jul 02 08:12:15 AM PDT 24
Peak memory 205368 kb
Host smart-72f5183e-8669-4eef-af2a-2206735ffcbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907300153 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 28.i2c_target_timeout.1907300153
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.1973913947
Short name T182
Test name
Test status
Simulation time 516877876 ps
CPU time 7.22 seconds
Started Jul 02 08:12:10 AM PDT 24
Finished Jul 02 08:12:20 AM PDT 24
Peak memory 204832 kb
Host smart-308ffb39-04de-4d24-9626-bc7ba5450edb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973913947 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.1973913947
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.427792744
Short name T1515
Test name
Test status
Simulation time 16495993 ps
CPU time 0.61 seconds
Started Jul 02 08:12:12 AM PDT 24
Finished Jul 02 08:12:15 AM PDT 24
Peak memory 204484 kb
Host smart-f0fba18f-3dc1-4d2e-906e-223490fda284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427792744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.427792744
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.1767239282
Short name T1394
Test name
Test status
Simulation time 950690613 ps
CPU time 1.38 seconds
Started Jul 02 08:12:08 AM PDT 24
Finished Jul 02 08:12:11 AM PDT 24
Peak memory 212988 kb
Host smart-d27276ae-8f36-42a7-8e4a-85b4031a1870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767239282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.1767239282
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.199009851
Short name T405
Test name
Test status
Simulation time 633209924 ps
CPU time 14.18 seconds
Started Jul 02 08:12:10 AM PDT 24
Finished Jul 02 08:12:27 AM PDT 24
Peak memory 348872 kb
Host smart-c8b63604-a59e-41b7-a282-fd2a359a2020
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199009851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_empt
y.199009851
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.3319424288
Short name T847
Test name
Test status
Simulation time 60449520622 ps
CPU time 118.79 seconds
Started Jul 02 08:12:08 AM PDT 24
Finished Jul 02 08:14:09 AM PDT 24
Peak memory 964012 kb
Host smart-8c4f9998-c5cd-45a5-8c81-4ec26b71e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319424288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.3319424288
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.3824338736
Short name T589
Test name
Test status
Simulation time 4933841487 ps
CPU time 88.78 seconds
Started Jul 02 08:12:10 AM PDT 24
Finished Jul 02 08:13:42 AM PDT 24
Peak memory 792068 kb
Host smart-9a4a15c5-52cd-4603-8c21-357c81ff48e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824338736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.3824338736
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.2699524586
Short name T1203
Test name
Test status
Simulation time 93588724 ps
CPU time 0.92 seconds
Started Jul 02 08:12:10 AM PDT 24
Finished Jul 02 08:12:14 AM PDT 24
Peak memory 204444 kb
Host smart-3b7d158f-30e2-4a8e-8c33-d282e51e843d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699524586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.2699524586
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.349856148
Short name T563
Test name
Test status
Simulation time 399775242 ps
CPU time 4 seconds
Started Jul 02 08:12:08 AM PDT 24
Finished Jul 02 08:12:14 AM PDT 24
Peak memory 204816 kb
Host smart-de18d9ab-eee6-4081-b6b6-d012cb7479fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349856148 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx.
349856148
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.3819256165
Short name T613
Test name
Test status
Simulation time 13464042411 ps
CPU time 207.86 seconds
Started Jul 02 08:12:11 AM PDT 24
Finished Jul 02 08:15:42 AM PDT 24
Peak memory 980160 kb
Host smart-821eccd0-b6c0-459a-a13b-97ea4368bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819256165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.3819256165
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.4130744033
Short name T389
Test name
Test status
Simulation time 694066410 ps
CPU time 14.37 seconds
Started Jul 02 08:12:13 AM PDT 24
Finished Jul 02 08:12:30 AM PDT 24
Peak memory 204820 kb
Host smart-92b607cc-d1dd-4cf4-ae35-16c447b8ee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130744033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.4130744033
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.4064411865
Short name T1530
Test name
Test status
Simulation time 2351277279 ps
CPU time 43.44 seconds
Started Jul 02 08:12:13 AM PDT 24
Finished Jul 02 08:12:59 AM PDT 24
Peak memory 374948 kb
Host smart-09a54457-4f5b-47ff-9fdb-20f99fc07fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064411865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.4064411865
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.3710064038
Short name T503
Test name
Test status
Simulation time 98540815 ps
CPU time 0.69 seconds
Started Jul 02 08:12:08 AM PDT 24
Finished Jul 02 08:12:10 AM PDT 24
Peak memory 204508 kb
Host smart-e0daf9b4-0d3c-4c71-b465-7c335c30ab04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710064038 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.3710064038
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf.1528630155
Short name T743
Test name
Test status
Simulation time 12354195659 ps
CPU time 86.43 seconds
Started Jul 02 08:12:10 AM PDT 24
Finished Jul 02 08:13:39 AM PDT 24
Peak memory 871540 kb
Host smart-b9947c7d-d999-404e-bc4e-8d5c0097d826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528630155 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf.1528630155
Directory /workspace/29.i2c_host_perf/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.1691548862
Short name T1128
Test name
Test status
Simulation time 485205510 ps
CPU time 1.85 seconds
Started Jul 02 08:12:09 AM PDT 24
Finished Jul 02 08:12:12 AM PDT 24
Peak memory 204656 kb
Host smart-6f9a11a7-adc8-407f-86ab-3973b95876f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691548862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.1691548862
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.4155854989
Short name T1053
Test name
Test status
Simulation time 1790459064 ps
CPU time 86.83 seconds
Started Jul 02 08:12:07 AM PDT 24
Finished Jul 02 08:13:36 AM PDT 24
Peak memory 371844 kb
Host smart-34c171f0-b1bd-4230-a84b-57671ea67662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155854989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.4155854989
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2123932819
Short name T1466
Test name
Test status
Simulation time 1920096845 ps
CPU time 18.7 seconds
Started Jul 02 08:12:10 AM PDT 24
Finished Jul 02 08:12:32 AM PDT 24
Peak memory 216048 kb
Host smart-d028f57e-dc5b-4272-a2e8-f819b23e3dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123932819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2123932819
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.241468001
Short name T368
Test name
Test status
Simulation time 2238033562 ps
CPU time 3.28 seconds
Started Jul 02 08:12:12 AM PDT 24
Finished Jul 02 08:12:18 AM PDT 24
Peak memory 204812 kb
Host smart-392db4a6-4117-423c-8d18-de331d666daf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241468001 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.241468001
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.1363401347
Short name T758
Test name
Test status
Simulation time 254349560 ps
CPU time 1.49 seconds
Started Jul 02 08:12:15 AM PDT 24
Finished Jul 02 08:12:19 AM PDT 24
Peak memory 204756 kb
Host smart-a2ef2d29-793e-4918-9bb1-da164f5bc343
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363401347 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.1363401347
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3495474110
Short name T1182
Test name
Test status
Simulation time 236793817 ps
CPU time 0.83 seconds
Started Jul 02 08:12:16 AM PDT 24
Finished Jul 02 08:12:19 AM PDT 24
Peak memory 217608 kb
Host smart-a10ff727-30a7-4385-b89d-d9a8ecc73b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495474110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3495474110
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.2410010814
Short name T266
Test name
Test status
Simulation time 2157236376 ps
CPU time 2.75 seconds
Started Jul 02 08:12:16 AM PDT 24
Finished Jul 02 08:12:21 AM PDT 24
Peak memory 204912 kb
Host smart-244001d4-8223-4663-b3d9-4ab73bef8d2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410010814 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.2410010814
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.3417605686
Short name T829
Test name
Test status
Simulation time 330288588 ps
CPU time 0.93 seconds
Started Jul 02 08:12:16 AM PDT 24
Finished Jul 02 08:12:19 AM PDT 24
Peak memory 204600 kb
Host smart-5c9e16d9-b5aa-456a-a8fc-0d1090824cdb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417605686 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.3417605686
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_hrst.412714476
Short name T439
Test name
Test status
Simulation time 1317260074 ps
CPU time 4.54 seconds
Started Jul 02 08:12:17 AM PDT 24
Finished Jul 02 08:12:24 AM PDT 24
Peak memory 204764 kb
Host smart-83621f8c-f85a-42e8-939a-04fb6efeb31f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412714476 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 29.i2c_target_hrst.412714476
Directory /workspace/29.i2c_target_hrst/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.2123050388
Short name T1266
Test name
Test status
Simulation time 4245467414 ps
CPU time 6.07 seconds
Started Jul 02 08:12:13 AM PDT 24
Finished Jul 02 08:12:21 AM PDT 24
Peak memory 215932 kb
Host smart-bdc4b058-3fde-45c5-8f7c-1bf3082176bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123050388 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 29.i2c_target_intr_smoke.2123050388
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.890929704
Short name T397
Test name
Test status
Simulation time 25321418828 ps
CPU time 32.72 seconds
Started Jul 02 08:12:13 AM PDT 24
Finished Jul 02 08:12:48 AM PDT 24
Peak memory 845044 kb
Host smart-f5884ab8-8b00-4dda-80c3-e3f21c5af36e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890929704 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.890929704
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.2133505284
Short name T526
Test name
Test status
Simulation time 3163011284 ps
CPU time 27.84 seconds
Started Jul 02 08:12:06 AM PDT 24
Finished Jul 02 08:12:36 AM PDT 24
Peak memory 204908 kb
Host smart-b8cd1cdf-0c67-45ea-8eef-9abaca456179
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133505284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_ta
rget_smoke.2133505284
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.589509809
Short name T144
Test name
Test status
Simulation time 13747197817 ps
CPU time 23.18 seconds
Started Jul 02 08:12:11 AM PDT 24
Finished Jul 02 08:12:37 AM PDT 24
Peak memory 232452 kb
Host smart-2656296a-8320-4eb5-a54f-0f2478a88607
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589509809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c
_target_stress_rd.589509809
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.3858609459
Short name T257
Test name
Test status
Simulation time 65916243014 ps
CPU time 191.63 seconds
Started Jul 02 08:12:12 AM PDT 24
Finished Jul 02 08:15:27 AM PDT 24
Peak memory 2138904 kb
Host smart-9521c32e-a0c6-44a4-a2f6-b32b1a89e08b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858609459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.3858609459
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1582450972
Short name T325
Test name
Test status
Simulation time 2691020111 ps
CPU time 10.2 seconds
Started Jul 02 08:12:10 AM PDT 24
Finished Jul 02 08:12:23 AM PDT 24
Peak memory 276476 kb
Host smart-7e262765-f881-414e-b69f-40bab5c58b76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582450972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1582450972
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.2976890269
Short name T907
Test name
Test status
Simulation time 2113126140 ps
CPU time 6.61 seconds
Started Jul 02 08:12:14 AM PDT 24
Finished Jul 02 08:12:23 AM PDT 24
Peak memory 213228 kb
Host smart-ab1cee2c-8b06-4b93-802b-8dd883c844f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976890269 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.2976890269
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.1555437280
Short name T344
Test name
Test status
Simulation time 34934719 ps
CPU time 1.05 seconds
Started Jul 02 08:12:16 AM PDT 24
Finished Jul 02 08:12:19 AM PDT 24
Peak memory 204832 kb
Host smart-5c2af41c-fe53-4aa2-b202-b353fb28800c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555437280 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.1555437280
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.3870440931
Short name T1504
Test name
Test status
Simulation time 69671056 ps
CPU time 0.67 seconds
Started Jul 02 08:09:16 AM PDT 24
Finished Jul 02 08:09:18 AM PDT 24
Peak memory 204460 kb
Host smart-e09bff89-2dd5-4057-b294-623dc705cb9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870440931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.3870440931
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1594779854
Short name T1163
Test name
Test status
Simulation time 1097753666 ps
CPU time 2.82 seconds
Started Jul 02 08:09:12 AM PDT 24
Finished Jul 02 08:09:17 AM PDT 24
Peak memory 222436 kb
Host smart-35c67bae-7931-40d5-8bbc-b46c3e6fabaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594779854 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1594779854
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.1407984147
Short name T1360
Test name
Test status
Simulation time 330116584 ps
CPU time 16.76 seconds
Started Jul 02 08:09:08 AM PDT 24
Finished Jul 02 08:09:28 AM PDT 24
Peak memory 272332 kb
Host smart-9ece6372-f1ae-4bbe-b1ff-98661636f8b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407984147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.1407984147
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.1874836859
Short name T378
Test name
Test status
Simulation time 2014568950 ps
CPU time 146.24 seconds
Started Jul 02 08:09:08 AM PDT 24
Finished Jul 02 08:11:37 AM PDT 24
Peak memory 699840 kb
Host smart-9b8342dd-0353-4a36-9aab-931bfcfe4c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874836859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.1874836859
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.3059240272
Short name T916
Test name
Test status
Simulation time 7293956951 ps
CPU time 60.87 seconds
Started Jul 02 08:09:09 AM PDT 24
Finished Jul 02 08:10:13 AM PDT 24
Peak memory 644136 kb
Host smart-de03ebb8-5e10-4cbf-be45-9b5a2d4fb9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059240272 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.3059240272
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.1719323845
Short name T1204
Test name
Test status
Simulation time 231245650 ps
CPU time 1.05 seconds
Started Jul 02 08:09:08 AM PDT 24
Finished Jul 02 08:09:12 AM PDT 24
Peak memory 204424 kb
Host smart-fe5ddb99-0ca3-4bb1-87b5-5326fa193376
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719323845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.1719323845
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.641388936
Short name T872
Test name
Test status
Simulation time 553385959 ps
CPU time 8.53 seconds
Started Jul 02 08:09:09 AM PDT 24
Finished Jul 02 08:09:20 AM PDT 24
Peak memory 229224 kb
Host smart-538de6a2-1745-465d-a9e9-3e3fa76097cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641388936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.641388936
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.3676177810
Short name T1484
Test name
Test status
Simulation time 3348143123 ps
CPU time 73.09 seconds
Started Jul 02 08:09:06 AM PDT 24
Finished Jul 02 08:10:23 AM PDT 24
Peak memory 1003868 kb
Host smart-74470421-8cea-42e4-b1af-5e70e99c7897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676177810 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.3676177810
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.3085781769
Short name T1246
Test name
Test status
Simulation time 1743720135 ps
CPU time 17.16 seconds
Started Jul 02 08:09:13 AM PDT 24
Finished Jul 02 08:09:32 AM PDT 24
Peak memory 204680 kb
Host smart-1a44fe2e-85c4-43cf-ac29-6269102e8a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085781769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.3085781769
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.725377798
Short name T339
Test name
Test status
Simulation time 3049632572 ps
CPU time 68.95 seconds
Started Jul 02 08:09:14 AM PDT 24
Finished Jul 02 08:10:25 AM PDT 24
Peak memory 333652 kb
Host smart-0ad6ba7c-0346-449e-98d5-b795e2e6159f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725377798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.725377798
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.1047506628
Short name T479
Test name
Test status
Simulation time 44990415 ps
CPU time 0.67 seconds
Started Jul 02 08:09:09 AM PDT 24
Finished Jul 02 08:09:13 AM PDT 24
Peak memory 204488 kb
Host smart-9a6fc517-cb1f-4ffb-a8f0-59f3d753432a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047506628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1047506628
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf.848764939
Short name T1263
Test name
Test status
Simulation time 28438655303 ps
CPU time 188.43 seconds
Started Jul 02 08:09:11 AM PDT 24
Finished Jul 02 08:12:22 AM PDT 24
Peak memory 410900 kb
Host smart-999ea93d-1141-471a-8871-75ce9f4cabbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848764939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf.848764939
Directory /workspace/3.i2c_host_perf/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.3795700277
Short name T424
Test name
Test status
Simulation time 356498731 ps
CPU time 1.95 seconds
Started Jul 02 08:09:12 AM PDT 24
Finished Jul 02 08:09:16 AM PDT 24
Peak memory 213208 kb
Host smart-1687c629-aa63-474e-9b9b-6c45d919edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795700277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.3795700277
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.2138372676
Short name T616
Test name
Test status
Simulation time 2578467838 ps
CPU time 64.01 seconds
Started Jul 02 08:09:08 AM PDT 24
Finished Jul 02 08:10:15 AM PDT 24
Peak memory 404844 kb
Host smart-079b2b1b-200e-42bc-aa70-2803bcc7f8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138372676 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.2138372676
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.2775402603
Short name T44
Test name
Test status
Simulation time 3417998201 ps
CPU time 53.76 seconds
Started Jul 02 08:09:11 AM PDT 24
Finished Jul 02 08:10:07 AM PDT 24
Peak memory 495448 kb
Host smart-4933f46b-3e94-46ec-81a7-35356a4a8457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775402603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.2775402603
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.3094716450
Short name T276
Test name
Test status
Simulation time 2584196815 ps
CPU time 28.73 seconds
Started Jul 02 08:09:13 AM PDT 24
Finished Jul 02 08:09:44 AM PDT 24
Peak memory 213072 kb
Host smart-a19dfd88-4725-424f-a589-7d44d2eb89f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094716450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.3094716450
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.1885325278
Short name T179
Test name
Test status
Simulation time 122258892 ps
CPU time 0.96 seconds
Started Jul 02 08:09:13 AM PDT 24
Finished Jul 02 08:09:16 AM PDT 24
Peak memory 223188 kb
Host smart-19b52604-3aa3-4bee-896f-4d40cb19836d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885325278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.1885325278
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.777036704
Short name T1488
Test name
Test status
Simulation time 10069491435 ps
CPU time 4.97 seconds
Started Jul 02 08:09:12 AM PDT 24
Finished Jul 02 08:09:19 AM PDT 24
Peak memory 213288 kb
Host smart-6c522511-76ae-4f80-a8f3-89276a8ade87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777036704 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.777036704
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.246743078
Short name T1304
Test name
Test status
Simulation time 2043739262 ps
CPU time 1.22 seconds
Started Jul 02 08:09:14 AM PDT 24
Finished Jul 02 08:09:17 AM PDT 24
Peak memory 204520 kb
Host smart-3fed38df-f0fc-4eda-a470-5db939accda5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246743078 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_acq.246743078
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.3667333175
Short name T1236
Test name
Test status
Simulation time 378210393 ps
CPU time 1.43 seconds
Started Jul 02 08:09:13 AM PDT 24
Finished Jul 02 08:09:17 AM PDT 24
Peak memory 213020 kb
Host smart-376bb5fc-674f-4e93-8820-287fd4264d38
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667333175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.3667333175
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.117260916
Short name T745
Test name
Test status
Simulation time 1918490021 ps
CPU time 2.7 seconds
Started Jul 02 08:09:10 AM PDT 24
Finished Jul 02 08:09:16 AM PDT 24
Peak memory 204768 kb
Host smart-d49dade2-4f76-4c40-9672-4ab2e0d1fa8d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117260916 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.117260916
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.1146196110
Short name T29
Test name
Test status
Simulation time 142398329 ps
CPU time 1.25 seconds
Started Jul 02 08:09:11 AM PDT 24
Finished Jul 02 08:09:15 AM PDT 24
Peak memory 204564 kb
Host smart-1dc94dd4-54ad-4c8a-ae8b-885cc161d1c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146196110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.1146196110
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.4028644212
Short name T260
Test name
Test status
Simulation time 392578302 ps
CPU time 3.11 seconds
Started Jul 02 08:09:15 AM PDT 24
Finished Jul 02 08:09:20 AM PDT 24
Peak memory 204760 kb
Host smart-9b366f58-f94f-4a9d-a12f-755411936ffc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028644212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.4028644212
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.604775243
Short name T1109
Test name
Test status
Simulation time 4276730674 ps
CPU time 5.96 seconds
Started Jul 02 08:09:11 AM PDT 24
Finished Jul 02 08:09:20 AM PDT 24
Peak memory 216212 kb
Host smart-2fbca508-c75c-4ead-9f79-f7208df3e63e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604775243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_intr_smoke.604775243
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.433314589
Short name T327
Test name
Test status
Simulation time 20309372356 ps
CPU time 7.39 seconds
Started Jul 02 08:09:11 AM PDT 24
Finished Jul 02 08:09:21 AM PDT 24
Peak memory 305956 kb
Host smart-acb9aa4c-23c9-4a71-92c2-ad48cef96f78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433314589 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.433314589
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.2816903233
Short name T1440
Test name
Test status
Simulation time 2446607027 ps
CPU time 8.75 seconds
Started Jul 02 08:09:12 AM PDT 24
Finished Jul 02 08:09:23 AM PDT 24
Peak memory 204872 kb
Host smart-bbb35ee6-efa8-4927-abe9-951c7a72a9da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816903233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.2816903233
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.2390889519
Short name T307
Test name
Test status
Simulation time 2264663463 ps
CPU time 30.27 seconds
Started Jul 02 08:09:11 AM PDT 24
Finished Jul 02 08:09:43 AM PDT 24
Peak memory 224548 kb
Host smart-9708252f-1a32-4f0c-88fd-f75adb28b600
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390889519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_rd.2390889519
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.3244665098
Short name T209
Test name
Test status
Simulation time 59561659053 ps
CPU time 38.77 seconds
Started Jul 02 08:09:14 AM PDT 24
Finished Jul 02 08:09:54 AM PDT 24
Peak memory 702800 kb
Host smart-a58bdbe0-b54e-411e-9370-8ce7a4576320
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244665098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c
_target_stress_wr.3244665098
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.1988221731
Short name T599
Test name
Test status
Simulation time 22774001942 ps
CPU time 1314.64 seconds
Started Jul 02 08:09:15 AM PDT 24
Finished Jul 02 08:31:12 AM PDT 24
Peak memory 5491836 kb
Host smart-2ca456af-8d5a-4f34-ba67-42338d096ba9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988221731 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.1988221731
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.667671951
Short name T372
Test name
Test status
Simulation time 4851511106 ps
CPU time 7.14 seconds
Started Jul 02 08:09:12 AM PDT 24
Finished Jul 02 08:09:21 AM PDT 24
Peak memory 214096 kb
Host smart-4bf177ea-d289-4991-baa6-0f30cf13d722
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667671951 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_timeout.667671951
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.1578050198
Short name T1442
Test name
Test status
Simulation time 131348614 ps
CPU time 2.19 seconds
Started Jul 02 08:09:11 AM PDT 24
Finished Jul 02 08:09:16 AM PDT 24
Peak memory 204828 kb
Host smart-543b66c2-16b4-45f7-b9b4-bce28825e637
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578050198 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.1578050198
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.1469904569
Short name T121
Test name
Test status
Simulation time 46385025 ps
CPU time 0.64 seconds
Started Jul 02 08:12:25 AM PDT 24
Finished Jul 02 08:12:29 AM PDT 24
Peak memory 204424 kb
Host smart-ceb9e0a9-9a71-4f18-ab5a-0e2fcba5e336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469904569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.1469904569
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.971836085
Short name T1291
Test name
Test status
Simulation time 146714220 ps
CPU time 5.31 seconds
Started Jul 02 08:12:14 AM PDT 24
Finished Jul 02 08:12:22 AM PDT 24
Peak memory 213100 kb
Host smart-f8bf0c34-632e-47d5-9db5-36e6d4ca9fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971836085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.971836085
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.863362462
Short name T790
Test name
Test status
Simulation time 936775104 ps
CPU time 9.59 seconds
Started Jul 02 08:12:17 AM PDT 24
Finished Jul 02 08:12:29 AM PDT 24
Peak memory 277164 kb
Host smart-40c9713b-068d-4d19-afe3-bfd554500dd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863362462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_empt
y.863362462
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.4083759651
Short name T400
Test name
Test status
Simulation time 3239105890 ps
CPU time 32.13 seconds
Started Jul 02 08:12:14 AM PDT 24
Finished Jul 02 08:12:48 AM PDT 24
Peak memory 214844 kb
Host smart-f6379595-818b-448f-a214-c7a9fb759b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083759651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.4083759651
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.4196038633
Short name T390
Test name
Test status
Simulation time 4297213272 ps
CPU time 75.03 seconds
Started Jul 02 08:12:15 AM PDT 24
Finished Jul 02 08:13:32 AM PDT 24
Peak memory 732400 kb
Host smart-3482f868-44d1-469c-ad6c-cf66e4c0ac3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196038633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.4196038633
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.1271192252
Short name T1045
Test name
Test status
Simulation time 328229648 ps
CPU time 0.96 seconds
Started Jul 02 08:12:15 AM PDT 24
Finished Jul 02 08:12:18 AM PDT 24
Peak memory 204460 kb
Host smart-5adbd202-120e-4c55-b9b1-26b48214af4e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271192252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.1271192252
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.535760516
Short name T1056
Test name
Test status
Simulation time 563515219 ps
CPU time 8.72 seconds
Started Jul 02 08:12:13 AM PDT 24
Finished Jul 02 08:12:24 AM PDT 24
Peak memory 229348 kb
Host smart-e344ed95-e263-4567-878f-27011131bfbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535760516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx.
535760516
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.3067766237
Short name T1169
Test name
Test status
Simulation time 3122350666 ps
CPU time 59.42 seconds
Started Jul 02 08:12:15 AM PDT 24
Finished Jul 02 08:13:17 AM PDT 24
Peak memory 880668 kb
Host smart-6d80621b-4963-4e6f-8a70-dd2076fd59aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067766237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.3067766237
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.2386193426
Short name T917
Test name
Test status
Simulation time 233272639 ps
CPU time 3.58 seconds
Started Jul 02 08:12:18 AM PDT 24
Finished Jul 02 08:12:24 AM PDT 24
Peak memory 204784 kb
Host smart-a1b581c5-9e35-45c1-a645-679a77b12bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386193426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.2386193426
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_mode_toggle.874657111
Short name T57
Test name
Test status
Simulation time 5755978010 ps
CPU time 26.41 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:12:51 AM PDT 24
Peak memory 278276 kb
Host smart-b21b6260-13a0-42d8-b28d-28ca686d8609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874657111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_mode_toggle.874657111
Directory /workspace/30.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/30.i2c_host_override.1339765706
Short name T1313
Test name
Test status
Simulation time 26484517 ps
CPU time 0.68 seconds
Started Jul 02 08:12:14 AM PDT 24
Finished Jul 02 08:12:17 AM PDT 24
Peak memory 204496 kb
Host smart-e45fcc0c-147f-43e1-8170-248c2ab7a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339765706 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.1339765706
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2989671303
Short name T183
Test name
Test status
Simulation time 6379982595 ps
CPU time 93.96 seconds
Started Jul 02 08:12:14 AM PDT 24
Finished Jul 02 08:13:50 AM PDT 24
Peak memory 530840 kb
Host smart-f25f1f4a-c980-4d8d-a2b9-80511dcbae5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989671303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2989671303
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.1732666413
Short name T1097
Test name
Test status
Simulation time 55127438 ps
CPU time 1.17 seconds
Started Jul 02 08:12:16 AM PDT 24
Finished Jul 02 08:12:20 AM PDT 24
Peak memory 224820 kb
Host smart-ece748f1-f88b-4b70-a702-81a64c2b7192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732666413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.1732666413
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.2771977037
Short name T345
Test name
Test status
Simulation time 2947746505 ps
CPU time 23.01 seconds
Started Jul 02 08:12:16 AM PDT 24
Finished Jul 02 08:12:42 AM PDT 24
Peak memory 349772 kb
Host smart-b8a023f8-76ab-4b2e-9cf9-46fcccc3eb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771977037 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.2771977037
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.2054190802
Short name T285
Test name
Test status
Simulation time 50800684948 ps
CPU time 1414.17 seconds
Started Jul 02 08:12:14 AM PDT 24
Finished Jul 02 08:35:51 AM PDT 24
Peak memory 2194176 kb
Host smart-7c3d08c7-bca2-42c8-a19f-be9049a5433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054190802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.2054190802
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.4055776593
Short name T1010
Test name
Test status
Simulation time 617904240 ps
CPU time 27.76 seconds
Started Jul 02 08:12:16 AM PDT 24
Finished Jul 02 08:12:46 AM PDT 24
Peak memory 212948 kb
Host smart-f4196d43-c77d-4328-b19f-1d7d3604ed93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055776593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.4055776593
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.1834486466
Short name T568
Test name
Test status
Simulation time 797551750 ps
CPU time 3.71 seconds
Started Jul 02 08:12:20 AM PDT 24
Finished Jul 02 08:12:26 AM PDT 24
Peak memory 212992 kb
Host smart-cde79187-a851-4a01-a3f9-f911569cf8be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834486466 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.1834486466
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.4263852966
Short name T1068
Test name
Test status
Simulation time 137876955 ps
CPU time 0.98 seconds
Started Jul 02 08:12:18 AM PDT 24
Finished Jul 02 08:12:21 AM PDT 24
Peak memory 204580 kb
Host smart-219fb90a-af96-45c5-b540-1dc01e44d7f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263852966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.4263852966
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2953690715
Short name T555
Test name
Test status
Simulation time 384534296 ps
CPU time 0.96 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:12:27 AM PDT 24
Peak memory 212768 kb
Host smart-7202e95e-02c6-4eec-be28-d5ee0c62bd05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953690715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2953690715
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.420629250
Short name T651
Test name
Test status
Simulation time 2029311087 ps
CPU time 2.68 seconds
Started Jul 02 08:12:17 AM PDT 24
Finished Jul 02 08:12:22 AM PDT 24
Peak memory 204800 kb
Host smart-5cce5241-0b59-4e4c-a680-16a01d97c21f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420629250 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.420629250
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.1026408191
Short name T1457
Test name
Test status
Simulation time 63226849 ps
CPU time 0.81 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:12:27 AM PDT 24
Peak memory 204568 kb
Host smart-a4831f18-36d3-4cd1-a9fe-a0f76ad00954
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026408191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.1026408191
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.3183140526
Short name T736
Test name
Test status
Simulation time 954940312 ps
CPU time 3.65 seconds
Started Jul 02 08:12:20 AM PDT 24
Finished Jul 02 08:12:26 AM PDT 24
Peak memory 204768 kb
Host smart-639223bf-3022-4ee4-b02b-38f8f702dc73
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183140526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.3183140526
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.2278955243
Short name T16
Test name
Test status
Simulation time 3389880142 ps
CPU time 5.35 seconds
Started Jul 02 08:12:19 AM PDT 24
Finished Jul 02 08:12:27 AM PDT 24
Peak memory 210260 kb
Host smart-77545bb6-b09f-4f42-a249-a911f8bbb3ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278955243 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.2278955243
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1864555122
Short name T487
Test name
Test status
Simulation time 3182325924 ps
CPU time 26.85 seconds
Started Jul 02 08:12:20 AM PDT 24
Finished Jul 02 08:12:49 AM PDT 24
Peak memory 922104 kb
Host smart-de2525ad-ea42-48ea-85b1-62f37c7bbac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864555122 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1864555122
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.942136047
Short name T161
Test name
Test status
Simulation time 1884211679 ps
CPU time 15.33 seconds
Started Jul 02 08:12:16 AM PDT 24
Finished Jul 02 08:12:34 AM PDT 24
Peak memory 204796 kb
Host smart-1e2bc8ed-5b14-4bce-9d2b-e51d60ad2551
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942136047 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_tar
get_smoke.942136047
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.3266725249
Short name T711
Test name
Test status
Simulation time 3128213552 ps
CPU time 14.32 seconds
Started Jul 02 08:12:13 AM PDT 24
Finished Jul 02 08:12:30 AM PDT 24
Peak memory 220044 kb
Host smart-93b8ede8-9f2c-4be3-9b17-0a6ae0cf5ae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266725249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_rd.3266725249
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.4138837041
Short name T570
Test name
Test status
Simulation time 61352766847 ps
CPU time 2023.36 seconds
Started Jul 02 08:12:15 AM PDT 24
Finished Jul 02 08:46:01 AM PDT 24
Peak memory 9913868 kb
Host smart-11e1ade3-8958-4b19-b853-47b913cf523c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138837041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.4138837041
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2841139602
Short name T1330
Test name
Test status
Simulation time 14916515799 ps
CPU time 726.14 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:24:31 AM PDT 24
Peak memory 3703556 kb
Host smart-14c39418-b756-4d75-82f0-619296c137e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841139602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2841139602
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2809649113
Short name T1030
Test name
Test status
Simulation time 2081396508 ps
CPU time 7.09 seconds
Started Jul 02 08:12:19 AM PDT 24
Finished Jul 02 08:12:28 AM PDT 24
Peak memory 213144 kb
Host smart-ef1c37c3-6821-478f-b3f0-f26a2c74a53b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809649113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2809649113
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.2592183078
Short name T699
Test name
Test status
Simulation time 510657882 ps
CPU time 6.79 seconds
Started Jul 02 08:12:19 AM PDT 24
Finished Jul 02 08:12:28 AM PDT 24
Peak memory 204748 kb
Host smart-66989e93-788d-4a66-bd97-e52e716bbdad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592183078 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.2592183078
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.1950633745
Short name T724
Test name
Test status
Simulation time 16371417 ps
CPU time 0.62 seconds
Started Jul 02 08:12:23 AM PDT 24
Finished Jul 02 08:12:26 AM PDT 24
Peak memory 204440 kb
Host smart-7092c142-6309-41e2-b38b-9e7a72d548da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950633745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.1950633745
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.958010832
Short name T1096
Test name
Test status
Simulation time 2306911322 ps
CPU time 6.12 seconds
Started Jul 02 08:12:19 AM PDT 24
Finished Jul 02 08:12:27 AM PDT 24
Peak memory 250320 kb
Host smart-26e6ee38-7b93-4c6c-852f-a3a4aba5c95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958010832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.958010832
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.2790813798
Short name T1485
Test name
Test status
Simulation time 902126473 ps
CPU time 5.01 seconds
Started Jul 02 08:12:18 AM PDT 24
Finished Jul 02 08:12:25 AM PDT 24
Peak memory 250040 kb
Host smart-95e71aa3-24bc-45e1-996f-f0b75601e742
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790813798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_emp
ty.2790813798
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.2334326487
Short name T1297
Test name
Test status
Simulation time 4253753238 ps
CPU time 66.38 seconds
Started Jul 02 08:12:21 AM PDT 24
Finished Jul 02 08:13:30 AM PDT 24
Peak memory 684784 kb
Host smart-c2685861-e648-4abd-9a0c-0773d26bf61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334326487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.2334326487
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.2576987210
Short name T1434
Test name
Test status
Simulation time 9202084666 ps
CPU time 49.96 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:13:14 AM PDT 24
Peak memory 664044 kb
Host smart-59adecf7-3abe-4f16-94fb-2699bde676fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576987210 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.2576987210
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2709277002
Short name T1492
Test name
Test status
Simulation time 152074829 ps
CPU time 1.06 seconds
Started Jul 02 08:12:25 AM PDT 24
Finished Jul 02 08:12:29 AM PDT 24
Peak memory 204480 kb
Host smart-a9b8bd75-0211-483a-8bb0-5c1f9192adee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709277002 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2709277002
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.4166419287
Short name T478
Test name
Test status
Simulation time 519092246 ps
CPU time 5.73 seconds
Started Jul 02 08:12:17 AM PDT 24
Finished Jul 02 08:12:25 AM PDT 24
Peak memory 204784 kb
Host smart-2ba73f36-0f6f-477a-b059-23f5c8b6b492
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166419287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.4166419287
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.1069977656
Short name T112
Test name
Test status
Simulation time 14157620419 ps
CPU time 128.89 seconds
Started Jul 02 08:12:21 AM PDT 24
Finished Jul 02 08:14:33 AM PDT 24
Peak memory 1228708 kb
Host smart-66634163-0efa-4b5e-b51a-3b8ee7c4cfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069977656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.1069977656
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.420733586
Short name T317
Test name
Test status
Simulation time 1225417540 ps
CPU time 12.73 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:12:37 AM PDT 24
Peak memory 204804 kb
Host smart-c1df5a5c-87b4-4abb-8175-9c0f7b9e88d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420733586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.420733586
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.3029390531
Short name T1397
Test name
Test status
Simulation time 7700090204 ps
CPU time 36.17 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:13:01 AM PDT 24
Peak memory 370300 kb
Host smart-35db7dc5-28bc-4fd3-a352-90b072af1dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029390531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.3029390531
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1279168664
Short name T3
Test name
Test status
Simulation time 46744981 ps
CPU time 0.67 seconds
Started Jul 02 08:12:19 AM PDT 24
Finished Jul 02 08:12:22 AM PDT 24
Peak memory 204728 kb
Host smart-456fdd8e-3bbd-41eb-8c81-85ed948c1414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279168664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1279168664
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1037479871
Short name T1065
Test name
Test status
Simulation time 17525644836 ps
CPU time 1559.05 seconds
Started Jul 02 08:12:25 AM PDT 24
Finished Jul 02 08:38:27 AM PDT 24
Peak memory 1547028 kb
Host smart-3f6e1b16-602d-4c5a-b815-06a8d80993de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037479871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1037479871
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.1520593885
Short name T60
Test name
Test status
Simulation time 731125427 ps
CPU time 7.42 seconds
Started Jul 02 08:12:19 AM PDT 24
Finished Jul 02 08:12:28 AM PDT 24
Peak memory 212940 kb
Host smart-3db46fd7-1790-4331-b0be-fdc73ac36b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520593885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.1520593885
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.3924922728
Short name T1320
Test name
Test status
Simulation time 2698917438 ps
CPU time 74.84 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:13:42 AM PDT 24
Peak memory 342972 kb
Host smart-13815023-85ac-4055-a12a-68dd34300c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924922728 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.3924922728
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.1574076857
Short name T117
Test name
Test status
Simulation time 57367183608 ps
CPU time 525.22 seconds
Started Jul 02 08:12:17 AM PDT 24
Finished Jul 02 08:21:05 AM PDT 24
Peak memory 1583916 kb
Host smart-2e773df2-29be-4381-8ea0-095cb0d9be49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574076857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1574076857
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.3259407758
Short name T1107
Test name
Test status
Simulation time 749641554 ps
CPU time 10.67 seconds
Started Jul 02 08:12:19 AM PDT 24
Finished Jul 02 08:12:32 AM PDT 24
Peak memory 221192 kb
Host smart-10a8a81b-eda7-438a-b059-a1a377e217d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259407758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.3259407758
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.411120915
Short name T1215
Test name
Test status
Simulation time 10185378941 ps
CPU time 3.4 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:12:28 AM PDT 24
Peak memory 204928 kb
Host smart-71753788-db83-4a34-a6c3-a1eb1604dcc6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411120915 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.411120915
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.3322082943
Short name T765
Test name
Test status
Simulation time 181463538 ps
CPU time 1.15 seconds
Started Jul 02 08:12:26 AM PDT 24
Finished Jul 02 08:12:30 AM PDT 24
Peak memory 204772 kb
Host smart-a2ad676f-4f97-48bd-9f5c-c7933cae6f57
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322082943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.3322082943
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3880972031
Short name T288
Test name
Test status
Simulation time 164449719 ps
CPU time 1.03 seconds
Started Jul 02 08:12:28 AM PDT 24
Finished Jul 02 08:12:32 AM PDT 24
Peak memory 204436 kb
Host smart-3c4e280e-b22f-4795-b736-6f0bcb938187
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880972031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3880972031
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.344286911
Short name T1158
Test name
Test status
Simulation time 4265217512 ps
CPU time 3.03 seconds
Started Jul 02 08:12:25 AM PDT 24
Finished Jul 02 08:12:32 AM PDT 24
Peak memory 204632 kb
Host smart-cce16b9d-7dde-4ba7-9cde-b4fd4f1c51b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344286911 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.344286911
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.2421055081
Short name T741
Test name
Test status
Simulation time 408830214 ps
CPU time 1.29 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:12:26 AM PDT 24
Peak memory 204508 kb
Host smart-b0d03287-4c8b-45ff-81e4-af3e7e196a3a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421055081 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.2421055081
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_hrst.133225842
Short name T580
Test name
Test status
Simulation time 314703320 ps
CPU time 2.94 seconds
Started Jul 02 08:12:26 AM PDT 24
Finished Jul 02 08:12:32 AM PDT 24
Peak memory 204812 kb
Host smart-bb7cd528-7842-40b1-8b89-0678bbfaa08a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133225842 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.i2c_target_hrst.133225842
Directory /workspace/31.i2c_target_hrst/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.1303330115
Short name T956
Test name
Test status
Simulation time 962759430 ps
CPU time 5.72 seconds
Started Jul 02 08:12:23 AM PDT 24
Finished Jul 02 08:12:31 AM PDT 24
Peak memory 213016 kb
Host smart-65336750-5f30-4b3b-a565-738cfbee7670
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303330115 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.1303330115
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.3134931984
Short name T1057
Test name
Test status
Simulation time 10541404183 ps
CPU time 6.08 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:12:31 AM PDT 24
Peak memory 204972 kb
Host smart-661ccf8d-71e0-43be-8024-92237b97cb70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134931984 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.3134931984
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2365235003
Short name T86
Test name
Test status
Simulation time 1767278908 ps
CPU time 31.83 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:12:59 AM PDT 24
Peak memory 204832 kb
Host smart-4b59fea4-1efd-4719-9705-13f1ad8a9ac5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365235003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2365235003
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.3392814294
Short name T302
Test name
Test status
Simulation time 4329206944 ps
CPU time 16.95 seconds
Started Jul 02 08:12:25 AM PDT 24
Finished Jul 02 08:12:45 AM PDT 24
Peak memory 223296 kb
Host smart-7ae9408e-9bfb-48cd-8f1b-85fb99857949
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392814294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.3392814294
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.19980497
Short name T536
Test name
Test status
Simulation time 56979474858 ps
CPU time 187.21 seconds
Started Jul 02 08:12:18 AM PDT 24
Finished Jul 02 08:15:27 AM PDT 24
Peak memory 2224196 kb
Host smart-42036fb2-a041-4729-aac6-505ab8d2776b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19980497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stress_wr.19980497
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.3417355575
Short name T388
Test name
Test status
Simulation time 33132411540 ps
CPU time 1784.94 seconds
Started Jul 02 08:12:20 AM PDT 24
Finished Jul 02 08:42:08 AM PDT 24
Peak memory 6223972 kb
Host smart-9fddf958-ec50-4b16-94b5-2a9002cd989b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417355575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.3417355575
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.2246627272
Short name T673
Test name
Test status
Simulation time 4283102547 ps
CPU time 6.18 seconds
Started Jul 02 08:12:25 AM PDT 24
Finished Jul 02 08:12:34 AM PDT 24
Peak memory 213536 kb
Host smart-2467b2a6-7205-419b-b7ef-5b6510291659
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246627272 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.2246627272
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.1250771887
Short name T1374
Test name
Test status
Simulation time 130184400 ps
CPU time 2.69 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:12:28 AM PDT 24
Peak memory 204812 kb
Host smart-0427583a-5857-415d-8df8-637ec01ad2f4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250771887 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.1250771887
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.943674163
Short name T380
Test name
Test status
Simulation time 121148428 ps
CPU time 2.86 seconds
Started Jul 02 08:12:25 AM PDT 24
Finished Jul 02 08:12:31 AM PDT 24
Peak memory 213060 kb
Host smart-f1fd2149-df55-4941-9e79-0aa845ee1da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943674163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.943674163
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.189169540
Short name T523
Test name
Test status
Simulation time 599008062 ps
CPU time 31.24 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:12:59 AM PDT 24
Peak memory 334124 kb
Host smart-e034f31a-b0d0-4dcc-96c8-3c6e4f7c8836
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189169540 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_empt
y.189169540
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2232584443
Short name T148
Test name
Test status
Simulation time 4867598354 ps
CPU time 64.97 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:13:31 AM PDT 24
Peak memory 654212 kb
Host smart-ef2c4554-a9f2-4b14-a2d9-3441c2e3d5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232584443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2232584443
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.372453469
Short name T5
Test name
Test status
Simulation time 9080750903 ps
CPU time 112.99 seconds
Started Jul 02 08:12:23 AM PDT 24
Finished Jul 02 08:14:19 AM PDT 24
Peak memory 613544 kb
Host smart-3b0d519a-d1c7-4171-b676-19110d589d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372453469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.372453469
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.3510391040
Short name T365
Test name
Test status
Simulation time 370325712 ps
CPU time 5.21 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 204772 kb
Host smart-d616282e-2d13-438b-83c2-327e2e7aac23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510391040 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.3510391040
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.80570236
Short name T739
Test name
Test status
Simulation time 5306482580 ps
CPU time 155.57 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:15:00 AM PDT 24
Peak memory 1404940 kb
Host smart-912c291d-3270-4618-ac92-e76b1abae18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80570236 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.80570236
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.273247349
Short name T1495
Test name
Test status
Simulation time 2200334265 ps
CPU time 22.12 seconds
Started Jul 02 08:12:29 AM PDT 24
Finished Jul 02 08:12:54 AM PDT 24
Peak memory 204844 kb
Host smart-2a897126-6764-4685-b32a-d1b9eefaf16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273247349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.273247349
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.3872387153
Short name T720
Test name
Test status
Simulation time 3347089093 ps
CPU time 77.77 seconds
Started Jul 02 08:12:28 AM PDT 24
Finished Jul 02 08:13:48 AM PDT 24
Peak memory 328192 kb
Host smart-71d894bb-d2d5-454d-85e1-034e7907444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872387153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.3872387153
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.2557644958
Short name T322
Test name
Test status
Simulation time 102477788 ps
CPU time 0.67 seconds
Started Jul 02 08:12:27 AM PDT 24
Finished Jul 02 08:12:31 AM PDT 24
Peak memory 204536 kb
Host smart-a0a5d52e-6967-4cb7-af91-6d9ff806d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557644958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.2557644958
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.475836133
Short name T1275
Test name
Test status
Simulation time 49529860696 ps
CPU time 480.79 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:20:26 AM PDT 24
Peak memory 570832 kb
Host smart-5fc2a719-5976-44d6-b3b2-0fdb84a5fc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475836133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.475836133
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.172161017
Short name T1082
Test name
Test status
Simulation time 246161524 ps
CPU time 9.96 seconds
Started Jul 02 08:12:26 AM PDT 24
Finished Jul 02 08:12:39 AM PDT 24
Peak memory 222600 kb
Host smart-bc4dd4ea-9ad9-41df-85d7-bfe2da65635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172161017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.172161017
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.682206986
Short name T1324
Test name
Test status
Simulation time 1468202395 ps
CPU time 64.58 seconds
Started Jul 02 08:12:28 AM PDT 24
Finished Jul 02 08:13:35 AM PDT 24
Peak memory 304416 kb
Host smart-d4ae7e30-536c-440b-b45c-ea944e7479b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682206986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.682206986
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1949098801
Short name T1402
Test name
Test status
Simulation time 28307881341 ps
CPU time 616.29 seconds
Started Jul 02 08:12:22 AM PDT 24
Finished Jul 02 08:22:41 AM PDT 24
Peak memory 2119492 kb
Host smart-e37b37bb-8dd5-4d51-9857-659e16ec8246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949098801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1949098801
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.1476659070
Short name T1220
Test name
Test status
Simulation time 3529553151 ps
CPU time 11.54 seconds
Started Jul 02 08:12:24 AM PDT 24
Finished Jul 02 08:12:39 AM PDT 24
Peak memory 212988 kb
Host smart-c84e71da-dc42-4036-8add-5e24b0ce6379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476659070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.1476659070
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.1185446359
Short name T841
Test name
Test status
Simulation time 456166632 ps
CPU time 2.78 seconds
Started Jul 02 08:12:28 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 204840 kb
Host smart-394b57a4-96b1-40b0-a615-a53b078d6524
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185446359 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.1185446359
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.269033264
Short name T887
Test name
Test status
Simulation time 327788860 ps
CPU time 1.36 seconds
Started Jul 02 08:12:29 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 204784 kb
Host smart-778707b9-7546-4de8-b3ea-df1b24aa36c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269033264 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_acq.269033264
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.2804328863
Short name T169
Test name
Test status
Simulation time 605578525 ps
CPU time 1.01 seconds
Started Jul 02 08:12:27 AM PDT 24
Finished Jul 02 08:12:31 AM PDT 24
Peak memory 204592 kb
Host smart-907de6f1-8ff2-438e-8836-0a0aa224c411
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804328863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.i2c_target_fifo_reset_tx.2804328863
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.974880317
Short name T691
Test name
Test status
Simulation time 1865696232 ps
CPU time 3.05 seconds
Started Jul 02 08:12:28 AM PDT 24
Finished Jul 02 08:12:34 AM PDT 24
Peak memory 204768 kb
Host smart-5c84c961-4a70-4dd5-ac34-be182fd23b61
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974880317 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.974880317
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.4126268699
Short name T294
Test name
Test status
Simulation time 557519553 ps
CPU time 1.25 seconds
Started Jul 02 08:12:29 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 204596 kb
Host smart-0110666c-a256-4b95-9ab0-c5eeb36fbb0d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126268699 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.4126268699
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.766705937
Short name T1125
Test name
Test status
Simulation time 4555514513 ps
CPU time 3.08 seconds
Started Jul 02 08:12:28 AM PDT 24
Finished Jul 02 08:12:33 AM PDT 24
Peak memory 204888 kb
Host smart-5811c5c1-3f68-4df4-bab4-ecb71c4eee87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766705937 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.766705937
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.1659481407
Short name T286
Test name
Test status
Simulation time 1855418413 ps
CPU time 5.4 seconds
Started Jul 02 08:12:31 AM PDT 24
Finished Jul 02 08:12:38 AM PDT 24
Peak memory 206920 kb
Host smart-ae2be3e8-38c1-4d9f-b836-c4e2624e9a5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659481407 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.1659481407
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.1125425459
Short name T1051
Test name
Test status
Simulation time 24025926303 ps
CPU time 51.75 seconds
Started Jul 02 08:12:29 AM PDT 24
Finished Jul 02 08:13:23 AM PDT 24
Peak memory 768628 kb
Host smart-273fc857-a02f-4f01-b1a5-4c059f3c39a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125425459 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.1125425459
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.47102059
Short name T85
Test name
Test status
Simulation time 671913697 ps
CPU time 23.75 seconds
Started Jul 02 08:12:27 AM PDT 24
Finished Jul 02 08:12:53 AM PDT 24
Peak memory 204792 kb
Host smart-05d28d28-e06d-4e90-b2f8-5fa0a76bef0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47102059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_targ
et_smoke.47102059
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3100003451
Short name T125
Test name
Test status
Simulation time 1232122757 ps
CPU time 22.32 seconds
Started Jul 02 08:12:25 AM PDT 24
Finished Jul 02 08:12:51 AM PDT 24
Peak memory 220764 kb
Host smart-89b39ea6-e93c-4c40-9b3c-6f161c8b69d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100003451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3100003451
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.2328743447
Short name T1150
Test name
Test status
Simulation time 44125146052 ps
CPU time 734.78 seconds
Started Jul 02 08:12:26 AM PDT 24
Finished Jul 02 08:24:44 AM PDT 24
Peak memory 6003508 kb
Host smart-1cc29efb-5110-40bb-a6ea-e57b82ccbd0f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328743447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.2328743447
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.3501341967
Short name T352
Test name
Test status
Simulation time 21337446798 ps
CPU time 8.5 seconds
Started Jul 02 08:12:29 AM PDT 24
Finished Jul 02 08:12:40 AM PDT 24
Peak memory 221236 kb
Host smart-d7ee3000-5cfa-43fb-b206-3eae40de69d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501341967 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.i2c_target_timeout.3501341967
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.2349818820
Short name T665
Test name
Test status
Simulation time 201576689 ps
CPU time 3.33 seconds
Started Jul 02 08:12:29 AM PDT 24
Finished Jul 02 08:12:35 AM PDT 24
Peak memory 204836 kb
Host smart-06fa1487-3de1-4aac-af9f-3d8064b3dd11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349818820 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.2349818820
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.3307608224
Short name T170
Test name
Test status
Simulation time 18699994 ps
CPU time 0.64 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:12:42 AM PDT 24
Peak memory 204444 kb
Host smart-8f6a5806-caf6-4f16-a0c4-c7bc5c559c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307608224 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.3307608224
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.3381945338
Short name T420
Test name
Test status
Simulation time 313006911 ps
CPU time 2.5 seconds
Started Jul 02 08:12:32 AM PDT 24
Finished Jul 02 08:12:36 AM PDT 24
Peak memory 213112 kb
Host smart-004ae5f0-6131-41c1-8df3-be16fe8e77a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381945338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.3381945338
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.4208389554
Short name T912
Test name
Test status
Simulation time 1772476500 ps
CPU time 10.06 seconds
Started Jul 02 08:12:32 AM PDT 24
Finished Jul 02 08:12:44 AM PDT 24
Peak memory 300072 kb
Host smart-542aab68-56d8-468b-874e-0b35df181b9e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208389554 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.4208389554
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.2729145870
Short name T783
Test name
Test status
Simulation time 9203405367 ps
CPU time 76.88 seconds
Started Jul 02 08:12:34 AM PDT 24
Finished Jul 02 08:13:52 AM PDT 24
Peak memory 779276 kb
Host smart-ec6bfe19-20b2-4157-b6a0-8fc27db6a5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729145870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.2729145870
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.1027874295
Short name T1475
Test name
Test status
Simulation time 2021248641 ps
CPU time 68.57 seconds
Started Jul 02 08:12:33 AM PDT 24
Finished Jul 02 08:13:43 AM PDT 24
Peak memory 698676 kb
Host smart-56d498d2-8323-4a61-8a9d-152ab4cd1050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027874295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.1027874295
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1225377853
Short name T1487
Test name
Test status
Simulation time 105191865 ps
CPU time 0.91 seconds
Started Jul 02 08:12:33 AM PDT 24
Finished Jul 02 08:12:35 AM PDT 24
Peak memory 204480 kb
Host smart-2a9a7f09-5e88-40f4-88f9-ca6b3e43f19d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225377853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1225377853
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.529574659
Short name T109
Test name
Test status
Simulation time 881806828 ps
CPU time 4.89 seconds
Started Jul 02 08:12:34 AM PDT 24
Finished Jul 02 08:12:40 AM PDT 24
Peak memory 243828 kb
Host smart-66adbf5a-251d-4513-8a13-14f1dcf027cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529574659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx.
529574659
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.990522082
Short name T943
Test name
Test status
Simulation time 5037924680 ps
CPU time 210.28 seconds
Started Jul 02 08:12:31 AM PDT 24
Finished Jul 02 08:16:04 AM PDT 24
Peak memory 999168 kb
Host smart-384b8893-ec56-40b6-9498-58fa9f9569b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990522082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.990522082
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.1203877397
Short name T1419
Test name
Test status
Simulation time 2003651998 ps
CPU time 20.13 seconds
Started Jul 02 08:12:31 AM PDT 24
Finished Jul 02 08:12:53 AM PDT 24
Peak memory 204824 kb
Host smart-88c4f575-b18a-4e06-8f4b-d8bfe8f4b582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203877397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.1203877397
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.1118926212
Short name T262
Test name
Test status
Simulation time 4114858826 ps
CPU time 37.45 seconds
Started Jul 02 08:12:41 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 369576 kb
Host smart-3f323350-8688-4c44-8dbf-c5fd6198bb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118926212 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.1118926212
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.1481749112
Short name T1309
Test name
Test status
Simulation time 25507473 ps
CPU time 0.71 seconds
Started Jul 02 08:12:29 AM PDT 24
Finished Jul 02 08:12:32 AM PDT 24
Peak memory 204480 kb
Host smart-d7db8d0e-eb41-4732-bc39-4d6bf0f1797e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481749112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.1481749112
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.2829357320
Short name T1494
Test name
Test status
Simulation time 147414060 ps
CPU time 1.21 seconds
Started Jul 02 08:12:35 AM PDT 24
Finished Jul 02 08:12:37 AM PDT 24
Peak memory 212868 kb
Host smart-7765e53a-5a96-400b-b167-d7c76099885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829357320 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.2829357320
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2983684404
Short name T1405
Test name
Test status
Simulation time 3155053078 ps
CPU time 96.4 seconds
Started Jul 02 08:12:30 AM PDT 24
Finished Jul 02 08:14:09 AM PDT 24
Peak memory 295456 kb
Host smart-5b41db78-3609-406e-875f-08611b0c87d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983684404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2983684404
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.724440263
Short name T1435
Test name
Test status
Simulation time 9428260070 ps
CPU time 234.25 seconds
Started Jul 02 08:12:33 AM PDT 24
Finished Jul 02 08:16:28 AM PDT 24
Peak memory 1230724 kb
Host smart-3ad5e2ab-1a6b-4e47-834b-a04452dc57e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724440263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.724440263
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.2649395402
Short name T415
Test name
Test status
Simulation time 3724759594 ps
CPU time 14.06 seconds
Started Jul 02 08:12:33 AM PDT 24
Finished Jul 02 08:12:48 AM PDT 24
Peak memory 221056 kb
Host smart-5914d396-4409-4535-9250-4413915a1be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649395402 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.2649395402
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.4155058484
Short name T23
Test name
Test status
Simulation time 2178625084 ps
CPU time 3.34 seconds
Started Jul 02 08:12:32 AM PDT 24
Finished Jul 02 08:12:37 AM PDT 24
Peak memory 204888 kb
Host smart-4491342a-820b-44d7-97d8-1f51599e8d2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155058484 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.4155058484
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3398228692
Short name T1172
Test name
Test status
Simulation time 216988381 ps
CPU time 1.1 seconds
Started Jul 02 08:12:34 AM PDT 24
Finished Jul 02 08:12:36 AM PDT 24
Peak memory 204608 kb
Host smart-a5af92e0-b1f2-4494-854e-855cb8073d22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398228692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3398228692
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.1821508187
Short name T756
Test name
Test status
Simulation time 196267711 ps
CPU time 1.19 seconds
Started Jul 02 08:12:35 AM PDT 24
Finished Jul 02 08:12:37 AM PDT 24
Peak memory 204552 kb
Host smart-cad93763-33d0-408a-b841-f11b6b76b833
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821508187 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.1821508187
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.1949713513
Short name T886
Test name
Test status
Simulation time 568375402 ps
CPU time 2.89 seconds
Started Jul 02 08:12:39 AM PDT 24
Finished Jul 02 08:12:43 AM PDT 24
Peak memory 204804 kb
Host smart-1b3c2cdc-3d5b-4925-a049-591bddcd1143
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949713513 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.1949713513
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.1156197633
Short name T1539
Test name
Test status
Simulation time 399511199 ps
CPU time 1.09 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:12:42 AM PDT 24
Peak memory 204592 kb
Host smart-f937f990-7d20-49dc-8738-8812e3a50dab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156197633 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.1156197633
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.1115627841
Short name T1062
Test name
Test status
Simulation time 1115920521 ps
CPU time 2.26 seconds
Started Jul 02 08:12:41 AM PDT 24
Finished Jul 02 08:12:45 AM PDT 24
Peak memory 204796 kb
Host smart-ad2342f5-1f26-4188-94b4-d0dcb51920fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115627841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.1115627841
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.889771922
Short name T567
Test name
Test status
Simulation time 3645686088 ps
CPU time 4.83 seconds
Started Jul 02 08:12:35 AM PDT 24
Finished Jul 02 08:12:41 AM PDT 24
Peak memory 213044 kb
Host smart-79e8aab8-3ac3-4c91-b0a5-6d3f0de8d193
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889771922 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.889771922
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.2690952890
Short name T1533
Test name
Test status
Simulation time 19560919605 ps
CPU time 149.2 seconds
Started Jul 02 08:12:37 AM PDT 24
Finished Jul 02 08:15:07 AM PDT 24
Peak memory 2682132 kb
Host smart-5121d6d9-8af1-4f86-b3ec-fa30771e137b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690952890 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.2690952890
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.2824563843
Short name T671
Test name
Test status
Simulation time 1590477679 ps
CPU time 18.92 seconds
Started Jul 02 08:12:36 AM PDT 24
Finished Jul 02 08:12:55 AM PDT 24
Peak memory 204772 kb
Host smart-b8745001-6048-4d02-aaad-8f7400fdee9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824563843 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.2824563843
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.3224818921
Short name T1436
Test name
Test status
Simulation time 15955433159 ps
CPU time 23.89 seconds
Started Jul 02 08:12:33 AM PDT 24
Finished Jul 02 08:12:58 AM PDT 24
Peak memory 223116 kb
Host smart-e75c532e-acce-4ddd-97d3-9904a6466169
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224818921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.3224818921
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.341774263
Short name T980
Test name
Test status
Simulation time 67087778481 ps
CPU time 61.53 seconds
Started Jul 02 08:12:32 AM PDT 24
Finished Jul 02 08:13:36 AM PDT 24
Peak memory 957836 kb
Host smart-d827c0a8-f0cb-4271-8b96-ddeb92fdc529
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341774263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c
_target_stress_wr.341774263
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.3755271709
Short name T576
Test name
Test status
Simulation time 36802452461 ps
CPU time 2795.53 seconds
Started Jul 02 08:12:38 AM PDT 24
Finished Jul 02 08:59:14 AM PDT 24
Peak memory 9069532 kb
Host smart-b89660a7-cd3b-4508-a167-498e59538408
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755271709 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.3755271709
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.4124723167
Short name T1148
Test name
Test status
Simulation time 5117524924 ps
CPU time 6.77 seconds
Started Jul 02 08:12:37 AM PDT 24
Finished Jul 02 08:12:44 AM PDT 24
Peak memory 221012 kb
Host smart-36a16e7f-df42-4d18-a950-623e8ea9c8b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124723167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.4124723167
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.2281199105
Short name T472
Test name
Test status
Simulation time 227531621 ps
CPU time 3.32 seconds
Started Jul 02 08:12:41 AM PDT 24
Finished Jul 02 08:12:46 AM PDT 24
Peak memory 204776 kb
Host smart-47b41f68-dcb6-433b-851e-698482c43f07
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281199105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.2281199105
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2669815510
Short name T1474
Test name
Test status
Simulation time 28345094 ps
CPU time 0.6 seconds
Started Jul 02 08:12:49 AM PDT 24
Finished Jul 02 08:12:51 AM PDT 24
Peak memory 204404 kb
Host smart-0d8a69f7-8adb-444e-ac76-4f862defda61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669815510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2669815510
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.1919672819
Short name T1134
Test name
Test status
Simulation time 905774555 ps
CPU time 7.32 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:12:49 AM PDT 24
Peak memory 229248 kb
Host smart-4344fb1e-4590-4371-9137-53749509b33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919672819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.1919672819
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.3796196715
Short name T890
Test name
Test status
Simulation time 1108649827 ps
CPU time 5.15 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:12:46 AM PDT 24
Peak memory 262360 kb
Host smart-ff68188f-470e-4c58-8b22-9708cf3a6008
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796196715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_emp
ty.3796196715
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2299482583
Short name T413
Test name
Test status
Simulation time 6053850278 ps
CPU time 48.69 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:13:30 AM PDT 24
Peak memory 566740 kb
Host smart-32deec96-a4c3-47d4-acc1-11f830a9904f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299482583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2299482583
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.3590649421
Short name T1257
Test name
Test status
Simulation time 2536263758 ps
CPU time 65.82 seconds
Started Jul 02 08:12:38 AM PDT 24
Finished Jul 02 08:13:45 AM PDT 24
Peak memory 676120 kb
Host smart-5cedd100-0272-48ad-bed8-dd363c9d1cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590649421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.3590649421
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.2967929842
Short name T768
Test name
Test status
Simulation time 167066554 ps
CPU time 0.88 seconds
Started Jul 02 08:12:41 AM PDT 24
Finished Jul 02 08:12:43 AM PDT 24
Peak memory 204432 kb
Host smart-0f31f404-0995-43c6-bbe2-4febba1bd7d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967929842 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.2967929842
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.2009418411
Short name T159
Test name
Test status
Simulation time 220232852 ps
CPU time 12.15 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:12:53 AM PDT 24
Peak memory 245284 kb
Host smart-d8bda1e5-3113-4f23-9f68-effe60a7a73d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009418411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx
.2009418411
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.879765767
Short name T184
Test name
Test status
Simulation time 4289258878 ps
CPU time 292.62 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:17:33 AM PDT 24
Peak memory 1242304 kb
Host smart-4a09732a-d960-48d7-8379-6b0fe374a61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879765767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.879765767
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.3978068230
Short name T830
Test name
Test status
Simulation time 869428096 ps
CPU time 6.74 seconds
Started Jul 02 08:12:44 AM PDT 24
Finished Jul 02 08:12:51 AM PDT 24
Peak memory 204796 kb
Host smart-efbb4121-3e7e-4630-a053-59cf7ca1426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978068230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.3978068230
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.999554563
Short name T1308
Test name
Test status
Simulation time 1955972731 ps
CPU time 95.91 seconds
Started Jul 02 08:12:44 AM PDT 24
Finished Jul 02 08:14:21 AM PDT 24
Peak memory 438316 kb
Host smart-1cc451b3-db8d-4d1e-ae4c-195c7e2dab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999554563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.999554563
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.1810592033
Short name T433
Test name
Test status
Simulation time 30268168 ps
CPU time 0.69 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:12:41 AM PDT 24
Peak memory 204540 kb
Host smart-0b40f1b8-b48c-48bc-81ab-eba0cebdcb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810592033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.1810592033
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.2714419564
Short name T1439
Test name
Test status
Simulation time 3136651628 ps
CPU time 129.46 seconds
Started Jul 02 08:12:38 AM PDT 24
Finished Jul 02 08:14:48 AM PDT 24
Peak memory 349788 kb
Host smart-be5d8c37-f454-47ba-b65b-7a38b3ba9e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714419564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.2714419564
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.4199327282
Short name T354
Test name
Test status
Simulation time 24366909166 ps
CPU time 1238.14 seconds
Started Jul 02 08:12:41 AM PDT 24
Finished Jul 02 08:33:21 AM PDT 24
Peak memory 3921888 kb
Host smart-8cb8c744-41a9-4356-941d-f2183185c876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199327282 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.4199327282
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.383847958
Short name T1221
Test name
Test status
Simulation time 7605929035 ps
CPU time 40.21 seconds
Started Jul 02 08:12:40 AM PDT 24
Finished Jul 02 08:13:21 AM PDT 24
Peak memory 381760 kb
Host smart-cb5795a0-13fe-4046-b998-64ce20b69be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383847958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.383847958
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.1567460171
Short name T977
Test name
Test status
Simulation time 606332193 ps
CPU time 11.44 seconds
Started Jul 02 08:12:41 AM PDT 24
Finished Jul 02 08:12:53 AM PDT 24
Peak memory 213000 kb
Host smart-c1a73c72-9f97-4c20-a695-b275cff34f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567460171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.1567460171
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.837925162
Short name T990
Test name
Test status
Simulation time 2049859092 ps
CPU time 2.64 seconds
Started Jul 02 08:12:45 AM PDT 24
Finished Jul 02 08:12:48 AM PDT 24
Peak memory 204852 kb
Host smart-5f082e90-df1c-4c4a-b0c6-5190d45d953e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837925162 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.837925162
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.2130536100
Short name T617
Test name
Test status
Simulation time 776834971 ps
CPU time 1.46 seconds
Started Jul 02 08:12:44 AM PDT 24
Finished Jul 02 08:12:46 AM PDT 24
Peak memory 204756 kb
Host smart-24ee4dbc-4614-4062-b8ca-4343f34ff99b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130536100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_fifo_reset_acq.2130536100
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.3500546882
Short name T426
Test name
Test status
Simulation time 396908845 ps
CPU time 1.31 seconds
Started Jul 02 08:12:44 AM PDT 24
Finished Jul 02 08:12:46 AM PDT 24
Peak memory 204956 kb
Host smart-34849776-dd42-47cd-ad71-9a9b89569d78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500546882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_tx.3500546882
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.506744991
Short name T819
Test name
Test status
Simulation time 345986166 ps
CPU time 1.9 seconds
Started Jul 02 08:12:45 AM PDT 24
Finished Jul 02 08:12:48 AM PDT 24
Peak memory 204748 kb
Host smart-3c228c29-c0dd-4267-9067-9e45508a4937
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506744991 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.506744991
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.1432709782
Short name T1362
Test name
Test status
Simulation time 599402346 ps
CPU time 1.24 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:12:53 AM PDT 24
Peak memory 204596 kb
Host smart-1d2b6c0a-c87e-4cb9-9ead-7101cb0c1a8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432709782 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1432709782
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.2961411924
Short name T358
Test name
Test status
Simulation time 306706891 ps
CPU time 2.83 seconds
Started Jul 02 08:12:46 AM PDT 24
Finished Jul 02 08:12:49 AM PDT 24
Peak memory 204716 kb
Host smart-d9dd2542-ad3f-4457-81cd-a8d834dca8da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961411924 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.2961411924
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.452377401
Short name T1518
Test name
Test status
Simulation time 660161620 ps
CPU time 4.03 seconds
Started Jul 02 08:12:46 AM PDT 24
Finished Jul 02 08:12:50 AM PDT 24
Peak memory 213212 kb
Host smart-833f3f74-3477-4bd1-8e19-ec79e24cdc40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452377401 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.452377401
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.3280778258
Short name T147
Test name
Test status
Simulation time 25682712559 ps
CPU time 8.89 seconds
Started Jul 02 08:12:43 AM PDT 24
Finished Jul 02 08:12:53 AM PDT 24
Peak memory 204944 kb
Host smart-5d7eb85d-1744-4d4a-98b5-f92fb6d502e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280778258 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.3280778258
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2905348169
Short name T1249
Test name
Test status
Simulation time 790809075 ps
CPU time 11.96 seconds
Started Jul 02 08:12:41 AM PDT 24
Finished Jul 02 08:12:55 AM PDT 24
Peak memory 204796 kb
Host smart-f6a6b299-a292-4a48-a43d-2e8164698c4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905348169 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2905348169
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.2566777380
Short name T158
Test name
Test status
Simulation time 4233307939 ps
CPU time 42.97 seconds
Started Jul 02 08:12:44 AM PDT 24
Finished Jul 02 08:13:28 AM PDT 24
Peak memory 207272 kb
Host smart-1b64bd8d-38b5-406e-8bfc-0252ecab3751
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566777380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.2566777380
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.2398420909
Short name T258
Test name
Test status
Simulation time 36725587055 ps
CPU time 331.75 seconds
Started Jul 02 08:12:39 AM PDT 24
Finished Jul 02 08:18:12 AM PDT 24
Peak memory 3627152 kb
Host smart-53bc04c7-7c09-4d6a-98bc-eb7c20229e40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398420909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_wr.2398420909
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.150985129
Short name T409
Test name
Test status
Simulation time 33055470364 ps
CPU time 609.84 seconds
Started Jul 02 08:12:44 AM PDT 24
Finished Jul 02 08:22:55 AM PDT 24
Peak memory 1906036 kb
Host smart-8e672633-b49e-4a20-9a03-0d5a82c6e42f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150985129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.150985129
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.712700042
Short name T1248
Test name
Test status
Simulation time 5433340942 ps
CPU time 7.52 seconds
Started Jul 02 08:12:44 AM PDT 24
Finished Jul 02 08:12:53 AM PDT 24
Peak memory 213148 kb
Host smart-747aba7c-a322-462f-8d43-e349d195bdf1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712700042 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 34.i2c_target_timeout.712700042
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.3456117054
Short name T1201
Test name
Test status
Simulation time 206521705 ps
CPU time 3.48 seconds
Started Jul 02 08:12:52 AM PDT 24
Finished Jul 02 08:12:57 AM PDT 24
Peak memory 204744 kb
Host smart-836a878f-345e-43f4-96cd-2db03823f980
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456117054 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.3456117054
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.1855918119
Short name T1243
Test name
Test status
Simulation time 36678633 ps
CPU time 0.68 seconds
Started Jul 02 08:12:56 AM PDT 24
Finished Jul 02 08:12:57 AM PDT 24
Peak memory 204432 kb
Host smart-b410166b-f985-4136-8015-167381afb189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855918119 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.1855918119
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.1766155395
Short name T404
Test name
Test status
Simulation time 189788161 ps
CPU time 1.97 seconds
Started Jul 02 08:12:52 AM PDT 24
Finished Jul 02 08:12:55 AM PDT 24
Peak memory 216904 kb
Host smart-1edba9ae-40f9-4b5c-9d92-56831c4938c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766155395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.1766155395
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.3780639046
Short name T785
Test name
Test status
Simulation time 1378828255 ps
CPU time 8.18 seconds
Started Jul 02 08:12:53 AM PDT 24
Finished Jul 02 08:13:02 AM PDT 24
Peak memory 280104 kb
Host smart-b4c158ff-311a-4a8c-b82d-83f4aebffb60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780639046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.3780639046
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.1908838787
Short name T965
Test name
Test status
Simulation time 1283331075 ps
CPU time 83.83 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:14:15 AM PDT 24
Peak memory 521152 kb
Host smart-3927ddaf-4491-4830-87ea-de2bf773cff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908838787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.1908838787
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1849340870
Short name T1055
Test name
Test status
Simulation time 3889032561 ps
CPU time 125.62 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:14:58 AM PDT 24
Peak memory 633848 kb
Host smart-e5343784-e803-4ef0-9577-b19b55a6cf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849340870 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1849340870
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.4227327191
Short name T1110
Test name
Test status
Simulation time 71331583 ps
CPU time 0.79 seconds
Started Jul 02 08:12:50 AM PDT 24
Finished Jul 02 08:12:51 AM PDT 24
Peak memory 204428 kb
Host smart-13f41d58-fe11-4da0-aa67-259ef07928fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227327191 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_f
mt.4227327191
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.2998140133
Short name T828
Test name
Test status
Simulation time 277490890 ps
CPU time 4.01 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:12:56 AM PDT 24
Peak memory 225940 kb
Host smart-8f3fd1d5-d208-4c3d-988a-40d732dd061b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998140133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.2998140133
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3641586255
Short name T1341
Test name
Test status
Simulation time 63999139286 ps
CPU time 368.93 seconds
Started Jul 02 08:12:49 AM PDT 24
Finished Jul 02 08:18:59 AM PDT 24
Peak memory 1379056 kb
Host smart-8e246701-74bd-4b58-8dd3-bdcdb26a6cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641586255 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3641586255
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.1702032378
Short name T1000
Test name
Test status
Simulation time 15011664806 ps
CPU time 11.76 seconds
Started Jul 02 08:12:58 AM PDT 24
Finished Jul 02 08:13:11 AM PDT 24
Peak memory 204940 kb
Host smart-691ddeb7-d0cd-4dc0-9068-f63697d9c30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702032378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.1702032378
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_override.1858563965
Short name T475
Test name
Test status
Simulation time 54678356 ps
CPU time 0.63 seconds
Started Jul 02 08:12:50 AM PDT 24
Finished Jul 02 08:12:51 AM PDT 24
Peak memory 204528 kb
Host smart-c5c39f3b-0b5d-4dea-974f-9344a18161ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858563965 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.1858563965
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.1800047261
Short name T1340
Test name
Test status
Simulation time 25550316242 ps
CPU time 360.82 seconds
Started Jul 02 08:12:53 AM PDT 24
Finished Jul 02 08:18:55 AM PDT 24
Peak memory 1001560 kb
Host smart-e5e0ca43-3175-42c0-8c59-2300e2af2dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800047261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.1800047261
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.2035607111
Short name T314
Test name
Test status
Simulation time 84600998 ps
CPU time 2.01 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:12:54 AM PDT 24
Peak memory 224676 kb
Host smart-abba1b4b-e25b-4fd1-bba7-2d4437a05ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035607111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2035607111
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.366588591
Short name T1111
Test name
Test status
Simulation time 1920613498 ps
CPU time 30.83 seconds
Started Jul 02 08:12:53 AM PDT 24
Finished Jul 02 08:13:25 AM PDT 24
Peak memory 385124 kb
Host smart-bd40ab0b-c243-4bd0-bc20-e817e1ce74f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366588591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.366588591
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1486578530
Short name T115
Test name
Test status
Simulation time 16914471596 ps
CPU time 316.99 seconds
Started Jul 02 08:12:50 AM PDT 24
Finished Jul 02 08:18:08 AM PDT 24
Peak memory 1547684 kb
Host smart-78d89c6a-5b20-4e36-b046-f7f3e23ec554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486578530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1486578530
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.3339638326
Short name T274
Test name
Test status
Simulation time 948769700 ps
CPU time 18.29 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:13:11 AM PDT 24
Peak memory 220792 kb
Host smart-2a9fa246-0105-40f2-bcc6-d8bf6a734b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339638326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.3339638326
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.3963151122
Short name T964
Test name
Test status
Simulation time 2102975777 ps
CPU time 5.72 seconds
Started Jul 02 08:13:01 AM PDT 24
Finished Jul 02 08:13:07 AM PDT 24
Peak memory 213028 kb
Host smart-334cdb50-5398-4298-ab40-84e8888a9ee6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963151122 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.i2c_target_bad_addr.3963151122
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.523603240
Short name T1034
Test name
Test status
Simulation time 199440791 ps
CPU time 1.25 seconds
Started Jul 02 08:12:56 AM PDT 24
Finished Jul 02 08:12:58 AM PDT 24
Peak memory 204608 kb
Host smart-ac122f51-ebcb-4305-97de-ce0c3e813628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523603240 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_acq.523603240
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.3094489664
Short name T871
Test name
Test status
Simulation time 385837024 ps
CPU time 1.34 seconds
Started Jul 02 08:12:55 AM PDT 24
Finished Jul 02 08:12:58 AM PDT 24
Peak memory 204604 kb
Host smart-706e5d41-be22-49e1-b304-0a577d138902
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094489664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 35.i2c_target_fifo_reset_tx.3094489664
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.1736894483
Short name T320
Test name
Test status
Simulation time 418831257 ps
CPU time 2.34 seconds
Started Jul 02 08:12:56 AM PDT 24
Finished Jul 02 08:13:00 AM PDT 24
Peak memory 204768 kb
Host smart-2ad3ea39-9433-4d37-ba02-1954c322c339
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736894483 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.1736894483
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.3034676398
Short name T1089
Test name
Test status
Simulation time 281367051 ps
CPU time 0.92 seconds
Started Jul 02 08:12:55 AM PDT 24
Finished Jul 02 08:12:57 AM PDT 24
Peak memory 204580 kb
Host smart-90c5dc93-d487-4fbb-86d9-35a6a2f6803d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034676398 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.3034676398
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.2832801499
Short name T1049
Test name
Test status
Simulation time 5822604738 ps
CPU time 2.56 seconds
Started Jul 02 08:12:57 AM PDT 24
Finished Jul 02 08:13:00 AM PDT 24
Peak memory 204908 kb
Host smart-baf5e2a7-9ba8-4c0a-bdec-3026835e6f42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832801499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.2832801499
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.4020495364
Short name T268
Test name
Test status
Simulation time 9104382546 ps
CPU time 6.89 seconds
Started Jul 02 08:12:55 AM PDT 24
Finished Jul 02 08:13:03 AM PDT 24
Peak memory 221128 kb
Host smart-eb2f4aa8-19ae-43a0-9fa4-230d27791038
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020495364 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.4020495364
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.4269599691
Short name T379
Test name
Test status
Simulation time 13177660619 ps
CPU time 26.97 seconds
Started Jul 02 08:12:55 AM PDT 24
Finished Jul 02 08:13:24 AM PDT 24
Peak memory 792576 kb
Host smart-7e4d54f8-d31b-42b8-b301-9503388db85e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269599691 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.4269599691
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.3481577059
Short name T1179
Test name
Test status
Simulation time 534954564 ps
CPU time 21.05 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:13:14 AM PDT 24
Peak memory 205024 kb
Host smart-0e542f8c-b530-4c5e-9ec1-ee2f33de9b7f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481577059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_ta
rget_smoke.3481577059
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.3345825951
Short name T1322
Test name
Test status
Simulation time 1267921985 ps
CPU time 9.77 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:13:01 AM PDT 24
Peak memory 207600 kb
Host smart-095ff028-a520-495f-8d0d-7d7d2e5140d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345825951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_rd.3345825951
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2159431054
Short name T726
Test name
Test status
Simulation time 9927177885 ps
CPU time 4.02 seconds
Started Jul 02 08:12:51 AM PDT 24
Finished Jul 02 08:12:56 AM PDT 24
Peak memory 204888 kb
Host smart-6a05ced6-da14-41cd-bf69-7e7764138a1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159431054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2159431054
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.2066131095
Short name T1162
Test name
Test status
Simulation time 14542737160 ps
CPU time 50.58 seconds
Started Jul 02 08:12:58 AM PDT 24
Finished Jul 02 08:13:50 AM PDT 24
Peak memory 680164 kb
Host smart-03df8161-64b4-438b-a608-3d71c18f5488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066131095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_
target_stretch.2066131095
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.1577357512
Short name T1139
Test name
Test status
Simulation time 1127132218 ps
CPU time 6.54 seconds
Started Jul 02 08:12:59 AM PDT 24
Finished Jul 02 08:13:07 AM PDT 24
Peak memory 218128 kb
Host smart-a20ad027-62bb-4498-b6de-9dd87b0728a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577357512 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.1577357512
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2761317763
Short name T715
Test name
Test status
Simulation time 22010261 ps
CPU time 0.62 seconds
Started Jul 02 08:13:04 AM PDT 24
Finished Jul 02 08:13:06 AM PDT 24
Peak memory 204480 kb
Host smart-1758941e-d68a-4c64-a589-5fede77172eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761317763 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2761317763
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.3722914045
Short name T840
Test name
Test status
Simulation time 246353107 ps
CPU time 1.67 seconds
Started Jul 02 08:12:55 AM PDT 24
Finished Jul 02 08:12:58 AM PDT 24
Peak memory 213124 kb
Host smart-60c47c2f-c2a1-4e19-b33c-a2ea3edf3175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722914045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.3722914045
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.2533802597
Short name T1353
Test name
Test status
Simulation time 632669025 ps
CPU time 5.65 seconds
Started Jul 02 08:12:55 AM PDT 24
Finished Jul 02 08:13:02 AM PDT 24
Peak memory 267936 kb
Host smart-36df7386-53af-4391-996f-102878a743b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533802597 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_emp
ty.2533802597
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.950757475
Short name T74
Test name
Test status
Simulation time 2375670655 ps
CPU time 159.67 seconds
Started Jul 02 08:12:57 AM PDT 24
Finished Jul 02 08:15:38 AM PDT 24
Peak memory 761980 kb
Host smart-bb90608a-2d57-448c-b16e-3a0992a9a4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950757475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.950757475
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.3393359132
Short name T513
Test name
Test status
Simulation time 1909527314 ps
CPU time 63.59 seconds
Started Jul 02 08:12:56 AM PDT 24
Finished Jul 02 08:14:01 AM PDT 24
Peak memory 680904 kb
Host smart-6acf3465-cd05-47ce-a452-9bf884add95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393359132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.3393359132
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3928554094
Short name T697
Test name
Test status
Simulation time 275355498 ps
CPU time 0.88 seconds
Started Jul 02 08:12:59 AM PDT 24
Finished Jul 02 08:13:01 AM PDT 24
Peak memory 204432 kb
Host smart-febb8fd7-b9fe-4ce3-8fd4-f56720bb0ecd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928554094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3928554094
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.4243015077
Short name T1276
Test name
Test status
Simulation time 297901841 ps
CPU time 3.92 seconds
Started Jul 02 08:12:54 AM PDT 24
Finished Jul 02 08:12:59 AM PDT 24
Peak memory 204840 kb
Host smart-bd10dee8-b358-475a-a114-62675f3fc2d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243015077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx
.4243015077
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.422544130
Short name T338
Test name
Test status
Simulation time 18962970593 ps
CPU time 356.78 seconds
Started Jul 02 08:12:56 AM PDT 24
Finished Jul 02 08:18:54 AM PDT 24
Peak memory 1360052 kb
Host smart-118fa4c4-da84-4291-b47c-8b6da9868ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422544130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.422544130
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2285784500
Short name T1328
Test name
Test status
Simulation time 1495891732 ps
CPU time 59.86 seconds
Started Jul 02 08:13:01 AM PDT 24
Finished Jul 02 08:14:02 AM PDT 24
Peak memory 285304 kb
Host smart-fa8fe413-6a82-4cc6-8d43-5bd68a22b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285784500 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2285784500
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.3617592583
Short name T129
Test name
Test status
Simulation time 46580710 ps
CPU time 0.68 seconds
Started Jul 02 08:12:56 AM PDT 24
Finished Jul 02 08:12:58 AM PDT 24
Peak memory 204512 kb
Host smart-8a119ebb-6711-49e2-8d51-fc7ae9dc7088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617592583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.3617592583
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.2888921378
Short name T776
Test name
Test status
Simulation time 525131221 ps
CPU time 6.09 seconds
Started Jul 02 08:12:58 AM PDT 24
Finished Jul 02 08:13:06 AM PDT 24
Peak memory 204768 kb
Host smart-fe7290f7-d160-4d2d-b6de-b6682949e36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888921378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.2888921378
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.3143675505
Short name T441
Test name
Test status
Simulation time 1512936466 ps
CPU time 22.3 seconds
Started Jul 02 08:12:58 AM PDT 24
Finished Jul 02 08:13:22 AM PDT 24
Peak memory 328648 kb
Host smart-48458a2c-9086-4bbb-a0a9-f6f95fa01368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143675505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.3143675505
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.2789612476
Short name T45
Test name
Test status
Simulation time 8885404317 ps
CPU time 339.95 seconds
Started Jul 02 08:12:58 AM PDT 24
Finished Jul 02 08:18:40 AM PDT 24
Peak memory 613640 kb
Host smart-84a8ace6-ce76-43a7-985b-d9391f95b417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789612476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.2789612476
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.1186341121
Short name T316
Test name
Test status
Simulation time 767061520 ps
CPU time 31.29 seconds
Started Jul 02 08:12:53 AM PDT 24
Finished Jul 02 08:13:25 AM PDT 24
Peak memory 212948 kb
Host smart-909594d9-45d5-42b1-a7a1-82553dc56558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186341121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.1186341121
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.2047640614
Short name T554
Test name
Test status
Simulation time 2804149362 ps
CPU time 4.12 seconds
Started Jul 02 08:13:04 AM PDT 24
Finished Jul 02 08:13:09 AM PDT 24
Peak memory 204900 kb
Host smart-1256fc9a-79c5-4588-8bd5-4d337c20eb05
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047640614 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.2047640614
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.746799058
Short name T87
Test name
Test status
Simulation time 639020646 ps
CPU time 1.39 seconds
Started Jul 02 08:13:01 AM PDT 24
Finished Jul 02 08:13:03 AM PDT 24
Peak memory 205120 kb
Host smart-022a236b-eb71-4356-be5f-eb4159feb1a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746799058 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_acq.746799058
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.181510783
Short name T1391
Test name
Test status
Simulation time 254033126 ps
CPU time 1.19 seconds
Started Jul 02 08:13:01 AM PDT 24
Finished Jul 02 08:13:03 AM PDT 24
Peak memory 204760 kb
Host smart-779db9e8-cf4e-40f6-8d8f-abb3b9115389
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181510783 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.i2c_target_fifo_reset_tx.181510783
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.4139888964
Short name T1020
Test name
Test status
Simulation time 674199390 ps
CPU time 1.27 seconds
Started Jul 02 08:13:00 AM PDT 24
Finished Jul 02 08:13:02 AM PDT 24
Peak memory 204536 kb
Host smart-2b4921de-4377-4746-a6b7-30ee9de7b509
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139888964 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.4139888964
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.336205010
Short name T775
Test name
Test status
Simulation time 252900904 ps
CPU time 1.23 seconds
Started Jul 02 08:13:03 AM PDT 24
Finished Jul 02 08:13:05 AM PDT 24
Peak memory 204592 kb
Host smart-6c32798b-1624-4ffe-9581-727e14446651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336205010 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.336205010
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_hrst.1675717805
Short name T334
Test name
Test status
Simulation time 2040638271 ps
CPU time 2.84 seconds
Started Jul 02 08:12:58 AM PDT 24
Finished Jul 02 08:13:03 AM PDT 24
Peak memory 204792 kb
Host smart-64913765-61e9-450f-8254-ed03e2003111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675717805 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_hrst.1675717805
Directory /workspace/36.i2c_target_hrst/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.1524498258
Short name T520
Test name
Test status
Simulation time 777126078 ps
CPU time 4.53 seconds
Started Jul 02 08:12:59 AM PDT 24
Finished Jul 02 08:13:05 AM PDT 24
Peak memory 205012 kb
Host smart-81649290-d8e8-44c9-aedd-7adfce5a8d46
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524498258 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 36.i2c_target_intr_smoke.1524498258
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.4061612721
Short name T1071
Test name
Test status
Simulation time 14660806193 ps
CPU time 48.93 seconds
Started Jul 02 08:12:59 AM PDT 24
Finished Jul 02 08:13:49 AM PDT 24
Peak memory 1006716 kb
Host smart-950edfe2-31fb-44a1-b34a-4e4edfee1cf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061612721 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.4061612721
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.4069212473
Short name T1505
Test name
Test status
Simulation time 3533693878 ps
CPU time 29.48 seconds
Started Jul 02 08:12:57 AM PDT 24
Finished Jul 02 08:13:27 AM PDT 24
Peak memory 204840 kb
Host smart-45d81abd-7c79-400f-91af-80e7c7caed29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069212473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.4069212473
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.716991796
Short name T25
Test name
Test status
Simulation time 1353542400 ps
CPU time 54.84 seconds
Started Jul 02 08:13:00 AM PDT 24
Finished Jul 02 08:13:56 AM PDT 24
Peak memory 207216 kb
Host smart-3c5c78e8-785e-47c5-9366-bbea233faa41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716991796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.716991796
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2641299015
Short name T1395
Test name
Test status
Simulation time 34578438933 ps
CPU time 46.91 seconds
Started Jul 02 08:12:55 AM PDT 24
Finished Jul 02 08:13:44 AM PDT 24
Peak memory 953812 kb
Host smart-311c4388-56de-447e-a26e-27ca34cb87a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641299015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2641299015
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.1966125378
Short name T945
Test name
Test status
Simulation time 12843409818 ps
CPU time 508.75 seconds
Started Jul 02 08:13:00 AM PDT 24
Finished Jul 02 08:21:30 AM PDT 24
Peak memory 1646892 kb
Host smart-1de9b905-5cfa-4d06-b403-2788811066d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966125378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.1966125378
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1514508853
Short name T1084
Test name
Test status
Simulation time 1416474450 ps
CPU time 7.12 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:13:13 AM PDT 24
Peak memory 220860 kb
Host smart-8d932848-e4a7-4172-b2c6-c4c0b4faefdf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514508853 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1514508853
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.1925290858
Short name T351
Test name
Test status
Simulation time 853135068 ps
CPU time 10.11 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:13:17 AM PDT 24
Peak memory 204804 kb
Host smart-31cc01a5-7725-4d5f-abe4-55ec510418a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925290858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.1925290858
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2390676647
Short name T454
Test name
Test status
Simulation time 57181131 ps
CPU time 0.62 seconds
Started Jul 02 08:13:07 AM PDT 24
Finished Jul 02 08:13:10 AM PDT 24
Peak memory 204104 kb
Host smart-7ff48f84-3a6f-4285-b469-afc69bc1743e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390676647 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2390676647
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1192891999
Short name T884
Test name
Test status
Simulation time 398885344 ps
CPU time 1.39 seconds
Started Jul 02 08:13:08 AM PDT 24
Finished Jul 02 08:13:12 AM PDT 24
Peak memory 213128 kb
Host smart-5fce2545-c34c-468b-8c55-1ffae947350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192891999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1192891999
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.3856261801
Short name T457
Test name
Test status
Simulation time 266730724 ps
CPU time 13.78 seconds
Started Jul 02 08:13:04 AM PDT 24
Finished Jul 02 08:13:19 AM PDT 24
Peak memory 261380 kb
Host smart-c7db7361-07cb-4e32-baa1-a2aaf656f1f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856261801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_emp
ty.3856261801
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.834865564
Short name T748
Test name
Test status
Simulation time 8566994821 ps
CPU time 85.54 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:14:33 AM PDT 24
Peak memory 721004 kb
Host smart-f9e83f62-9798-48f1-96ea-a375b96b890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834865564 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.834865564
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.3443700060
Short name T1052
Test name
Test status
Simulation time 19539584550 ps
CPU time 140.79 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:15:29 AM PDT 24
Peak memory 660524 kb
Host smart-39980b50-48e6-4526-96a2-17c8417af91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443700060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.3443700060
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.174051603
Short name T1396
Test name
Test status
Simulation time 71558893 ps
CPU time 0.88 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:13:08 AM PDT 24
Peak memory 204448 kb
Host smart-d4683446-df1d-46aa-899f-7bbe35823425
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174051603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.174051603
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1611916930
Short name T1121
Test name
Test status
Simulation time 289082376 ps
CPU time 7.85 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:13:14 AM PDT 24
Peak memory 204832 kb
Host smart-950572fa-c40a-4788-be32-e771c770aa62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611916930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1611916930
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.1754495640
Short name T1238
Test name
Test status
Simulation time 20714849492 ps
CPU time 127.94 seconds
Started Jul 02 08:13:08 AM PDT 24
Finished Jul 02 08:15:17 AM PDT 24
Peak memory 1440988 kb
Host smart-63e05cff-d82e-413e-934d-dd1533e24ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754495640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.1754495640
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.1854678117
Short name T989
Test name
Test status
Simulation time 1067074835 ps
CPU time 4.36 seconds
Started Jul 02 08:13:07 AM PDT 24
Finished Jul 02 08:13:14 AM PDT 24
Peak memory 204808 kb
Host smart-2e689f2c-7a71-4396-9fe9-2dee04f6b303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854678117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.1854678117
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.3296908303
Short name T328
Test name
Test status
Simulation time 1418716604 ps
CPU time 65.33 seconds
Started Jul 02 08:13:07 AM PDT 24
Finished Jul 02 08:14:14 AM PDT 24
Peak memory 344104 kb
Host smart-902c221e-2195-44dd-abc0-1ed5472eb401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296908303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.3296908303
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.2696883508
Short name T787
Test name
Test status
Simulation time 24382425 ps
CPU time 0.66 seconds
Started Jul 02 08:13:01 AM PDT 24
Finished Jul 02 08:13:02 AM PDT 24
Peak memory 204492 kb
Host smart-69b345ea-b16e-40a2-828a-6a7824810c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696883508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.2696883508
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3999530805
Short name T929
Test name
Test status
Simulation time 6894912044 ps
CPU time 64.71 seconds
Started Jul 02 08:13:07 AM PDT 24
Finished Jul 02 08:14:14 AM PDT 24
Peak memory 204948 kb
Host smart-9865d721-7362-44e0-abf3-ab9f3e7c1e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999530805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3999530805
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.1553950705
Short name T861
Test name
Test status
Simulation time 238935206 ps
CPU time 1.52 seconds
Started Jul 02 08:13:08 AM PDT 24
Finished Jul 02 08:13:11 AM PDT 24
Peak memory 204712 kb
Host smart-d8920e53-d729-4b3c-91a2-3ba8375c6d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553950705 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.1553950705
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.3141003926
Short name T848
Test name
Test status
Simulation time 1533920911 ps
CPU time 32.04 seconds
Started Jul 02 08:12:59 AM PDT 24
Finished Jul 02 08:13:32 AM PDT 24
Peak memory 362420 kb
Host smart-7bac0690-10e4-4b26-85d0-be2fe3305d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141003926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.3141003926
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.1052736118
Short name T1005
Test name
Test status
Simulation time 997319735 ps
CPU time 19.46 seconds
Started Jul 02 08:13:07 AM PDT 24
Finished Jul 02 08:13:29 AM PDT 24
Peak memory 220828 kb
Host smart-84a0e5c3-8264-4a8e-a8f7-b44592162a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052736118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1052736118
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.3365127511
Short name T565
Test name
Test status
Simulation time 589351210 ps
CPU time 3.2 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:13:10 AM PDT 24
Peak memory 213032 kb
Host smart-3972a798-35f8-4c1b-bc81-0a99fe6a7740
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365127511 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.3365127511
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.359980919
Short name T931
Test name
Test status
Simulation time 279075139 ps
CPU time 1.03 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:13:08 AM PDT 24
Peak memory 204620 kb
Host smart-669a8dce-1430-4c0a-9eae-1dd1f7054b2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359980919 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.359980919
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1850081195
Short name T844
Test name
Test status
Simulation time 234842445 ps
CPU time 0.98 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:13:09 AM PDT 24
Peak memory 204576 kb
Host smart-124e12e2-73d7-4928-9f74-f4af149be6f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850081195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1850081195
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.4212804785
Short name T527
Test name
Test status
Simulation time 402525575 ps
CPU time 1.78 seconds
Started Jul 02 08:13:08 AM PDT 24
Finished Jul 02 08:13:12 AM PDT 24
Peak memory 204580 kb
Host smart-6ee24a0d-827c-498c-9998-f6c67cc2dc4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212804785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.4212804785
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.2827795607
Short name T1252
Test name
Test status
Simulation time 105117571 ps
CPU time 1.13 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:13:08 AM PDT 24
Peak memory 204568 kb
Host smart-6e195391-2a40-4526-b268-91f664417de5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827795607 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.2827795607
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.621529442
Short name T657
Test name
Test status
Simulation time 5197086213 ps
CPU time 6.75 seconds
Started Jul 02 08:13:04 AM PDT 24
Finished Jul 02 08:13:11 AM PDT 24
Peak memory 213732 kb
Host smart-b8516c33-e7a5-447d-a140-56b093753db0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621529442 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 37.i2c_target_intr_smoke.621529442
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.3294505965
Short name T1132
Test name
Test status
Simulation time 11839672291 ps
CPU time 200.18 seconds
Started Jul 02 08:13:12 AM PDT 24
Finished Jul 02 08:16:34 AM PDT 24
Peak memory 3011852 kb
Host smart-4d1b2da6-e324-4eb6-8b1f-082cdf214c17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294505965 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.3294505965
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.3269761960
Short name T162
Test name
Test status
Simulation time 4831809564 ps
CPU time 48.71 seconds
Started Jul 02 08:13:03 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 204904 kb
Host smart-32eb169c-54b6-43ce-bde8-c9449c12e4d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269761960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.3269761960
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.1692968357
Short name T156
Test name
Test status
Simulation time 741518971 ps
CPU time 14.46 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:13:22 AM PDT 24
Peak memory 212284 kb
Host smart-f240395c-fd00-4173-8759-844c60c3af97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692968357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.1692968357
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3364800604
Short name T1083
Test name
Test status
Simulation time 35379154552 ps
CPU time 425.8 seconds
Started Jul 02 08:13:04 AM PDT 24
Finished Jul 02 08:20:11 AM PDT 24
Peak memory 3988560 kb
Host smart-f61505b4-2ad4-4822-b8a8-5afc6d9bcb70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364800604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3364800604
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.2192843858
Short name T113
Test name
Test status
Simulation time 31665962076 ps
CPU time 148.52 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:15:37 AM PDT 24
Peak memory 611572 kb
Host smart-5d285f81-9d09-428e-acdc-689618da0d63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192843858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.2192843858
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.1609015837
Short name T1375
Test name
Test status
Simulation time 12146877707 ps
CPU time 8.67 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:13:17 AM PDT 24
Peak memory 221188 kb
Host smart-8edc8969-e2ce-47b8-a597-d0ce80f5779c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609015837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 37.i2c_target_timeout.1609015837
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.1362015413
Short name T449
Test name
Test status
Simulation time 114476470 ps
CPU time 2.41 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:13:11 AM PDT 24
Peak memory 204764 kb
Host smart-6b3591ae-2f41-4680-9d25-17a92c5f3c29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362015413 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.1362015413
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2787355233
Short name T1448
Test name
Test status
Simulation time 43145848 ps
CPU time 0.61 seconds
Started Jul 02 08:13:10 AM PDT 24
Finished Jul 02 08:13:12 AM PDT 24
Peak memory 204436 kb
Host smart-fe87675c-b5e5-43b3-ad5d-6bcfdff922a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787355233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2787355233
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.4167763391
Short name T186
Test name
Test status
Simulation time 271986357 ps
CPU time 1.68 seconds
Started Jul 02 08:13:12 AM PDT 24
Finished Jul 02 08:13:16 AM PDT 24
Peak memory 213028 kb
Host smart-00628837-d5db-4bc9-a02a-20983650ed92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167763391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.4167763391
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1796506153
Short name T934
Test name
Test status
Simulation time 441309796 ps
CPU time 11.61 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 248552 kb
Host smart-09b54426-26f4-4892-af31-122d53af5b5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796506153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1796506153
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.818599503
Short name T71
Test name
Test status
Simulation time 6944883811 ps
CPU time 91.53 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:14:39 AM PDT 24
Peak memory 522536 kb
Host smart-4d6b9f11-fc22-4b87-b763-45c8a8190d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818599503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.818599503
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.189538723
Short name T309
Test name
Test status
Simulation time 6373567742 ps
CPU time 48.42 seconds
Started Jul 02 08:13:07 AM PDT 24
Finished Jul 02 08:13:57 AM PDT 24
Peak memory 554160 kb
Host smart-ebf19b8f-0e58-4613-849f-1d82913fc654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189538723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.189538723
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2197661025
Short name T1146
Test name
Test status
Simulation time 1312100997 ps
CPU time 1.13 seconds
Started Jul 02 08:13:07 AM PDT 24
Finished Jul 02 08:13:10 AM PDT 24
Peak memory 204136 kb
Host smart-228ff1b1-8116-464c-ad30-fcfdb7b88994
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197661025 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2197661025
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.1138160840
Short name T1481
Test name
Test status
Simulation time 755330743 ps
CPU time 5.54 seconds
Started Jul 02 08:13:05 AM PDT 24
Finished Jul 02 08:13:13 AM PDT 24
Peak memory 240744 kb
Host smart-7f801003-0248-4279-b281-d02397595ac6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138160840 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx
.1138160840
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.1365026287
Short name T142
Test name
Test status
Simulation time 19076591686 ps
CPU time 372.74 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:19:20 AM PDT 24
Peak memory 1397208 kb
Host smart-2e4c10fc-116d-4e4b-9326-7938e946d156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365026287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.1365026287
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.934199287
Short name T263
Test name
Test status
Simulation time 399105269 ps
CPU time 8.19 seconds
Started Jul 02 08:13:13 AM PDT 24
Finished Jul 02 08:13:24 AM PDT 24
Peak memory 204808 kb
Host smart-c0e0bf48-fd93-4198-9dac-59572b5424a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934199287 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.934199287
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.1994305543
Short name T248
Test name
Test status
Simulation time 1740544519 ps
CPU time 75.24 seconds
Started Jul 02 08:13:13 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 312728 kb
Host smart-30ce6e24-9028-4e47-87e7-43c54f84c53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994305543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.1994305543
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.2265698969
Short name T735
Test name
Test status
Simulation time 29435817 ps
CPU time 0.66 seconds
Started Jul 02 08:13:08 AM PDT 24
Finished Jul 02 08:13:11 AM PDT 24
Peak memory 204724 kb
Host smart-288c0d38-0232-4561-aa04-7b5160c864a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265698969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2265698969
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2694562261
Short name T416
Test name
Test status
Simulation time 28432325993 ps
CPU time 338.08 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:18:46 AM PDT 24
Peak memory 204956 kb
Host smart-4a02e5ff-78b4-4e19-809c-ab11b2f0013f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694562261 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2694562261
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.1457385375
Short name T729
Test name
Test status
Simulation time 555168709 ps
CPU time 1.1 seconds
Started Jul 02 08:13:07 AM PDT 24
Finished Jul 02 08:13:10 AM PDT 24
Peak memory 204656 kb
Host smart-a9dfdf45-0084-43a9-9e85-74f857a0c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457385375 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.1457385375
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.1844973885
Short name T1476
Test name
Test status
Simulation time 2173502437 ps
CPU time 100.81 seconds
Started Jul 02 08:13:06 AM PDT 24
Finished Jul 02 08:14:50 AM PDT 24
Peak memory 429820 kb
Host smart-790e5828-4875-4c0c-b9d7-ba158091e54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844973885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.1844973885
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.2782993506
Short name T116
Test name
Test status
Simulation time 83605619290 ps
CPU time 1042.19 seconds
Started Jul 02 08:13:09 AM PDT 24
Finished Jul 02 08:30:33 AM PDT 24
Peak memory 3827788 kb
Host smart-37fd613c-c967-4021-9565-18004a626794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782993506 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.2782993506
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.2560316380
Short name T682
Test name
Test status
Simulation time 2833625650 ps
CPU time 26.21 seconds
Started Jul 02 08:13:12 AM PDT 24
Finished Jul 02 08:13:41 AM PDT 24
Peak memory 213120 kb
Host smart-836ea00c-4a4d-46f4-aebd-19a5b3b116be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560316380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2560316380
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.3979541732
Short name T1255
Test name
Test status
Simulation time 1769121489 ps
CPU time 5.08 seconds
Started Jul 02 08:13:12 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 213052 kb
Host smart-42736116-4ab6-4b80-89bc-c9315ce3d2f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979541732 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.3979541732
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2659588576
Short name T242
Test name
Test status
Simulation time 150766450 ps
CPU time 0.91 seconds
Started Jul 02 08:13:10 AM PDT 24
Finished Jul 02 08:13:13 AM PDT 24
Peak memory 204628 kb
Host smart-da553c61-492c-4e3c-9256-5e7b069d64a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659588576 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2659588576
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.3814912781
Short name T207
Test name
Test status
Simulation time 225051429 ps
CPU time 1.51 seconds
Started Jul 02 08:13:11 AM PDT 24
Finished Jul 02 08:13:14 AM PDT 24
Peak memory 204828 kb
Host smart-aa3f46f2-9050-4c6f-9746-b356eaa4c84a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814912781 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.3814912781
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.1464694876
Short name T1250
Test name
Test status
Simulation time 1398847365 ps
CPU time 2.05 seconds
Started Jul 02 08:13:12 AM PDT 24
Finished Jul 02 08:13:17 AM PDT 24
Peak memory 204804 kb
Host smart-685eece7-429c-4faf-bea1-965a3e275608
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464694876 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.1464694876
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.739532481
Short name T323
Test name
Test status
Simulation time 370289928 ps
CPU time 1.31 seconds
Started Jul 02 08:13:11 AM PDT 24
Finished Jul 02 08:13:15 AM PDT 24
Peak memory 204580 kb
Host smart-b06b0373-f534-482d-ace8-ba24823e102c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739532481 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.739532481
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.3543609694
Short name T1212
Test name
Test status
Simulation time 1386410468 ps
CPU time 2.93 seconds
Started Jul 02 08:13:11 AM PDT 24
Finished Jul 02 08:13:17 AM PDT 24
Peak memory 204828 kb
Host smart-27bdddf3-2ed1-4bf5-a114-afe6cff1a804
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543609694 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.3543609694
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.2378444557
Short name T926
Test name
Test status
Simulation time 1124032291 ps
CPU time 6.32 seconds
Started Jul 02 08:13:11 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 213076 kb
Host smart-c5da02fc-638c-4e20-bb9f-b073a43fdb4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378444557 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_intr_smoke.2378444557
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.2324737082
Short name T363
Test name
Test status
Simulation time 12487967664 ps
CPU time 30.28 seconds
Started Jul 02 08:13:10 AM PDT 24
Finished Jul 02 08:13:43 AM PDT 24
Peak memory 662748 kb
Host smart-c577831d-a411-413b-99b1-00e992090320
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324737082 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.2324737082
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.3305197142
Short name T793
Test name
Test status
Simulation time 955412138 ps
CPU time 32.43 seconds
Started Jul 02 08:13:10 AM PDT 24
Finished Jul 02 08:13:44 AM PDT 24
Peak memory 204776 kb
Host smart-c7c14a9c-694f-4508-9d3e-d108914ed04d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305197142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_ta
rget_smoke.3305197142
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.975115492
Short name T346
Test name
Test status
Simulation time 762760959 ps
CPU time 31.88 seconds
Started Jul 02 08:13:10 AM PDT 24
Finished Jul 02 08:13:44 AM PDT 24
Peak memory 204788 kb
Host smart-ecaed3fe-af89-4b9c-a18a-e76bf13694ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975115492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c
_target_stress_rd.975115492
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.4034154583
Short name T1197
Test name
Test status
Simulation time 32042938929 ps
CPU time 270.03 seconds
Started Jul 02 08:13:11 AM PDT 24
Finished Jul 02 08:17:43 AM PDT 24
Peak memory 3142672 kb
Host smart-6c0684ba-2fee-49ec-ada2-6e2e8fd29eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034154583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.4034154583
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.370729251
Short name T1463
Test name
Test status
Simulation time 162310406 ps
CPU time 2.76 seconds
Started Jul 02 08:13:11 AM PDT 24
Finished Jul 02 08:13:16 AM PDT 24
Peak memory 204880 kb
Host smart-86439b2c-3251-4da9-9d1f-f3b8b484fd6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370729251 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.370729251
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.2123116522
Short name T625
Test name
Test status
Simulation time 18751304 ps
CPU time 0.64 seconds
Started Jul 02 08:13:22 AM PDT 24
Finished Jul 02 08:13:24 AM PDT 24
Peak memory 204492 kb
Host smart-0abc6ad2-219a-494b-b06c-0afe8bd7972c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123116522 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.2123116522
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1822193268
Short name T688
Test name
Test status
Simulation time 214746718 ps
CPU time 6.41 seconds
Started Jul 02 08:13:15 AM PDT 24
Finished Jul 02 08:13:24 AM PDT 24
Peak memory 213132 kb
Host smart-b5aea7f9-18e4-4455-8ac4-df019225e165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822193268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1822193268
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2055416094
Short name T514
Test name
Test status
Simulation time 677426085 ps
CPU time 6.87 seconds
Started Jul 02 08:13:14 AM PDT 24
Finished Jul 02 08:13:23 AM PDT 24
Peak memory 243172 kb
Host smart-228f56b4-cd71-4ab9-b1a5-06a6a1f200bc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055416094 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2055416094
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.2529343023
Short name T77
Test name
Test status
Simulation time 2364210444 ps
CPU time 75.46 seconds
Started Jul 02 08:13:17 AM PDT 24
Finished Jul 02 08:14:35 AM PDT 24
Peak memory 692532 kb
Host smart-91886ad0-1433-445c-afaf-c104c472aa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529343023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.2529343023
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.2912985284
Short name T357
Test name
Test status
Simulation time 3270733668 ps
CPU time 41.63 seconds
Started Jul 02 08:13:12 AM PDT 24
Finished Jul 02 08:13:56 AM PDT 24
Peak memory 583144 kb
Host smart-f3a548f6-3f3f-4eff-9a36-8020f221e22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912985284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.2912985284
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.3849659278
Short name T476
Test name
Test status
Simulation time 238442545 ps
CPU time 0.99 seconds
Started Jul 02 08:13:15 AM PDT 24
Finished Jul 02 08:13:18 AM PDT 24
Peak memory 204364 kb
Host smart-652667bd-39f2-412a-9810-b02251d2fb25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849659278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_f
mt.3849659278
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.1276159080
Short name T991
Test name
Test status
Simulation time 150241115 ps
CPU time 7.9 seconds
Started Jul 02 08:13:11 AM PDT 24
Finished Jul 02 08:13:22 AM PDT 24
Peak memory 227604 kb
Host smart-a2e36fa6-c1a1-40be-9acc-876c07f3937b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276159080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.1276159080
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.2210249244
Short name T908
Test name
Test status
Simulation time 5008777759 ps
CPU time 156.99 seconds
Started Jul 02 08:13:09 AM PDT 24
Finished Jul 02 08:15:48 AM PDT 24
Peak memory 1410176 kb
Host smart-a4f82418-975c-4511-8197-6e97c5137279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210249244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.2210249244
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1738241391
Short name T484
Test name
Test status
Simulation time 548726712 ps
CPU time 22.58 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:13:46 AM PDT 24
Peak memory 204736 kb
Host smart-77a05642-8b75-4b3f-9f2f-03bff7a1a757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738241391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1738241391
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.1947332072
Short name T377
Test name
Test status
Simulation time 5731411722 ps
CPU time 127.21 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:15:30 AM PDT 24
Peak memory 403080 kb
Host smart-ab01cb3b-8df7-492d-b1ec-1620a320d29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947332072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.1947332072
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.403371992
Short name T1376
Test name
Test status
Simulation time 94641300 ps
CPU time 0.67 seconds
Started Jul 02 08:13:15 AM PDT 24
Finished Jul 02 08:13:17 AM PDT 24
Peak memory 204420 kb
Host smart-db46c8be-3c24-4d16-8c88-46c7b30c181a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403371992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.403371992
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.3448613593
Short name T370
Test name
Test status
Simulation time 26779355775 ps
CPU time 344.98 seconds
Started Jul 02 08:13:16 AM PDT 24
Finished Jul 02 08:19:03 AM PDT 24
Peak memory 1852516 kb
Host smart-d88d980a-d999-41b1-a683-29592e6012d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448613593 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.3448613593
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.997373249
Short name T821
Test name
Test status
Simulation time 205911928 ps
CPU time 1.31 seconds
Started Jul 02 08:13:16 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 225984 kb
Host smart-d7f4425b-7c23-411d-b2f5-ec89819d05ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997373249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.997373249
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1347245700
Short name T1473
Test name
Test status
Simulation time 1873224480 ps
CPU time 28.51 seconds
Started Jul 02 08:13:15 AM PDT 24
Finished Jul 02 08:13:45 AM PDT 24
Peak memory 287924 kb
Host smart-e36a77e7-4f3b-4ee4-a09d-47abad988702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347245700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1347245700
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stress_all.3733836310
Short name T104
Test name
Test status
Simulation time 19003949793 ps
CPU time 379.53 seconds
Started Jul 02 08:13:17 AM PDT 24
Finished Jul 02 08:19:39 AM PDT 24
Peak memory 2043560 kb
Host smart-edc99742-fba6-4537-8b95-cca9e06ace9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733836310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stress_all.3733836310
Directory /workspace/39.i2c_host_stress_all/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.228692868
Short name T806
Test name
Test status
Simulation time 1099122544 ps
CPU time 23.68 seconds
Started Jul 02 08:13:16 AM PDT 24
Finished Jul 02 08:13:42 AM PDT 24
Peak memory 213052 kb
Host smart-b6883fb7-c3d8-469f-8091-7f5f45cf9bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228692868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.228692868
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.66359134
Short name T1500
Test name
Test status
Simulation time 2218577627 ps
CPU time 5.7 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:13:28 AM PDT 24
Peak memory 213732 kb
Host smart-69fffe8c-6f0c-4f6d-8e87-6e7e9ceb7cc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66359134 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_bad_addr.66359134
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.2125265158
Short name T1274
Test name
Test status
Simulation time 408538048 ps
CPU time 1.11 seconds
Started Jul 02 08:13:16 AM PDT 24
Finished Jul 02 08:13:19 AM PDT 24
Peak memory 204784 kb
Host smart-115d8253-2650-4685-bc04-2a7193514ee5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125265158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.2125265158
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.34940552
Short name T492
Test name
Test status
Simulation time 161036073 ps
CPU time 1.09 seconds
Started Jul 02 08:13:17 AM PDT 24
Finished Jul 02 08:13:20 AM PDT 24
Peak memory 204584 kb
Host smart-71e4f3e2-820b-4598-b4d6-65a6ef1c134b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34940552 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.i2c_target_fifo_reset_tx.34940552
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.2638003090
Short name T81
Test name
Test status
Simulation time 137380143 ps
CPU time 1.21 seconds
Started Jul 02 08:13:23 AM PDT 24
Finished Jul 02 08:13:26 AM PDT 24
Peak memory 204588 kb
Host smart-a72f3fc7-6ce6-454f-bbcc-8b5369f03474
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638003090 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.2638003090
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.606351269
Short name T820
Test name
Test status
Simulation time 149139109 ps
CPU time 1.28 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:13:24 AM PDT 24
Peak memory 204600 kb
Host smart-f5f5451f-7b12-46d9-ae47-9d654046cdf5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606351269 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.606351269
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_hrst.4145476966
Short name T528
Test name
Test status
Simulation time 340637747 ps
CPU time 2.99 seconds
Started Jul 02 08:13:20 AM PDT 24
Finished Jul 02 08:13:24 AM PDT 24
Peak memory 204784 kb
Host smart-3fe9d7b6-de51-4500-b2e0-2ed145826c0b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145476966 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 39.i2c_target_hrst.4145476966
Directory /workspace/39.i2c_target_hrst/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.2663121304
Short name T143
Test name
Test status
Simulation time 2123566942 ps
CPU time 5.44 seconds
Started Jul 02 08:13:16 AM PDT 24
Finished Jul 02 08:13:24 AM PDT 24
Peak memory 217416 kb
Host smart-a5c0ee4c-a937-4d1e-92fb-e7f0af02be90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663121304 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.2663121304
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.1211504940
Short name T666
Test name
Test status
Simulation time 11377981259 ps
CPU time 64.41 seconds
Started Jul 02 08:13:16 AM PDT 24
Finished Jul 02 08:14:23 AM PDT 24
Peak memory 1247172 kb
Host smart-ebea4198-ac2d-4623-8626-2b6f435d0bda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211504940 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.1211504940
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.723354507
Short name T727
Test name
Test status
Simulation time 782419949 ps
CPU time 13.39 seconds
Started Jul 02 08:13:18 AM PDT 24
Finished Jul 02 08:13:33 AM PDT 24
Peak memory 204808 kb
Host smart-4764d358-4fee-403f-8330-308035519f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723354507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_tar
get_smoke.723354507
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.461520365
Short name T754
Test name
Test status
Simulation time 5812924314 ps
CPU time 9.95 seconds
Started Jul 02 08:13:19 AM PDT 24
Finished Jul 02 08:13:31 AM PDT 24
Peak memory 211000 kb
Host smart-7930d59c-545a-459f-b427-4988d29621cb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461520365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.461520365
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.3897535495
Short name T1370
Test name
Test status
Simulation time 52457879359 ps
CPU time 12.14 seconds
Started Jul 02 08:13:17 AM PDT 24
Finished Jul 02 08:13:31 AM PDT 24
Peak memory 298392 kb
Host smart-2ef8197c-5fab-40d4-b63f-1c09ac93d06c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897535495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.3897535495
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.2536923616
Short name T966
Test name
Test status
Simulation time 39665680914 ps
CPU time 223.56 seconds
Started Jul 02 08:13:17 AM PDT 24
Finished Jul 02 08:17:03 AM PDT 24
Peak memory 2107612 kb
Host smart-ad2401ca-e415-48d7-bd1c-4751f6c8b48b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536923616 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.2536923616
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3681318514
Short name T1277
Test name
Test status
Simulation time 9743491248 ps
CPU time 7 seconds
Started Jul 02 08:13:17 AM PDT 24
Finished Jul 02 08:13:26 AM PDT 24
Peak memory 213120 kb
Host smart-6e726e82-a2ac-4898-aec3-5af159f5b3de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681318514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3681318514
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.1185367175
Short name T843
Test name
Test status
Simulation time 157225487 ps
CPU time 3.37 seconds
Started Jul 02 08:13:24 AM PDT 24
Finished Jul 02 08:13:28 AM PDT 24
Peak memory 204780 kb
Host smart-2572870c-88a1-4587-883d-fb9926760cbd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185367175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.1185367175
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.956029943
Short name T1467
Test name
Test status
Simulation time 26811208 ps
CPU time 0.64 seconds
Started Jul 02 08:09:20 AM PDT 24
Finished Jul 02 08:09:23 AM PDT 24
Peak memory 204372 kb
Host smart-eed25c3f-723e-471e-88d2-c4678d27f4c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956029943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.956029943
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.119951031
Short name T639
Test name
Test status
Simulation time 149453195 ps
CPU time 1.59 seconds
Started Jul 02 08:09:18 AM PDT 24
Finished Jul 02 08:09:22 AM PDT 24
Peak memory 213076 kb
Host smart-a2ff4eab-9809-48fa-9119-69129a0ad87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119951031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.119951031
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.4067229469
Short name T1327
Test name
Test status
Simulation time 394191692 ps
CPU time 20.39 seconds
Started Jul 02 08:09:14 AM PDT 24
Finished Jul 02 08:09:37 AM PDT 24
Peak memory 283628 kb
Host smart-d9ff8088-4156-4852-b2b4-938a6247f285
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067229469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.4067229469
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3697990334
Short name T1472
Test name
Test status
Simulation time 2373044994 ps
CPU time 164.74 seconds
Started Jul 02 08:09:13 AM PDT 24
Finished Jul 02 08:12:00 AM PDT 24
Peak memory 765468 kb
Host smart-3fad0748-a432-450d-9476-eb3d3858581a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697990334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3697990334
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.964350990
Short name T1443
Test name
Test status
Simulation time 9551353648 ps
CPU time 158.7 seconds
Started Jul 02 08:09:16 AM PDT 24
Finished Jul 02 08:11:56 AM PDT 24
Peak memory 730540 kb
Host smart-4f951b32-1b66-4be5-bf8b-b19304de1c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964350990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.964350990
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.3436800242
Short name T1312
Test name
Test status
Simulation time 96699691 ps
CPU time 0.97 seconds
Started Jul 02 08:09:12 AM PDT 24
Finished Jul 02 08:09:15 AM PDT 24
Peak memory 204380 kb
Host smart-e94f0ad8-c7bd-4232-9191-03d0ba835a40
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436800242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.3436800242
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.2828590024
Short name T998
Test name
Test status
Simulation time 3966786026 ps
CPU time 4.96 seconds
Started Jul 02 08:09:14 AM PDT 24
Finished Jul 02 08:09:21 AM PDT 24
Peak memory 243028 kb
Host smart-332d0f22-0852-4ccd-b98c-cc871bcfd9ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828590024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
2828590024
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.312825113
Short name T957
Test name
Test status
Simulation time 3402657462 ps
CPU time 85.95 seconds
Started Jul 02 08:09:15 AM PDT 24
Finished Jul 02 08:10:43 AM PDT 24
Peak memory 949552 kb
Host smart-1c7c6ac9-e3f2-42eb-98d8-5a181d85bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312825113 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.312825113
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.2875844264
Short name T483
Test name
Test status
Simulation time 510842791 ps
CPU time 8 seconds
Started Jul 02 08:09:16 AM PDT 24
Finished Jul 02 08:09:26 AM PDT 24
Peak memory 204780 kb
Host smart-ef1a7eeb-1756-4384-b2ab-955a2a162970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875844264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.2875844264
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.590272586
Short name T332
Test name
Test status
Simulation time 6531205650 ps
CPU time 64.4 seconds
Started Jul 02 08:09:19 AM PDT 24
Finished Jul 02 08:10:26 AM PDT 24
Peak memory 305072 kb
Host smart-d8fe1338-c8e7-44fc-aa2a-9963a5d07d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590272586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.590272586
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.3289500623
Short name T135
Test name
Test status
Simulation time 54897048 ps
CPU time 0.74 seconds
Started Jul 02 08:09:11 AM PDT 24
Finished Jul 02 08:09:15 AM PDT 24
Peak memory 204500 kb
Host smart-246cd7ab-3ee0-4efb-865c-e1ca947f67ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289500623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.3289500623
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.3262843797
Short name T1113
Test name
Test status
Simulation time 8089550529 ps
CPU time 14.54 seconds
Started Jul 02 08:09:15 AM PDT 24
Finished Jul 02 08:09:31 AM PDT 24
Peak memory 242888 kb
Host smart-f6967946-de09-4195-b262-94024fd7621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262843797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.3262843797
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.1902847785
Short name T111
Test name
Test status
Simulation time 137872516 ps
CPU time 2.34 seconds
Started Jul 02 08:09:13 AM PDT 24
Finished Jul 02 08:09:17 AM PDT 24
Peak memory 205340 kb
Host smart-48ec814e-23d3-4074-8eea-9c895f7d5693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902847785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.1902847785
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.2838337994
Short name T1462
Test name
Test status
Simulation time 1437550784 ps
CPU time 21.86 seconds
Started Jul 02 08:09:14 AM PDT 24
Finished Jul 02 08:09:38 AM PDT 24
Peak memory 285460 kb
Host smart-12b73a63-4c00-4443-b036-ce1557f532f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838337994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.2838337994
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.3745260590
Short name T278
Test name
Test status
Simulation time 21523421320 ps
CPU time 887.08 seconds
Started Jul 02 08:09:19 AM PDT 24
Finished Jul 02 08:24:09 AM PDT 24
Peak memory 1854188 kb
Host smart-06bee150-c7b4-4356-a89d-9d7179261aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745260590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.3745260590
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.862496939
Short name T347
Test name
Test status
Simulation time 12852891210 ps
CPU time 37.15 seconds
Started Jul 02 08:09:15 AM PDT 24
Finished Jul 02 08:09:55 AM PDT 24
Peak memory 221268 kb
Host smart-a4f9e216-a185-4be0-8d33-7b3e4d982829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862496939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.862496939
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.2269129305
Short name T177
Test name
Test status
Simulation time 62363064 ps
CPU time 0.93 seconds
Started Jul 02 08:09:18 AM PDT 24
Finished Jul 02 08:09:21 AM PDT 24
Peak memory 223196 kb
Host smart-31316b88-0331-4b1a-a01a-5df70a809124
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269129305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.2269129305
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.1143750398
Short name T1346
Test name
Test status
Simulation time 1480569586 ps
CPU time 4.29 seconds
Started Jul 02 08:09:16 AM PDT 24
Finished Jul 02 08:09:22 AM PDT 24
Peak memory 213036 kb
Host smart-f498b9aa-6b30-4b9c-b472-a408636710fa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143750398 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.1143750398
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.4149288014
Short name T696
Test name
Test status
Simulation time 233478393 ps
CPU time 1.23 seconds
Started Jul 02 08:09:17 AM PDT 24
Finished Jul 02 08:09:20 AM PDT 24
Peak memory 212816 kb
Host smart-f9089d19-f9fa-41bc-84c6-62c55b332cc3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149288014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_fifo_reset_acq.4149288014
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1803308973
Short name T1092
Test name
Test status
Simulation time 574740769 ps
CPU time 1.34 seconds
Started Jul 02 08:09:18 AM PDT 24
Finished Jul 02 08:09:22 AM PDT 24
Peak memory 204756 kb
Host smart-a28d152c-ee69-46e7-b967-57abed6c1b86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803308973 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1803308973
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.120113734
Short name T1401
Test name
Test status
Simulation time 332034461 ps
CPU time 2.06 seconds
Started Jul 02 08:09:19 AM PDT 24
Finished Jul 02 08:09:23 AM PDT 24
Peak memory 204752 kb
Host smart-4d3e8aeb-9d21-47ea-a559-b4c1fdb9d6c1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120113734 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.120113734
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.696803454
Short name T549
Test name
Test status
Simulation time 644875802 ps
CPU time 1.31 seconds
Started Jul 02 08:09:19 AM PDT 24
Finished Jul 02 08:09:23 AM PDT 24
Peak memory 204564 kb
Host smart-6d03b6bc-47d8-4953-8b59-ef5c59ec640e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696803454 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.696803454
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.590336513
Short name T769
Test name
Test status
Simulation time 772511985 ps
CPU time 3.61 seconds
Started Jul 02 08:09:22 AM PDT 24
Finished Jul 02 08:09:28 AM PDT 24
Peak memory 204752 kb
Host smart-4bbde274-7c28-4f62-8db6-3367f770ccd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590336513 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.590336513
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.2793933981
Short name T79
Test name
Test status
Simulation time 1049802019 ps
CPU time 6.16 seconds
Started Jul 02 08:09:23 AM PDT 24
Finished Jul 02 08:09:31 AM PDT 24
Peak memory 209116 kb
Host smart-ec5a8f44-307d-4aef-8a47-f28ffe6263b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793933981 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_intr_smoke.2793933981
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.2987381404
Short name T321
Test name
Test status
Simulation time 7514056974 ps
CPU time 8.05 seconds
Started Jul 02 08:09:19 AM PDT 24
Finished Jul 02 08:09:30 AM PDT 24
Peak memory 407544 kb
Host smart-f43554a7-01c2-46bf-8e8a-802f7ae53dc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987381404 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.2987381404
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.3779417744
Short name T950
Test name
Test status
Simulation time 1520324649 ps
CPU time 56.71 seconds
Started Jul 02 08:09:17 AM PDT 24
Finished Jul 02 08:10:15 AM PDT 24
Peak memory 204736 kb
Host smart-6777495a-1fa2-481f-bd2c-22f1b8ef4048
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779417744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_tar
get_smoke.3779417744
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.1547403220
Short name T780
Test name
Test status
Simulation time 5522429318 ps
CPU time 54.22 seconds
Started Jul 02 08:09:17 AM PDT 24
Finished Jul 02 08:10:13 AM PDT 24
Peak memory 205640 kb
Host smart-d1e0a9e1-91a6-41cc-b115-14f896cc710d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547403220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_rd.1547403220
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.1073600561
Short name T1498
Test name
Test status
Simulation time 12777824207 ps
CPU time 7.22 seconds
Started Jul 02 08:09:18 AM PDT 24
Finished Jul 02 08:09:28 AM PDT 24
Peak memory 205112 kb
Host smart-2abff54b-779d-41c9-84f0-2e676c455570
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073600561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.1073600561
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.2717025799
Short name T1416
Test name
Test status
Simulation time 31029549737 ps
CPU time 1575.03 seconds
Started Jul 02 08:09:18 AM PDT 24
Finished Jul 02 08:35:36 AM PDT 24
Peak memory 6641916 kb
Host smart-44df0cc3-fd7d-418a-a45b-a3d57a73eec3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717025799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_t
arget_stretch.2717025799
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.657620851
Short name T1175
Test name
Test status
Simulation time 5598057925 ps
CPU time 7.32 seconds
Started Jul 02 08:09:18 AM PDT 24
Finished Jul 02 08:09:28 AM PDT 24
Peak memory 221236 kb
Host smart-c18d873c-f7a0-4be0-8095-cd8c62f1b110
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657620851 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 4.i2c_target_timeout.657620851
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.1399628536
Short name T630
Test name
Test status
Simulation time 415281989 ps
CPU time 5.32 seconds
Started Jul 02 08:09:16 AM PDT 24
Finished Jul 02 08:09:23 AM PDT 24
Peak memory 204788 kb
Host smart-0b4b5b16-718b-483e-b510-3411bd1b6094
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399628536 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.1399628536
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2022531630
Short name T1264
Test name
Test status
Simulation time 17922787 ps
CPU time 0.64 seconds
Started Jul 02 08:13:31 AM PDT 24
Finished Jul 02 08:13:34 AM PDT 24
Peak memory 204444 kb
Host smart-552a8553-a4bf-4e1f-94e4-96a968c32d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022531630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2022531630
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.645110024
Short name T1300
Test name
Test status
Simulation time 1388345940 ps
CPU time 6.81 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:13:36 AM PDT 24
Peak memory 232992 kb
Host smart-0402a71c-5525-4414-af68-276330e2317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645110024 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.645110024
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3268508005
Short name T383
Test name
Test status
Simulation time 754883373 ps
CPU time 18.77 seconds
Started Jul 02 08:13:22 AM PDT 24
Finished Jul 02 08:13:42 AM PDT 24
Peak memory 284368 kb
Host smart-64c6e172-8a66-491f-9375-0e94e8206874
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268508005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3268508005
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.734699999
Short name T1230
Test name
Test status
Simulation time 2410477666 ps
CPU time 75.61 seconds
Started Jul 02 08:13:23 AM PDT 24
Finished Jul 02 08:14:40 AM PDT 24
Peak memory 780520 kb
Host smart-67ee122c-b828-47b3-9102-f9b53f2bf64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734699999 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.734699999
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.3716361345
Short name T1411
Test name
Test status
Simulation time 2607434510 ps
CPU time 82.25 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:14:44 AM PDT 24
Peak memory 828276 kb
Host smart-4d67f3d7-2026-4b89-a3b0-393e8d683dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716361345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.3716361345
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.1752546095
Short name T1007
Test name
Test status
Simulation time 111598327 ps
CPU time 0.93 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:13:23 AM PDT 24
Peak memory 204452 kb
Host smart-32385518-0591-4c98-8346-00588d053e6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752546095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.1752546095
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.1959211858
Short name T1069
Test name
Test status
Simulation time 797081639 ps
CPU time 3.57 seconds
Started Jul 02 08:13:22 AM PDT 24
Finished Jul 02 08:13:27 AM PDT 24
Peak memory 204840 kb
Host smart-26ca428c-b522-4fa9-81fd-be6d43eb109b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959211858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.1959211858
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.2288176135
Short name T486
Test name
Test status
Simulation time 11638984750 ps
CPU time 155.78 seconds
Started Jul 02 08:13:22 AM PDT 24
Finished Jul 02 08:16:00 AM PDT 24
Peak memory 816088 kb
Host smart-acb8c15e-ec18-476f-8d72-72809539cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288176135 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.2288176135
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.3233983702
Short name T807
Test name
Test status
Simulation time 2370771583 ps
CPU time 4.66 seconds
Started Jul 02 08:13:26 AM PDT 24
Finished Jul 02 08:13:32 AM PDT 24
Peak memory 204904 kb
Host smart-0aa63ed5-632e-4484-a258-6fe358c2e05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233983702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.3233983702
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.3637333050
Short name T1337
Test name
Test status
Simulation time 1951623030 ps
CPU time 35.23 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:14:04 AM PDT 24
Peak memory 350924 kb
Host smart-d49462cb-2eb4-446a-9559-12ce7e0699dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637333050 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.3637333050
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.952080496
Short name T1460
Test name
Test status
Simulation time 27093367 ps
CPU time 0.64 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:13:24 AM PDT 24
Peak memory 204540 kb
Host smart-d516e967-9fd7-4a47-91f2-c4e2381bc5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952080496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.952080496
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.1230361778
Short name T303
Test name
Test status
Simulation time 6156976692 ps
CPU time 62.24 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:14:24 AM PDT 24
Peak memory 221212 kb
Host smart-9661a991-aa45-4171-b06f-00230e84d604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230361778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.1230361778
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.553547638
Short name T10
Test name
Test status
Simulation time 6397770077 ps
CPU time 20.24 seconds
Started Jul 02 08:13:21 AM PDT 24
Finished Jul 02 08:13:43 AM PDT 24
Peak memory 204816 kb
Host smart-dce696b4-8a2f-4f8f-906f-583c85fd8218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553547638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.553547638
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.3299332003
Short name T537
Test name
Test status
Simulation time 5075084602 ps
CPU time 63.76 seconds
Started Jul 02 08:13:20 AM PDT 24
Finished Jul 02 08:14:25 AM PDT 24
Peak memory 311536 kb
Host smart-e8bfc084-d8a3-4fa4-989a-9f120c5b759c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299332003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.3299332003
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.1776333654
Short name T1021
Test name
Test status
Simulation time 1436826793 ps
CPU time 6.2 seconds
Started Jul 02 08:13:26 AM PDT 24
Finished Jul 02 08:13:33 AM PDT 24
Peak memory 220184 kb
Host smart-96341513-3ae8-4741-bc04-d6867cfc20f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776333654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.1776333654
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.2845493817
Short name T882
Test name
Test status
Simulation time 3112341726 ps
CPU time 4.02 seconds
Started Jul 02 08:13:25 AM PDT 24
Finished Jul 02 08:13:30 AM PDT 24
Peak memory 204932 kb
Host smart-e868bc96-894a-4d41-aedc-8d5760812fe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845493817 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.i2c_target_bad_addr.2845493817
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.934068719
Short name T825
Test name
Test status
Simulation time 253753586 ps
CPU time 1.13 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:13:31 AM PDT 24
Peak memory 204520 kb
Host smart-6d86a5fb-7e7c-47bf-b736-bd8f6e31331a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934068719 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 40.i2c_target_fifo_reset_acq.934068719
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.746567953
Short name T84
Test name
Test status
Simulation time 228979184 ps
CPU time 0.84 seconds
Started Jul 02 08:13:27 AM PDT 24
Finished Jul 02 08:13:29 AM PDT 24
Peak memory 204496 kb
Host smart-295e95f3-0012-4cf9-9967-7af4e3f73d28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746567953 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.i2c_target_fifo_reset_tx.746567953
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.3027497143
Short name T815
Test name
Test status
Simulation time 4872027184 ps
CPU time 3.09 seconds
Started Jul 02 08:13:27 AM PDT 24
Finished Jul 02 08:13:31 AM PDT 24
Peak memory 204956 kb
Host smart-abd98252-2767-4cb8-bb6e-75eb372f6ec1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027497143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.3027497143
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.1515719869
Short name T1269
Test name
Test status
Simulation time 127105615 ps
CPU time 1.14 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:13:31 AM PDT 24
Peak memory 204588 kb
Host smart-b2bd0262-9556-46aa-bbc0-31f5a82936b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515719869 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.1515719869
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.1130991066
Short name T422
Test name
Test status
Simulation time 1072969523 ps
CPU time 3.91 seconds
Started Jul 02 08:13:26 AM PDT 24
Finished Jul 02 08:13:31 AM PDT 24
Peak memory 204800 kb
Host smart-27b3dd28-e8de-4f2f-9b61-5a279cc6ae76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130991066 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.1130991066
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.1372796275
Short name T575
Test name
Test status
Simulation time 4402850159 ps
CPU time 6.4 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:13:36 AM PDT 24
Peak memory 218452 kb
Host smart-02a8567f-33b1-46a5-9e22-5c176b03e26c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372796275 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.1372796275
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.794844636
Short name T704
Test name
Test status
Simulation time 10615040535 ps
CPU time 25.4 seconds
Started Jul 02 08:13:29 AM PDT 24
Finished Jul 02 08:13:56 AM PDT 24
Peak memory 737548 kb
Host smart-a3d40365-7cb5-4aef-a873-f6026430f42b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794844636 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.794844636
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.970603752
Short name T435
Test name
Test status
Simulation time 1028651023 ps
CPU time 40.33 seconds
Started Jul 02 08:13:27 AM PDT 24
Finished Jul 02 08:14:08 AM PDT 24
Peak memory 204832 kb
Host smart-82412189-700a-4957-8c48-f355ff2074be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970603752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.970603752
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.1260071303
Short name T331
Test name
Test status
Simulation time 601700210 ps
CPU time 4.62 seconds
Started Jul 02 08:13:26 AM PDT 24
Finished Jul 02 08:13:32 AM PDT 24
Peak memory 204824 kb
Host smart-3106d4fd-8172-458b-baa9-b90cbb972ef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260071303 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.1260071303
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.4077848775
Short name T714
Test name
Test status
Simulation time 36466069366 ps
CPU time 106.72 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:15:16 AM PDT 24
Peak memory 1653076 kb
Host smart-55b82dc0-a6ea-42fd-83c1-6f097881749d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077848775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.4077848775
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.3494223917
Short name T1222
Test name
Test status
Simulation time 26634486945 ps
CPU time 399.42 seconds
Started Jul 02 08:13:25 AM PDT 24
Finished Jul 02 08:20:05 AM PDT 24
Peak memory 1496536 kb
Host smart-d3754591-8852-48e2-b699-2ebc77770cac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494223917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.3494223917
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1913702931
Short name T1119
Test name
Test status
Simulation time 4023459204 ps
CPU time 6.32 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:13:36 AM PDT 24
Peak memory 213912 kb
Host smart-cdac42d6-d5ee-4b6d-b5ec-5fd82e309e53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913702931 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1913702931
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.1020720719
Short name T374
Test name
Test status
Simulation time 715128862 ps
CPU time 8.78 seconds
Started Jul 02 08:13:30 AM PDT 24
Finished Jul 02 08:13:40 AM PDT 24
Peak memory 204776 kb
Host smart-e208de8b-7052-4c2d-b87b-5bbcd66db6c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020720719 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.1020720719
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.451576992
Short name T473
Test name
Test status
Simulation time 23670809 ps
CPU time 0.63 seconds
Started Jul 02 08:13:36 AM PDT 24
Finished Jul 02 08:13:39 AM PDT 24
Peak memory 204416 kb
Host smart-10a7ae76-bfd5-4fb8-b080-963f0202fb81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451576992 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.451576992
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.3342780887
Short name T868
Test name
Test status
Simulation time 222316896 ps
CPU time 1.89 seconds
Started Jul 02 08:13:33 AM PDT 24
Finished Jul 02 08:13:36 AM PDT 24
Peak memory 213056 kb
Host smart-6a657c8c-f14b-453b-8e1a-10ba7aa941e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342780887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.3342780887
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.441986493
Short name T689
Test name
Test status
Simulation time 356188576 ps
CPU time 6.85 seconds
Started Jul 02 08:13:33 AM PDT 24
Finished Jul 02 08:13:41 AM PDT 24
Peak memory 227104 kb
Host smart-159f53a9-47ad-4ca3-9c55-fe0770dd68b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441986493 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_empt
y.441986493
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.3683462906
Short name T918
Test name
Test status
Simulation time 2088633435 ps
CPU time 98.62 seconds
Started Jul 02 08:13:30 AM PDT 24
Finished Jul 02 08:15:11 AM PDT 24
Peak memory 213020 kb
Host smart-5ffd41f5-1c90-486d-9194-e7a768e49545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683462906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.3683462906
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.1665302229
Short name T620
Test name
Test status
Simulation time 2601976127 ps
CPU time 78.23 seconds
Started Jul 02 08:13:31 AM PDT 24
Finished Jul 02 08:14:51 AM PDT 24
Peak memory 798680 kb
Host smart-42ee15c6-a6aa-4065-a86b-06fdde5cf4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665302229 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.1665302229
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.1486117927
Short name T1426
Test name
Test status
Simulation time 114089549 ps
CPU time 1 seconds
Started Jul 02 08:13:33 AM PDT 24
Finished Jul 02 08:13:36 AM PDT 24
Peak memory 204432 kb
Host smart-ff2e0023-6681-474f-9ecc-55c0e1faf5cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486117927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.1486117927
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.1492697635
Short name T971
Test name
Test status
Simulation time 281564964 ps
CPU time 6.57 seconds
Started Jul 02 08:13:31 AM PDT 24
Finished Jul 02 08:13:40 AM PDT 24
Peak memory 204720 kb
Host smart-a5076a50-29ac-40bd-bb4b-ad0ad76ba327
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492697635 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx
.1492697635
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1824531562
Short name T510
Test name
Test status
Simulation time 5270543615 ps
CPU time 391.92 seconds
Started Jul 02 08:13:34 AM PDT 24
Finished Jul 02 08:20:08 AM PDT 24
Peak memory 1481520 kb
Host smart-7aa28ccd-f30a-4851-85d6-e363b89b03c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824531562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1824531562
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.2738266258
Short name T447
Test name
Test status
Simulation time 2220436782 ps
CPU time 21.76 seconds
Started Jul 02 08:13:36 AM PDT 24
Finished Jul 02 08:13:59 AM PDT 24
Peak memory 204892 kb
Host smart-40b0c94d-eca2-4a84-8fb5-ed2e0ae47d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738266258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.2738266258
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.1980269452
Short name T1237
Test name
Test status
Simulation time 8553147719 ps
CPU time 75.46 seconds
Started Jul 02 08:13:39 AM PDT 24
Finished Jul 02 08:14:55 AM PDT 24
Peak memory 310596 kb
Host smart-ae93e330-a495-4050-a7b2-5abf864f812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980269452 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.1980269452
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3351345514
Short name T534
Test name
Test status
Simulation time 26343020 ps
CPU time 0.69 seconds
Started Jul 02 08:13:31 AM PDT 24
Finished Jul 02 08:13:34 AM PDT 24
Peak memory 204516 kb
Host smart-9c40918a-8739-4663-a94d-456cfd725146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351345514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3351345514
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3770168531
Short name T548
Test name
Test status
Simulation time 6787652643 ps
CPU time 172.81 seconds
Started Jul 02 08:13:30 AM PDT 24
Finished Jul 02 08:16:25 AM PDT 24
Peak memory 677644 kb
Host smart-6d522f50-eb64-48d5-b743-5c4216eb2e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770168531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3770168531
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.2072425228
Short name T467
Test name
Test status
Simulation time 23200956649 ps
CPU time 451.22 seconds
Started Jul 02 08:13:32 AM PDT 24
Finished Jul 02 08:21:05 AM PDT 24
Peak memory 204800 kb
Host smart-bb67c3dd-3533-43d1-92a3-ac20fbd2cbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072425228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.2072425228
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.1415843765
Short name T59
Test name
Test status
Simulation time 1357828701 ps
CPU time 25.61 seconds
Started Jul 02 08:13:29 AM PDT 24
Finished Jul 02 08:13:57 AM PDT 24
Peak memory 365280 kb
Host smart-8d1f0b74-01a0-402a-98bf-fc2af8c929f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415843765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.1415843765
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.1257337898
Short name T41
Test name
Test status
Simulation time 18343471788 ps
CPU time 549.35 seconds
Started Jul 02 08:13:28 AM PDT 24
Finished Jul 02 08:22:39 AM PDT 24
Peak memory 1803576 kb
Host smart-04c0c18b-d977-4085-ba32-82b98dc35165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257337898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.1257337898
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.1959327672
Short name T140
Test name
Test status
Simulation time 2870918746 ps
CPU time 31.84 seconds
Started Jul 02 08:13:33 AM PDT 24
Finished Jul 02 08:14:07 AM PDT 24
Peak memory 213036 kb
Host smart-f293e347-cb7d-4944-8980-5cdd277b904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959327672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.1959327672
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.1178750833
Short name T329
Test name
Test status
Simulation time 3547615540 ps
CPU time 4.45 seconds
Started Jul 02 08:13:37 AM PDT 24
Finished Jul 02 08:13:43 AM PDT 24
Peak memory 213312 kb
Host smart-cf89d4a6-7ffd-4dcf-8adc-bba9e5bb6cc0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178750833 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.1178750833
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.3395555882
Short name T915
Test name
Test status
Simulation time 221968718 ps
CPU time 1.37 seconds
Started Jul 02 08:13:31 AM PDT 24
Finished Jul 02 08:13:34 AM PDT 24
Peak memory 204768 kb
Host smart-b718c239-3d1e-4102-99ee-40af6e346308
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395555882 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_fifo_reset_acq.3395555882
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.1240790603
Short name T1431
Test name
Test status
Simulation time 474997575 ps
CPU time 1.06 seconds
Started Jul 02 08:13:33 AM PDT 24
Finished Jul 02 08:13:36 AM PDT 24
Peak memory 204568 kb
Host smart-c8635ad7-6408-4fe1-ac76-1b77a187e2a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240790603 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.1240790603
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.1800762690
Short name T742
Test name
Test status
Simulation time 442464149 ps
CPU time 2.67 seconds
Started Jul 02 08:13:38 AM PDT 24
Finished Jul 02 08:13:42 AM PDT 24
Peak memory 204772 kb
Host smart-2fa48f98-6bb6-4273-b332-7acbef5cdf20
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800762690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.1800762690
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.3172145384
Short name T436
Test name
Test status
Simulation time 501126703 ps
CPU time 1.26 seconds
Started Jul 02 08:13:35 AM PDT 24
Finished Jul 02 08:13:37 AM PDT 24
Peak memory 204620 kb
Host smart-19e586f3-a5ca-4e91-9b63-791ce79ac9b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172145384 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.3172145384
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2946395631
Short name T1458
Test name
Test status
Simulation time 314287954 ps
CPU time 2.58 seconds
Started Jul 02 08:13:37 AM PDT 24
Finished Jul 02 08:13:41 AM PDT 24
Peak memory 205008 kb
Host smart-b471b386-c6fb-4ccd-bdd4-6d9c471af5d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946395631 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2946395631
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.620826007
Short name T1151
Test name
Test status
Simulation time 2111699436 ps
CPU time 6.03 seconds
Started Jul 02 08:13:33 AM PDT 24
Finished Jul 02 08:13:41 AM PDT 24
Peak memory 209720 kb
Host smart-6f5003a6-92cc-4a6d-8a39-94929c2285e7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620826007 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_intr_smoke.620826007
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.1939406755
Short name T803
Test name
Test status
Simulation time 5552050355 ps
CPU time 59.38 seconds
Started Jul 02 08:13:29 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 1499348 kb
Host smart-701fbf31-52ae-4568-8021-17a359e8622f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939406755 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.1939406755
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.149946163
Short name T1202
Test name
Test status
Simulation time 1279579664 ps
CPU time 16.42 seconds
Started Jul 02 08:13:34 AM PDT 24
Finished Jul 02 08:13:52 AM PDT 24
Peak memory 204832 kb
Host smart-fb83eb0e-f008-43b7-99c2-59b07616d146
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149946163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_tar
get_smoke.149946163
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.3777763664
Short name T1217
Test name
Test status
Simulation time 15345833757 ps
CPU time 21.55 seconds
Started Jul 02 08:13:34 AM PDT 24
Finished Jul 02 08:13:57 AM PDT 24
Peak memory 226464 kb
Host smart-491e89d1-06c7-4f34-a161-3e3a96ee36f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777763664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.3777763664
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.3337458404
Short name T497
Test name
Test status
Simulation time 27530657530 ps
CPU time 132.23 seconds
Started Jul 02 08:13:31 AM PDT 24
Finished Jul 02 08:15:46 AM PDT 24
Peak memory 1949892 kb
Host smart-cbe6a92b-073c-403f-a90f-17585cd89042
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337458404 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.3337458404
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.1904242868
Short name T574
Test name
Test status
Simulation time 5327574546 ps
CPU time 141.65 seconds
Started Jul 02 08:13:32 AM PDT 24
Finished Jul 02 08:15:56 AM PDT 24
Peak memory 1375040 kb
Host smart-ec22aa9d-25bd-4226-b246-1cfeb0eba084
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904242868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.1904242868
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3284751883
Short name T1441
Test name
Test status
Simulation time 2902952321 ps
CPU time 7.44 seconds
Started Jul 02 08:13:29 AM PDT 24
Finished Jul 02 08:13:38 AM PDT 24
Peak memory 212144 kb
Host smart-668d0822-015e-4760-8689-89230c68b5b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284751883 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3284751883
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.444325937
Short name T933
Test name
Test status
Simulation time 137799107 ps
CPU time 2 seconds
Started Jul 02 08:13:37 AM PDT 24
Finished Jul 02 08:13:41 AM PDT 24
Peak memory 204796 kb
Host smart-5d37b75d-2354-4e7e-ae38-5233e0736079
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444325937 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.444325937
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3508868031
Short name T822
Test name
Test status
Simulation time 22984131 ps
CPU time 0.6 seconds
Started Jul 02 08:13:40 AM PDT 24
Finished Jul 02 08:13:41 AM PDT 24
Peak memory 204460 kb
Host smart-4788dc56-df60-4e73-a232-cde183f2a197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508868031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3508868031
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.2789023265
Short name T1449
Test name
Test status
Simulation time 387426309 ps
CPU time 16.28 seconds
Started Jul 02 08:13:36 AM PDT 24
Finished Jul 02 08:13:54 AM PDT 24
Peak memory 251376 kb
Host smart-ae430610-0847-41d4-993a-a971bdf8957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789023265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.2789023265
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.680456754
Short name T1147
Test name
Test status
Simulation time 547461274 ps
CPU time 9.36 seconds
Started Jul 02 08:13:36 AM PDT 24
Finished Jul 02 08:13:47 AM PDT 24
Peak memory 322372 kb
Host smart-5c723bcc-48d3-406c-aa2f-6cc71d4ddda2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680456754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.680456754
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.1611545984
Short name T1050
Test name
Test status
Simulation time 3726146676 ps
CPU time 127.69 seconds
Started Jul 02 08:13:37 AM PDT 24
Finished Jul 02 08:15:46 AM PDT 24
Peak memory 659280 kb
Host smart-4b0d7a22-10a0-4889-90c0-b271cd710069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611545984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.1611545984
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.1787731984
Short name T628
Test name
Test status
Simulation time 9481514710 ps
CPU time 61.93 seconds
Started Jul 02 08:13:35 AM PDT 24
Finished Jul 02 08:14:38 AM PDT 24
Peak memory 697616 kb
Host smart-0a92e8e8-41fc-4ba2-a289-dedbee5ea08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787731984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.1787731984
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.2610356126
Short name T1265
Test name
Test status
Simulation time 323919871 ps
CPU time 0.86 seconds
Started Jul 02 08:13:37 AM PDT 24
Finished Jul 02 08:13:39 AM PDT 24
Peak memory 204420 kb
Host smart-622f2f5d-00ca-48c2-af83-159d007c0357
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610356126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.2610356126
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.1552692736
Short name T1239
Test name
Test status
Simulation time 155168462 ps
CPU time 8.16 seconds
Started Jul 02 08:13:39 AM PDT 24
Finished Jul 02 08:13:48 AM PDT 24
Peak memory 204784 kb
Host smart-86757ef7-355a-4e55-bc44-8083f7694532
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552692736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.1552692736
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.1718067924
Short name T853
Test name
Test status
Simulation time 3281882413 ps
CPU time 196.75 seconds
Started Jul 02 08:13:34 AM PDT 24
Finished Jul 02 08:16:52 AM PDT 24
Peak memory 949744 kb
Host smart-af8b3dfa-5a71-424d-8054-05531b1fdb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718067924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.1718067924
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.777656425
Short name T1273
Test name
Test status
Simulation time 453810700 ps
CPU time 5.69 seconds
Started Jul 02 08:13:43 AM PDT 24
Finished Jul 02 08:13:50 AM PDT 24
Peak memory 204772 kb
Host smart-09734766-46a5-4c30-bdf7-05d1e32249d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777656425 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.777656425
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.4017986412
Short name T1345
Test name
Test status
Simulation time 2610543642 ps
CPU time 59.63 seconds
Started Jul 02 08:13:44 AM PDT 24
Finished Jul 02 08:14:45 AM PDT 24
Peak memory 307376 kb
Host smart-90e0966e-f6df-4cbf-bce8-74b14d0a1741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017986412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.4017986412
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.3319857562
Short name T1145
Test name
Test status
Simulation time 17502567 ps
CPU time 0.67 seconds
Started Jul 02 08:13:40 AM PDT 24
Finished Jul 02 08:13:42 AM PDT 24
Peak memory 204516 kb
Host smart-3d7f5291-a717-4f01-b92d-8c4bfaf29d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319857562 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.3319857562
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.3621524973
Short name T8
Test name
Test status
Simulation time 900212865 ps
CPU time 14.28 seconds
Started Jul 02 08:13:35 AM PDT 24
Finished Jul 02 08:13:50 AM PDT 24
Peak memory 279624 kb
Host smart-c7f410d1-4454-4a1b-8e28-48c04d075b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621524973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.3621524973
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.2761221767
Short name T1073
Test name
Test status
Simulation time 438390495 ps
CPU time 1.11 seconds
Started Jul 02 08:13:37 AM PDT 24
Finished Jul 02 08:13:40 AM PDT 24
Peak memory 204492 kb
Host smart-d6712115-8ce8-471d-ad79-be9effa25c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761221767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.2761221767
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3663453744
Short name T1372
Test name
Test status
Simulation time 36625976066 ps
CPU time 28.34 seconds
Started Jul 02 08:13:38 AM PDT 24
Finished Jul 02 08:14:07 AM PDT 24
Peak memory 340504 kb
Host smart-6b4895d6-047f-4a34-80f6-47dfbf1e16be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663453744 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3663453744
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.2048363657
Short name T102
Test name
Test status
Simulation time 9017455816 ps
CPU time 291.26 seconds
Started Jul 02 08:13:37 AM PDT 24
Finished Jul 02 08:18:30 AM PDT 24
Peak memory 1995716 kb
Host smart-7071989c-7afd-46e6-8bbf-e4a5170b8fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048363657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.2048363657
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.1303024682
Short name T1027
Test name
Test status
Simulation time 1607599958 ps
CPU time 14.87 seconds
Started Jul 02 08:13:36 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 221116 kb
Host smart-c810a5d6-bea0-4aed-a885-5df0c5f34d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303024682 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.1303024682
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.2760842018
Short name T414
Test name
Test status
Simulation time 8765504818 ps
CPU time 5.56 seconds
Started Jul 02 08:13:42 AM PDT 24
Finished Jul 02 08:13:49 AM PDT 24
Peak memory 214688 kb
Host smart-784432eb-e3db-4544-892c-80415947d02c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760842018 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.2760842018
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.3865359888
Short name T1133
Test name
Test status
Simulation time 467887487 ps
CPU time 1.01 seconds
Started Jul 02 08:13:43 AM PDT 24
Finished Jul 02 08:13:45 AM PDT 24
Peak memory 204608 kb
Host smart-72c58438-4312-4135-966a-7eb8db304145
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865359888 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.3865359888
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.779912320
Short name T1042
Test name
Test status
Simulation time 638165913 ps
CPU time 1.26 seconds
Started Jul 02 08:13:43 AM PDT 24
Finished Jul 02 08:13:46 AM PDT 24
Peak memory 212772 kb
Host smart-45e91c49-7aa8-4d76-a4fc-a69f95387226
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779912320 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.i2c_target_fifo_reset_tx.779912320
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.3168306925
Short name T1048
Test name
Test status
Simulation time 1651553922 ps
CPU time 2.22 seconds
Started Jul 02 08:13:41 AM PDT 24
Finished Jul 02 08:13:44 AM PDT 24
Peak memory 204820 kb
Host smart-8cc90ad7-04bf-4ae8-b6bd-d59034397259
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168306925 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.3168306925
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.449626450
Short name T558
Test name
Test status
Simulation time 216925615 ps
CPU time 1.2 seconds
Started Jul 02 08:13:42 AM PDT 24
Finished Jul 02 08:13:45 AM PDT 24
Peak memory 204600 kb
Host smart-3b538bbb-bad1-4071-8db9-966a2b00129d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449626450 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.449626450
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.748670619
Short name T1254
Test name
Test status
Simulation time 621751614 ps
CPU time 2.51 seconds
Started Jul 02 08:13:42 AM PDT 24
Finished Jul 02 08:13:46 AM PDT 24
Peak memory 204720 kb
Host smart-8851391d-7771-4b5a-9b53-d80f0a1bb3e4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748670619 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 42.i2c_target_hrst.748670619
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2014447588
Short name T695
Test name
Test status
Simulation time 1265839794 ps
CPU time 7.14 seconds
Started Jul 02 08:13:42 AM PDT 24
Finished Jul 02 08:13:50 AM PDT 24
Peak memory 218960 kb
Host smart-ae4bee66-e0f1-4241-9f23-54f59e33945e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014447588 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2014447588
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.535630388
Short name T2
Test name
Test status
Simulation time 21966957140 ps
CPU time 394.91 seconds
Started Jul 02 08:13:40 AM PDT 24
Finished Jul 02 08:20:16 AM PDT 24
Peak memory 3794928 kb
Host smart-7e222b7c-ac91-4fc9-ae20-2555c267c934
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535630388 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.535630388
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.3515493602
Short name T461
Test name
Test status
Simulation time 1045515672 ps
CPU time 14.39 seconds
Started Jul 02 08:13:38 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 204828 kb
Host smart-bb1d0392-19ae-4750-8bb2-affd38453c43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515493602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.3515493602
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.638064938
Short name T812
Test name
Test status
Simulation time 9417715291 ps
CPU time 23.86 seconds
Started Jul 02 08:13:43 AM PDT 24
Finished Jul 02 08:14:08 AM PDT 24
Peak memory 227480 kb
Host smart-5bce0f5f-695d-41eb-927d-d3ce282737b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638064938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_rd.638064938
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.41318487
Short name T126
Test name
Test status
Simulation time 24455057404 ps
CPU time 73.98 seconds
Started Jul 02 08:13:37 AM PDT 24
Finished Jul 02 08:14:53 AM PDT 24
Peak memory 1058932 kb
Host smart-d50ab943-3525-4845-8bd6-3bd5ef16c02d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41318487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stress_wr.41318487
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.167919570
Short name T994
Test name
Test status
Simulation time 24545171502 ps
CPU time 239.08 seconds
Started Jul 02 08:13:41 AM PDT 24
Finished Jul 02 08:17:41 AM PDT 24
Peak memory 1011564 kb
Host smart-9aca9781-779a-4935-896a-9b7f44c2fe94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167919570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_t
arget_stretch.167919570
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.1347404316
Short name T586
Test name
Test status
Simulation time 1530826752 ps
CPU time 7.99 seconds
Started Jul 02 08:13:43 AM PDT 24
Finished Jul 02 08:13:52 AM PDT 24
Peak memory 213016 kb
Host smart-27cdbc8a-7b9f-409b-b0bf-22d567b72e27
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347404316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.1347404316
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.2967630010
Short name T546
Test name
Test status
Simulation time 198146486 ps
CPU time 1.75 seconds
Started Jul 02 08:13:44 AM PDT 24
Finished Jul 02 08:13:47 AM PDT 24
Peak memory 204816 kb
Host smart-481f5916-568c-4582-b9e8-229b9734ff1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967630010 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.2967630010
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.1179881462
Short name T172
Test name
Test status
Simulation time 47248413 ps
CPU time 0.63 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:13:55 AM PDT 24
Peak memory 204436 kb
Host smart-739a1326-83e3-460b-b31f-176575b3568c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179881462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.1179881462
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1821988584
Short name T633
Test name
Test status
Simulation time 352778893 ps
CPU time 17.87 seconds
Started Jul 02 08:13:46 AM PDT 24
Finished Jul 02 08:14:05 AM PDT 24
Peak memory 278364 kb
Host smart-2a538782-ab15-4eaa-b287-587c003a204e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821988584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1821988584
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.4132159486
Short name T1160
Test name
Test status
Simulation time 10786258955 ps
CPU time 99.28 seconds
Started Jul 02 08:13:47 AM PDT 24
Finished Jul 02 08:15:27 AM PDT 24
Peak memory 878724 kb
Host smart-bfd12174-df8c-4654-8c30-24a030b794ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132159486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.4132159486
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.93281655
Short name T792
Test name
Test status
Simulation time 8314584564 ps
CPU time 42.84 seconds
Started Jul 02 08:13:43 AM PDT 24
Finished Jul 02 08:14:27 AM PDT 24
Peak memory 538232 kb
Host smart-f8a5eb8c-6e50-47de-84a2-bc002ca2ed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93281655 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.93281655
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.3669843656
Short name T655
Test name
Test status
Simulation time 309348666 ps
CPU time 0.85 seconds
Started Jul 02 08:13:46 AM PDT 24
Finished Jul 02 08:13:48 AM PDT 24
Peak memory 204444 kb
Host smart-531c3fda-33a6-4bd6-9eb5-68630a578ec5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669843656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.3669843656
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.3533006443
Short name T387
Test name
Test status
Simulation time 126043221 ps
CPU time 3.82 seconds
Started Jul 02 08:13:47 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 224784 kb
Host smart-c72acf0f-ab85-40cc-8630-b4d3ec5d0884
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533006443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.3533006443
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.3207221741
Short name T888
Test name
Test status
Simulation time 21380099623 ps
CPU time 127.79 seconds
Started Jul 02 08:13:41 AM PDT 24
Finished Jul 02 08:15:50 AM PDT 24
Peak memory 1454396 kb
Host smart-3fa35816-b870-4df1-b5ea-0ead4c3a163a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207221741 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.3207221741
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.2456109316
Short name T925
Test name
Test status
Simulation time 1696042802 ps
CPU time 17.05 seconds
Started Jul 02 08:13:48 AM PDT 24
Finished Jul 02 08:14:06 AM PDT 24
Peak memory 204756 kb
Host smart-ff991c38-7327-496e-a17f-cd7c7ad76b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456109316 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.2456109316
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3390949308
Short name T982
Test name
Test status
Simulation time 1507367810 ps
CPU time 70.08 seconds
Started Jul 02 08:13:48 AM PDT 24
Finished Jul 02 08:14:59 AM PDT 24
Peak memory 406656 kb
Host smart-942f64c6-9bec-4878-83d4-615878affba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390949308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3390949308
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.185032125
Short name T1367
Test name
Test status
Simulation time 77376423 ps
CPU time 0.68 seconds
Started Jul 02 08:13:43 AM PDT 24
Finished Jul 02 08:13:45 AM PDT 24
Peak memory 204520 kb
Host smart-32e8feb7-44ad-4e70-b8c9-ada20dd36ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185032125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.185032125
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.2504703537
Short name T798
Test name
Test status
Simulation time 8241012649 ps
CPU time 89.53 seconds
Started Jul 02 08:13:47 AM PDT 24
Finished Jul 02 08:15:18 AM PDT 24
Peak memory 261532 kb
Host smart-eb9a9d58-8f57-41d7-b464-2d5d3e764fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504703537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.2504703537
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.938303234
Short name T237
Test name
Test status
Simulation time 234950437 ps
CPU time 1.84 seconds
Started Jul 02 08:13:46 AM PDT 24
Finished Jul 02 08:13:48 AM PDT 24
Peak memory 204720 kb
Host smart-d6e18df7-ae86-4d0c-8e9c-b25de16fd9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938303234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.938303234
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.3709649153
Short name T425
Test name
Test status
Simulation time 6511561827 ps
CPU time 27.56 seconds
Started Jul 02 08:13:43 AM PDT 24
Finished Jul 02 08:14:12 AM PDT 24
Peak memory 358712 kb
Host smart-83955040-7a16-47a5-a053-c406407dd8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709649153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.3709649153
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.2973425674
Short name T494
Test name
Test status
Simulation time 32708886042 ps
CPU time 1852.75 seconds
Started Jul 02 08:13:48 AM PDT 24
Finished Jul 02 08:44:42 AM PDT 24
Peak memory 2662800 kb
Host smart-ac0ae94c-a1d5-4fe0-9d48-ac28764e9dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973425674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.2973425674
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.686447353
Short name T878
Test name
Test status
Simulation time 1079856231 ps
CPU time 5.16 seconds
Started Jul 02 08:13:46 AM PDT 24
Finished Jul 02 08:13:52 AM PDT 24
Peak memory 212948 kb
Host smart-fa842034-70fc-4e3a-b56c-743f4037d5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686447353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.686447353
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.1319866413
Short name T566
Test name
Test status
Simulation time 3745979290 ps
CPU time 3.62 seconds
Started Jul 02 08:13:48 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 213040 kb
Host smart-0839a1d7-5289-4bbb-a8d0-05a2890fd578
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319866413 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.1319866413
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.901308485
Short name T1293
Test name
Test status
Simulation time 249094126 ps
CPU time 1.07 seconds
Started Jul 02 08:13:46 AM PDT 24
Finished Jul 02 08:13:48 AM PDT 24
Peak memory 204576 kb
Host smart-f13bfcb5-3fef-466a-aa0f-a24b32d8a862
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901308485 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_acq.901308485
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2041000472
Short name T1256
Test name
Test status
Simulation time 286855718 ps
CPU time 1.72 seconds
Started Jul 02 08:13:50 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 208520 kb
Host smart-fc7c308b-ff87-4f6e-9add-7090a5a19a22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041000472 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2041000472
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.3278426594
Short name T1418
Test name
Test status
Simulation time 1207144104 ps
CPU time 3.31 seconds
Started Jul 02 08:13:49 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 204776 kb
Host smart-a18e3e36-7734-4e51-82b6-6b77ad7aa29c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278426594 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.3278426594
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.180742712
Short name T308
Test name
Test status
Simulation time 212047792 ps
CPU time 1.06 seconds
Started Jul 02 08:13:55 AM PDT 24
Finished Jul 02 08:13:57 AM PDT 24
Peak memory 204612 kb
Host smart-6ef4e6df-45e0-48ca-9c89-1e1a3355d3ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180742712 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.180742712
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_hrst.4138160352
Short name T451
Test name
Test status
Simulation time 1418934635 ps
CPU time 1.88 seconds
Started Jul 02 08:13:50 AM PDT 24
Finished Jul 02 08:13:53 AM PDT 24
Peak memory 204776 kb
Host smart-bb4b9cf6-b5f2-4111-b5ca-96fca3446364
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138160352 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_hrst.4138160352
Directory /workspace/43.i2c_target_hrst/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.562208744
Short name T482
Test name
Test status
Simulation time 4857339716 ps
CPU time 5.51 seconds
Started Jul 02 08:13:47 AM PDT 24
Finished Jul 02 08:13:54 AM PDT 24
Peak memory 220860 kb
Host smart-1009a616-4647-40de-833e-55afbc9574ae
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562208744 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.562208744
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.2091018086
Short name T1216
Test name
Test status
Simulation time 22010263098 ps
CPU time 61 seconds
Started Jul 02 08:13:49 AM PDT 24
Finished Jul 02 08:14:51 AM PDT 24
Peak memory 976816 kb
Host smart-476d1741-d984-43e6-aeb8-06947bf2e98e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091018086 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.2091018086
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3609498663
Short name T1283
Test name
Test status
Simulation time 3972445669 ps
CPU time 41.03 seconds
Started Jul 02 08:13:47 AM PDT 24
Finished Jul 02 08:14:29 AM PDT 24
Peak memory 205496 kb
Host smart-d7112466-3596-4704-ac1e-46feacba4924
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609498663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3609498663
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.3398677443
Short name T1453
Test name
Test status
Simulation time 50460330815 ps
CPU time 304.38 seconds
Started Jul 02 08:13:48 AM PDT 24
Finished Jul 02 08:18:53 AM PDT 24
Peak memory 3168200 kb
Host smart-9acea153-f973-4554-9b40-19b3e7e1061d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398677443 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_wr.3398677443
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.3643041568
Short name T333
Test name
Test status
Simulation time 4877382580 ps
CPU time 6.81 seconds
Started Jul 02 08:13:47 AM PDT 24
Finished Jul 02 08:13:55 AM PDT 24
Peak memory 213216 kb
Host smart-41ae5da0-a498-4c54-98f2-2605cbf90d59
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643041568 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 43.i2c_target_timeout.3643041568
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.698309846
Short name T1144
Test name
Test status
Simulation time 847560175 ps
CPU time 10.12 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:14:05 AM PDT 24
Peak memory 204796 kb
Host smart-4fbb6a86-7efa-4a27-baab-68f9090e4a3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698309846 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.698309846
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.1424228879
Short name T1231
Test name
Test status
Simulation time 47295099 ps
CPU time 0.62 seconds
Started Jul 02 08:14:00 AM PDT 24
Finished Jul 02 08:14:02 AM PDT 24
Peak memory 204468 kb
Host smart-3a244d15-02f9-4153-99c9-3d9b903969ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424228879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.1424228879
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.3797389027
Short name T648
Test name
Test status
Simulation time 391625066 ps
CPU time 3.54 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:13:58 AM PDT 24
Peak memory 213068 kb
Host smart-3a2643dd-9ba6-462d-8fa7-0016eae07ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797389027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.3797389027
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.2504622030
Short name T826
Test name
Test status
Simulation time 514289035 ps
CPU time 7.68 seconds
Started Jul 02 08:13:56 AM PDT 24
Finished Jul 02 08:14:05 AM PDT 24
Peak memory 286864 kb
Host smart-5c664ffb-c906-4ff9-b8b6-725e27a1e187
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504622030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.2504622030
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.891034686
Short name T1247
Test name
Test status
Simulation time 2121700750 ps
CPU time 57.87 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:14:52 AM PDT 24
Peak memory 678952 kb
Host smart-618c62d0-5192-4aa7-bb83-d397d86b3f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891034686 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.891034686
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.823229421
Short name T1399
Test name
Test status
Simulation time 1918370398 ps
CPU time 49.1 seconds
Started Jul 02 08:13:51 AM PDT 24
Finished Jul 02 08:14:42 AM PDT 24
Peak memory 647720 kb
Host smart-271f5094-3ad8-459d-94e2-260b882fd6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823229421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.823229421
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.4131441805
Short name T1242
Test name
Test status
Simulation time 242745652 ps
CPU time 1.18 seconds
Started Jul 02 08:13:54 AM PDT 24
Finished Jul 02 08:13:57 AM PDT 24
Peak memory 204468 kb
Host smart-d842d886-930c-4eb2-8e93-6af57c1b202e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131441805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.4131441805
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.2842523718
Short name T1486
Test name
Test status
Simulation time 769868585 ps
CPU time 10.65 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:14:05 AM PDT 24
Peak memory 241500 kb
Host smart-ad16ed1a-2779-4f51-9d06-66c41878cd62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842523718 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx
.2842523718
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.2853204364
Short name T1503
Test name
Test status
Simulation time 3977724281 ps
CPU time 260.93 seconds
Started Jul 02 08:13:51 AM PDT 24
Finished Jul 02 08:18:14 AM PDT 24
Peak memory 1155060 kb
Host smart-328e5d82-8928-40bc-8459-bb8da421ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853204364 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.2853204364
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.3461133465
Short name T763
Test name
Test status
Simulation time 1913058201 ps
CPU time 5.23 seconds
Started Jul 02 08:13:59 AM PDT 24
Finished Jul 02 08:14:06 AM PDT 24
Peak memory 204816 kb
Host smart-5298e21a-88d6-44a8-b8d0-bea1bdf5b7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461133465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.3461133465
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.1010435442
Short name T1464
Test name
Test status
Simulation time 7162318521 ps
CPU time 71.75 seconds
Started Jul 02 08:13:57 AM PDT 24
Finished Jul 02 08:15:10 AM PDT 24
Peak memory 381840 kb
Host smart-6564939f-a21f-4aff-b06d-c0df05c143c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010435442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.1010435442
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2070243892
Short name T444
Test name
Test status
Simulation time 75629528 ps
CPU time 0.66 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:13:54 AM PDT 24
Peak memory 204544 kb
Host smart-7910eebd-665a-402d-aeed-c74e68c456e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070243892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2070243892
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.4241618334
Short name T318
Test name
Test status
Simulation time 3740798039 ps
CPU time 35.9 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:14:30 AM PDT 24
Peak memory 229352 kb
Host smart-810236cb-f81f-4023-8ecd-f751e4a6d7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241618334 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.4241618334
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.2762042533
Short name T767
Test name
Test status
Simulation time 842141136 ps
CPU time 2.93 seconds
Started Jul 02 08:13:54 AM PDT 24
Finished Jul 02 08:13:59 AM PDT 24
Peak memory 204712 kb
Host smart-f6ee40d8-37d7-42b1-9550-8e043146b9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762042533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.2762042533
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.1563856209
Short name T366
Test name
Test status
Simulation time 1504302998 ps
CPU time 28.69 seconds
Started Jul 02 08:13:51 AM PDT 24
Finished Jul 02 08:14:22 AM PDT 24
Peak memory 329668 kb
Host smart-b82cc5b4-d58f-44a5-80c4-4c27985137de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563856209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.1563856209
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.2788564863
Short name T953
Test name
Test status
Simulation time 41637710085 ps
CPU time 325.63 seconds
Started Jul 02 08:13:50 AM PDT 24
Finished Jul 02 08:19:17 AM PDT 24
Peak memory 1153796 kb
Host smart-23b64de8-bdc5-42e0-a993-d1a03047c8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788564863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.2788564863
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.4246758944
Short name T342
Test name
Test status
Simulation time 796632064 ps
CPU time 13.42 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:14:08 AM PDT 24
Peak memory 220964 kb
Host smart-68b19397-4700-4abe-948f-85c37d2882e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246758944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.4246758944
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.3510254502
Short name T1135
Test name
Test status
Simulation time 3439277742 ps
CPU time 4.28 seconds
Started Jul 02 08:13:58 AM PDT 24
Finished Jul 02 08:14:04 AM PDT 24
Peak memory 213108 kb
Host smart-9d46752a-c658-4bc3-9dc8-f96c716b29ad
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510254502 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.3510254502
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1876791833
Short name T831
Test name
Test status
Simulation time 273228298 ps
CPU time 0.9 seconds
Started Jul 02 08:13:58 AM PDT 24
Finished Jul 02 08:14:00 AM PDT 24
Peak memory 204596 kb
Host smart-c5006f62-c934-4605-a679-9a64df636073
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876791833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1876791833
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.3445037626
Short name T854
Test name
Test status
Simulation time 174142667 ps
CPU time 1.09 seconds
Started Jul 02 08:13:56 AM PDT 24
Finished Jul 02 08:13:59 AM PDT 24
Peak memory 204596 kb
Host smart-dbeb77e3-bbb2-421a-a29e-a6d01080e635
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445037626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.3445037626
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.98231275
Short name T539
Test name
Test status
Simulation time 333736947 ps
CPU time 1.9 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:07 AM PDT 24
Peak memory 204816 kb
Host smart-d397dbd5-5796-4882-b22c-0ed9650a7c2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98231275 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.98231275
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.184363097
Short name T1501
Test name
Test status
Simulation time 152391077 ps
CPU time 0.9 seconds
Started Jul 02 08:13:59 AM PDT 24
Finished Jul 02 08:14:01 AM PDT 24
Peak memory 204612 kb
Host smart-aa52aad7-0d04-4e82-a12d-4405f2d5ad2d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184363097 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.184363097
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_hrst.1247169368
Short name T1039
Test name
Test status
Simulation time 1690063331 ps
CPU time 2.71 seconds
Started Jul 02 08:13:57 AM PDT 24
Finished Jul 02 08:14:01 AM PDT 24
Peak memory 204832 kb
Host smart-4f3ded60-6682-4d3d-9277-8c733b3449b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247169368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_hrst.1247169368
Directory /workspace/44.i2c_target_hrst/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.2596532827
Short name T1478
Test name
Test status
Simulation time 820170138 ps
CPU time 4.24 seconds
Started Jul 02 08:13:51 AM PDT 24
Finished Jul 02 08:13:56 AM PDT 24
Peak memory 204820 kb
Host smart-0a03c427-eac2-4760-a1a4-eb1369e0869b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596532827 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_intr_smoke.2596532827
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.1945492429
Short name T311
Test name
Test status
Simulation time 6296902501 ps
CPU time 7.59 seconds
Started Jul 02 08:13:58 AM PDT 24
Finished Jul 02 08:14:07 AM PDT 24
Peak memory 204988 kb
Host smart-341b546f-e277-47fe-a99e-165e1466251b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945492429 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.1945492429
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.3332964943
Short name T1455
Test name
Test status
Simulation time 1880369490 ps
CPU time 27.82 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:14:21 AM PDT 24
Peak memory 204736 kb
Host smart-a638aede-17ae-4a9e-bfed-9204f9e848b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332964943 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.3332964943
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.990046749
Short name T1228
Test name
Test status
Simulation time 5770182630 ps
CPU time 25.05 seconds
Started Jul 02 08:13:54 AM PDT 24
Finished Jul 02 08:14:21 AM PDT 24
Peak memory 226292 kb
Host smart-f33492a5-b12d-444f-bad8-e17f81c51289
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990046749 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c
_target_stress_rd.990046749
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.3042609317
Short name T928
Test name
Test status
Simulation time 41535112892 ps
CPU time 647.51 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:24:41 AM PDT 24
Peak memory 5504308 kb
Host smart-62d097bb-fbd7-4cdf-abd1-3dba4b2ba8b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042609317 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.3042609317
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.1116429696
Short name T757
Test name
Test status
Simulation time 19093076612 ps
CPU time 39.65 seconds
Started Jul 02 08:13:52 AM PDT 24
Finished Jul 02 08:14:34 AM PDT 24
Peak memory 771232 kb
Host smart-9747b91b-e9f8-4063-840c-318355918566
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116429696 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_
target_stretch.1116429696
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.548071911
Short name T1013
Test name
Test status
Simulation time 1510926618 ps
CPU time 6.8 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:11 AM PDT 24
Peak memory 215856 kb
Host smart-18bd56e6-fe9e-4c7c-8a3c-75b0396fc912
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548071911 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 44.i2c_target_timeout.548071911
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.1808204387
Short name T324
Test name
Test status
Simulation time 145708184 ps
CPU time 2.89 seconds
Started Jul 02 08:13:57 AM PDT 24
Finished Jul 02 08:14:01 AM PDT 24
Peak memory 204832 kb
Host smart-f9cc520e-58dd-408d-9ecf-874696eee7f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808204387 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.1808204387
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.147008420
Short name T800
Test name
Test status
Simulation time 48167525 ps
CPU time 0.62 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:20 AM PDT 24
Peak memory 204444 kb
Host smart-e4b9fe6b-49fb-42a0-bf3c-46a1cd3709b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147008420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.147008420
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.572971345
Short name T1510
Test name
Test status
Simulation time 232102923 ps
CPU time 1.74 seconds
Started Jul 02 08:14:00 AM PDT 24
Finished Jul 02 08:14:03 AM PDT 24
Peak memory 204856 kb
Host smart-9d41cdb6-db16-4cc5-8663-4ef5455e7c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572971345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.572971345
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.505440972
Short name T1513
Test name
Test status
Simulation time 191960519 ps
CPU time 4.02 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:09 AM PDT 24
Peak memory 237664 kb
Host smart-1cc7cf91-c9c0-4395-92ca-8aeae90195af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505440972 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_empt
y.505440972
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1788759446
Short name T1130
Test name
Test status
Simulation time 5877625121 ps
CPU time 82.06 seconds
Started Jul 02 08:14:02 AM PDT 24
Finished Jul 02 08:15:26 AM PDT 24
Peak memory 686804 kb
Host smart-35ccd8bc-f1fa-4d9e-a57c-d568fee72e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788759446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1788759446
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.3674602806
Short name T940
Test name
Test status
Simulation time 1709785791 ps
CPU time 109.82 seconds
Started Jul 02 08:13:58 AM PDT 24
Finished Jul 02 08:15:49 AM PDT 24
Peak memory 582120 kb
Host smart-e2dabfa6-1616-4d80-97fe-08cffd6e7d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674602806 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.3674602806
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.3709351931
Short name T1502
Test name
Test status
Simulation time 281545007 ps
CPU time 0.86 seconds
Started Jul 02 08:13:58 AM PDT 24
Finished Jul 02 08:14:00 AM PDT 24
Peak memory 204444 kb
Host smart-0fd70903-e0c3-4acb-a373-ee537ca85223
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709351931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.3709351931
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.536855035
Short name T903
Test name
Test status
Simulation time 264773793 ps
CPU time 7.02 seconds
Started Jul 02 08:14:00 AM PDT 24
Finished Jul 02 08:14:09 AM PDT 24
Peak memory 254236 kb
Host smart-27a813af-7bf8-47b2-b539-459bd4e6e052
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536855035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx.
536855035
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1198867893
Short name T100
Test name
Test status
Simulation time 3560068243 ps
CPU time 78.7 seconds
Started Jul 02 08:13:58 AM PDT 24
Finished Jul 02 08:15:17 AM PDT 24
Peak memory 1072920 kb
Host smart-d290dab6-015c-46ee-8999-59cbd78fda6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198867893 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1198867893
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.1566651441
Short name T801
Test name
Test status
Simulation time 503579122 ps
CPU time 6.1 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:11 AM PDT 24
Peak memory 204836 kb
Host smart-153bca19-1bf4-4579-8e84-ded5927d46fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566651441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.1566651441
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.3817631412
Short name T61
Test name
Test status
Simulation time 1027636998 ps
CPU time 46.46 seconds
Started Jul 02 08:14:02 AM PDT 24
Finished Jul 02 08:14:50 AM PDT 24
Peak memory 260672 kb
Host smart-42cbd07b-a1f7-45de-8f5a-51000c58f05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817631412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.3817631412
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.1426637868
Short name T133
Test name
Test status
Simulation time 20696038 ps
CPU time 0.65 seconds
Started Jul 02 08:14:00 AM PDT 24
Finished Jul 02 08:14:02 AM PDT 24
Peak memory 204516 kb
Host smart-45cb0aaa-7ee3-4787-b162-5f2bcc4f960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426637868 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.1426637868
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.3585579745
Short name T54
Test name
Test status
Simulation time 878698249 ps
CPU time 42.54 seconds
Started Jul 02 08:13:59 AM PDT 24
Finished Jul 02 08:14:43 AM PDT 24
Peak memory 333564 kb
Host smart-4a478830-aa12-4b3f-a3d9-e8db8d933bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585579745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.3585579745
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.778142545
Short name T970
Test name
Test status
Simulation time 481250164 ps
CPU time 4.58 seconds
Started Jul 02 08:13:56 AM PDT 24
Finished Jul 02 08:14:02 AM PDT 24
Peak memory 204612 kb
Host smart-13af820d-21f7-4f3c-bf8b-36df9b3e66cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778142545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.778142545
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.3818867748
Short name T1081
Test name
Test status
Simulation time 1540085185 ps
CPU time 72.46 seconds
Started Jul 02 08:13:57 AM PDT 24
Finished Jul 02 08:15:11 AM PDT 24
Peak memory 304920 kb
Host smart-ded5f57c-6584-46d0-95a7-5a6dba731309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818867748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.3818867748
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.2077856708
Short name T280
Test name
Test status
Simulation time 17289497832 ps
CPU time 816.2 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:27:42 AM PDT 24
Peak memory 1387420 kb
Host smart-282f8795-9578-477b-a298-2823260cb41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077856708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.2077856708
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.680327588
Short name T631
Test name
Test status
Simulation time 2318511407 ps
CPU time 12.99 seconds
Started Jul 02 08:13:59 AM PDT 24
Finished Jul 02 08:14:14 AM PDT 24
Peak memory 221312 kb
Host smart-0d8a3da4-3206-47fc-b425-c6256fc776c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680327588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.680327588
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.379810210
Short name T1521
Test name
Test status
Simulation time 1684990783 ps
CPU time 2.83 seconds
Started Jul 02 08:14:04 AM PDT 24
Finished Jul 02 08:14:09 AM PDT 24
Peak memory 204772 kb
Host smart-e9b258bd-ee27-4e32-afc0-3e8cc1bb3155
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379810210 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.379810210
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.3643409543
Short name T442
Test name
Test status
Simulation time 138281631 ps
CPU time 1.1 seconds
Started Jul 02 08:14:02 AM PDT 24
Finished Jul 02 08:14:04 AM PDT 24
Peak memory 204584 kb
Host smart-2447900e-54ee-4149-a018-0d006124f3ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643409543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_fifo_reset_acq.3643409543
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.1269867934
Short name T394
Test name
Test status
Simulation time 658662475 ps
CPU time 1.4 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:06 AM PDT 24
Peak memory 204600 kb
Host smart-c3033745-ec05-4f36-a36a-48bf46be9bef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269867934 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.1269867934
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.3069755498
Short name T396
Test name
Test status
Simulation time 1262434314 ps
CPU time 1.84 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:21 AM PDT 24
Peak memory 204784 kb
Host smart-3f67999e-b21f-4bc6-a77e-cb736b33ce4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069755498 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.3069755498
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.2995030859
Short name T1323
Test name
Test status
Simulation time 776948501 ps
CPU time 1.35 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:07 AM PDT 24
Peak memory 204628 kb
Host smart-7e667eae-8dd2-4ca7-8bd7-318b6db08efe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995030859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.2995030859
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_hrst.1442186580
Short name T249
Test name
Test status
Simulation time 1989360164 ps
CPU time 3.07 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:07 AM PDT 24
Peak memory 204792 kb
Host smart-222eaf00-de7c-43d3-818c-ddaf47253ffd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442186580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 45.i2c_target_hrst.1442186580
Directory /workspace/45.i2c_target_hrst/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.2833421973
Short name T1538
Test name
Test status
Simulation time 4283076428 ps
CPU time 5.82 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:11 AM PDT 24
Peak memory 213080 kb
Host smart-5126ef02-0d08-43cc-b7f1-0f55b41f99d5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833421973 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.2833421973
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.754794767
Short name T935
Test name
Test status
Simulation time 16121049037 ps
CPU time 270.63 seconds
Started Jul 02 08:14:02 AM PDT 24
Finished Jul 02 08:18:34 AM PDT 24
Peak memory 3815932 kb
Host smart-123c0b80-7f5b-43d2-914e-e5e13f3cc216
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754794767 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.754794767
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.4262738034
Short name T431
Test name
Test status
Simulation time 556765903 ps
CPU time 15.97 seconds
Started Jul 02 08:14:01 AM PDT 24
Finished Jul 02 08:14:18 AM PDT 24
Peak memory 204828 kb
Host smart-776f6570-c4bb-4b22-a5a2-5ce128e36a14
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262738034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_ta
rget_smoke.4262738034
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.9100610
Short name T313
Test name
Test status
Simulation time 5980144050 ps
CPU time 63.05 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:15:08 AM PDT 24
Peak memory 209344 kb
Host smart-c20b2d47-f0da-424b-ac06-a4c8dc895131
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9100610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i
2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_t
arget_stress_rd.9100610
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2176606280
Short name T421
Test name
Test status
Simulation time 10905034978 ps
CPU time 2.39 seconds
Started Jul 02 08:14:04 AM PDT 24
Finished Jul 02 08:14:08 AM PDT 24
Peak memory 204936 kb
Host smart-dcc2fe49-629f-4114-bbaf-dbfbb8130f9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176606280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2176606280
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1764794486
Short name T618
Test name
Test status
Simulation time 21850257398 ps
CPU time 54.98 seconds
Started Jul 02 08:14:04 AM PDT 24
Finished Jul 02 08:15:01 AM PDT 24
Peak memory 763580 kb
Host smart-b9798d8c-b523-4217-851b-f71d5279579e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764794486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1764794486
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.1441752428
Short name T502
Test name
Test status
Simulation time 1343547844 ps
CPU time 7.09 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:12 AM PDT 24
Peak memory 204832 kb
Host smart-9ef11306-6298-4e9f-90b2-9618b41e76d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441752428 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 45.i2c_target_timeout.1441752428
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.52393024
Short name T1095
Test name
Test status
Simulation time 627786158 ps
CPU time 8.08 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:13 AM PDT 24
Peak memory 204732 kb
Host smart-1f57db1b-3fcf-4003-a3a4-3f96431839df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52393024 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.52393024
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.44338217
Short name T1140
Test name
Test status
Simulation time 28068964 ps
CPU time 0.66 seconds
Started Jul 02 08:14:13 AM PDT 24
Finished Jul 02 08:14:16 AM PDT 24
Peak memory 204484 kb
Host smart-28054524-af29-4012-b49c-e0d68eb78324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44338217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.44338217
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.2730045724
Short name T996
Test name
Test status
Simulation time 362923896 ps
CPU time 1.75 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:21 AM PDT 24
Peak memory 213064 kb
Host smart-47adab6a-99a1-45bd-9453-efa4021dc9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730045724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.2730045724
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.651323064
Short name T909
Test name
Test status
Simulation time 1401983582 ps
CPU time 6.5 seconds
Started Jul 02 08:14:08 AM PDT 24
Finished Jul 02 08:14:16 AM PDT 24
Peak memory 260900 kb
Host smart-449748ac-fcaf-46a8-aee1-b2c792a8caea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651323064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.651323064
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.2910752459
Short name T656
Test name
Test status
Simulation time 8842234023 ps
CPU time 57.03 seconds
Started Jul 02 08:14:11 AM PDT 24
Finished Jul 02 08:15:09 AM PDT 24
Peak memory 528180 kb
Host smart-fbdb9046-3a54-4e3b-b18f-7c8cf5da4f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910752459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2910752459
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.3344811785
Short name T1386
Test name
Test status
Simulation time 4588935467 ps
CPU time 79.91 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:15:39 AM PDT 24
Peak memory 747100 kb
Host smart-1dc1bcc6-424a-4b10-bcfe-1f1537f5d859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344811785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3344811785
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.635083153
Short name T244
Test name
Test status
Simulation time 209908811 ps
CPU time 0.97 seconds
Started Jul 02 08:14:02 AM PDT 24
Finished Jul 02 08:14:05 AM PDT 24
Peak memory 204452 kb
Host smart-d0970130-cb5a-4cf4-b99f-5754bd2e2420
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635083153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_fm
t.635083153
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.4017296510
Short name T239
Test name
Test status
Simulation time 148302725 ps
CPU time 7.31 seconds
Started Jul 02 08:14:08 AM PDT 24
Finished Jul 02 08:14:16 AM PDT 24
Peak memory 204796 kb
Host smart-de000291-19a2-496c-b547-ea8608158b19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017296510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.4017296510
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.3113762345
Short name T875
Test name
Test status
Simulation time 16285254281 ps
CPU time 263.76 seconds
Started Jul 02 08:14:02 AM PDT 24
Finished Jul 02 08:18:28 AM PDT 24
Peak memory 1096828 kb
Host smart-c73473fa-947e-4db3-8072-570562c798d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113762345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.3113762345
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.2773355302
Short name T40
Test name
Test status
Simulation time 1278294980 ps
CPU time 14.4 seconds
Started Jul 02 08:14:14 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 204820 kb
Host smart-24a0c6f5-5f1d-4841-b038-6254b093cc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773355302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.2773355302
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.535999310
Short name T349
Test name
Test status
Simulation time 2902199618 ps
CPU time 26.37 seconds
Started Jul 02 08:14:14 AM PDT 24
Finished Jul 02 08:14:44 AM PDT 24
Peak memory 417032 kb
Host smart-5d1697f8-cde1-4c94-a6ec-d91514073b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535999310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.535999310
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.4262782788
Short name T134
Test name
Test status
Simulation time 38354342 ps
CPU time 0.71 seconds
Started Jul 02 08:14:03 AM PDT 24
Finished Jul 02 08:14:06 AM PDT 24
Peak memory 204516 kb
Host smart-c9fb2aff-fba6-4e37-939e-541c91a60c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262782788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.4262782788
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.72187239
Short name T873
Test name
Test status
Simulation time 4836583979 ps
CPU time 64.82 seconds
Started Jul 02 08:14:07 AM PDT 24
Finished Jul 02 08:15:13 AM PDT 24
Peak memory 222736 kb
Host smart-69625da9-2dd4-4fe6-a40e-3863bfcead39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72187239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.72187239
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.3270256483
Short name T1469
Test name
Test status
Simulation time 2598572066 ps
CPU time 9.41 seconds
Started Jul 02 08:14:09 AM PDT 24
Finished Jul 02 08:14:19 AM PDT 24
Peak memory 225896 kb
Host smart-89ef5034-c99d-4aee-b2fb-59ae771e4038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270256483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.3270256483
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.3307854631
Short name T1078
Test name
Test status
Simulation time 8277534270 ps
CPU time 30.03 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:49 AM PDT 24
Peak memory 311628 kb
Host smart-c54f3872-b531-4b5f-8849-0905b6f61efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307854631 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.3307854631
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.3438910502
Short name T867
Test name
Test status
Simulation time 14647034648 ps
CPU time 1848.22 seconds
Started Jul 02 08:14:08 AM PDT 24
Finished Jul 02 08:44:58 AM PDT 24
Peak memory 3216828 kb
Host smart-441447e1-4fbe-4dc3-b96f-94a786070ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438910502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.3438910502
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.1312580626
Short name T1210
Test name
Test status
Simulation time 9659326692 ps
CPU time 26.94 seconds
Started Jul 02 08:14:06 AM PDT 24
Finished Jul 02 08:14:34 AM PDT 24
Peak memory 213100 kb
Host smart-1d0602e8-bed9-4a8a-8c4f-47980901fe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312580626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.1312580626
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.72567059
Short name T949
Test name
Test status
Simulation time 781594849 ps
CPU time 4.48 seconds
Started Jul 02 08:14:08 AM PDT 24
Finished Jul 02 08:14:14 AM PDT 24
Peak memory 213048 kb
Host smart-d3352500-e709-47fd-b587-b460ad869e49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72567059 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_bad_addr.72567059
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.1529473143
Short name T123
Test name
Test status
Simulation time 161457860 ps
CPU time 0.93 seconds
Started Jul 02 08:14:09 AM PDT 24
Finished Jul 02 08:14:11 AM PDT 24
Peak memory 204540 kb
Host smart-fa652f1b-8d16-463c-8b29-086fbe09cd80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529473143 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.1529473143
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.2663179592
Short name T1272
Test name
Test status
Simulation time 293799368 ps
CPU time 1.56 seconds
Started Jul 02 08:14:10 AM PDT 24
Finished Jul 02 08:14:12 AM PDT 24
Peak memory 215548 kb
Host smart-8213d1ed-7c6d-4f22-84dd-bc2298ba71b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663179592 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 46.i2c_target_fifo_reset_tx.2663179592
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.2884902501
Short name T759
Test name
Test status
Simulation time 788160805 ps
CPU time 2.49 seconds
Started Jul 02 08:14:12 AM PDT 24
Finished Jul 02 08:14:17 AM PDT 24
Peak memory 205072 kb
Host smart-de86453c-3bcd-41ad-848c-ff59f827cf9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884902501 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.2884902501
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.1257239597
Short name T1517
Test name
Test status
Simulation time 140059969 ps
CPU time 1.26 seconds
Started Jul 02 08:14:12 AM PDT 24
Finished Jul 02 08:14:15 AM PDT 24
Peak memory 204568 kb
Host smart-f85b69b7-371d-4681-b77d-1e20c001e6fc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257239597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.1257239597
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.498056579
Short name T1032
Test name
Test status
Simulation time 626725015 ps
CPU time 3.4 seconds
Started Jul 02 08:14:08 AM PDT 24
Finished Jul 02 08:14:12 AM PDT 24
Peak memory 204848 kb
Host smart-b2658737-4b64-4485-935e-6b3509c4994a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498056579 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_intr_smoke.498056579
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.1916446206
Short name T722
Test name
Test status
Simulation time 8808204544 ps
CPU time 142.49 seconds
Started Jul 02 08:14:08 AM PDT 24
Finished Jul 02 08:16:32 AM PDT 24
Peak memory 2251080 kb
Host smart-670d1992-8ddd-4bd8-9249-ec60c4c6b946
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916446206 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.1916446206
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1420769431
Short name T1008
Test name
Test status
Simulation time 2279733534 ps
CPU time 17.35 seconds
Started Jul 02 08:14:11 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 204884 kb
Host smart-8d7ebf65-6f09-47e7-b3c4-0a1ea6753d8e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420769431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1420769431
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.4141217825
Short name T734
Test name
Test status
Simulation time 1441088553 ps
CPU time 20.63 seconds
Started Jul 02 08:14:09 AM PDT 24
Finished Jul 02 08:14:30 AM PDT 24
Peak memory 221296 kb
Host smart-169d3f52-f0ff-4488-9b86-76662d873629
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141217825 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.4141217825
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.3656449403
Short name T1496
Test name
Test status
Simulation time 10570371756 ps
CPU time 4.86 seconds
Started Jul 02 08:14:07 AM PDT 24
Finished Jul 02 08:14:13 AM PDT 24
Peak memory 204892 kb
Host smart-8b67b7e9-f509-4b58-aa3d-5bfa5a1bdd01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656449403 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.3656449403
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_stretch.51172898
Short name T381
Test name
Test status
Simulation time 5316940487 ps
CPU time 44.15 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:15:03 AM PDT 24
Peak memory 774688 kb
Host smart-50dd70fc-3e18-4c3f-b484-dce765289a62
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51172898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_stretch.51172898
Directory /workspace/46.i2c_target_stretch/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.3921638841
Short name T1114
Test name
Test status
Simulation time 1570878296 ps
CPU time 8.55 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:28 AM PDT 24
Peak memory 221000 kb
Host smart-ad3a18d2-d753-42b2-91b8-0579114e0836
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921638841 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 46.i2c_target_timeout.3921638841
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.2204772569
Short name T794
Test name
Test status
Simulation time 767895441 ps
CPU time 9.36 seconds
Started Jul 02 08:14:13 AM PDT 24
Finished Jul 02 08:14:25 AM PDT 24
Peak memory 204740 kb
Host smart-9fb3af5f-8833-4fdb-9b92-9b6af592718b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204772569 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.2204772569
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.868557259
Short name T171
Test name
Test status
Simulation time 51454920 ps
CPU time 0.64 seconds
Started Jul 02 08:14:19 AM PDT 24
Finished Jul 02 08:14:23 AM PDT 24
Peak memory 204384 kb
Host smart-2f76c867-4fb0-4b23-adb7-55aa9848f137
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868557259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.868557259
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.4244179215
Short name T914
Test name
Test status
Simulation time 367086911 ps
CPU time 17.09 seconds
Started Jul 02 08:14:13 AM PDT 24
Finished Jul 02 08:14:33 AM PDT 24
Peak memory 231580 kb
Host smart-0bcfda75-bdf0-4dd2-9176-ddae46c7fafd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244179215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_emp
ty.4244179215
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1740270799
Short name T1378
Test name
Test status
Simulation time 2056380463 ps
CPU time 74.97 seconds
Started Jul 02 08:14:13 AM PDT 24
Finished Jul 02 08:15:31 AM PDT 24
Peak memory 710096 kb
Host smart-0a2b7574-ba74-4c2e-a32b-0812665ce71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740270799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1740270799
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.2297841694
Short name T652
Test name
Test status
Simulation time 10987869942 ps
CPU time 96.39 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:15:56 AM PDT 24
Peak memory 833652 kb
Host smart-3e5ce253-e18e-4b44-9487-f65e36e0270b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297841694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.2297841694
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.3597038477
Short name T53
Test name
Test status
Simulation time 141935151 ps
CPU time 1.05 seconds
Started Jul 02 08:14:11 AM PDT 24
Finished Jul 02 08:14:14 AM PDT 24
Peak memory 204484 kb
Host smart-778cbf85-3d10-48bb-98ef-1282859cab7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597038477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.3597038477
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.961906691
Short name T305
Test name
Test status
Simulation time 427810307 ps
CPU time 12.29 seconds
Started Jul 02 08:14:12 AM PDT 24
Finished Jul 02 08:14:27 AM PDT 24
Peak memory 247604 kb
Host smart-af9bb770-78c6-4f40-b475-7bde52657eb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961906691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx.
961906691
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.1965042178
Short name T1157
Test name
Test status
Simulation time 22254197303 ps
CPU time 101.19 seconds
Started Jul 02 08:14:15 AM PDT 24
Finished Jul 02 08:15:59 AM PDT 24
Peak memory 1053692 kb
Host smart-259af901-6b67-4dff-894f-3591ed00c995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965042178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.1965042178
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.2521295619
Short name T490
Test name
Test status
Simulation time 6026817953 ps
CPU time 8 seconds
Started Jul 02 08:14:20 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 204964 kb
Host smart-154a0ad3-62bf-4b44-8608-d0c0e38711b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521295619 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.2521295619
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.315220146
Short name T33
Test name
Test status
Simulation time 1748441652 ps
CPU time 31.75 seconds
Started Jul 02 08:14:17 AM PDT 24
Finished Jul 02 08:14:52 AM PDT 24
Peak memory 456020 kb
Host smart-3a1ec255-f7f0-4de7-b90e-cd8841089ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315220146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.315220146
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.1769439153
Short name T65
Test name
Test status
Simulation time 14953159 ps
CPU time 0.65 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:20 AM PDT 24
Peak memory 204484 kb
Host smart-742ffd57-e4fa-4e89-a056-4402eba319cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769439153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.1769439153
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.447031739
Short name T499
Test name
Test status
Simulation time 8051405173 ps
CPU time 84.08 seconds
Started Jul 02 08:14:13 AM PDT 24
Finished Jul 02 08:15:40 AM PDT 24
Peak memory 228740 kb
Host smart-8dd136c8-2b68-46fe-bb3a-d62a19f07c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447031739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.447031739
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.1016624448
Short name T31
Test name
Test status
Simulation time 5852415377 ps
CPU time 57.18 seconds
Started Jul 02 08:14:12 AM PDT 24
Finished Jul 02 08:15:12 AM PDT 24
Peak memory 204784 kb
Host smart-b9c983bc-7283-4c39-9223-654a4fb0223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016624448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.1016624448
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.1945521044
Short name T674
Test name
Test status
Simulation time 9442969321 ps
CPU time 52.16 seconds
Started Jul 02 08:14:13 AM PDT 24
Finished Jul 02 08:15:08 AM PDT 24
Peak memory 269928 kb
Host smart-3a67181f-23f4-4dfe-b7ae-a4e3240f67d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945521044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.1945521044
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stress_all.919173062
Short name T78
Test name
Test status
Simulation time 94243430550 ps
CPU time 614.41 seconds
Started Jul 02 08:14:14 AM PDT 24
Finished Jul 02 08:24:32 AM PDT 24
Peak memory 1685808 kb
Host smart-536e9046-6fed-4808-8f26-174559780233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919173062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stress_all.919173062
Directory /workspace/47.i2c_host_stress_all/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.1974150829
Short name T1024
Test name
Test status
Simulation time 2383149147 ps
CPU time 29.2 seconds
Started Jul 02 08:14:12 AM PDT 24
Finished Jul 02 08:14:43 AM PDT 24
Peak memory 213060 kb
Host smart-91006563-e5a5-4603-9f66-12dca6e520fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974150829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.1974150829
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.746154356
Short name T1311
Test name
Test status
Simulation time 747446052 ps
CPU time 2.33 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:22 AM PDT 24
Peak memory 205004 kb
Host smart-ff032f5f-5ede-4978-af60-e3e558c0ba02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746154356 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 47.i2c_target_bad_addr.746154356
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.27422502
Short name T1368
Test name
Test status
Simulation time 164989027 ps
CPU time 1.06 seconds
Started Jul 02 08:14:15 AM PDT 24
Finished Jul 02 08:14:20 AM PDT 24
Peak memory 204592 kb
Host smart-438a6a83-dac5-4ee8-93b7-8cc5b5a91e42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27422502 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_acq.27422502
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.536038200
Short name T852
Test name
Test status
Simulation time 221264016 ps
CPU time 1.05 seconds
Started Jul 02 08:14:18 AM PDT 24
Finished Jul 02 08:14:23 AM PDT 24
Peak memory 204572 kb
Host smart-f66ecceb-7861-4056-bd45-91a575fab34f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536038200 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.i2c_target_fifo_reset_tx.536038200
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.202809923
Short name T1106
Test name
Test status
Simulation time 4429783068 ps
CPU time 2.2 seconds
Started Jul 02 08:14:20 AM PDT 24
Finished Jul 02 08:14:26 AM PDT 24
Peak memory 204828 kb
Host smart-1ffe5b75-ab4d-4a23-be3b-56c1de664e2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202809923 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.202809923
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.979878226
Short name T842
Test name
Test status
Simulation time 223039618 ps
CPU time 0.94 seconds
Started Jul 02 08:14:17 AM PDT 24
Finished Jul 02 08:14:22 AM PDT 24
Peak memory 204596 kb
Host smart-ba8eebc0-e272-4c2a-9b23-7c2df97d9b2a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979878226 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.979878226
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.2418124362
Short name T646
Test name
Test status
Simulation time 1023969837 ps
CPU time 5.22 seconds
Started Jul 02 08:14:17 AM PDT 24
Finished Jul 02 08:14:26 AM PDT 24
Peak memory 214492 kb
Host smart-c2788792-b7d1-4937-a682-e705ab609b75
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418124362 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.2418124362
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.1522643068
Short name T474
Test name
Test status
Simulation time 14569799668 ps
CPU time 17.86 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:37 AM PDT 24
Peak memory 494608 kb
Host smart-96dfc629-a65e-424f-b5a8-9da5d79a3b7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522643068 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.1522643068
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.2483565106
Short name T166
Test name
Test status
Simulation time 1569020513 ps
CPU time 17.41 seconds
Started Jul 02 08:14:15 AM PDT 24
Finished Jul 02 08:14:36 AM PDT 24
Peak memory 204796 kb
Host smart-32c8facf-f9b9-4c1d-9770-aa8fdd33c414
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483565106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_smoke.2483565106
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.150494775
Short name T1087
Test name
Test status
Simulation time 256405724 ps
CPU time 3.96 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:24 AM PDT 24
Peak memory 204808 kb
Host smart-7806c456-5621-4b3c-bc2b-bcef0eeb32a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150494775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c
_target_stress_rd.150494775
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.1770996189
Short name T417
Test name
Test status
Simulation time 14553393009 ps
CPU time 13.6 seconds
Started Jul 02 08:14:12 AM PDT 24
Finished Jul 02 08:14:28 AM PDT 24
Peak memory 204920 kb
Host smart-a5470112-78bb-4bbf-8809-14fc2efcda7a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770996189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.1770996189
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.4042880827
Short name T1534
Test name
Test status
Simulation time 11145000648 ps
CPU time 109.49 seconds
Started Jul 02 08:14:17 AM PDT 24
Finished Jul 02 08:16:10 AM PDT 24
Peak memory 1363008 kb
Host smart-ad9531a1-e8d3-4744-a354-435613dc26cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042880827 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_
target_stretch.4042880827
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.1823465552
Short name T330
Test name
Test status
Simulation time 1181103682 ps
CPU time 6.81 seconds
Started Jul 02 08:14:18 AM PDT 24
Finished Jul 02 08:14:28 AM PDT 24
Peak memory 216728 kb
Host smart-ad8388d6-02b2-4ef2-a8b0-01ec39e4fde6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823465552 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.i2c_target_timeout.1823465552
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.1444066833
Short name T469
Test name
Test status
Simulation time 59867589 ps
CPU time 1.45 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:14:21 AM PDT 24
Peak memory 204804 kb
Host smart-44952163-b2ef-482f-b300-21c25e2489b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444066833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.1444066833
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.847375809
Short name T1382
Test name
Test status
Simulation time 21868119 ps
CPU time 0.63 seconds
Started Jul 02 08:14:29 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 204668 kb
Host smart-db344b98-32fc-4ecf-9a70-53b61b5bbbff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847375809 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.847375809
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.2207693776
Short name T883
Test name
Test status
Simulation time 166790729 ps
CPU time 1.57 seconds
Started Jul 02 08:14:24 AM PDT 24
Finished Jul 02 08:14:28 AM PDT 24
Peak memory 212992 kb
Host smart-72dd2085-7023-4d2e-a26a-d42945817799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207693776 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.2207693776
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.1897937100
Short name T300
Test name
Test status
Simulation time 321496667 ps
CPU time 6.91 seconds
Started Jul 02 08:14:21 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 273032 kb
Host smart-6a1cfed6-b05c-4dd2-a858-b8dd89681887
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897937100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.1897937100
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2353889595
Short name T68
Test name
Test status
Simulation time 2263907398 ps
CPU time 142.3 seconds
Started Jul 02 08:14:18 AM PDT 24
Finished Jul 02 08:16:45 AM PDT 24
Peak memory 702432 kb
Host smart-095cbb8a-f2b1-4aa1-a04c-ba8e77d4eaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353889595 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2353889595
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.2791996603
Short name T1154
Test name
Test status
Simulation time 2623764643 ps
CPU time 103.59 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:16:03 AM PDT 24
Peak memory 858084 kb
Host smart-af88bc01-06d5-4e4c-abdc-ccca2bc5f954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791996603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.2791996603
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.638873599
Short name T552
Test name
Test status
Simulation time 102532765 ps
CPU time 0.91 seconds
Started Jul 02 08:14:17 AM PDT 24
Finished Jul 02 08:14:21 AM PDT 24
Peak memory 204348 kb
Host smart-55918e14-d772-4128-8fcd-5e9a6f5ae01b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638873599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.638873599
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.1578260174
Short name T869
Test name
Test status
Simulation time 204047083 ps
CPU time 4.49 seconds
Started Jul 02 08:14:21 AM PDT 24
Finished Jul 02 08:14:29 AM PDT 24
Peak memory 204780 kb
Host smart-cb6fc373-9be5-4702-8e34-6fc8813c51a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578260174 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx
.1578260174
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.913225444
Short name T401
Test name
Test status
Simulation time 4293464883 ps
CPU time 122.52 seconds
Started Jul 02 08:14:20 AM PDT 24
Finished Jul 02 08:16:26 AM PDT 24
Peak memory 1241744 kb
Host smart-599ea916-719a-45fd-ab4c-342b4f9e73f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913225444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.913225444
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.2477824766
Short name T39
Test name
Test status
Simulation time 1091366633 ps
CPU time 3.47 seconds
Started Jul 02 08:14:24 AM PDT 24
Finished Jul 02 08:14:30 AM PDT 24
Peak memory 204824 kb
Host smart-6e6773c8-b63d-45f8-bafe-3cb28e00fe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477824766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.2477824766
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.1743765822
Short name T740
Test name
Test status
Simulation time 12392226625 ps
CPU time 24.1 seconds
Started Jul 02 08:14:24 AM PDT 24
Finished Jul 02 08:14:50 AM PDT 24
Peak memory 344684 kb
Host smart-a963db3e-a072-4929-bac7-d426e491f7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743765822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.1743765822
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.3336447268
Short name T1193
Test name
Test status
Simulation time 76218636 ps
CPU time 0.7 seconds
Started Jul 02 08:14:17 AM PDT 24
Finished Jul 02 08:14:21 AM PDT 24
Peak memory 204516 kb
Host smart-eb39e8dd-fe28-4ee0-9a07-528c8cefc461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336447268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.3336447268
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.645375994
Short name T399
Test name
Test status
Simulation time 6399269219 ps
CPU time 69.22 seconds
Started Jul 02 08:14:20 AM PDT 24
Finished Jul 02 08:15:33 AM PDT 24
Peak memory 670732 kb
Host smart-f1b52f5d-ab37-4c54-ae5c-f846fdf3529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645375994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.645375994
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.1514236271
Short name T371
Test name
Test status
Simulation time 71871176 ps
CPU time 1.81 seconds
Started Jul 02 08:14:20 AM PDT 24
Finished Jul 02 08:14:25 AM PDT 24
Peak memory 204688 kb
Host smart-04b29782-ad9d-44f0-b9ae-c897e6a1a364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514236271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.1514236271
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2272052521
Short name T315
Test name
Test status
Simulation time 1664677591 ps
CPU time 77.51 seconds
Started Jul 02 08:14:16 AM PDT 24
Finished Jul 02 08:15:37 AM PDT 24
Peak memory 328880 kb
Host smart-bbe6ae83-c17b-4cc0-b3c7-aeb160ffe323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272052521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2272052521
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.1042539885
Short name T1166
Test name
Test status
Simulation time 116584881655 ps
CPU time 647.41 seconds
Started Jul 02 08:14:23 AM PDT 24
Finished Jul 02 08:25:13 AM PDT 24
Peak memory 2645692 kb
Host smart-ff345db2-13af-45bd-81b5-f253ad7c84b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042539885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.1042539885
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.2802769061
Short name T1189
Test name
Test status
Simulation time 713574970 ps
CPU time 11.42 seconds
Started Jul 02 08:14:26 AM PDT 24
Finished Jul 02 08:14:39 AM PDT 24
Peak memory 217312 kb
Host smart-a42f60ad-597f-421e-9eff-30f0485e4fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802769061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.2802769061
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.3003072438
Short name T1514
Test name
Test status
Simulation time 2964606982 ps
CPU time 4.22 seconds
Started Jul 02 08:14:24 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 213136 kb
Host smart-6881d324-a9c5-4ace-9112-b8c4d7ca142d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003072438 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.3003072438
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.3595941046
Short name T1342
Test name
Test status
Simulation time 205125077 ps
CPU time 0.96 seconds
Started Jul 02 08:14:24 AM PDT 24
Finished Jul 02 08:14:27 AM PDT 24
Peak memory 204604 kb
Host smart-6fecaf6d-41a8-42f4-b4cf-dfd07193c8fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595941046 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.3595941046
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.3959658316
Short name T1535
Test name
Test status
Simulation time 276308176 ps
CPU time 1.59 seconds
Started Jul 02 08:14:25 AM PDT 24
Finished Jul 02 08:14:29 AM PDT 24
Peak memory 204888 kb
Host smart-0a6dd9fc-fee1-4585-941f-b80fa91f897e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959658316 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.3959658316
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.134917947
Short name T905
Test name
Test status
Simulation time 1631363362 ps
CPU time 2.17 seconds
Started Jul 02 08:14:24 AM PDT 24
Finished Jul 02 08:14:29 AM PDT 24
Peak memory 204800 kb
Host smart-5c22b297-8467-4bc5-be74-44a4b3a1224d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134917947 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.134917947
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.3430940337
Short name T1509
Test name
Test status
Simulation time 139994452 ps
CPU time 1.2 seconds
Started Jul 02 08:14:29 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 204604 kb
Host smart-ef7dbcdc-0d13-4150-888f-8fa24eb2a435
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430940337 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.3430940337
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.2634894022
Short name T761
Test name
Test status
Simulation time 1780557253 ps
CPU time 3.48 seconds
Started Jul 02 08:14:22 AM PDT 24
Finished Jul 02 08:14:29 AM PDT 24
Peak memory 204832 kb
Host smart-2687a434-3b5c-4aa1-a8e8-d6efb2ef6583
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634894022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.2634894022
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.3814742530
Short name T1465
Test name
Test status
Simulation time 957522749 ps
CPU time 4.95 seconds
Started Jul 02 08:14:24 AM PDT 24
Finished Jul 02 08:14:32 AM PDT 24
Peak memory 213016 kb
Host smart-81efe61a-04ac-4851-8cac-57f83a2a1f81
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814742530 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_intr_smoke.3814742530
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.4176950595
Short name T881
Test name
Test status
Simulation time 26118621189 ps
CPU time 25.39 seconds
Started Jul 02 08:14:22 AM PDT 24
Finished Jul 02 08:14:51 AM PDT 24
Peak memory 732076 kb
Host smart-11b58131-00d3-4f10-823a-fbdc3a9450a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176950595 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.4176950595
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2414221794
Short name T827
Test name
Test status
Simulation time 1176338335 ps
CPU time 20.23 seconds
Started Jul 02 08:14:23 AM PDT 24
Finished Jul 02 08:14:46 AM PDT 24
Peak memory 204836 kb
Host smart-3a9ba1df-e28c-451e-a458-eaa40e0545eb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414221794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2414221794
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.3049540855
Short name T752
Test name
Test status
Simulation time 1559999813 ps
CPU time 4.48 seconds
Started Jul 02 08:14:25 AM PDT 24
Finished Jul 02 08:14:32 AM PDT 24
Peak memory 204800 kb
Host smart-24c6e05f-40f1-4b97-900f-e07983614b5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049540855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.3049540855
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.2098580664
Short name T892
Test name
Test status
Simulation time 15957571719 ps
CPU time 9.42 seconds
Started Jul 02 08:14:22 AM PDT 24
Finished Jul 02 08:14:35 AM PDT 24
Peak memory 204912 kb
Host smart-411c0e1e-4161-45b3-848f-81c268ff7190
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098580664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.2098580664
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.4175447039
Short name T418
Test name
Test status
Simulation time 3018827099 ps
CPU time 8.09 seconds
Started Jul 02 08:14:23 AM PDT 24
Finished Jul 02 08:14:34 AM PDT 24
Peak memory 221168 kb
Host smart-18e14507-4b55-4c07-82d9-05cbf8f667f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175447039 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 48.i2c_target_timeout.4175447039
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.2393793842
Short name T1001
Test name
Test status
Simulation time 280978868 ps
CPU time 3.78 seconds
Started Jul 02 08:14:33 AM PDT 24
Finished Jul 02 08:14:38 AM PDT 24
Peak memory 204788 kb
Host smart-9520d09d-5144-4f8d-a061-de098a5bbe8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393793842 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.2393793842
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.1477691785
Short name T1400
Test name
Test status
Simulation time 15607178 ps
CPU time 0.65 seconds
Started Jul 02 08:14:34 AM PDT 24
Finished Jul 02 08:14:36 AM PDT 24
Peak memory 204392 kb
Host smart-d2ef74e0-f1cd-456a-a9da-1b6494007fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477691785 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.1477691785
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.2684819469
Short name T941
Test name
Test status
Simulation time 69014879 ps
CPU time 1.24 seconds
Started Jul 02 08:14:28 AM PDT 24
Finished Jul 02 08:14:30 AM PDT 24
Peak memory 213052 kb
Host smart-c3677549-7694-4465-9fb8-a2c3454f8428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684819469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.2684819469
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.1741678163
Short name T816
Test name
Test status
Simulation time 1863367503 ps
CPU time 5.21 seconds
Started Jul 02 08:14:26 AM PDT 24
Finished Jul 02 08:14:33 AM PDT 24
Peak memory 262160 kb
Host smart-b37c7f0b-45db-4c88-bf48-65df0b92a8e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741678163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_emp
ty.1741678163
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.55453987
Short name T532
Test name
Test status
Simulation time 8266600012 ps
CPU time 84.6 seconds
Started Jul 02 08:14:32 AM PDT 24
Finished Jul 02 08:15:58 AM PDT 24
Peak memory 761984 kb
Host smart-a2de4313-aaa8-4af9-bbc1-4c89f8de5101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55453987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.55453987
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.1843193755
Short name T542
Test name
Test status
Simulation time 5939534929 ps
CPU time 46.81 seconds
Started Jul 02 08:14:31 AM PDT 24
Finished Jul 02 08:15:19 AM PDT 24
Peak memory 550496 kb
Host smart-03f7ff0a-6987-4d35-a0d4-0f31e0607276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843193755 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.1843193755
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.4009700798
Short name T243
Test name
Test status
Simulation time 902531984 ps
CPU time 1.1 seconds
Started Jul 02 08:14:32 AM PDT 24
Finished Jul 02 08:14:34 AM PDT 24
Peak memory 204440 kb
Host smart-6b7cd44f-7b52-4732-9e90-d17c8fb24a59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009700798 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_f
mt.4009700798
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.2730142472
Short name T240
Test name
Test status
Simulation time 614511528 ps
CPU time 8.04 seconds
Started Jul 02 08:14:27 AM PDT 24
Finished Jul 02 08:14:37 AM PDT 24
Peak memory 204748 kb
Host smart-1184a7c7-5d02-4ce0-bc20-f4206de89a9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730142472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.2730142472
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.3719280837
Short name T1289
Test name
Test status
Simulation time 8858814569 ps
CPU time 133.44 seconds
Started Jul 02 08:14:31 AM PDT 24
Finished Jul 02 08:16:45 AM PDT 24
Peak memory 1284964 kb
Host smart-1e5f4be6-125e-4d1d-915b-b01201ff1aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719280837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.3719280837
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.1392626565
Short name T1493
Test name
Test status
Simulation time 3058341100 ps
CPU time 23.56 seconds
Started Jul 02 08:14:33 AM PDT 24
Finished Jul 02 08:14:58 AM PDT 24
Peak memory 204836 kb
Host smart-c3d4d48b-6f58-466c-a3ed-43c41bc4f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392626565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.1392626565
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.3139583930
Short name T1186
Test name
Test status
Simulation time 6423409829 ps
CPU time 77.09 seconds
Started Jul 02 08:14:34 AM PDT 24
Finished Jul 02 08:15:52 AM PDT 24
Peak memory 357716 kb
Host smart-26158ae7-626b-40d2-ae41-833539fe5a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139583930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.3139583930
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.820833244
Short name T252
Test name
Test status
Simulation time 14912451 ps
CPU time 0.66 seconds
Started Jul 02 08:14:27 AM PDT 24
Finished Jul 02 08:14:28 AM PDT 24
Peak memory 204516 kb
Host smart-5c81e454-f0f1-48fc-ad61-5be87e45554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820833244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.820833244
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.448969295
Short name T364
Test name
Test status
Simulation time 1017347450 ps
CPU time 7.35 seconds
Started Jul 02 08:14:28 AM PDT 24
Finished Jul 02 08:14:37 AM PDT 24
Peak memory 204824 kb
Host smart-b29c7599-6abc-4c08-9679-ddaef2f7baa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448969295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.448969295
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.18355818
Short name T598
Test name
Test status
Simulation time 105817609 ps
CPU time 1.15 seconds
Started Jul 02 08:14:28 AM PDT 24
Finished Jul 02 08:14:31 AM PDT 24
Peak memory 204656 kb
Host smart-9723a183-4f9d-40ef-a764-ec8d1618de22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18355818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.18355818
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.4095321154
Short name T1307
Test name
Test status
Simulation time 12633142319 ps
CPU time 97.56 seconds
Started Jul 02 08:14:32 AM PDT 24
Finished Jul 02 08:16:11 AM PDT 24
Peak memory 422888 kb
Host smart-8c90290e-b5d9-490b-9a2a-d1a69cf231fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095321154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.4095321154
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.1024659058
Short name T495
Test name
Test status
Simulation time 2576525266 ps
CPU time 11.49 seconds
Started Jul 02 08:14:30 AM PDT 24
Finished Jul 02 08:14:42 AM PDT 24
Peak memory 213080 kb
Host smart-7eda74a6-e1e4-440f-aa32-a6c62eb99aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024659058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.1024659058
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.709220130
Short name T693
Test name
Test status
Simulation time 2725236969 ps
CPU time 3.96 seconds
Started Jul 02 08:14:34 AM PDT 24
Finished Jul 02 08:14:40 AM PDT 24
Peak memory 204888 kb
Host smart-6b27a713-0952-4a99-bd15-5b99f61bc9a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709220130 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.709220130
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2530950674
Short name T846
Test name
Test status
Simulation time 678084366 ps
CPU time 1.2 seconds
Started Jul 02 08:14:30 AM PDT 24
Finished Jul 02 08:14:33 AM PDT 24
Peak memory 204800 kb
Host smart-49e26f4f-7af2-4de3-9859-bbf5f7fea80b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530950674 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2530950674
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.472813300
Short name T1167
Test name
Test status
Simulation time 157337284 ps
CPU time 1.04 seconds
Started Jul 02 08:14:30 AM PDT 24
Finished Jul 02 08:14:32 AM PDT 24
Peak memory 204584 kb
Host smart-c6ae2300-2d83-4a5e-9583-377cf44d39aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472813300 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.i2c_target_fifo_reset_tx.472813300
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.880691805
Short name T667
Test name
Test status
Simulation time 1475616694 ps
CPU time 2.16 seconds
Started Jul 02 08:14:35 AM PDT 24
Finished Jul 02 08:14:38 AM PDT 24
Peak memory 204732 kb
Host smart-0db0ce69-0b82-4827-9666-7ab33ae4b617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880691805 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.880691805
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.2068694261
Short name T1271
Test name
Test status
Simulation time 526794578 ps
CPU time 0.86 seconds
Started Jul 02 08:14:32 AM PDT 24
Finished Jul 02 08:14:34 AM PDT 24
Peak memory 204852 kb
Host smart-62b9c072-bd49-4a0a-ac08-00663ccea5e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068694261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.2068694261
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.1220497277
Short name T832
Test name
Test status
Simulation time 3995182419 ps
CPU time 3.09 seconds
Started Jul 02 08:14:36 AM PDT 24
Finished Jul 02 08:14:40 AM PDT 24
Peak memory 204868 kb
Host smart-27efd498-56ae-4ed3-b19c-1443b72ee5a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220497277 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.1220497277
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.962858408
Short name T1174
Test name
Test status
Simulation time 10163681362 ps
CPU time 7.58 seconds
Started Jul 02 08:14:28 AM PDT 24
Finished Jul 02 08:14:37 AM PDT 24
Peak memory 205488 kb
Host smart-0c1ebbe3-9f85-4cdd-b06e-3d625cdc68a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962858408 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_intr_smoke.962858408
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1627513744
Short name T463
Test name
Test status
Simulation time 5306875817 ps
CPU time 42.68 seconds
Started Jul 02 08:14:30 AM PDT 24
Finished Jul 02 08:15:14 AM PDT 24
Peak memory 1213704 kb
Host smart-e58ba324-d4fd-4275-9bd9-4b19ddbfda5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627513744 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1627513744
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.2117606781
Short name T1529
Test name
Test status
Simulation time 12176544655 ps
CPU time 17.09 seconds
Started Jul 02 08:14:28 AM PDT 24
Finished Jul 02 08:14:46 AM PDT 24
Peak memory 204992 kb
Host smart-0e322bea-f759-4848-a978-b2bf39603a03
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117606781 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_ta
rget_smoke.2117606781
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.479630327
Short name T968
Test name
Test status
Simulation time 1630238136 ps
CPU time 68.12 seconds
Started Jul 02 08:14:31 AM PDT 24
Finished Jul 02 08:15:40 AM PDT 24
Peak memory 207336 kb
Host smart-54c337c0-0e27-4148-a354-870fd1a21300
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479630327 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.479630327
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.3476442611
Short name T506
Test name
Test status
Simulation time 30269544993 ps
CPU time 25.92 seconds
Started Jul 02 08:14:29 AM PDT 24
Finished Jul 02 08:14:56 AM PDT 24
Peak memory 583132 kb
Host smart-56ac2616-8672-4741-9a4a-111b9a805904
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476442611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2
c_target_stress_wr.3476442611
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.2143650365
Short name T1338
Test name
Test status
Simulation time 5515240225 ps
CPU time 59.79 seconds
Started Jul 02 08:14:29 AM PDT 24
Finished Jul 02 08:15:30 AM PDT 24
Peak memory 450812 kb
Host smart-044d04a4-92b6-45ee-a2d6-d913fd21dc42
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143650365 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_
target_stretch.2143650365
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3204000130
Short name T619
Test name
Test status
Simulation time 2290889892 ps
CPU time 8.06 seconds
Started Jul 02 08:14:28 AM PDT 24
Finished Jul 02 08:14:38 AM PDT 24
Peak memory 221028 kb
Host smart-2c329c63-355a-4c6d-bb16-2e56280dd27f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204000130 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3204000130
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.1559285614
Short name T705
Test name
Test status
Simulation time 39088286 ps
CPU time 1.04 seconds
Started Jul 02 08:14:33 AM PDT 24
Finished Jul 02 08:14:36 AM PDT 24
Peak memory 204832 kb
Host smart-fbf76d83-f1d5-4171-a15e-3ddd8f43c375
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559285614 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.1559285614
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.2504892194
Short name T1112
Test name
Test status
Simulation time 37799433 ps
CPU time 0.66 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:09:39 AM PDT 24
Peak memory 204472 kb
Host smart-86be8d4d-05b6-4a85-814b-f0e8f17b6120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504892194 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.2504892194
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.2094433335
Short name T42
Test name
Test status
Simulation time 377704665 ps
CPU time 1.28 seconds
Started Jul 02 08:09:32 AM PDT 24
Finished Jul 02 08:09:37 AM PDT 24
Peak memory 204932 kb
Host smart-4da09e5e-2c0c-4b3e-ae0a-7c2770d8db20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094433335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.2094433335
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.4059026132
Short name T1433
Test name
Test status
Simulation time 191570889 ps
CPU time 3.94 seconds
Started Jul 02 08:09:24 AM PDT 24
Finished Jul 02 08:09:30 AM PDT 24
Peak memory 223128 kb
Host smart-205f18ab-013e-423f-b04f-a53610db522a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059026132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.4059026132
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.781777357
Short name T386
Test name
Test status
Simulation time 1267226518 ps
CPU time 83.83 seconds
Started Jul 02 08:09:23 AM PDT 24
Finished Jul 02 08:10:48 AM PDT 24
Peak memory 516620 kb
Host smart-f134677a-22dd-4449-996f-8fc9b4794b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781777357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.781777357
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.2580826986
Short name T1164
Test name
Test status
Simulation time 123524518 ps
CPU time 0.96 seconds
Started Jul 02 08:09:23 AM PDT 24
Finished Jul 02 08:09:26 AM PDT 24
Peak memory 204432 kb
Host smart-e08b2368-659e-4790-b015-6da07e800c7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580826986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.2580826986
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.1910504011
Short name T1427
Test name
Test status
Simulation time 225207392 ps
CPU time 11.02 seconds
Started Jul 02 08:09:24 AM PDT 24
Finished Jul 02 08:09:37 AM PDT 24
Peak memory 204840 kb
Host smart-f47d9c13-57b8-4f58-8edb-dab9e12cbddb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910504011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
1910504011
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.958475344
Short name T273
Test name
Test status
Simulation time 9681053219 ps
CPU time 390.77 seconds
Started Jul 02 08:09:22 AM PDT 24
Finished Jul 02 08:15:55 AM PDT 24
Peak memory 1387748 kb
Host smart-31b85af0-34b3-4042-b3c6-172692202b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958475344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.958475344
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.99865095
Short name T128
Test name
Test status
Simulation time 481692389 ps
CPU time 19.5 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:09:57 AM PDT 24
Peak memory 204876 kb
Host smart-0ec82621-5b00-413e-bf8f-ae168e273faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99865095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.99865095
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.310696978
Short name T632
Test name
Test status
Simulation time 3210844934 ps
CPU time 24.81 seconds
Started Jul 02 08:09:24 AM PDT 24
Finished Jul 02 08:09:51 AM PDT 24
Peak memory 359464 kb
Host smart-ecac00d9-d547-4230-92b3-a9ddbc9e548b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310696978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.310696978
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.3555078830
Short name T1080
Test name
Test status
Simulation time 40961563 ps
CPU time 0.65 seconds
Started Jul 02 08:09:19 AM PDT 24
Finished Jul 02 08:09:22 AM PDT 24
Peak memory 204480 kb
Host smart-0701129f-9569-402b-b963-8ae4eabe9f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555078830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.3555078830
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.4175001964
Short name T55
Test name
Test status
Simulation time 51808590580 ps
CPU time 119.21 seconds
Started Jul 02 08:09:32 AM PDT 24
Finished Jul 02 08:11:36 AM PDT 24
Peak memory 746824 kb
Host smart-cb5a5dcc-0281-49b8-8ffa-1548d77a88fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175001964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.4175001964
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.903923607
Short name T517
Test name
Test status
Simulation time 545996477 ps
CPU time 5.64 seconds
Started Jul 02 08:09:25 AM PDT 24
Finished Jul 02 08:09:32 AM PDT 24
Peak memory 204668 kb
Host smart-e83e5b8b-cefd-4ee1-add2-82cbb969a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903923607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.903923607
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3163291922
Short name T295
Test name
Test status
Simulation time 10291908209 ps
CPU time 25.76 seconds
Started Jul 02 08:09:16 AM PDT 24
Finished Jul 02 08:09:44 AM PDT 24
Peak memory 286296 kb
Host smart-aa5700c4-0078-43bd-b2cb-9e3837234c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163291922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3163291922
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.1926378108
Short name T284
Test name
Test status
Simulation time 13210726802 ps
CPU time 1545.99 seconds
Started Jul 02 08:09:23 AM PDT 24
Finished Jul 02 08:35:11 AM PDT 24
Peak memory 3182608 kb
Host smart-a5709692-da66-4281-a527-dd2a24bbee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926378108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.1926378108
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.118237250
Short name T293
Test name
Test status
Simulation time 2665859549 ps
CPU time 30.9 seconds
Started Jul 02 08:09:24 AM PDT 24
Finished Jul 02 08:09:57 AM PDT 24
Peak memory 213124 kb
Host smart-64aa6e3d-124c-473d-87f5-d8e4cfea59d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118237250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.118237250
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.4150140657
Short name T1407
Test name
Test status
Simulation time 600167348 ps
CPU time 3.3 seconds
Started Jul 02 08:09:25 AM PDT 24
Finished Jul 02 08:09:30 AM PDT 24
Peak memory 204796 kb
Host smart-06290e2a-589f-4eff-8f86-80df162a4a9d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150140657 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.4150140657
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.377566285
Short name T582
Test name
Test status
Simulation time 454454895 ps
CPU time 1.17 seconds
Started Jul 02 08:09:25 AM PDT 24
Finished Jul 02 08:09:28 AM PDT 24
Peak memory 204580 kb
Host smart-b8d6267e-c736-470d-9154-de1ab06793f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377566285 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.377566285
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.3575324623
Short name T1156
Test name
Test status
Simulation time 253286158 ps
CPU time 1.02 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:09:40 AM PDT 24
Peak memory 204544 kb
Host smart-b605e613-1973-47ca-97ed-e956c2e358fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575324623 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.3575324623
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.1505841285
Short name T1422
Test name
Test status
Simulation time 7794025064 ps
CPU time 2.11 seconds
Started Jul 02 08:09:22 AM PDT 24
Finished Jul 02 08:09:26 AM PDT 24
Peak memory 204908 kb
Host smart-be756fbb-5a16-41dd-81bc-352eb68700f1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505841285 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.1505841285
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.2888955547
Short name T808
Test name
Test status
Simulation time 357670558 ps
CPU time 1.17 seconds
Started Jul 02 08:09:26 AM PDT 24
Finished Jul 02 08:09:29 AM PDT 24
Peak memory 204552 kb
Host smart-1223b084-d66c-4679-a672-0d781466981b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888955547 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.2888955547
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.1235881523
Short name T250
Test name
Test status
Simulation time 1235914744 ps
CPU time 2.71 seconds
Started Jul 02 08:09:27 AM PDT 24
Finished Jul 02 08:09:32 AM PDT 24
Peak memory 204540 kb
Host smart-39ac131c-23ae-4c27-ab24-c89294f08d02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235881523 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.1235881523
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.1127317990
Short name T838
Test name
Test status
Simulation time 630343071 ps
CPU time 3.94 seconds
Started Jul 02 08:09:27 AM PDT 24
Finished Jul 02 08:09:33 AM PDT 24
Peak memory 204580 kb
Host smart-e9858eeb-eb1c-4721-87ec-88aa506ba2b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127317990 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.1127317990
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.3829948854
Short name T1489
Test name
Test status
Simulation time 8541426938 ps
CPU time 16.5 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:09:56 AM PDT 24
Peak memory 343172 kb
Host smart-f3f6300a-d1f4-4fab-b06a-cd0051b7deb0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829948854 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.3829948854
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.2802573601
Short name T1314
Test name
Test status
Simulation time 1356176985 ps
CPU time 54.48 seconds
Started Jul 02 08:09:22 AM PDT 24
Finished Jul 02 08:10:18 AM PDT 24
Peak memory 204808 kb
Host smart-d31fd397-45e4-4d61-afa3-7014ce82264c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802573601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.2802573601
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3156107548
Short name T256
Test name
Test status
Simulation time 1257502522 ps
CPU time 21.77 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:10:01 AM PDT 24
Peak memory 220568 kb
Host smart-e0563888-0603-4724-9d90-eca7bd6cfd08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156107548 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3156107548
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.2634170173
Short name T1477
Test name
Test status
Simulation time 14663916126 ps
CPU time 8.17 seconds
Started Jul 02 08:09:23 AM PDT 24
Finished Jul 02 08:09:32 AM PDT 24
Peak memory 204932 kb
Host smart-945e5643-b3bd-4799-90ec-3b731ef87122
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634170173 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.2634170173
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3082580379
Short name T6
Test name
Test status
Simulation time 43521546705 ps
CPU time 55.9 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:10:35 AM PDT 24
Peak memory 749716 kb
Host smart-ae650a16-4141-4ff9-9693-a488fb9e3c90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082580379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3082580379
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2884319638
Short name T468
Test name
Test status
Simulation time 2853614989 ps
CPU time 6.53 seconds
Started Jul 02 08:09:22 AM PDT 24
Finished Jul 02 08:09:30 AM PDT 24
Peak memory 213332 kb
Host smart-96543aa7-c38d-4fa3-a824-df1cfefbd3c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884319638 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2884319638
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.2958118557
Short name T597
Test name
Test status
Simulation time 360405937 ps
CPU time 4.87 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:09:45 AM PDT 24
Peak memory 204756 kb
Host smart-5cb54ddc-dfff-47fa-81a1-55fa437702ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958118557 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.2958118557
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2996653701
Short name T1016
Test name
Test status
Simulation time 73186943 ps
CPU time 0.66 seconds
Started Jul 02 08:09:30 AM PDT 24
Finished Jul 02 08:09:34 AM PDT 24
Peak memory 204460 kb
Host smart-d81e4c91-a1a1-40cc-bc99-3e48ea402afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996653701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2996653701
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.723993642
Short name T1459
Test name
Test status
Simulation time 590851294 ps
CPU time 1.65 seconds
Started Jul 02 08:09:40 AM PDT 24
Finished Jul 02 08:09:44 AM PDT 24
Peak memory 213176 kb
Host smart-93c2c600-f9f6-4b64-9148-45d0a972426c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723993642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.723993642
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.3102313951
Short name T1103
Test name
Test status
Simulation time 974176516 ps
CPU time 12.79 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:09:50 AM PDT 24
Peak memory 253524 kb
Host smart-9e3f10d8-294f-4342-ae9e-37c75707f966
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102313951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empt
y.3102313951
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.3403358957
Short name T362
Test name
Test status
Simulation time 55713213160 ps
CPU time 95.79 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:11:14 AM PDT 24
Peak memory 810520 kb
Host smart-c9967de4-0e67-4dfd-9392-730224fb1b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403358957 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.3403358957
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3719436428
Short name T893
Test name
Test status
Simulation time 1375757987 ps
CPU time 40.81 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:10:20 AM PDT 24
Peak memory 543444 kb
Host smart-e0d77d75-fc53-4c3c-b12b-8a6bd60f8a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719436428 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3719436428
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.4015869197
Short name T851
Test name
Test status
Simulation time 137886662 ps
CPU time 1.07 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:09:39 AM PDT 24
Peak memory 204464 kb
Host smart-2b94db89-988b-41e3-9b27-84904fcaf747
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015869197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fm
t.4015869197
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.834856430
Short name T1070
Test name
Test status
Simulation time 748734582 ps
CPU time 5.12 seconds
Started Jul 02 08:09:21 AM PDT 24
Finished Jul 02 08:09:28 AM PDT 24
Peak memory 242180 kb
Host smart-a76948a3-3f63-4d36-87cb-df843e866974
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834856430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.834856430
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2996371256
Short name T98
Test name
Test status
Simulation time 19584345976 ps
CPU time 68.38 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:10:48 AM PDT 24
Peak memory 960484 kb
Host smart-ad1d32af-a62e-4697-97df-340a01a2467a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996371256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2996371256
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1611273732
Short name T1141
Test name
Test status
Simulation time 359370230 ps
CPU time 5.44 seconds
Started Jul 02 08:09:30 AM PDT 24
Finished Jul 02 08:09:39 AM PDT 24
Peak memory 204596 kb
Host smart-b0673a89-b0ba-4a84-9005-6989cb87d6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611273732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1611273732
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.1461430774
Short name T1253
Test name
Test status
Simulation time 1240885161 ps
CPU time 19.47 seconds
Started Jul 02 08:09:40 AM PDT 24
Finished Jul 02 08:10:02 AM PDT 24
Peak memory 347880 kb
Host smart-f3778f1e-ba6b-452a-92d4-c57009b941d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461430774 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.1461430774
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_perf.1595082563
Short name T1511
Test name
Test status
Simulation time 7179701219 ps
CPU time 153.21 seconds
Started Jul 02 08:09:23 AM PDT 24
Finished Jul 02 08:11:58 AM PDT 24
Peak memory 204820 kb
Host smart-1056c2d1-e5cf-41e7-8c1a-5db623a14e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595082563 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.1595082563
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.301770777
Short name T301
Test name
Test status
Simulation time 150311266 ps
CPU time 3.15 seconds
Started Jul 02 08:09:22 AM PDT 24
Finished Jul 02 08:09:27 AM PDT 24
Peak memory 218392 kb
Host smart-f7a45860-7ff1-4c14-8980-34d610735391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301770777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.301770777
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.1494656012
Short name T1380
Test name
Test status
Simulation time 2310908401 ps
CPU time 18.47 seconds
Started Jul 02 08:09:27 AM PDT 24
Finished Jul 02 08:09:47 AM PDT 24
Peak memory 330756 kb
Host smart-98923e31-7088-4c01-a7a5-dfe58112ce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494656012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.1494656012
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.3466761983
Short name T247
Test name
Test status
Simulation time 28056389107 ps
CPU time 1495.79 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:34:34 AM PDT 24
Peak memory 2971156 kb
Host smart-539a0dfc-2e14-4c27-b8a5-bfbf43076f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466761983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.3466761983
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.2806676460
Short name T403
Test name
Test status
Simulation time 2998106172 ps
CPU time 16.45 seconds
Started Jul 02 08:09:23 AM PDT 24
Finished Jul 02 08:09:41 AM PDT 24
Peak memory 217252 kb
Host smart-599fedc3-182f-433e-bb0e-30695edeea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806676460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.2806676460
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.4011023403
Short name T606
Test name
Test status
Simulation time 1571410996 ps
CPU time 5.54 seconds
Started Jul 02 08:09:29 AM PDT 24
Finished Jul 02 08:09:37 AM PDT 24
Peak memory 213088 kb
Host smart-adf3c639-389c-4ea3-b1af-de0055fafb1d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011023403 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.4011023403
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.2471002795
Short name T153
Test name
Test status
Simulation time 425906016 ps
CPU time 1.09 seconds
Started Jul 02 08:09:28 AM PDT 24
Finished Jul 02 08:09:31 AM PDT 24
Peak memory 204608 kb
Host smart-337ca26d-eb8b-4c67-b097-967aa6555e4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471002795 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.2471002795
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.1889162715
Short name T904
Test name
Test status
Simulation time 772438748 ps
CPU time 1.41 seconds
Started Jul 02 08:09:29 AM PDT 24
Finished Jul 02 08:09:32 AM PDT 24
Peak memory 208124 kb
Host smart-0f8e72e6-616d-49ba-b5fa-13aa52cbf05b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889162715 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.1889162715
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.4062028152
Short name T805
Test name
Test status
Simulation time 490062847 ps
CPU time 2.61 seconds
Started Jul 02 08:09:29 AM PDT 24
Finished Jul 02 08:09:35 AM PDT 24
Peak memory 204792 kb
Host smart-547af29e-73ef-4b10-bc85-19a46ba957d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062028152 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.4062028152
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.2278906868
Short name T1019
Test name
Test status
Simulation time 302964944 ps
CPU time 1.2 seconds
Started Jul 02 08:09:28 AM PDT 24
Finished Jul 02 08:09:32 AM PDT 24
Peak memory 204544 kb
Host smart-fdd09266-fd13-40b7-9934-cb39c40df856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278906868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.2278906868
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.2593538953
Short name T835
Test name
Test status
Simulation time 404332594 ps
CPU time 4.47 seconds
Started Jul 02 08:09:30 AM PDT 24
Finished Jul 02 08:09:38 AM PDT 24
Peak memory 204808 kb
Host smart-689b5469-8074-4e3d-8ea8-dcb145392d2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593538953 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.2593538953
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.4082826301
Short name T1531
Test name
Test status
Simulation time 4126886104 ps
CPU time 5.88 seconds
Started Jul 02 08:09:29 AM PDT 24
Finished Jul 02 08:09:39 AM PDT 24
Peak memory 218720 kb
Host smart-56b5e51f-b01d-4bef-97ad-15788523a010
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082826301 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.4082826301
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.2935159262
Short name T1302
Test name
Test status
Simulation time 9234312592 ps
CPU time 26.97 seconds
Started Jul 02 08:09:28 AM PDT 24
Finished Jul 02 08:09:57 AM PDT 24
Peak memory 591076 kb
Host smart-d70c2e7f-d551-4051-801d-6662cf8f671e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935159262 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.2935159262
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.202332412
Short name T834
Test name
Test status
Simulation time 4597616864 ps
CPU time 43.32 seconds
Started Jul 02 08:09:32 AM PDT 24
Finished Jul 02 08:10:19 AM PDT 24
Peak memory 204900 kb
Host smart-4e54db7e-69ab-4a6f-8d40-1a794f40b037
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202332412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_targ
et_smoke.202332412
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.365802398
Short name T255
Test name
Test status
Simulation time 1218307038 ps
CPU time 20.51 seconds
Started Jul 02 08:09:28 AM PDT 24
Finished Jul 02 08:09:51 AM PDT 24
Peak memory 230544 kb
Host smart-583adb02-6017-4227-bb5d-fe1a476c4b02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365802398 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_
target_stress_rd.365802398
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1543356271
Short name T1279
Test name
Test status
Simulation time 60769224336 ps
CPU time 609.29 seconds
Started Jul 02 08:09:29 AM PDT 24
Finished Jul 02 08:19:41 AM PDT 24
Peak memory 5084092 kb
Host smart-f1497428-1fde-46fb-9313-c88df6089b6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543356271 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1543356271
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.1178521041
Short name T623
Test name
Test status
Simulation time 11121269521 ps
CPU time 52.66 seconds
Started Jul 02 08:09:30 AM PDT 24
Finished Jul 02 08:10:26 AM PDT 24
Peak memory 644060 kb
Host smart-a403c24d-cea8-4533-8f05-38aa2565e3b4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178521041 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_t
arget_stretch.1178521041
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.2052089288
Short name T577
Test name
Test status
Simulation time 4902180409 ps
CPU time 7.59 seconds
Started Jul 02 08:09:29 AM PDT 24
Finished Jul 02 08:09:40 AM PDT 24
Peak memory 219180 kb
Host smart-9c127914-686e-458e-89ae-1e6a17b9791f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052089288 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.2052089288
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.1887713135
Short name T1506
Test name
Test status
Simulation time 421286013 ps
CPU time 5.24 seconds
Started Jul 02 08:09:29 AM PDT 24
Finished Jul 02 08:09:36 AM PDT 24
Peak memory 204840 kb
Host smart-d86bc59c-3de1-4860-958b-41849a976cb1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887713135 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.1887713135
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.3772683994
Short name T910
Test name
Test status
Simulation time 16067054 ps
CPU time 0.64 seconds
Started Jul 02 08:09:40 AM PDT 24
Finished Jul 02 08:09:43 AM PDT 24
Peak memory 204492 kb
Host smart-782085e8-7ee2-433a-8fb3-6babbfdbd7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772683994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.3772683994
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2914793672
Short name T1452
Test name
Test status
Simulation time 175093646 ps
CPU time 2.42 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:09:42 AM PDT 24
Peak memory 213144 kb
Host smart-d33cc5cb-0fd1-4915-819b-68dcf0801427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914793672 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2914793672
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.803793583
Short name T1287
Test name
Test status
Simulation time 486187631 ps
CPU time 4.72 seconds
Started Jul 02 08:09:36 AM PDT 24
Finished Jul 02 08:09:45 AM PDT 24
Peak memory 257496 kb
Host smart-b8a96c18-a3e4-41f5-9d1d-f7e0887fb495
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803793583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.803793583
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.2396342572
Short name T649
Test name
Test status
Simulation time 1547926984 ps
CPU time 100.88 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:11:19 AM PDT 24
Peak memory 547400 kb
Host smart-4284f3f8-75bb-4877-97d4-bd0ff6650e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396342572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.2396342572
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.2770364275
Short name T1470
Test name
Test status
Simulation time 2361444979 ps
CPU time 73.64 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:10:51 AM PDT 24
Peak memory 786656 kb
Host smart-259f3f12-3982-41a6-925d-49476c940f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770364275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.2770364275
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.4078025455
Short name T1432
Test name
Test status
Simulation time 158527059 ps
CPU time 1.01 seconds
Started Jul 02 08:09:42 AM PDT 24
Finished Jul 02 08:09:45 AM PDT 24
Peak memory 204484 kb
Host smart-a37a9dbf-0009-4a16-949c-da583cf34830
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078025455 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fm
t.4078025455
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.3566903627
Short name T465
Test name
Test status
Simulation time 450933044 ps
CPU time 5.44 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:09:44 AM PDT 24
Peak memory 204828 kb
Host smart-8c0b0bd3-b947-4aa5-b29e-734fe174a4c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566903627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.
3566903627
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3212888253
Short name T660
Test name
Test status
Simulation time 103385773137 ps
CPU time 358.26 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:15:38 AM PDT 24
Peak memory 1356268 kb
Host smart-1c33be82-54a9-4c45-9eba-f711ef07fc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212888253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3212888253
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.237544541
Short name T498
Test name
Test status
Simulation time 2919114889 ps
CPU time 4.62 seconds
Started Jul 02 08:09:42 AM PDT 24
Finished Jul 02 08:09:49 AM PDT 24
Peak memory 204880 kb
Host smart-666d9173-1ac7-462c-a7c2-9ded2f450b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237544541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.237544541
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.1193116418
Short name T1301
Test name
Test status
Simulation time 2175932092 ps
CPU time 92.59 seconds
Started Jul 02 08:09:31 AM PDT 24
Finished Jul 02 08:11:08 AM PDT 24
Peak memory 355060 kb
Host smart-f2bd3083-194b-424c-b2c6-41ad23f3aa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193116418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.1193116418
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.4258697008
Short name T66
Test name
Test status
Simulation time 26050605 ps
CPU time 0.68 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:09:39 AM PDT 24
Peak memory 204496 kb
Host smart-54b27405-cc56-4bda-a81b-8ccf79e23391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258697008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.4258697008
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.483875335
Short name T1090
Test name
Test status
Simulation time 7280948328 ps
CPU time 27.52 seconds
Started Jul 02 08:09:37 AM PDT 24
Finished Jul 02 08:10:09 AM PDT 24
Peak memory 237316 kb
Host smart-58193b0c-4a47-48d6-ab47-4b0a039a830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483875335 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.483875335
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.1768539152
Short name T185
Test name
Test status
Simulation time 2526766868 ps
CPU time 47.51 seconds
Started Jul 02 08:09:42 AM PDT 24
Finished Jul 02 08:10:32 AM PDT 24
Peak memory 205760 kb
Host smart-224d86e7-38ed-49a5-96a5-49c19691dba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768539152 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.1768539152
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.248947381
Short name T1430
Test name
Test status
Simulation time 8436991690 ps
CPU time 38.68 seconds
Started Jul 02 08:09:31 AM PDT 24
Finished Jul 02 08:10:14 AM PDT 24
Peak memory 349604 kb
Host smart-bd97a5c9-0666-4087-bbd7-8f0e90ced63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248947381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.248947381
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.657541336
Short name T118
Test name
Test status
Simulation time 47580307110 ps
CPU time 366.68 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:15:47 AM PDT 24
Peak memory 1786640 kb
Host smart-0173046a-7df2-4b7d-9662-6f14709432d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657541336 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.657541336
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.2950692472
Short name T913
Test name
Test status
Simulation time 669485192 ps
CPU time 12.05 seconds
Started Jul 02 08:09:42 AM PDT 24
Finished Jul 02 08:09:56 AM PDT 24
Peak memory 213000 kb
Host smart-dbe4fbf0-217e-436e-8dca-67d22f17955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950692472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.2950692472
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.908853491
Short name T1100
Test name
Test status
Simulation time 4131730293 ps
CPU time 5.07 seconds
Started Jul 02 08:09:42 AM PDT 24
Finished Jul 02 08:09:49 AM PDT 24
Peak memory 215236 kb
Host smart-4c472628-a866-4a9d-b7c3-62f4e4e2e965
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908853491 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.908853491
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.270762790
Short name T1002
Test name
Test status
Simulation time 215793732 ps
CPU time 1.34 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:09:41 AM PDT 24
Peak memory 204836 kb
Host smart-7980e239-2601-45d1-b716-db06c716475c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270762790 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.270762790
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3264420575
Short name T459
Test name
Test status
Simulation time 256117023 ps
CPU time 1.52 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:09:42 AM PDT 24
Peak memory 212964 kb
Host smart-6a9d32e8-c286-4b08-aee4-f7bd45eb0709
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264420575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3264420575
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.1182535433
Short name T1321
Test name
Test status
Simulation time 532255517 ps
CPU time 2.82 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:09:42 AM PDT 24
Peak memory 204764 kb
Host smart-ef37cccd-6ba8-4aae-886e-186a99cfb1f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182535433 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.1182535433
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.2260261608
Short name T712
Test name
Test status
Simulation time 447143285 ps
CPU time 1.01 seconds
Started Jul 02 08:09:38 AM PDT 24
Finished Jul 02 08:09:43 AM PDT 24
Peak memory 204616 kb
Host smart-27d3a112-825d-4c38-9aeb-bf5de48b97ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260261608 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.2260261608
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.1103826896
Short name T1161
Test name
Test status
Simulation time 3627408344 ps
CPU time 5.65 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:09:46 AM PDT 24
Peak memory 215972 kb
Host smart-641529df-4e5d-4462-b2d5-67a86f3a0596
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103826896 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.1103826896
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2130948650
Short name T824
Test name
Test status
Simulation time 20911825990 ps
CPU time 52.42 seconds
Started Jul 02 08:09:34 AM PDT 24
Finished Jul 02 08:10:31 AM PDT 24
Peak memory 861728 kb
Host smart-73ee1f27-028b-45f4-89c2-ad3456e3ce6f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130948650 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2130948650
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.560277549
Short name T1537
Test name
Test status
Simulation time 4619776479 ps
CPU time 47.72 seconds
Started Jul 02 08:09:33 AM PDT 24
Finished Jul 02 08:10:26 AM PDT 24
Peak memory 204980 kb
Host smart-f5d4163b-f771-4ca3-99f3-97c2f97e4fc5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560277549 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_targ
et_smoke.560277549
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.2179443590
Short name T30
Test name
Test status
Simulation time 9469777394 ps
CPU time 29.55 seconds
Started Jul 02 08:09:36 AM PDT 24
Finished Jul 02 08:10:11 AM PDT 24
Peak memory 226048 kb
Host smart-ffdc6d08-f876-4e31-acec-660b91d76711
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179443590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_rd.2179443590
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.4263771656
Short name T731
Test name
Test status
Simulation time 44138932219 ps
CPU time 262.2 seconds
Started Jul 02 08:09:35 AM PDT 24
Finished Jul 02 08:14:02 AM PDT 24
Peak memory 2985652 kb
Host smart-0c450c2f-7e59-4600-8728-6e390651d19c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263771656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c
_target_stress_wr.4263771656
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.1387074859
Short name T811
Test name
Test status
Simulation time 1409092276 ps
CPU time 7.25 seconds
Started Jul 02 08:09:37 AM PDT 24
Finished Jul 02 08:09:49 AM PDT 24
Peak memory 213000 kb
Host smart-2bf4d9f7-bec8-4c3c-ab20-9914792e998b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387074859 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.1387074859
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.287051269
Short name T518
Test name
Test status
Simulation time 301883364 ps
CPU time 4.21 seconds
Started Jul 02 08:09:38 AM PDT 24
Finished Jul 02 08:09:46 AM PDT 24
Peak memory 204820 kb
Host smart-e3c4ab15-82dd-45b1-9cad-67a5fd059e5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287051269 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.287051269
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.891004859
Short name T687
Test name
Test status
Simulation time 15028134 ps
CPU time 0.61 seconds
Started Jul 02 08:09:47 AM PDT 24
Finished Jul 02 08:09:50 AM PDT 24
Peak memory 204484 kb
Host smart-06dc1c6f-d0ce-477e-b959-754995aec952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891004859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.891004859
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3531177573
Short name T1033
Test name
Test status
Simulation time 506231101 ps
CPU time 2.24 seconds
Started Jul 02 08:09:40 AM PDT 24
Finished Jul 02 08:09:45 AM PDT 24
Peak memory 213088 kb
Host smart-5019e010-b017-4604-aeb0-10811e1b36a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531177573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3531177573
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.989237168
Short name T1296
Test name
Test status
Simulation time 1952523821 ps
CPU time 8.99 seconds
Started Jul 02 08:09:48 AM PDT 24
Finished Jul 02 08:09:59 AM PDT 24
Peak memory 314600 kb
Host smart-1c6e86fd-6830-4352-ba79-dc9b2bc26928
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989237168 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empty
.989237168
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.157287503
Short name T1438
Test name
Test status
Simulation time 3878705242 ps
CPU time 65.47 seconds
Started Jul 02 08:09:42 AM PDT 24
Finished Jul 02 08:10:50 AM PDT 24
Peak memory 668584 kb
Host smart-791a7537-cbd2-4ee7-a5c6-7e92453ccb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157287503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.157287503
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.2541500725
Short name T1136
Test name
Test status
Simulation time 3394867997 ps
CPU time 106.52 seconds
Started Jul 02 08:09:38 AM PDT 24
Finished Jul 02 08:11:28 AM PDT 24
Peak memory 565880 kb
Host smart-b6455d3f-cbc7-4391-a10c-1319cd4c1aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541500725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.2541500725
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.1574889971
Short name T51
Test name
Test status
Simulation time 132141522 ps
CPU time 1.13 seconds
Started Jul 02 08:09:42 AM PDT 24
Finished Jul 02 08:09:45 AM PDT 24
Peak memory 204452 kb
Host smart-e23e5b37-998c-4060-b642-aceee35dfa2c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574889971 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fm
t.1574889971
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.4023392660
Short name T766
Test name
Test status
Simulation time 2216222548 ps
CPU time 4.18 seconds
Started Jul 02 08:09:40 AM PDT 24
Finished Jul 02 08:09:47 AM PDT 24
Peak memory 204856 kb
Host smart-8ed1cb53-885c-4771-8b13-de67813c0467
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023392660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.
4023392660
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.188085808
Short name T1091
Test name
Test status
Simulation time 14504059924 ps
CPU time 89.25 seconds
Started Jul 02 08:09:40 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 971956 kb
Host smart-1e162e29-063b-4f46-82d9-f54057e84130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188085808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.188085808
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.1971994643
Short name T428
Test name
Test status
Simulation time 637941548 ps
CPU time 5.1 seconds
Started Jul 02 08:09:47 AM PDT 24
Finished Jul 02 08:09:54 AM PDT 24
Peak memory 204824 kb
Host smart-a438c65e-d869-4495-a36d-55c94a25a4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971994643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.1971994643
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.852835701
Short name T353
Test name
Test status
Simulation time 2422078807 ps
CPU time 121.5 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:11:49 AM PDT 24
Peak memory 516448 kb
Host smart-b4805c9c-eda0-49e9-bbd9-b31e7f703944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852835701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.852835701
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.1126500159
Short name T573
Test name
Test status
Simulation time 46602855 ps
CPU time 0.65 seconds
Started Jul 02 08:09:39 AM PDT 24
Finished Jul 02 08:09:43 AM PDT 24
Peak memory 204500 kb
Host smart-b5957ab1-18c3-4a3f-8adb-00437eb3a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126500159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.1126500159
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1033372758
Short name T1261
Test name
Test status
Simulation time 47756453613 ps
CPU time 1863.48 seconds
Started Jul 02 08:09:40 AM PDT 24
Finished Jul 02 08:40:47 AM PDT 24
Peak memory 204964 kb
Host smart-099509f4-a943-4b56-b25a-5215b37444dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033372758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1033372758
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.405108815
Short name T1525
Test name
Test status
Simulation time 1818659445 ps
CPU time 2.15 seconds
Started Jul 02 08:09:40 AM PDT 24
Finished Jul 02 08:09:45 AM PDT 24
Peak memory 204696 kb
Host smart-352ff198-340b-48c3-b85b-b1d978e3c26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405108815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.405108815
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.3561096691
Short name T1208
Test name
Test status
Simulation time 1921272116 ps
CPU time 81.23 seconds
Started Jul 02 08:09:42 AM PDT 24
Finished Jul 02 08:11:06 AM PDT 24
Peak memory 353944 kb
Host smart-8655d6b3-71b4-48d8-b26d-4b5c8ec73826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561096691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.3561096691
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.2269453319
Short name T608
Test name
Test status
Simulation time 115106206997 ps
CPU time 1293 seconds
Started Jul 02 08:09:39 AM PDT 24
Finished Jul 02 08:31:16 AM PDT 24
Peak memory 3765844 kb
Host smart-91572e30-32a2-424c-90e9-ddf307267d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269453319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.2269453319
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.442239673
Short name T392
Test name
Test status
Simulation time 1050345857 ps
CPU time 18.41 seconds
Started Jul 02 08:09:39 AM PDT 24
Finished Jul 02 08:10:01 AM PDT 24
Peak memory 220592 kb
Host smart-e4649844-4ac5-421e-a0e4-2233bf17f271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442239673 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.442239673
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.3242762196
Short name T341
Test name
Test status
Simulation time 1116431462 ps
CPU time 5.54 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:09:54 AM PDT 24
Peak memory 213332 kb
Host smart-091522bf-e830-4f3d-be10-a4408e0ca5c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242762196 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.3242762196
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.2916368250
Short name T1177
Test name
Test status
Simulation time 176948705 ps
CPU time 0.91 seconds
Started Jul 02 08:09:47 AM PDT 24
Finished Jul 02 08:09:49 AM PDT 24
Peak memory 204632 kb
Host smart-4a24232d-a6fa-4ba9-833a-847a6290d323
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916368250 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.2916368250
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.1391143017
Short name T1318
Test name
Test status
Simulation time 242788997 ps
CPU time 0.84 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:09:49 AM PDT 24
Peak memory 204600 kb
Host smart-c5b467f7-1214-45b8-b4ba-b6f1c1ef90e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391143017 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.1391143017
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.476870192
Short name T1064
Test name
Test status
Simulation time 657447317 ps
CPU time 3.41 seconds
Started Jul 02 08:10:09 AM PDT 24
Finished Jul 02 08:10:14 AM PDT 24
Peak memory 204796 kb
Host smart-1848e3f1-e025-40cd-b0c9-8717d90df8e8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476870192 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.476870192
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.3713447860
Short name T587
Test name
Test status
Simulation time 115326266 ps
CPU time 1.18 seconds
Started Jul 02 08:09:47 AM PDT 24
Finished Jul 02 08:09:50 AM PDT 24
Peak memory 204552 kb
Host smart-68c9e7fd-5270-445d-bf9a-fefbb3c09de4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713447860 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.3713447860
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.3826290815
Short name T703
Test name
Test status
Simulation time 510369521 ps
CPU time 2.85 seconds
Started Jul 02 08:09:45 AM PDT 24
Finished Jul 02 08:09:49 AM PDT 24
Peak memory 204776 kb
Host smart-42c3bc5b-57da-46b8-8d9e-b2e09c352a82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826290815 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.3826290815
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.59704793
Short name T1017
Test name
Test status
Simulation time 1297031581 ps
CPU time 4.04 seconds
Started Jul 02 08:09:48 AM PDT 24
Finished Jul 02 08:09:54 AM PDT 24
Peak memory 204748 kb
Host smart-5a925db0-c3e5-4220-9f38-ab881c7bca2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59704793 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_intr_smoke.59704793
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.2948019086
Short name T995
Test name
Test status
Simulation time 25092225107 ps
CPU time 58.49 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:10:47 AM PDT 24
Peak memory 1252840 kb
Host smart-16307bfe-23b7-41d5-8e06-db4c875481b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948019086 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.2948019086
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.576008012
Short name T270
Test name
Test status
Simulation time 743931492 ps
CPU time 12.38 seconds
Started Jul 02 08:09:39 AM PDT 24
Finished Jul 02 08:09:55 AM PDT 24
Peak memory 205052 kb
Host smart-930f6d3a-3666-4355-933a-38a7ff5d65be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576008012 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_targ
et_smoke.576008012
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.4041387163
Short name T124
Test name
Test status
Simulation time 8388560476 ps
CPU time 68.21 seconds
Started Jul 02 08:09:49 AM PDT 24
Finished Jul 02 08:11:00 AM PDT 24
Peak memory 209544 kb
Host smart-779e3bfb-6337-4130-9996-d35dc7e2f127
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041387163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.4041387163
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.567974284
Short name T1131
Test name
Test status
Simulation time 10214738719 ps
CPU time 18.68 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:10:07 AM PDT 24
Peak memory 204924 kb
Host smart-cd2538b6-0f39-451b-91c3-031d4c17277c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567974284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_
target_stress_wr.567974284
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.504616695
Short name T1180
Test name
Test status
Simulation time 27390560664 ps
CPU time 1319.95 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:31:48 AM PDT 24
Peak memory 3354096 kb
Host smart-0815d0a3-9e28-400a-a4b6-a8eeee3adc5f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504616695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_ta
rget_stretch.504616695
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.3887665829
Short name T402
Test name
Test status
Simulation time 4987018481 ps
CPU time 7.4 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:09:55 AM PDT 24
Peak memory 213224 kb
Host smart-932403fc-3dd5-4620-a202-f79fe728a554
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887665829 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.3887665829
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.4114611195
Short name T753
Test name
Test status
Simulation time 104616324 ps
CPU time 2.28 seconds
Started Jul 02 08:09:45 AM PDT 24
Finished Jul 02 08:09:49 AM PDT 24
Peak memory 204788 kb
Host smart-890c4ebe-71ea-4145-8f35-7db8b7d7d34f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114611195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.4114611195
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.161587613
Short name T423
Test name
Test status
Simulation time 96250846 ps
CPU time 0.64 seconds
Started Jul 02 08:09:53 AM PDT 24
Finished Jul 02 08:09:55 AM PDT 24
Peak memory 204264 kb
Host smart-e9e6fa6b-7080-4e79-ae52-6df08f615651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161587613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.161587613
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.462004863
Short name T1226
Test name
Test status
Simulation time 193522249 ps
CPU time 1.16 seconds
Started Jul 02 08:09:49 AM PDT 24
Finished Jul 02 08:09:52 AM PDT 24
Peak memory 213108 kb
Host smart-6d6621c7-8707-44e0-add0-6ce269d593d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462004863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.462004863
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.2857733684
Short name T139
Test name
Test status
Simulation time 3674605511 ps
CPU time 8.77 seconds
Started Jul 02 08:09:45 AM PDT 24
Finished Jul 02 08:09:55 AM PDT 24
Peak memory 306792 kb
Host smart-853b6f7e-d253-48b7-ad0a-10f93a27a6c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857733684 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.2857733684
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.1822128371
Short name T569
Test name
Test status
Simulation time 4528682164 ps
CPU time 78.03 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:11:05 AM PDT 24
Peak memory 696016 kb
Host smart-16b6fa9a-733a-4a62-a95f-0a23dcd7bb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822128371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.1822128371
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.3404943486
Short name T1129
Test name
Test status
Simulation time 2531059693 ps
CPU time 191.35 seconds
Started Jul 02 08:09:47 AM PDT 24
Finished Jul 02 08:13:00 AM PDT 24
Peak memory 806284 kb
Host smart-aad27260-0c05-4a4e-a6f2-31e4f4e59406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404943486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.3404943486
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.1914690475
Short name T1152
Test name
Test status
Simulation time 74905203 ps
CPU time 0.88 seconds
Started Jul 02 08:09:48 AM PDT 24
Finished Jul 02 08:09:51 AM PDT 24
Peak memory 204472 kb
Host smart-ebb24e30-b578-44ec-934b-d169b792647b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914690475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fm
t.1914690475
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3460834556
Short name T635
Test name
Test status
Simulation time 144067053 ps
CPU time 3.94 seconds
Started Jul 02 08:09:48 AM PDT 24
Finished Jul 02 08:09:53 AM PDT 24
Peak memory 228892 kb
Host smart-ad295e38-5233-4f05-9231-5f66d3434236
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460834556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3460834556
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.2227406892
Short name T999
Test name
Test status
Simulation time 7440505056 ps
CPU time 235.63 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:13:44 AM PDT 24
Peak memory 1096724 kb
Host smart-b2dd8a49-ba35-430e-8c2e-7d4345dee0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227406892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.2227406892
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.234463823
Short name T1127
Test name
Test status
Simulation time 862390070 ps
CPU time 5.52 seconds
Started Jul 02 08:09:51 AM PDT 24
Finished Jul 02 08:09:58 AM PDT 24
Peak memory 204820 kb
Host smart-928624af-7914-4ae2-b508-7b8ddabb94dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234463823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.234463823
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.323125140
Short name T56
Test name
Test status
Simulation time 4745030870 ps
CPU time 55.38 seconds
Started Jul 02 08:09:51 AM PDT 24
Finished Jul 02 08:10:49 AM PDT 24
Peak memory 311624 kb
Host smart-444d3109-2fe2-449f-95c8-618b62258623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323125140 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.323125140
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.157526165
Short name T382
Test name
Test status
Simulation time 48928184 ps
CPU time 0.67 seconds
Started Jul 02 08:09:45 AM PDT 24
Finished Jul 02 08:09:47 AM PDT 24
Peak memory 204516 kb
Host smart-62f18469-bcec-443e-a81e-1a0dfe132a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157526165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.157526165
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.2599334879
Short name T1451
Test name
Test status
Simulation time 60913504 ps
CPU time 2.63 seconds
Started Jul 02 08:09:49 AM PDT 24
Finished Jul 02 08:09:53 AM PDT 24
Peak memory 205328 kb
Host smart-1985c798-220d-4bec-800d-c37377f0e1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599334879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.2599334879
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.3024575217
Short name T937
Test name
Test status
Simulation time 1149436592 ps
CPU time 15.78 seconds
Started Jul 02 08:09:46 AM PDT 24
Finished Jul 02 08:10:04 AM PDT 24
Peak memory 278376 kb
Host smart-d074bf15-d610-4397-bf0b-8f388337f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024575217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.3024575217
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.1938449498
Short name T988
Test name
Test status
Simulation time 55212641867 ps
CPU time 609.95 seconds
Started Jul 02 08:09:47 AM PDT 24
Finished Jul 02 08:19:59 AM PDT 24
Peak memory 932120 kb
Host smart-f780f36e-c514-42dc-b837-61e81d830bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938449498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.1938449498
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.2062497823
Short name T460
Test name
Test status
Simulation time 828934611 ps
CPU time 13.65 seconds
Started Jul 02 08:09:49 AM PDT 24
Finished Jul 02 08:10:05 AM PDT 24
Peak memory 217944 kb
Host smart-3512b091-8a10-4f98-a55d-808f661360bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062497823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.2062497823
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.245750501
Short name T1354
Test name
Test status
Simulation time 3314481462 ps
CPU time 3.98 seconds
Started Jul 02 08:09:51 AM PDT 24
Finished Jul 02 08:09:57 AM PDT 24
Peak memory 204796 kb
Host smart-98a08a66-5f4c-4178-bb1e-db7d6c1dedfc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245750501 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.245750501
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.1174069050
Short name T13
Test name
Test status
Simulation time 253920758 ps
CPU time 0.82 seconds
Started Jul 02 08:09:52 AM PDT 24
Finished Jul 02 08:09:54 AM PDT 24
Peak memory 204536 kb
Host smart-fc45ca1f-ee21-471f-82f9-b370dca6aedb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174069050 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.1174069050
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.4242934775
Short name T1185
Test name
Test status
Simulation time 383620444 ps
CPU time 0.98 seconds
Started Jul 02 08:09:55 AM PDT 24
Finished Jul 02 08:09:57 AM PDT 24
Peak memory 204524 kb
Host smart-f6020b92-5b65-4963-8500-72453989a546
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242934775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.i2c_target_fifo_reset_tx.4242934775
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.2325177399
Short name T1359
Test name
Test status
Simulation time 275955309 ps
CPU time 1.68 seconds
Started Jul 02 08:09:58 AM PDT 24
Finished Jul 02 08:10:02 AM PDT 24
Peak memory 204104 kb
Host smart-08c71036-78a8-4c60-ae55-70a7e1e6c404
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325177399 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.2325177399
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.1860160315
Short name T1126
Test name
Test status
Simulation time 3393479847 ps
CPU time 1.43 seconds
Started Jul 02 08:09:51 AM PDT 24
Finished Jul 02 08:09:54 AM PDT 24
Peak memory 204632 kb
Host smart-cc5f59b4-efbf-4e61-b151-75ae07289fd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860160315 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.1860160315
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.3016609301
Short name T340
Test name
Test status
Simulation time 3741473451 ps
CPU time 4.43 seconds
Started Jul 02 08:09:56 AM PDT 24
Finished Jul 02 08:10:02 AM PDT 24
Peak memory 204916 kb
Host smart-5bce73d8-1f08-4f43-a742-7c8b6192b3b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016609301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.3016609301
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.3993682606
Short name T1404
Test name
Test status
Simulation time 3877850325 ps
CPU time 4.96 seconds
Started Jul 02 08:09:50 AM PDT 24
Finished Jul 02 08:09:57 AM PDT 24
Peak memory 204832 kb
Host smart-b59de4d0-8656-4ebb-8738-e87422ed7684
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993682606 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_intr_smoke.3993682606
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.1571821993
Short name T1191
Test name
Test status
Simulation time 10312876232 ps
CPU time 45.38 seconds
Started Jul 02 08:09:54 AM PDT 24
Finished Jul 02 08:10:42 AM PDT 24
Peak memory 910180 kb
Host smart-2035c4ff-1355-44e7-bcfe-6562f9b23780
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571821993 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.1571821993
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.3045198910
Short name T992
Test name
Test status
Simulation time 4402927055 ps
CPU time 39.43 seconds
Started Jul 02 08:09:53 AM PDT 24
Finished Jul 02 08:10:34 AM PDT 24
Peak memory 204884 kb
Host smart-d6c3b7f8-1359-411a-b59b-a377ba6a3a86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045198910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_tar
get_smoke.3045198910
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.1709335833
Short name T369
Test name
Test status
Simulation time 1492838325 ps
CPU time 16.16 seconds
Started Jul 02 08:09:50 AM PDT 24
Finished Jul 02 08:10:09 AM PDT 24
Peak memory 204728 kb
Host smart-b689e477-d863-4271-b961-8c095a721f89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709335833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.1709335833
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.4004635448
Short name T684
Test name
Test status
Simulation time 23757251551 ps
CPU time 74.24 seconds
Started Jul 02 08:09:56 AM PDT 24
Finished Jul 02 08:11:12 AM PDT 24
Peak memory 1048220 kb
Host smart-32ef0b24-5dfd-4b97-b7f3-a9e709602592
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004635448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_wr.4004635448
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.2979024934
Short name T641
Test name
Test status
Simulation time 17577975410 ps
CPU time 945.78 seconds
Started Jul 02 08:09:55 AM PDT 24
Finished Jul 02 08:25:43 AM PDT 24
Peak memory 4321992 kb
Host smart-7ef74072-0b1c-4bdf-bca9-1cb3f2f93656
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979024934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.2979024934
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.1380486776
Short name T1200
Test name
Test status
Simulation time 1630472382 ps
CPU time 7.98 seconds
Started Jul 02 08:09:53 AM PDT 24
Finished Jul 02 08:10:03 AM PDT 24
Peak memory 221052 kb
Host smart-dc5f91e9-cf69-4836-a888-20a88b4f309e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380486776 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.i2c_target_timeout.1380486776
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.2556512693
Short name T938
Test name
Test status
Simulation time 160284892 ps
CPU time 2.68 seconds
Started Jul 02 08:09:54 AM PDT 24
Finished Jul 02 08:09:59 AM PDT 24
Peak memory 204764 kb
Host smart-d4abe5a8-2499-467a-8a57-460b3ab05d52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556512693 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.2556512693
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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