Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	931977	1			T1	3		T2	202		T3	9
all_values[1]	931977	1			T1	3		T2	202		T3	9
all_values[2]	931977	1			T1	3		T2	202		T3	9
all_values[3]	931977	1			T1	3		T2	202		T3	9
all_values[4]	931977	1			T1	3		T2	202		T3	9
all_values[5]	931977	1			T1	3		T2	202		T3	9
all_values[6]	931977	1			T1	3		T2	202		T3	9
all_values[7]	931977	1			T1	3		T2	202		T3	9
all_values[8]	931977	1			T1	3		T2	202		T3	9
all_values[9]	931977	1			T1	3		T2	202		T3	9
all_values[10]	931977	1			T1	3		T2	202		T3	9
all_values[11]	931977	1			T1	3		T2	202		T3	9
all_values[12]	931977	1			T1	3		T2	202		T3	9
all_values[13]	931977	1			T1	3		T2	202		T3	9
all_values[14]	931977	1			T1	3		T2	202		T3	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11447089

1

T1

39

T2

2595

T3

135

auto[1]

2532566

1

T1

6

T2

435

T4

4

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12435416

1

T1

45

T2

3030

T3

135

auto[1]

1544239

1

T41

197

T37

354

T95

260

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	90040	1			T1	1		T2	6		T3	9
all_values[0]	auto[0]	auto[1]	9570	1			T37	16		T95	3		T122	541
all_values[0]	auto[1]	auto[0]	740510	1			T1	2		T2	196		T4	2
all_values[0]	auto[1]	auto[1]	91857	1			T41	15		T37	8		T95	3
all_values[1]	auto[0]	auto[0]	827360	1			T1	3		T2	202		T3	9
all_values[1]	auto[0]	auto[1]	104157	1			T41	12		T37	22		T95	18
all_values[1]	auto[1]	auto[0]	255	1			T47	4		T187	7		T87	8
all_values[1]	auto[1]	auto[1]	205	1			T41	3		T37	2		T95	1
all_values[2]	auto[0]	auto[0]	827855	1			T1	3		T2	202		T3	9
all_values[2]	auto[0]	auto[1]	103855	1			T41	13		T37	23		T95	17
all_values[2]	auto[1]	auto[0]	51	1			T10	1		T17	1		T252	1
all_values[2]	auto[1]	auto[1]	216	1			T41	2		T37	1		T95	2
all_values[3]	auto[0]	auto[0]	830807	1			T1	3		T2	202		T3	9
all_values[3]	auto[0]	auto[1]	100941	1			T41	11		T37	20		T95	16
all_values[3]	auto[1]	auto[1]	229	1			T41	3		T37	4		T95	4
all_values[4]	auto[0]	auto[0]	830515	1			T1	3		T2	202		T3	9
all_values[4]	auto[0]	auto[1]	101218	1			T41	12		T37	21		T95	16
all_values[4]	auto[1]	auto[0]	18	1			T253	1		T254	1		T255	2
all_values[4]	auto[1]	auto[1]	226	1			T41	2		T37	1		T95	3
all_values[5]	auto[0]	auto[0]	834537	1			T1	3		T2	202		T3	9
all_values[5]	auto[0]	auto[1]	97207	1			T41	11		T37	23		T95	2
all_values[5]	auto[1]	auto[1]	233	1			T41	3		T37	1		T95	3
all_values[6]	auto[0]	auto[0]	827336	1			T1	3		T2	202		T3	9
all_values[6]	auto[0]	auto[1]	104388	1			T41	11		T37	22		T95	18
all_values[6]	auto[1]	auto[1]	253	1			T41	3		T95	2		T122	6
all_values[7]	auto[0]	auto[0]	801140	1			T1	2		T2	175		T3	9
all_values[7]	auto[0]	auto[1]	97795	1			T37	18		T95	12		T122	9169
all_values[7]	auto[1]	auto[0]	29432	1			T1	1		T2	27		T32	319
all_values[7]	auto[1]	auto[1]	3610	1			T37	6		T95	7		T122	375
all_values[8]	auto[0]	auto[0]	830552	1			T1	3		T2	202		T3	9
all_values[8]	auto[0]	auto[1]	101193	1			T41	11		T37	22		T95	16
all_values[8]	auto[1]	auto[1]	232	1			T41	3		T37	2		T95	4
all_values[9]	auto[0]	auto[0]	184151	1			T1	2		T2	188		T3	9
all_values[9]	auto[0]	auto[1]	12041	1			T41	8		T37	18		T95	12
all_values[9]	auto[1]	auto[0]	643175	1			T1	1		T2	14		T6	1
all_values[9]	auto[1]	auto[1]	92610	1			T41	5		T37	6		T95	6
all_values[10]	auto[0]	auto[0]	827997	1			T1	3		T2	202		T3	9
all_values[10]	auto[0]	auto[1]	103772	1			T41	13		T37	21		T95	18
all_values[10]	auto[1]	auto[1]	208	1			T41	2		T37	3		T95	2
all_values[11]	auto[0]	auto[0]	2857	1			T1	1		T2	4		T3	9
all_values[11]	auto[0]	auto[1]	583	1			T37	15		T95	8		T122	11
all_values[11]	auto[1]	auto[0]	824519	1			T1	2		T2	198		T4	2
all_values[11]	auto[1]	auto[1]	104018	1			T41	13		T37	8		T95	11
all_values[12]	auto[0]	auto[0]	827316	1			T1	3		T2	202		T3	9
all_values[12]	auto[0]	auto[1]	104420	1			T41	14		T37	21		T95	16
all_values[12]	auto[1]	auto[0]	17	1			T256	1		T257	1		T258	1
all_values[12]	auto[1]	auto[1]	224	1			T41	1		T37	2		T95	4
all_values[13]	auto[0]	auto[0]	827350	1			T1	3		T2	202		T3	9
all_values[13]	auto[0]	auto[1]	104385	1			T41	11		T37	22		T95	17
all_values[13]	auto[1]	auto[1]	242	1			T41	2		T37	2		T95	1
all_values[14]	auto[0]	auto[0]	827626	1			T1	3		T2	202		T3	9
all_values[14]	auto[0]	auto[1]	104125	1			T41	11		T37	21		T95	15
all_values[14]	auto[1]	auto[1]	226	1			T41	2		T37	3		T95	3