Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	931977	1			T1	3		T2	202		T3	9
all_pins[1]	931977	1			T1	3		T2	202		T3	9
all_pins[2]	931977	1			T1	3		T2	202		T3	9
all_pins[3]	931977	1			T1	3		T2	202		T3	9
all_pins[4]	931977	1			T1	3		T2	202		T3	9
all_pins[5]	931977	1			T1	3		T2	202		T3	9
all_pins[6]	931977	1			T1	3		T2	202		T3	9
all_pins[7]	931977	1			T1	3		T2	202		T3	9
all_pins[8]	931977	1			T1	3		T2	202		T3	9
all_pins[9]	931977	1			T1	3		T2	202		T3	9
all_pins[10]	931977	1			T1	3		T2	202		T3	9
all_pins[11]	931977	1			T1	3		T2	202		T3	9
all_pins[12]	931977	1			T1	3		T2	202		T3	9
all_pins[13]	931977	1			T1	3		T2	202		T3	9
all_pins[14]	931977	1			T1	3		T2	202		T3	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	11452182	1			T1	39		T2	2594		T3	135
values[0x1]	2527473	1			T1	6		T2	436		T4	4
transitions[0x0=>0x1]	2526720	1			T1	6		T2	436		T4	4
transitions[0x1=>0x0]	2525520	1			T1	5		T2	435		T4	3

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	102871	1			T1	1		T2	6		T3	9
all_pins[0]	values[0x1]	829106	1			T1	2		T2	196		T4	2
all_pins[0]	transitions[0x0=>0x1]	828763	1			T1	2		T2	196		T4	2
all_pins[0]	transitions[0x1=>0x0]	69	1			T95	1		T122	1		T45	1
all_pins[1]	values[0x0]	931565	1			T1	3		T2	202		T3	9
all_pins[1]	values[0x1]	412	1			T47	4		T41	1		T187	9
all_pins[1]	transitions[0x0=>0x1]	393	1			T47	4		T41	1		T187	9
all_pins[1]	transitions[0x1=>0x0]	124	1			T10	1		T17	1		T41	1
all_pins[2]	values[0x0]	931834	1			T1	3		T2	202		T3	9
all_pins[2]	values[0x1]	143	1			T10	1		T17	1		T41	1
all_pins[2]	transitions[0x0=>0x1]	123	1			T10	1		T17	1		T41	1
all_pins[2]	transitions[0x1=>0x0]	86	1			T122	1		T46	1		T62	2
all_pins[3]	values[0x0]	931871	1			T1	3		T2	202		T3	9
all_pins[3]	values[0x1]	106	1			T122	1		T46	1		T62	2
all_pins[3]	transitions[0x0=>0x1]	75	1			T122	1		T46	1		T62	2
all_pins[3]	transitions[0x1=>0x0]	99	1			T41	1		T95	2		T122	3
all_pins[4]	values[0x0]	931847	1			T1	3		T2	202		T3	9
all_pins[4]	values[0x1]	130	1			T41	1		T95	2		T122	3
all_pins[4]	transitions[0x0=>0x1]	105	1			T41	1		T95	2		T122	3
all_pins[4]	transitions[0x1=>0x0]	104	1			T41	2		T95	3		T122	3
all_pins[5]	values[0x0]	931848	1			T1	3		T2	202		T3	9
all_pins[5]	values[0x1]	129	1			T41	2		T95	3		T122	3
all_pins[5]	transitions[0x0=>0x1]	95	1			T95	3		T122	2		T45	1
all_pins[5]	transitions[0x1=>0x0]	86	1			T95	1		T122	2		T46	3
all_pins[6]	values[0x0]	931857	1			T1	3		T2	202		T3	9
all_pins[6]	values[0x1]	120	1			T41	2		T95	1		T122	3
all_pins[6]	transitions[0x0=>0x1]	90	1			T41	2		T95	1		T45	1
all_pins[6]	transitions[0x1=>0x0]	36269	1			T1	1		T2	28		T32	330
all_pins[7]	values[0x0]	895678	1			T1	2		T2	174		T3	9
all_pins[7]	values[0x1]	36299	1			T1	1		T2	28		T32	330
all_pins[7]	transitions[0x0=>0x1]	36274	1			T1	1		T2	28		T32	330
all_pins[7]	transitions[0x1=>0x0]	79	1			T41	1		T95	2		T45	2
all_pins[8]	values[0x0]	931873	1			T1	3		T2	202		T3	9
all_pins[8]	values[0x1]	104	1			T41	1		T95	3		T122	2
all_pins[8]	transitions[0x0=>0x1]	78	1			T41	1		T95	3		T45	2
all_pins[8]	transitions[0x1=>0x0]	735675	1			T1	1		T2	14		T6	1
all_pins[9]	values[0x0]	196276	1			T1	2		T2	188		T3	9
all_pins[9]	values[0x1]	735701	1			T1	1		T2	14		T6	1
all_pins[9]	transitions[0x0=>0x1]	735673	1			T1	1		T2	14		T6	1
all_pins[9]	transitions[0x1=>0x0]	70	1			T95	1		T122	2		T46	6
all_pins[10]	values[0x0]	931879	1			T1	3		T2	202		T3	9
all_pins[10]	values[0x1]	98	1			T37	2		T95	1		T122	3
all_pins[10]	transitions[0x0=>0x1]	72	1			T37	1		T95	1		T122	3
all_pins[10]	transitions[0x1=>0x0]	924743	1			T1	2		T2	198		T4	2
all_pins[11]	values[0x0]	7208	1			T1	1		T2	4		T3	9
all_pins[11]	values[0x1]	924769	1			T1	2		T2	198		T4	2
all_pins[11]	transitions[0x0=>0x1]	924723	1			T1	2		T2	198		T4	2
all_pins[11]	transitions[0x1=>0x0]	83	1			T37	1		T95	1		T122	2
all_pins[12]	values[0x0]	931848	1			T1	3		T2	202		T3	9
all_pins[12]	values[0x1]	129	1			T10	1		T17	1		T37	2
all_pins[12]	transitions[0x0=>0x1]	100	1			T10	1		T17	1		T37	2
all_pins[12]	transitions[0x1=>0x0]	86	1			T41	2		T37	1		T95	1
all_pins[13]	values[0x0]	931862	1			T1	3		T2	202		T3	9
all_pins[13]	values[0x1]	115	1			T41	2		T37	1		T95	1
all_pins[13]	transitions[0x0=>0x1]	86	1			T41	2		T37	1		T95	1
all_pins[13]	transitions[0x1=>0x0]	83	1			T122	3		T45	2		T46	2
all_pins[14]	values[0x0]	931865	1			T1	3		T2	202		T3	9
all_pins[14]	values[0x1]	112	1			T122	3		T45	2		T46	2
all_pins[14]	transitions[0x0=>0x1]	70	1			T122	1		T45	2		T46	2
all_pins[14]	transitions[0x1=>0x0]	827864	1			T1	1		T2	195		T4	1