Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	523	1			T41	4		T37	4		T95	8
all_values[1]	523	1			T41	4		T37	4		T95	8
all_values[2]	523	1			T41	4		T37	4		T95	8
all_values[3]	523	1			T41	4		T37	4		T95	8
all_values[4]	523	1			T41	4		T37	4		T95	8
all_values[5]	523	1			T41	4		T37	4		T95	8
all_values[6]	523	1			T41	4		T37	4		T95	8
all_values[7]	523	1			T41	4		T37	4		T95	8
all_values[8]	523	1			T41	4		T37	4		T95	8
all_values[9]	523	1			T41	4		T37	4		T95	8
all_values[10]	523	1			T41	4		T37	4		T95	8
all_values[11]	523	1			T41	4		T37	4		T95	8
all_values[12]	523	1			T41	4		T37	4		T95	8
all_values[13]	523	1			T41	4		T37	4		T95	8
all_values[14]	523	1			T41	4		T37	4		T95	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4149

1

T41

25

T37

31

T95

64

auto[1]

3696

1

T41

35

T37

29

T95

56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1195

1

T41

17

T37

6

T95

20

auto[1]

6650

1

T41

43

T37

54

T95

100

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4668

1

T41

37

T37

31

T95

78

auto[1]

3177

1

T41

23

T37

29

T95

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	48	1			T45	1		T46	2		T43	1
all_values[0]	auto[0]	auto[0]	auto[1]	133	1			T41	1		T37	1		T122	4
all_values[0]	auto[0]	auto[1]	auto[0]	27	1			T95	4		T45	2		T62	1
all_values[0]	auto[0]	auto[1]	auto[1]	104	1			T41	1		T37	1		T95	1
all_values[0]	auto[1]	auto[0]	auto[1]	117	1			T37	2		T95	3		T122	3
all_values[0]	auto[1]	auto[1]	auto[1]	94	1			T41	2		T122	2		T46	3
all_values[1]	auto[0]	auto[0]	auto[0]	55	1			T95	1		T45	1		T123	2
all_values[1]	auto[0]	auto[0]	auto[1]	125	1			T41	1		T37	1		T95	3
all_values[1]	auto[0]	auto[1]	auto[0]	35	1			T122	2		T45	1		T112	2
all_values[1]	auto[0]	auto[1]	auto[1]	118	1			T37	1		T95	3		T122	2
all_values[1]	auto[1]	auto[0]	auto[1]	115	1			T41	2		T37	2		T122	1
all_values[1]	auto[1]	auto[1]	auto[1]	75	1			T41	1		T95	1		T122	3
all_values[2]	auto[0]	auto[0]	auto[0]	49	1			T45	2		T46	1		T51	1
all_values[2]	auto[0]	auto[0]	auto[1]	112	1			T37	1		T95	3		T122	2
all_values[2]	auto[0]	auto[1]	auto[0]	40	1			T95	1		T122	1		T45	2
all_values[2]	auto[0]	auto[1]	auto[1]	106	1			T41	2		T37	2		T95	2
all_values[2]	auto[1]	auto[0]	auto[1]	121	1			T37	1		T122	6		T45	1
all_values[2]	auto[1]	auto[1]	auto[1]	95	1			T41	2		T95	2		T122	1
all_values[3]	auto[0]	auto[0]	auto[0]	32	1			T45	1		T62	1		T123	1
all_values[3]	auto[0]	auto[0]	auto[1]	129	1			T41	1		T37	1		T95	5
all_values[3]	auto[0]	auto[1]	auto[0]	52	1			T41	1		T45	4		T62	3
all_values[3]	auto[0]	auto[1]	auto[1]	102	1			T95	1		T122	4		T45	1
all_values[3]	auto[1]	auto[0]	auto[1]	110	1			T41	2		T37	3		T95	2
all_values[3]	auto[1]	auto[1]	auto[1]	98	1			T122	2		T45	1		T46	2
all_values[4]	auto[0]	auto[0]	auto[0]	41	1			T46	2		T123	2		T271	3
all_values[4]	auto[0]	auto[0]	auto[1]	129	1			T41	1		T37	1		T95	2
all_values[4]	auto[0]	auto[1]	auto[0]	23	1			T41	1		T37	2		T95	1
all_values[4]	auto[0]	auto[1]	auto[1]	104	1			T95	2		T45	2		T46	4
all_values[4]	auto[1]	auto[0]	auto[1]	123	1			T41	1		T37	1		T122	3
all_values[4]	auto[1]	auto[1]	auto[1]	103	1			T41	1		T95	3		T122	3
all_values[5]	auto[0]	auto[0]	auto[0]	54	1			T95	3		T45	3		T46	2
all_values[5]	auto[0]	auto[0]	auto[1]	106	1			T37	2		T122	1		T45	1
all_values[5]	auto[0]	auto[1]	auto[0]	44	1			T41	1		T95	2		T122	2
all_values[5]	auto[0]	auto[1]	auto[1]	122	1			T41	1		T37	1		T95	2
all_values[5]	auto[1]	auto[0]	auto[1]	106	1			T41	1		T37	1		T95	1
all_values[5]	auto[1]	auto[1]	auto[1]	91	1			T41	1		T122	2		T45	2
all_values[6]	auto[0]	auto[0]	auto[0]	38	1			T62	1		T43	3		T272	2
all_values[6]	auto[0]	auto[0]	auto[1]	105	1			T95	3		T122	4		T45	1
all_values[6]	auto[0]	auto[1]	auto[0]	30	1			T41	1		T37	2		T62	1
all_values[6]	auto[0]	auto[1]	auto[1]	123	1			T41	2		T37	1		T95	2
all_values[6]	auto[1]	auto[0]	auto[1]	125	1			T41	1		T37	1		T95	2
all_values[6]	auto[1]	auto[1]	auto[1]	102	1			T95	1		T122	3		T45	1
all_values[7]	auto[0]	auto[0]	auto[0]	52	1			T41	2		T95	1		T271	3
all_values[7]	auto[0]	auto[0]	auto[1]	106	1			T37	1		T95	2		T45	3
all_values[7]	auto[0]	auto[1]	auto[0]	37	1			T41	2		T271	1		T265	2
all_values[7]	auto[0]	auto[1]	auto[1]	117	1			T95	1		T122	4		T45	1
all_values[7]	auto[1]	auto[0]	auto[1]	97	1			T37	1		T95	2		T122	1
all_values[7]	auto[1]	auto[1]	auto[1]	114	1			T37	2		T95	2		T122	6
all_values[8]	auto[0]	auto[0]	auto[0]	39	1			T271	2		T124	1		T113	1
all_values[8]	auto[0]	auto[0]	auto[1]	121	1			T41	1		T37	1		T95	2
all_values[8]	auto[0]	auto[1]	auto[0]	45	1			T41	1		T122	3		T43	2
all_values[8]	auto[0]	auto[1]	auto[1]	111	1			T37	1		T95	1		T122	4
all_values[8]	auto[1]	auto[0]	auto[1]	121	1			T41	1		T37	2		T95	2
all_values[8]	auto[1]	auto[1]	auto[1]	86	1			T41	1		T95	3		T122	2
all_values[9]	auto[0]	auto[0]	auto[0]	32	1			T41	1		T46	4		T43	1
all_values[9]	auto[0]	auto[0]	auto[1]	124	1			T41	1		T95	2		T122	2
all_values[9]	auto[0]	auto[1]	auto[0]	27	1			T41	1		T95	2		T62	1
all_values[9]	auto[0]	auto[1]	auto[1]	120	1			T37	2		T95	2		T122	3
all_values[9]	auto[1]	auto[0]	auto[1]	123	1			T41	1		T122	4		T45	2
all_values[9]	auto[1]	auto[1]	auto[1]	97	1			T37	2		T95	2		T122	2
all_values[10]	auto[0]	auto[0]	auto[0]	35	1			T45	2		T112	1		T265	2
all_values[10]	auto[0]	auto[0]	auto[1]	126	1			T41	1		T95	2		T122	1
all_values[10]	auto[0]	auto[1]	auto[0]	35	1			T122	2		T62	1		T273	1
all_values[10]	auto[0]	auto[1]	auto[1]	119	1			T41	1		T37	1		T95	4
all_values[10]	auto[1]	auto[0]	auto[1]	128	1			T41	1		T37	2		T95	2
all_values[10]	auto[1]	auto[1]	auto[1]	80	1			T41	1		T37	1		T122	3
all_values[11]	auto[0]	auto[0]	auto[0]	37	1			T41	1		T45	1		T46	1
all_values[11]	auto[0]	auto[0]	auto[1]	119	1			T37	1		T95	3		T122	3
all_values[11]	auto[0]	auto[1]	auto[0]	44	1			T41	1		T37	1		T95	1
all_values[11]	auto[0]	auto[1]	auto[1]	123	1			T41	1		T122	4		T45	3
all_values[11]	auto[1]	auto[0]	auto[1]	103	1			T95	3		T122	1		T45	3
all_values[11]	auto[1]	auto[1]	auto[1]	97	1			T41	1		T37	2		T95	1
all_values[12]	auto[0]	auto[0]	auto[0]	31	1			T122	1		T51	1		T265	2
all_values[12]	auto[0]	auto[0]	auto[1]	111	1			T41	2		T95	2		T122	4
all_values[12]	auto[0]	auto[1]	auto[0]	33	1			T37	1		T122	1		T271	1
all_values[12]	auto[0]	auto[1]	auto[1]	124	1			T41	1		T37	1		T95	2
all_values[12]	auto[1]	auto[0]	auto[1]	133	1			T95	3		T122	1		T45	2
all_values[12]	auto[1]	auto[1]	auto[1]	91	1			T41	1		T37	2		T95	1
all_values[13]	auto[0]	auto[0]	auto[0]	41	1			T95	1		T46	1		T271	1
all_values[13]	auto[0]	auto[0]	auto[1]	106	1			T37	2		T95	1		T122	1
all_values[13]	auto[0]	auto[1]	auto[0]	39	1			T41	2		T95	1		T46	1
all_values[13]	auto[0]	auto[1]	auto[1]	115	1			T41	1		T95	2		T122	4
all_values[13]	auto[1]	auto[0]	auto[1]	123	1			T95	2		T122	3		T45	1
all_values[13]	auto[1]	auto[1]	auto[1]	99	1			T41	1		T37	2		T95	1
all_values[14]	auto[0]	auto[0]	auto[0]	55	1			T95	1		T45	2		T62	1
all_values[14]	auto[0]	auto[0]	auto[1]	112	1			T41	1		T37	2		T95	2
all_values[14]	auto[0]	auto[1]	auto[0]	45	1			T41	2		T95	1		T122	1
all_values[14]	auto[0]	auto[1]	auto[1]	101	1			T95	1		T122	3		T46	3
all_values[14]	auto[1]	auto[0]	auto[1]	101	1			T41	1		T37	1		T95	3
all_values[14]	auto[1]	auto[1]	auto[1]	109	1			T37	1		T122	1		T45	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal