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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.83 96.57 89.88 97.22 69.64 93.55 98.44 90.53


Total test records in report: 1644
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T226 /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1351128262 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:20 PM PDT 24 84214628 ps
T227 /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3542504013 Jul 03 05:38:32 PM PDT 24 Jul 03 05:38:34 PM PDT 24 164851213 ps
T228 /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1590038082 Jul 03 05:38:28 PM PDT 24 Jul 03 05:38:29 PM PDT 24 31342836 ps
T101 /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.756625724 Jul 03 05:38:07 PM PDT 24 Jul 03 05:38:10 PM PDT 24 484873000 ps
T211 /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2143669417 Jul 03 05:38:06 PM PDT 24 Jul 03 05:38:08 PM PDT 24 143416399 ps
T102 /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.329604539 Jul 03 05:38:02 PM PDT 24 Jul 03 05:38:08 PM PDT 24 2398338138 ps
T103 /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4265511078 Jul 03 05:38:00 PM PDT 24 Jul 03 05:38:01 PM PDT 24 133061823 ps
T191 /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1763060381 Jul 03 05:38:00 PM PDT 24 Jul 03 05:38:02 PM PDT 24 44354332 ps
T1542 /workspace/coverage/cover_reg_top/11.i2c_intr_test.26262368 Jul 03 05:38:16 PM PDT 24 Jul 03 05:38:17 PM PDT 24 78515868 ps
T1543 /workspace/coverage/cover_reg_top/1.i2c_intr_test.3936256764 Jul 03 05:38:02 PM PDT 24 Jul 03 05:38:02 PM PDT 24 117184552 ps
T1544 /workspace/coverage/cover_reg_top/32.i2c_intr_test.830510410 Jul 03 05:38:32 PM PDT 24 Jul 03 05:38:33 PM PDT 24 18591180 ps
T104 /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2195260027 Jul 03 05:38:04 PM PDT 24 Jul 03 05:38:06 PM PDT 24 45331809 ps
T229 /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1865695297 Jul 03 05:38:02 PM PDT 24 Jul 03 05:38:04 PM PDT 24 101847953 ps
T105 /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2514666469 Jul 03 05:38:09 PM PDT 24 Jul 03 05:38:11 PM PDT 24 220065978 ps
T194 /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3729884054 Jul 03 05:38:13 PM PDT 24 Jul 03 05:38:16 PM PDT 24 150888257 ps
T212 /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4104004467 Jul 03 05:38:20 PM PDT 24 Jul 03 05:38:21 PM PDT 24 45727907 ps
T201 /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1555720293 Jul 03 05:38:02 PM PDT 24 Jul 03 05:38:04 PM PDT 24 52189321 ps
T198 /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2453003630 Jul 03 05:38:09 PM PDT 24 Jul 03 05:38:11 PM PDT 24 262019310 ps
T106 /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3434836171 Jul 03 05:38:12 PM PDT 24 Jul 03 05:38:15 PM PDT 24 281303228 ps
T121 /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3030054872 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:20 PM PDT 24 222952038 ps
T1545 /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3773051950 Jul 03 05:37:59 PM PDT 24 Jul 03 05:38:00 PM PDT 24 52534746 ps
T1546 /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3786784918 Jul 03 05:38:08 PM PDT 24 Jul 03 05:38:09 PM PDT 24 19815177 ps
T1547 /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2095790073 Jul 03 05:38:06 PM PDT 24 Jul 03 05:38:07 PM PDT 24 23558012 ps
T195 /workspace/coverage/cover_reg_top/2.i2c_tl_errors.532991373 Jul 03 05:38:01 PM PDT 24 Jul 03 05:38:03 PM PDT 24 54319165 ps
T1548 /workspace/coverage/cover_reg_top/36.i2c_intr_test.3368728903 Jul 03 05:38:33 PM PDT 24 Jul 03 05:38:34 PM PDT 24 18887885 ps
T1549 /workspace/coverage/cover_reg_top/21.i2c_intr_test.159620473 Jul 03 05:38:32 PM PDT 24 Jul 03 05:38:34 PM PDT 24 37198706 ps
T107 /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3581054323 Jul 03 05:38:03 PM PDT 24 Jul 03 05:38:06 PM PDT 24 351973752 ps
T141 /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4210382663 Jul 03 05:38:08 PM PDT 24 Jul 03 05:38:10 PM PDT 24 478491804 ps
T1550 /workspace/coverage/cover_reg_top/49.i2c_intr_test.371025723 Jul 03 05:38:35 PM PDT 24 Jul 03 05:38:36 PM PDT 24 51027824 ps
T1551 /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3397756214 Jul 03 05:38:19 PM PDT 24 Jul 03 05:38:21 PM PDT 24 56337500 ps
T1552 /workspace/coverage/cover_reg_top/6.i2c_csr_rw.919824790 Jul 03 05:38:07 PM PDT 24 Jul 03 05:38:08 PM PDT 24 20748613 ps
T1553 /workspace/coverage/cover_reg_top/23.i2c_intr_test.3260525217 Jul 03 05:38:27 PM PDT 24 Jul 03 05:38:28 PM PDT 24 43857139 ps
T1554 /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2366322978 Jul 03 05:37:58 PM PDT 24 Jul 03 05:37:59 PM PDT 24 183840336 ps
T1555 /workspace/coverage/cover_reg_top/17.i2c_intr_test.2078615296 Jul 03 05:38:30 PM PDT 24 Jul 03 05:38:32 PM PDT 24 41691249 ps
T1556 /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3066693848 Jul 03 05:38:25 PM PDT 24 Jul 03 05:38:26 PM PDT 24 71521750 ps
T1557 /workspace/coverage/cover_reg_top/26.i2c_intr_test.948662078 Jul 03 05:38:32 PM PDT 24 Jul 03 05:38:34 PM PDT 24 17366550 ps
T199 /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4109156098 Jul 03 05:38:12 PM PDT 24 Jul 03 05:38:15 PM PDT 24 126229868 ps
T196 /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1286125732 Jul 03 05:38:24 PM PDT 24 Jul 03 05:38:27 PM PDT 24 127966592 ps
T213 /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2706054929 Jul 03 05:38:13 PM PDT 24 Jul 03 05:38:15 PM PDT 24 66181092 ps
T1558 /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.670908632 Jul 03 05:38:09 PM PDT 24 Jul 03 05:38:10 PM PDT 24 57961145 ps
T197 /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3260646380 Jul 03 05:38:13 PM PDT 24 Jul 03 05:38:15 PM PDT 24 78543837 ps
T1559 /workspace/coverage/cover_reg_top/40.i2c_intr_test.2730022910 Jul 03 05:38:30 PM PDT 24 Jul 03 05:38:32 PM PDT 24 15899785 ps
T1560 /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3597375285 Jul 03 05:38:26 PM PDT 24 Jul 03 05:38:28 PM PDT 24 318124993 ps
T221 /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2294611471 Jul 03 05:38:06 PM PDT 24 Jul 03 05:38:09 PM PDT 24 1194990697 ps
T1561 /workspace/coverage/cover_reg_top/37.i2c_intr_test.1284251308 Jul 03 05:38:32 PM PDT 24 Jul 03 05:38:33 PM PDT 24 88430240 ps
T1562 /workspace/coverage/cover_reg_top/46.i2c_intr_test.1844627297 Jul 03 05:38:33 PM PDT 24 Jul 03 05:38:34 PM PDT 24 14519331 ps
T1563 /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3346183773 Jul 03 05:38:08 PM PDT 24 Jul 03 05:38:09 PM PDT 24 320724903 ps
T1564 /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.93547551 Jul 03 05:38:04 PM PDT 24 Jul 03 05:38:05 PM PDT 24 313575793 ps
T1565 /workspace/coverage/cover_reg_top/4.i2c_intr_test.2502084413 Jul 03 05:38:06 PM PDT 24 Jul 03 05:38:07 PM PDT 24 43406882 ps
T1566 /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4177608198 Jul 03 05:38:15 PM PDT 24 Jul 03 05:38:16 PM PDT 24 135348935 ps
T1567 /workspace/coverage/cover_reg_top/16.i2c_intr_test.364343629 Jul 03 05:38:30 PM PDT 24 Jul 03 05:38:32 PM PDT 24 21908337 ps
T1568 /workspace/coverage/cover_reg_top/15.i2c_intr_test.178925687 Jul 03 05:38:22 PM PDT 24 Jul 03 05:38:23 PM PDT 24 28445530 ps
T1569 /workspace/coverage/cover_reg_top/42.i2c_intr_test.2079341691 Jul 03 05:38:31 PM PDT 24 Jul 03 05:38:32 PM PDT 24 26801704 ps
T1570 /workspace/coverage/cover_reg_top/13.i2c_intr_test.3588610459 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:19 PM PDT 24 91005896 ps
T192 /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4250965991 Jul 03 05:38:12 PM PDT 24 Jul 03 05:38:13 PM PDT 24 73701325 ps
T1571 /workspace/coverage/cover_reg_top/10.i2c_intr_test.4181705469 Jul 03 05:38:17 PM PDT 24 Jul 03 05:38:18 PM PDT 24 42878212 ps
T1572 /workspace/coverage/cover_reg_top/2.i2c_intr_test.554063382 Jul 03 05:38:00 PM PDT 24 Jul 03 05:38:01 PM PDT 24 40618260 ps
T1573 /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.246541575 Jul 03 05:38:01 PM PDT 24 Jul 03 05:38:03 PM PDT 24 30784760 ps
T1574 /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3807836128 Jul 03 05:38:09 PM PDT 24 Jul 03 05:38:11 PM PDT 24 116797525 ps
T1575 /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.457593484 Jul 03 05:38:17 PM PDT 24 Jul 03 05:38:18 PM PDT 24 148929359 ps
T1576 /workspace/coverage/cover_reg_top/14.i2c_intr_test.3829487560 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:19 PM PDT 24 16497343 ps
T1577 /workspace/coverage/cover_reg_top/47.i2c_intr_test.2853952426 Jul 03 05:38:36 PM PDT 24 Jul 03 05:38:36 PM PDT 24 32758513 ps
T1578 /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1904664845 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:20 PM PDT 24 41959443 ps
T1579 /workspace/coverage/cover_reg_top/18.i2c_intr_test.1902847453 Jul 03 05:38:27 PM PDT 24 Jul 03 05:38:28 PM PDT 24 22312491 ps
T1580 /workspace/coverage/cover_reg_top/44.i2c_intr_test.3040257319 Jul 03 05:38:36 PM PDT 24 Jul 03 05:38:37 PM PDT 24 42699457 ps
T1581 /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3792162713 Jul 03 05:38:19 PM PDT 24 Jul 03 05:38:21 PM PDT 24 53643767 ps
T1582 /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.631986039 Jul 03 05:38:11 PM PDT 24 Jul 03 05:38:12 PM PDT 24 25088664 ps
T1583 /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1037323142 Jul 03 05:37:59 PM PDT 24 Jul 03 05:38:01 PM PDT 24 165751949 ps
T1584 /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1331352483 Jul 03 05:38:12 PM PDT 24 Jul 03 05:38:13 PM PDT 24 131867979 ps
T1585 /workspace/coverage/cover_reg_top/9.i2c_csr_rw.862425296 Jul 03 05:38:13 PM PDT 24 Jul 03 05:38:14 PM PDT 24 25967161 ps
T1586 /workspace/coverage/cover_reg_top/38.i2c_intr_test.2739721055 Jul 03 05:38:32 PM PDT 24 Jul 03 05:38:33 PM PDT 24 16582118 ps
T1587 /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3823566130 Jul 03 05:38:01 PM PDT 24 Jul 03 05:38:02 PM PDT 24 22864183 ps
T1588 /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3833049754 Jul 03 05:38:27 PM PDT 24 Jul 03 05:38:29 PM PDT 24 150487158 ps
T1589 /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.807125082 Jul 03 05:38:00 PM PDT 24 Jul 03 05:38:01 PM PDT 24 46301671 ps
T1590 /workspace/coverage/cover_reg_top/15.i2c_tl_errors.829375515 Jul 03 05:38:19 PM PDT 24 Jul 03 05:38:21 PM PDT 24 85105426 ps
T1591 /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2591769121 Jul 03 05:37:57 PM PDT 24 Jul 03 05:37:58 PM PDT 24 50050199 ps
T1592 /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2094840279 Jul 03 05:38:03 PM PDT 24 Jul 03 05:38:04 PM PDT 24 24743246 ps
T214 /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2617824138 Jul 03 05:38:02 PM PDT 24 Jul 03 05:38:03 PM PDT 24 243171517 ps
T1593 /workspace/coverage/cover_reg_top/31.i2c_intr_test.4146920722 Jul 03 05:38:32 PM PDT 24 Jul 03 05:38:33 PM PDT 24 27645678 ps
T1594 /workspace/coverage/cover_reg_top/27.i2c_intr_test.2433172671 Jul 03 05:38:27 PM PDT 24 Jul 03 05:38:29 PM PDT 24 18323060 ps
T1595 /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3761574756 Jul 03 05:37:57 PM PDT 24 Jul 03 05:37:59 PM PDT 24 223481668 ps
T1596 /workspace/coverage/cover_reg_top/0.i2c_intr_test.110490643 Jul 03 05:37:56 PM PDT 24 Jul 03 05:37:57 PM PDT 24 26673538 ps
T1597 /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1534467586 Jul 03 05:38:11 PM PDT 24 Jul 03 05:38:13 PM PDT 24 136274215 ps
T215 /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3720793182 Jul 03 05:38:03 PM PDT 24 Jul 03 05:38:04 PM PDT 24 17751240 ps
T1598 /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1117655198 Jul 03 05:38:11 PM PDT 24 Jul 03 05:38:13 PM PDT 24 674247463 ps
T1599 /workspace/coverage/cover_reg_top/20.i2c_intr_test.3389999331 Jul 03 05:38:26 PM PDT 24 Jul 03 05:38:27 PM PDT 24 25190242 ps
T216 /workspace/coverage/cover_reg_top/13.i2c_csr_rw.708815824 Jul 03 05:38:23 PM PDT 24 Jul 03 05:38:24 PM PDT 24 26452692 ps
T217 /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.129107068 Jul 03 05:38:01 PM PDT 24 Jul 03 05:38:02 PM PDT 24 88881636 ps
T193 /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2593430011 Jul 03 05:38:22 PM PDT 24 Jul 03 05:38:25 PM PDT 24 137650057 ps
T1600 /workspace/coverage/cover_reg_top/35.i2c_intr_test.2009533424 Jul 03 05:38:31 PM PDT 24 Jul 03 05:38:32 PM PDT 24 32956976 ps
T1601 /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1634371467 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:20 PM PDT 24 112172868 ps
T1602 /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3655965105 Jul 03 05:38:09 PM PDT 24 Jul 03 05:38:10 PM PDT 24 53936830 ps
T1603 /workspace/coverage/cover_reg_top/19.i2c_intr_test.1627521583 Jul 03 05:38:28 PM PDT 24 Jul 03 05:38:29 PM PDT 24 104143652 ps
T1604 /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3589791392 Jul 03 05:38:12 PM PDT 24 Jul 03 05:38:13 PM PDT 24 58218017 ps
T218 /workspace/coverage/cover_reg_top/7.i2c_csr_rw.399727265 Jul 03 05:38:08 PM PDT 24 Jul 03 05:38:09 PM PDT 24 47511712 ps
T204 /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3520600341 Jul 03 05:38:05 PM PDT 24 Jul 03 05:38:06 PM PDT 24 138853974 ps
T1605 /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2751030856 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:20 PM PDT 24 83968792 ps
T1606 /workspace/coverage/cover_reg_top/34.i2c_intr_test.1174877017 Jul 03 05:38:33 PM PDT 24 Jul 03 05:38:34 PM PDT 24 81254936 ps
T1607 /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2754694385 Jul 03 05:37:58 PM PDT 24 Jul 03 05:37:59 PM PDT 24 40636047 ps
T1608 /workspace/coverage/cover_reg_top/8.i2c_intr_test.4038195535 Jul 03 05:38:09 PM PDT 24 Jul 03 05:38:10 PM PDT 24 19272767 ps
T219 /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2496193166 Jul 03 05:38:01 PM PDT 24 Jul 03 05:38:02 PM PDT 24 20699723 ps
T203 /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2267697186 Jul 03 05:38:02 PM PDT 24 Jul 03 05:38:03 PM PDT 24 706674617 ps
T1609 /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3102857401 Jul 03 05:38:27 PM PDT 24 Jul 03 05:38:28 PM PDT 24 75855698 ps
T1610 /workspace/coverage/cover_reg_top/41.i2c_intr_test.2669147764 Jul 03 05:38:29 PM PDT 24 Jul 03 05:38:30 PM PDT 24 18357037 ps
T1611 /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1220161880 Jul 03 05:38:24 PM PDT 24 Jul 03 05:38:26 PM PDT 24 81318239 ps
T1612 /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.405174678 Jul 03 05:38:01 PM PDT 24 Jul 03 05:38:02 PM PDT 24 69068779 ps
T1613 /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2950390915 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:20 PM PDT 24 325220614 ps
T1614 /workspace/coverage/cover_reg_top/3.i2c_intr_test.383850592 Jul 03 05:38:02 PM PDT 24 Jul 03 05:38:04 PM PDT 24 40842228 ps
T220 /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3855228509 Jul 03 05:38:15 PM PDT 24 Jul 03 05:38:16 PM PDT 24 19344173 ps
T1615 /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2560733770 Jul 03 05:38:22 PM PDT 24 Jul 03 05:38:24 PM PDT 24 183259815 ps
T1616 /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3694064349 Jul 03 05:38:13 PM PDT 24 Jul 03 05:38:18 PM PDT 24 1389653208 ps
T1617 /workspace/coverage/cover_reg_top/12.i2c_intr_test.2536307909 Jul 03 05:38:19 PM PDT 24 Jul 03 05:38:20 PM PDT 24 18065119 ps
T1618 /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1750758824 Jul 03 05:38:29 PM PDT 24 Jul 03 05:38:31 PM PDT 24 83193987 ps
T1619 /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2143005116 Jul 03 05:38:27 PM PDT 24 Jul 03 05:38:29 PM PDT 24 38241548 ps
T205 /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2894013799 Jul 03 05:38:12 PM PDT 24 Jul 03 05:38:14 PM PDT 24 87673244 ps
T1620 /workspace/coverage/cover_reg_top/48.i2c_intr_test.2087838880 Jul 03 05:38:37 PM PDT 24 Jul 03 05:38:38 PM PDT 24 19065430 ps
T1621 /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3513111913 Jul 03 05:38:23 PM PDT 24 Jul 03 05:38:26 PM PDT 24 505502805 ps
T1622 /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3085274594 Jul 03 05:38:16 PM PDT 24 Jul 03 05:38:17 PM PDT 24 237907811 ps
T1623 /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2226562510 Jul 03 05:38:05 PM PDT 24 Jul 03 05:38:07 PM PDT 24 130075889 ps
T1624 /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2375480270 Jul 03 05:38:13 PM PDT 24 Jul 03 05:38:14 PM PDT 24 58722765 ps
T222 /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3955181730 Jul 03 05:38:05 PM PDT 24 Jul 03 05:38:06 PM PDT 24 29679954 ps
T1625 /workspace/coverage/cover_reg_top/39.i2c_intr_test.1179556571 Jul 03 05:38:33 PM PDT 24 Jul 03 05:38:34 PM PDT 24 14560593 ps
T1626 /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3914226739 Jul 03 05:38:30 PM PDT 24 Jul 03 05:38:33 PM PDT 24 60090967 ps
T1627 /workspace/coverage/cover_reg_top/30.i2c_intr_test.992249707 Jul 03 05:38:30 PM PDT 24 Jul 03 05:38:31 PM PDT 24 57645558 ps
T200 /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1894259552 Jul 03 05:38:14 PM PDT 24 Jul 03 05:38:17 PM PDT 24 523624393 ps
T1628 /workspace/coverage/cover_reg_top/12.i2c_csr_rw.659883445 Jul 03 05:38:22 PM PDT 24 Jul 03 05:38:23 PM PDT 24 21552623 ps
T1629 /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2979028302 Jul 03 05:38:08 PM PDT 24 Jul 03 05:38:11 PM PDT 24 499387738 ps
T202 /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.378745373 Jul 03 05:38:26 PM PDT 24 Jul 03 05:38:28 PM PDT 24 1000927262 ps
T223 /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1523834227 Jul 03 05:38:16 PM PDT 24 Jul 03 05:38:17 PM PDT 24 99371207 ps
T1630 /workspace/coverage/cover_reg_top/43.i2c_intr_test.3304288392 Jul 03 05:38:35 PM PDT 24 Jul 03 05:38:36 PM PDT 24 27043840 ps
T1631 /workspace/coverage/cover_reg_top/6.i2c_intr_test.1078948543 Jul 03 05:38:09 PM PDT 24 Jul 03 05:38:10 PM PDT 24 33665863 ps
T1632 /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1035950725 Jul 03 05:38:23 PM PDT 24 Jul 03 05:38:24 PM PDT 24 23596135 ps
T1633 /workspace/coverage/cover_reg_top/28.i2c_intr_test.131187406 Jul 03 05:38:27 PM PDT 24 Jul 03 05:38:29 PM PDT 24 41863630 ps
T1634 /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3299504106 Jul 03 05:38:03 PM PDT 24 Jul 03 05:38:05 PM PDT 24 806339345 ps
T1635 /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.517953600 Jul 03 05:38:22 PM PDT 24 Jul 03 05:38:24 PM PDT 24 177070706 ps
T1636 /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3426401496 Jul 03 05:38:14 PM PDT 24 Jul 03 05:38:16 PM PDT 24 127744256 ps
T1637 /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2153792833 Jul 03 05:38:24 PM PDT 24 Jul 03 05:38:26 PM PDT 24 54139721 ps
T1638 /workspace/coverage/cover_reg_top/5.i2c_tl_errors.16751560 Jul 03 05:38:05 PM PDT 24 Jul 03 05:38:07 PM PDT 24 413609453 ps
T1639 /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3506295486 Jul 03 05:38:16 PM PDT 24 Jul 03 05:38:18 PM PDT 24 102525694 ps
T1640 /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3029943387 Jul 03 05:38:19 PM PDT 24 Jul 03 05:38:21 PM PDT 24 273673286 ps
T1641 /workspace/coverage/cover_reg_top/24.i2c_intr_test.431920661 Jul 03 05:38:27 PM PDT 24 Jul 03 05:38:28 PM PDT 24 20758361 ps
T1642 /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2738758735 Jul 03 05:37:58 PM PDT 24 Jul 03 05:38:01 PM PDT 24 245504102 ps
T1643 /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3123229911 Jul 03 05:38:18 PM PDT 24 Jul 03 05:38:20 PM PDT 24 333163850 ps
T1644 /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.290869714 Jul 03 05:38:05 PM PDT 24 Jul 03 05:38:06 PM PDT 24 32656325 ps

Test location /workspace/coverage/default/19.i2c_target_hrst.1573626606
Short name T4
Test name
Test status
Simulation time 739422593 ps
CPU time 2.87 seconds
Started Jul 03 05:26:31 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 204752 kb
Host smart-4ad720db-9dc5-4e2c-b2ab-6b992cab241e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573626606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_hrst.1573626606
Directory /workspace/19.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_watermark.3865426939
Short name T1
Test name
Test status
Simulation time 3854787797 ps
CPU time 239.93 seconds
Started Jul 03 05:24:49 PM PDT 24
Finished Jul 03 05:28:51 PM PDT 24
Peak memory 1088932 kb
Host smart-7d645723-0873-4d72-8d15-94848deecce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865426939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_watermark.3865426939
Directory /workspace/0.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_stress_all.1935098675
Short name T37
Test name
Test status
Simulation time 14098972115 ps
CPU time 511.91 seconds
Started Jul 03 05:26:16 PM PDT 24
Finished Jul 03 05:34:48 PM PDT 24
Peak memory 1805736 kb
Host smart-4dadc152-4ee1-45e3-a9ae-06135dd229b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935098675 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stress_all.1935098675
Directory /workspace/13.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_target_glitch.419366449
Short name T14
Test name
Test status
Simulation time 2287654541 ps
CPU time 10.56 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:14 PM PDT 24
Peak memory 213564 kb
Host smart-4d97bca1-4aa2-426d-aa42-49579b22d640
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419366449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_target_glitch.419366449
Directory /workspace/1.i2c_target_glitch/latest

Test location /workspace/coverage/default/48.i2c_host_stress_all.1462676516
Short name T41
Test name
Test status
Simulation time 22839373179 ps
CPU time 905.08 seconds
Started Jul 03 05:28:51 PM PDT 24
Finished Jul 03 05:43:57 PM PDT 24
Peak memory 2064444 kb
Host smart-9a88f47b-f6ff-424e-84e7-a6c82b64852d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462676516 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stress_all.1462676516
Directory /workspace/48.i2c_host_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_intg_err.756625724
Short name T101
Test name
Test status
Simulation time 484873000 ps
CPU time 2.31 seconds
Started Jul 03 05:38:07 PM PDT 24
Finished Jul 03 05:38:10 PM PDT 24
Peak memory 204588 kb
Host smart-832adff9-66d5-4a04-82bf-8920e369f3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756625724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_intg_err.756625724
Directory /workspace/7.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/24.i2c_target_stress_wr.768534586
Short name T16
Test name
Test status
Simulation time 30474488058 ps
CPU time 32.2 seconds
Started Jul 03 05:27:02 PM PDT 24
Finished Jul 03 05:27:35 PM PDT 24
Peak memory 701436 kb
Host smart-9495d986-a994-440e-b384-4e5ba9414f18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768534586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_wr.768534586
Directory /workspace/24.i2c_target_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_mem_rw_with_rand_reset.1761980297
Short name T178
Test name
Test status
Simulation time 27203837 ps
CPU time 0.83 seconds
Started Jul 03 05:38:15 PM PDT 24
Finished Jul 03 05:38:16 PM PDT 24
Peak memory 204540 kb
Host smart-bfe51052-6bcd-4b49-8a13-134a302e1155
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761980297 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.i2c_csr_mem_rw_with_rand_reset.1761980297
Directory /workspace/11.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/16.i2c_host_override.3210147084
Short name T131
Test name
Test status
Simulation time 20730716 ps
CPU time 0.66 seconds
Started Jul 03 05:26:29 PM PDT 24
Finished Jul 03 05:26:30 PM PDT 24
Peak memory 204528 kb
Host smart-3dae90ff-e650-4820-b457-3ee3ae8e618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210147084 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_override.3210147084
Directory /workspace/16.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_target_timeout.1139346385
Short name T8
Test name
Test status
Simulation time 12187709993 ps
CPU time 6.45 seconds
Started Jul 03 05:27:58 PM PDT 24
Finished Jul 03 05:28:05 PM PDT 24
Peak memory 205024 kb
Host smart-83fed043-45e3-4574-a108-665f7bf457d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139346385 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 36.i2c_target_timeout.1139346385
Directory /workspace/36.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_host_stress_all.2727574077
Short name T46
Test name
Test status
Simulation time 37658235064 ps
CPU time 216.89 seconds
Started Jul 03 05:26:31 PM PDT 24
Finished Jul 03 05:30:09 PM PDT 24
Peak memory 972972 kb
Host smart-cd6c8636-66a6-43cf-b013-cbfd24cc9562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727574077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stress_all.2727574077
Directory /workspace/19.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_sec_cm.1208078700
Short name T180
Test name
Test status
Simulation time 144498480 ps
CPU time 0.88 seconds
Started Jul 03 05:25:08 PM PDT 24
Finished Jul 03 05:25:10 PM PDT 24
Peak memory 222236 kb
Host smart-eccc2c83-df68-4cfb-907d-83e1d7becc42
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208078700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_sec_cm.1208078700
Directory /workspace/2.i2c_sec_cm/latest

Test location /workspace/coverage/default/16.i2c_host_may_nack.1002004285
Short name T261
Test name
Test status
Simulation time 3202358880 ps
CPU time 18.26 seconds
Started Jul 03 05:26:22 PM PDT 24
Finished Jul 03 05:26:41 PM PDT 24
Peak memory 204888 kb
Host smart-a203c442-eb9d-460c-900c-186a9570a446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002004285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_may_nack.1002004285
Directory /workspace/16.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_acq.3282486643
Short name T13
Test name
Test status
Simulation time 445421495 ps
CPU time 1.18 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:26:51 PM PDT 24
Peak memory 204588 kb
Host smart-ddf00c33-69ac-41d9-91c4-4365513142a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282486643 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_fifo_reset_acq.3282486643
Directory /workspace/23.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_hw_reset.129107068
Short name T217
Test name
Test status
Simulation time 88881636 ps
CPU time 0.8 seconds
Started Jul 03 05:38:01 PM PDT 24
Finished Jul 03 05:38:02 PM PDT 24
Peak memory 204456 kb
Host smart-1d028db3-bb3f-43bb-95b3-3769c5863db2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129107068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_hw_reset.129107068
Directory /workspace/2.i2c_csr_hw_reset/latest

Test location /workspace/coverage/default/11.i2c_target_tx_stretch_ctrl.975630590
Short name T18
Test name
Test status
Simulation time 57968234 ps
CPU time 1.43 seconds
Started Jul 03 05:25:52 PM PDT 24
Finished Jul 03 05:25:54 PM PDT 24
Peak memory 204812 kb
Host smart-678b724f-8079-42af-874b-27cbda628b32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975630590 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_tx_stretch_ctrl.975630590
Directory /workspace/11.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_fmt.1678493931
Short name T58
Test name
Test status
Simulation time 160013125 ps
CPU time 0.96 seconds
Started Jul 03 05:28:22 PM PDT 24
Finished Jul 03 05:28:23 PM PDT 24
Peak memory 204432 kb
Host smart-4e8f59c0-9fb0-4f10-9733-b049321662b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678493931 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_f
mt.1678493931
Directory /workspace/42.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_target_bad_addr.245683310
Short name T11
Test name
Test status
Simulation time 793782700 ps
CPU time 4.3 seconds
Started Jul 03 05:24:59 PM PDT 24
Finished Jul 03 05:25:04 PM PDT 24
Peak memory 213032 kb
Host smart-2f1dbfe4-dbbb-46b0-911b-09196917c477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245683310 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.i2c_target_bad_addr.245683310
Directory /workspace/0.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_host_stress_all.3377798888
Short name T1152
Test name
Test status
Simulation time 57637381624 ps
CPU time 1898.06 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 06:00:09 PM PDT 24
Peak memory 3126852 kb
Host smart-c9fc8295-2905-4fa9-9031-0914ef3ec41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377798888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stress_all.3377798888
Directory /workspace/42.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_error_intr.1782597028
Short name T50
Test name
Test status
Simulation time 393756553 ps
CPU time 3.28 seconds
Started Jul 03 05:25:18 PM PDT 24
Finished Jul 03 05:25:21 PM PDT 24
Peak memory 215148 kb
Host smart-daa013ae-aaa3-47f1-928f-7b895440afd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782597028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_error_intr.1782597028
Directory /workspace/3.i2c_host_error_intr/latest

Test location /workspace/coverage/default/3.i2c_target_smoke.3264211869
Short name T97
Test name
Test status
Simulation time 5323905316 ps
CPU time 11.66 seconds
Started Jul 03 05:25:13 PM PDT 24
Finished Jul 03 05:25:25 PM PDT 24
Peak memory 204860 kb
Host smart-99bdef34-dcf9-412e-ae84-e3f7454b5b77
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264211869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_tar
get_smoke.3264211869
Directory /workspace/3.i2c_target_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_errors.4109156098
Short name T199
Test name
Test status
Simulation time 126229868 ps
CPU time 3.19 seconds
Started Jul 03 05:38:12 PM PDT 24
Finished Jul 03 05:38:15 PM PDT 24
Peak memory 212748 kb
Host smart-c159094a-4cb7-4cb0-9de4-74062264be81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109156098 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_errors.4109156098
Directory /workspace/9.i2c_tl_errors/latest

Test location /workspace/coverage/default/13.i2c_alert_test.206389305
Short name T138
Test name
Test status
Simulation time 47610891 ps
CPU time 0.61 seconds
Started Jul 03 05:26:24 PM PDT 24
Finished Jul 03 05:26:25 PM PDT 24
Peak memory 204476 kb
Host smart-d4e468ce-803a-4498-8d8e-a15e0a447cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206389305 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_alert_test.206389305
Directory /workspace/13.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_stress_all.35395341
Short name T95
Test name
Test status
Simulation time 30884921788 ps
CPU time 1599.82 seconds
Started Jul 03 05:26:43 PM PDT 24
Finished Jul 03 05:53:23 PM PDT 24
Peak memory 3175340 kb
Host smart-1466d1b7-3900-4264-a867-8eafc1f1e167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35395341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stress_all.35395341
Directory /workspace/22.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_target_stress_rd.3791464892
Short name T206
Test name
Test status
Simulation time 3035477639 ps
CPU time 25.3 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:27:54 PM PDT 24
Peak memory 225968 kb
Host smart-288606b1-c6c4-40ac-a3b6-a1122aafa618
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791464892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_rd.3791464892
Directory /workspace/31.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_rx.1491500561
Short name T407
Test name
Test status
Simulation time 167941814 ps
CPU time 3.31 seconds
Started Jul 03 05:27:35 PM PDT 24
Finished Jul 03 05:27:39 PM PDT 24
Peak memory 220616 kb
Host smart-9d8e3f67-967d-4412-b91a-23beec930b8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491500561 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_rx
.1491500561
Directory /workspace/32.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_mode_toggle.2178233046
Short name T63
Test name
Test status
Simulation time 5338708362 ps
CPU time 30.18 seconds
Started Jul 03 05:26:14 PM PDT 24
Finished Jul 03 05:26:45 PM PDT 24
Peak memory 343536 kb
Host smart-b3c54054-33c0-46b4-843e-6ca93d7fa00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178233046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_mode_toggle.2178233046
Directory /workspace/13.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_full.2674423582
Short name T84
Test name
Test status
Simulation time 8270032533 ps
CPU time 126.83 seconds
Started Jul 03 05:24:50 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 608612 kb
Host smart-59c29564-7590-4c45-9849-c6ad19fbd9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674423582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_full.2674423582
Directory /workspace/0.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_target_intr_stress_wr.4026942286
Short name T149
Test name
Test status
Simulation time 20105307506 ps
CPU time 51.67 seconds
Started Jul 03 05:27:12 PM PDT 24
Finished Jul 03 05:28:04 PM PDT 24
Peak memory 792132 kb
Host smart-eda5fbe0-d9c7-4b57-b62d-ea7f8b159a0e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026942286 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.i2c_target_intr_stress_wr.4026942286
Directory /workspace/27.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_same_csr_outstanding.1865695297
Short name T229
Test name
Test status
Simulation time 101847953 ps
CPU time 1.22 seconds
Started Jul 03 05:38:02 PM PDT 24
Finished Jul 03 05:38:04 PM PDT 24
Peak memory 204556 kb
Host smart-290bda99-4fd7-429a-b284-3c811689b0a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865695297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_same_csr_ou
tstanding.1865695297
Directory /workspace/1.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/25.i2c_intr_test.226162058
Short name T1536
Test name
Test status
Simulation time 55052337 ps
CPU time 0.65 seconds
Started Jul 03 05:38:28 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204344 kb
Host smart-22976824-a2b5-4043-8933-f8ca09e1ac59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226162058 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.i2c_intr_test.226162058
Directory /workspace/25.i2c_intr_test/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_fmt.3199750216
Short name T237
Test name
Test status
Simulation time 750258291 ps
CPU time 0.91 seconds
Started Jul 03 05:25:54 PM PDT 24
Finished Jul 03 05:25:55 PM PDT 24
Peak memory 204344 kb
Host smart-e587f227-e888-4430-818a-c24c2fffbfea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199750216 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_f
mt.3199750216
Directory /workspace/12.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_acq.210316842
Short name T230
Test name
Test status
Simulation time 175712452 ps
CPU time 1.09 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:35 PM PDT 24
Peak memory 212856 kb
Host smart-b428ffc9-0d7e-4646-a974-81ded21f2b39
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210316842 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_acq.210316842
Directory /workspace/18.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_tx.838383787
Short name T231
Test name
Test status
Simulation time 221793188 ps
CPU time 1.48 seconds
Started Jul 03 05:27:05 PM PDT 24
Finished Jul 03 05:27:07 PM PDT 24
Peak memory 207996 kb
Host smart-44b787b8-2ca2-4e87-b69d-4f761855c466
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838383787 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.i2c_target_fifo_reset_tx.838383787
Directory /workspace/24.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_hrst.3984449270
Short name T266
Test name
Test status
Simulation time 1257633839 ps
CPU time 2.66 seconds
Started Jul 03 05:27:50 PM PDT 24
Finished Jul 03 05:27:53 PM PDT 24
Peak memory 204796 kb
Host smart-a3075669-9ad0-471f-939c-3f91eb3c6667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984449270 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 35.i2c_target_hrst.3984449270
Directory /workspace/35.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_acq.2153642857
Short name T186
Test name
Test status
Simulation time 385368881 ps
CPU time 2.23 seconds
Started Jul 03 05:29:04 PM PDT 24
Finished Jul 03 05:29:07 PM PDT 24
Peak memory 204828 kb
Host smart-9534adab-5365-40f1-b0f7-b847b4c20f01
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153642857 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.i2c_target_fifo_watermarks_acq.2153642857
Directory /workspace/49.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_full.2367440852
Short name T77
Test name
Test status
Simulation time 8842878999 ps
CPU time 147.54 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:28:46 PM PDT 24
Peak memory 657548 kb
Host smart-943c6ce3-3918-4c0d-93be-d833680b5baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367440852 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_full.2367440852
Directory /workspace/15.i2c_host_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_intg_err.1894259552
Short name T200
Test name
Test status
Simulation time 523624393 ps
CPU time 2.35 seconds
Started Jul 03 05:38:14 PM PDT 24
Finished Jul 03 05:38:17 PM PDT 24
Peak memory 204640 kb
Host smart-6509ef9f-e854-4d8d-be79-a7f43e78fab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894259552 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_intg_err.1894259552
Directory /workspace/11.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/21.i2c_host_mode_toggle.55095291
Short name T239
Test name
Test status
Simulation time 2017599569 ps
CPU time 94.59 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:28:13 PM PDT 24
Peak memory 415520 kb
Host smart-3b0326b1-781e-4733-8f3c-323e6ba62e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55095291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_mode_toggle.55095291
Directory /workspace/21.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_acq.2528811757
Short name T174
Test name
Test status
Simulation time 290771194 ps
CPU time 1.28 seconds
Started Jul 03 05:26:47 PM PDT 24
Finished Jul 03 05:26:49 PM PDT 24
Peak memory 204604 kb
Host smart-92ece415-2932-4354-a8ad-9a80dada24a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528811757 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_fifo_reset_acq.2528811757
Directory /workspace/22.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_host_perf.224643786
Short name T59
Test name
Test status
Simulation time 6305247731 ps
CPU time 130.68 seconds
Started Jul 03 05:25:00 PM PDT 24
Finished Jul 03 05:27:11 PM PDT 24
Peak memory 204960 kb
Host smart-2aced00e-9b83-4fe5-bc41-09c8b04f00cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224643786 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf.224643786
Directory /workspace/1.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_may_nack.1077999659
Short name T253
Test name
Test status
Simulation time 427361269 ps
CPU time 5.42 seconds
Started Jul 03 05:24:59 PM PDT 24
Finished Jul 03 05:25:05 PM PDT 24
Peak memory 204896 kb
Host smart-96b2ccbe-fc3f-4ec5-9150-519353dcd564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077999659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_may_nack.1077999659
Directory /workspace/0.i2c_host_may_nack/latest

Test location /workspace/coverage/default/0.i2c_host_stress_all.1290591307
Short name T76
Test name
Test status
Simulation time 9711538368 ps
CPU time 316.01 seconds
Started Jul 03 05:24:49 PM PDT 24
Finished Jul 03 05:30:07 PM PDT 24
Peak memory 1298048 kb
Host smart-bb568322-4718-4ef9-9e42-d7fc12eeb646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290591307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stress_all.1290591307
Directory /workspace/0.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_mode_toggle.3661937654
Short name T957
Test name
Test status
Simulation time 3467493124 ps
CPU time 32.36 seconds
Started Jul 03 05:25:00 PM PDT 24
Finished Jul 03 05:25:33 PM PDT 24
Peak memory 358116 kb
Host smart-87fe7cea-48f6-490d-8ccc-555ea57f334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661937654 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_mode_toggle.3661937654
Directory /workspace/1.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_stress_all.711583777
Short name T265
Test name
Test status
Simulation time 26484290617 ps
CPU time 682.71 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:37:07 PM PDT 24
Peak memory 1043796 kb
Host smart-e947c09c-9896-4265-88bf-e77b0f9b95a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711583777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stress_all.711583777
Directory /workspace/10.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_target_bad_addr.461486802
Short name T279
Test name
Test status
Simulation time 1314023144 ps
CPU time 3.52 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:25:55 PM PDT 24
Peak memory 204788 kb
Host smart-ce9d44a0-74b6-41c6-8850-07b48e479fd0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461486802 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.i2c_target_bad_addr.461486802
Directory /workspace/11.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_acq.1482482009
Short name T966
Test name
Test status
Simulation time 593798507 ps
CPU time 3.01 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:26:01 PM PDT 24
Peak memory 204776 kb
Host smart-9644eca1-7db4-47d7-8a62-e7ff36ae4c56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482482009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.i2c_target_fifo_watermarks_acq.1482482009
Directory /workspace/11.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_watermark.2397869483
Short name T155
Test name
Test status
Simulation time 16329357826 ps
CPU time 302.09 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 1181856 kb
Host smart-c1f5e911-cf59-478d-bc1d-cdbc63278629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397869483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_watermark.2397869483
Directory /workspace/12.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_watermark.2487843491
Short name T264
Test name
Test status
Simulation time 14230153083 ps
CPU time 282.02 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:31:21 PM PDT 24
Peak memory 1194812 kb
Host smart-5ad35210-de09-40ba-8f05-3aca28cfd81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487843491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_watermark.2487843491
Directory /workspace/19.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_stretch_timeout.1702994291
Short name T390
Test name
Test status
Simulation time 514470934 ps
CPU time 21.84 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 213008 kb
Host smart-0e46888a-6d55-424b-bb3c-470716afd890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702994291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stretch_timeout.1702994291
Directory /workspace/20.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_intg_err.2593430011
Short name T193
Test name
Test status
Simulation time 137650057 ps
CPU time 2.16 seconds
Started Jul 03 05:38:22 PM PDT 24
Finished Jul 03 05:38:25 PM PDT 24
Peak memory 204576 kb
Host smart-ccb8701b-39e1-4176-a4dd-88e56d7aad9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593430011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_intg_err.2593430011
Directory /workspace/14.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_errors.829375515
Short name T1590
Test name
Test status
Simulation time 85105426 ps
CPU time 1.29 seconds
Started Jul 03 05:38:19 PM PDT 24
Finished Jul 03 05:38:21 PM PDT 24
Peak memory 204584 kb
Host smart-bc0ec641-3aef-47ec-9482-873f56432ac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829375515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_errors.829375515
Directory /workspace/15.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_intg_err.2267697186
Short name T203
Test name
Test status
Simulation time 706674617 ps
CPU time 1.45 seconds
Started Jul 03 05:38:02 PM PDT 24
Finished Jul 03 05:38:03 PM PDT 24
Peak memory 204524 kb
Host smart-50a1c362-815b-4d8b-b260-7ec8afc5f349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267697186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_intg_err.2267697186
Directory /workspace/1.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_intg_err.2131968850
Short name T179
Test name
Test status
Simulation time 90508664 ps
CPU time 2.03 seconds
Started Jul 03 05:38:23 PM PDT 24
Finished Jul 03 05:38:25 PM PDT 24
Peak memory 204596 kb
Host smart-6317c5e2-9d9b-429b-aa64-6c01ad107d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131968850 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_intg_err.2131968850
Directory /workspace/17.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_intg_err.3434836171
Short name T106
Test name
Test status
Simulation time 281303228 ps
CPU time 2.31 seconds
Started Jul 03 05:38:12 PM PDT 24
Finished Jul 03 05:38:15 PM PDT 24
Peak memory 204588 kb
Host smart-1ef0c224-4904-4c7c-bfcd-767fe90a7e3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434836171 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_intg_err.3434836171
Directory /workspace/5.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_same_csr_outstanding.4210382663
Short name T141
Test name
Test status
Simulation time 478491804 ps
CPU time 1.22 seconds
Started Jul 03 05:38:08 PM PDT 24
Finished Jul 03 05:38:10 PM PDT 24
Peak memory 204528 kb
Host smart-31f15472-40d3-4e5b-9ecb-b48e0cf84246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210382663 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_same_csr_ou
tstanding.4210382663
Directory /workspace/6.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_acq.3739221595
Short name T150
Test name
Test status
Simulation time 526601248 ps
CPU time 1.23 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:27:10 PM PDT 24
Peak memory 204788 kb
Host smart-3f663346-ad0a-413a-b2ff-9c1d183bb7a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739221595 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_fifo_reset_acq.3739221595
Directory /workspace/26.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_aliasing.2591769121
Short name T1591
Test name
Test status
Simulation time 50050199 ps
CPU time 1.22 seconds
Started Jul 03 05:37:57 PM PDT 24
Finished Jul 03 05:37:58 PM PDT 24
Peak memory 204572 kb
Host smart-c02236fa-3a00-44ba-9675-ae4cd5f8bea1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591769121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_aliasing.2591769121
Directory /workspace/0.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_bit_bash.1182070918
Short name T99
Test name
Test status
Simulation time 478636205 ps
CPU time 3.05 seconds
Started Jul 03 05:37:57 PM PDT 24
Finished Jul 03 05:38:00 PM PDT 24
Peak memory 204572 kb
Host smart-c33b6218-b294-4aba-b632-ef068832f5e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182070918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_bit_bash.1182070918
Directory /workspace/0.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_hw_reset.2366322978
Short name T1554
Test name
Test status
Simulation time 183840336 ps
CPU time 0.72 seconds
Started Jul 03 05:37:58 PM PDT 24
Finished Jul 03 05:37:59 PM PDT 24
Peak memory 204436 kb
Host smart-8d77516d-6f48-4565-af33-60d6d701cdd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366322978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_hw_reset.2366322978
Directory /workspace/0.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.246541575
Short name T1573
Test name
Test status
Simulation time 30784760 ps
CPU time 1.49 seconds
Started Jul 03 05:38:01 PM PDT 24
Finished Jul 03 05:38:03 PM PDT 24
Peak memory 204672 kb
Host smart-883e96cb-88dc-4e5d-84fe-668ecb59daf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246541575 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.i2c_csr_mem_rw_with_rand_reset.246541575
Directory /workspace/0.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_csr_rw.2754694385
Short name T1607
Test name
Test status
Simulation time 40636047 ps
CPU time 0.76 seconds
Started Jul 03 05:37:58 PM PDT 24
Finished Jul 03 05:37:59 PM PDT 24
Peak memory 204404 kb
Host smart-87114925-534a-4601-8e2e-c490bcbf60b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754694385 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_csr_rw.2754694385
Directory /workspace/0.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_intr_test.110490643
Short name T1596
Test name
Test status
Simulation time 26673538 ps
CPU time 0.64 seconds
Started Jul 03 05:37:56 PM PDT 24
Finished Jul 03 05:37:57 PM PDT 24
Peak memory 204380 kb
Host smart-61f46a11-0faf-4ccc-9241-d7eef00457f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110490643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_intr_test.110490643
Directory /workspace/0.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_same_csr_outstanding.3773051950
Short name T1545
Test name
Test status
Simulation time 52534746 ps
CPU time 0.83 seconds
Started Jul 03 05:37:59 PM PDT 24
Finished Jul 03 05:38:00 PM PDT 24
Peak memory 204460 kb
Host smart-fe354b6a-79c1-4d5f-ad29-9acc74239872
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773051950 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_same_csr_ou
tstanding.3773051950
Directory /workspace/0.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_errors.1763060381
Short name T191
Test name
Test status
Simulation time 44354332 ps
CPU time 2.24 seconds
Started Jul 03 05:38:00 PM PDT 24
Finished Jul 03 05:38:02 PM PDT 24
Peak memory 204620 kb
Host smart-753f3730-8c3d-49c1-b5fd-c6757413b4e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763060381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_errors.1763060381
Directory /workspace/0.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.i2c_tl_intg_err.3761574756
Short name T1595
Test name
Test status
Simulation time 223481668 ps
CPU time 1.38 seconds
Started Jul 03 05:37:57 PM PDT 24
Finished Jul 03 05:37:59 PM PDT 24
Peak memory 204568 kb
Host smart-3d1fb1fe-fae1-4e00-8810-35b5cd4d76a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761574756 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.i2c_tl_intg_err.3761574756
Directory /workspace/0.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_aliasing.3299504106
Short name T1634
Test name
Test status
Simulation time 806339345 ps
CPU time 1.98 seconds
Started Jul 03 05:38:03 PM PDT 24
Finished Jul 03 05:38:05 PM PDT 24
Peak memory 204520 kb
Host smart-979f0764-1fae-44ff-9dd6-bd55366cddd9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299504106 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_aliasing.3299504106
Directory /workspace/1.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_bit_bash.2738758735
Short name T1642
Test name
Test status
Simulation time 245504102 ps
CPU time 2.57 seconds
Started Jul 03 05:37:58 PM PDT 24
Finished Jul 03 05:38:01 PM PDT 24
Peak memory 204572 kb
Host smart-64651e7e-abab-4ad8-872d-7cc79a953021
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738758735 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_bit_bash.2738758735
Directory /workspace/1.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_hw_reset.2496193166
Short name T219
Test name
Test status
Simulation time 20699723 ps
CPU time 0.78 seconds
Started Jul 03 05:38:01 PM PDT 24
Finished Jul 03 05:38:02 PM PDT 24
Peak memory 204440 kb
Host smart-4c2094f5-388a-4c28-a51c-c34f0b8f6da3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496193166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_hw_reset.2496193166
Directory /workspace/1.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.405174678
Short name T1612
Test name
Test status
Simulation time 69068779 ps
CPU time 0.92 seconds
Started Jul 03 05:38:01 PM PDT 24
Finished Jul 03 05:38:02 PM PDT 24
Peak memory 204512 kb
Host smart-c42900a9-e584-4ca9-87e4-c1a317e7290d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405174678 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.i2c_csr_mem_rw_with_rand_reset.405174678
Directory /workspace/1.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_csr_rw.3720793182
Short name T215
Test name
Test status
Simulation time 17751240 ps
CPU time 0.81 seconds
Started Jul 03 05:38:03 PM PDT 24
Finished Jul 03 05:38:04 PM PDT 24
Peak memory 204372 kb
Host smart-be23c45a-a3b8-4d17-b1e4-a7b6937a9b60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720793182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_csr_rw.3720793182
Directory /workspace/1.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_intr_test.3936256764
Short name T1543
Test name
Test status
Simulation time 117184552 ps
CPU time 0.6 seconds
Started Jul 03 05:38:02 PM PDT 24
Finished Jul 03 05:38:02 PM PDT 24
Peak memory 204388 kb
Host smart-6e61c528-1870-4449-9388-cb872c5f0dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936256764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_intr_test.3936256764
Directory /workspace/1.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.i2c_tl_errors.1037323142
Short name T1583
Test name
Test status
Simulation time 165751949 ps
CPU time 1.18 seconds
Started Jul 03 05:37:59 PM PDT 24
Finished Jul 03 05:38:01 PM PDT 24
Peak memory 204592 kb
Host smart-74ea2fad-8591-4c49-857e-3ad890829aed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037323142 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.i2c_tl_errors.1037323142
Directory /workspace/1.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_mem_rw_with_rand_reset.4177608198
Short name T1566
Test name
Test status
Simulation time 135348935 ps
CPU time 0.96 seconds
Started Jul 03 05:38:15 PM PDT 24
Finished Jul 03 05:38:16 PM PDT 24
Peak memory 204484 kb
Host smart-8c986443-c7c0-4003-b480-3c827f4a3171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177608198 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.i2c_csr_mem_rw_with_rand_reset.4177608198
Directory /workspace/10.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_csr_rw.1523834227
Short name T223
Test name
Test status
Simulation time 99371207 ps
CPU time 0.81 seconds
Started Jul 03 05:38:16 PM PDT 24
Finished Jul 03 05:38:17 PM PDT 24
Peak memory 204436 kb
Host smart-a15a2e5f-6633-440d-ba3f-70dbf52b698b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523834227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_csr_rw.1523834227
Directory /workspace/10.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_intr_test.4181705469
Short name T1571
Test name
Test status
Simulation time 42878212 ps
CPU time 0.66 seconds
Started Jul 03 05:38:17 PM PDT 24
Finished Jul 03 05:38:18 PM PDT 24
Peak memory 204316 kb
Host smart-b21b7579-77d6-4e28-a62d-ddf5baea9102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181705469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_intr_test.4181705469
Directory /workspace/10.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_same_csr_outstanding.3426401496
Short name T1636
Test name
Test status
Simulation time 127744256 ps
CPU time 0.88 seconds
Started Jul 03 05:38:14 PM PDT 24
Finished Jul 03 05:38:16 PM PDT 24
Peak memory 204432 kb
Host smart-c90496e9-ac8e-48a6-8755-0e770984e561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426401496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_same_csr_o
utstanding.3426401496
Directory /workspace/10.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_errors.1534467586
Short name T1597
Test name
Test status
Simulation time 136274215 ps
CPU time 1.3 seconds
Started Jul 03 05:38:11 PM PDT 24
Finished Jul 03 05:38:13 PM PDT 24
Peak memory 204572 kb
Host smart-6ad152e4-2a7e-4f81-afe2-61d7284399f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534467586 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_errors.1534467586
Directory /workspace/10.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.i2c_tl_intg_err.2894013799
Short name T205
Test name
Test status
Simulation time 87673244 ps
CPU time 2.13 seconds
Started Jul 03 05:38:12 PM PDT 24
Finished Jul 03 05:38:14 PM PDT 24
Peak memory 204588 kb
Host smart-dddcd6b4-a285-48e9-9dca-3e621fb7b4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894013799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.i2c_tl_intg_err.2894013799
Directory /workspace/10.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_csr_rw.3855228509
Short name T220
Test name
Test status
Simulation time 19344173 ps
CPU time 0.74 seconds
Started Jul 03 05:38:15 PM PDT 24
Finished Jul 03 05:38:16 PM PDT 24
Peak memory 204464 kb
Host smart-d855fd08-091e-4842-b9bb-1b972bad7086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855228509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_csr_rw.3855228509
Directory /workspace/11.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_intr_test.26262368
Short name T1542
Test name
Test status
Simulation time 78515868 ps
CPU time 0.68 seconds
Started Jul 03 05:38:16 PM PDT 24
Finished Jul 03 05:38:17 PM PDT 24
Peak memory 204332 kb
Host smart-b1a492c9-8c62-4cab-b9ac-bf699cc94100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26262368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_intr_test.26262368
Directory /workspace/11.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_same_csr_outstanding.3085274594
Short name T1622
Test name
Test status
Simulation time 237907811 ps
CPU time 1.18 seconds
Started Jul 03 05:38:16 PM PDT 24
Finished Jul 03 05:38:17 PM PDT 24
Peak memory 204532 kb
Host smart-2aae1fda-a960-47c1-a845-a351bfefa622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085274594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_same_csr_o
utstanding.3085274594
Directory /workspace/11.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.i2c_tl_errors.3506295486
Short name T1639
Test name
Test status
Simulation time 102525694 ps
CPU time 2.38 seconds
Started Jul 03 05:38:16 PM PDT 24
Finished Jul 03 05:38:18 PM PDT 24
Peak memory 204560 kb
Host smart-b1913645-1fe0-4ced-9d8d-0abf44456d8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506295486 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.i2c_tl_errors.3506295486
Directory /workspace/11.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_mem_rw_with_rand_reset.1904664845
Short name T1578
Test name
Test status
Simulation time 41959443 ps
CPU time 1.01 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:20 PM PDT 24
Peak memory 204496 kb
Host smart-73223ae5-ca45-48ba-a2c9-b92d83df36bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904664845 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 12.i2c_csr_mem_rw_with_rand_reset.1904664845
Directory /workspace/12.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_csr_rw.659883445
Short name T1628
Test name
Test status
Simulation time 21552623 ps
CPU time 0.74 seconds
Started Jul 03 05:38:22 PM PDT 24
Finished Jul 03 05:38:23 PM PDT 24
Peak memory 204436 kb
Host smart-ea620d9d-bf1d-4f9d-8444-d0bbb3f765f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659883445 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_csr_rw.659883445
Directory /workspace/12.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_intr_test.2536307909
Short name T1617
Test name
Test status
Simulation time 18065119 ps
CPU time 0.75 seconds
Started Jul 03 05:38:19 PM PDT 24
Finished Jul 03 05:38:20 PM PDT 24
Peak memory 204364 kb
Host smart-1fa94a7e-83c4-4aa6-990a-8f0f824404e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536307909 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_intr_test.2536307909
Directory /workspace/12.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_same_csr_outstanding.3792162713
Short name T1581
Test name
Test status
Simulation time 53643767 ps
CPU time 1.16 seconds
Started Jul 03 05:38:19 PM PDT 24
Finished Jul 03 05:38:21 PM PDT 24
Peak memory 204536 kb
Host smart-311c094f-0627-4a9d-884b-9773aa393614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792162713 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_same_csr_o
utstanding.3792162713
Directory /workspace/12.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_errors.2950390915
Short name T1613
Test name
Test status
Simulation time 325220614 ps
CPU time 1.42 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:20 PM PDT 24
Peak memory 204612 kb
Host smart-fb2e19b0-f0a0-4916-8cec-858c7e6de4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950390915 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_errors.2950390915
Directory /workspace/12.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.i2c_tl_intg_err.3123229911
Short name T1643
Test name
Test status
Simulation time 333163850 ps
CPU time 1.38 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:20 PM PDT 24
Peak memory 204612 kb
Host smart-e3f19b21-c6f0-4726-9d77-5ff2ca68aa5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123229911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.i2c_tl_intg_err.3123229911
Directory /workspace/12.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_mem_rw_with_rand_reset.1634371467
Short name T1601
Test name
Test status
Simulation time 112172868 ps
CPU time 1 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:20 PM PDT 24
Peak memory 204416 kb
Host smart-9e85c497-eae7-4bd8-a5aa-df0f820b8772
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634371467 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 13.i2c_csr_mem_rw_with_rand_reset.1634371467
Directory /workspace/13.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_csr_rw.708815824
Short name T216
Test name
Test status
Simulation time 26452692 ps
CPU time 0.83 seconds
Started Jul 03 05:38:23 PM PDT 24
Finished Jul 03 05:38:24 PM PDT 24
Peak memory 204440 kb
Host smart-8c7a11a9-a8cd-4304-9769-66e4c9390623
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708815824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_csr_rw.708815824
Directory /workspace/13.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_intr_test.3588610459
Short name T1570
Test name
Test status
Simulation time 91005896 ps
CPU time 0.66 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:19 PM PDT 24
Peak memory 204344 kb
Host smart-25b0e705-6ca5-4e91-b4b6-32708c004194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588610459 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_intr_test.3588610459
Directory /workspace/13.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_same_csr_outstanding.1351128262
Short name T226
Test name
Test status
Simulation time 84214628 ps
CPU time 1.13 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:20 PM PDT 24
Peak memory 204540 kb
Host smart-3f84c3be-b47f-438c-ad28-63a04a61ada3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351128262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_same_csr_o
utstanding.1351128262
Directory /workspace/13.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_errors.3030054872
Short name T121
Test name
Test status
Simulation time 222952038 ps
CPU time 1.09 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:20 PM PDT 24
Peak memory 204496 kb
Host smart-0ad7fe3c-984e-43dd-a350-4996b6ad19cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030054872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_errors.3030054872
Directory /workspace/13.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.i2c_tl_intg_err.3397756214
Short name T1551
Test name
Test status
Simulation time 56337500 ps
CPU time 1.43 seconds
Started Jul 03 05:38:19 PM PDT 24
Finished Jul 03 05:38:21 PM PDT 24
Peak memory 204624 kb
Host smart-4d918d0f-e6ad-435d-8522-de0dee12587c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397756214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.i2c_tl_intg_err.3397756214
Directory /workspace/13.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_mem_rw_with_rand_reset.457593484
Short name T1575
Test name
Test status
Simulation time 148929359 ps
CPU time 1.24 seconds
Started Jul 03 05:38:17 PM PDT 24
Finished Jul 03 05:38:18 PM PDT 24
Peak memory 204660 kb
Host smart-dfff4633-a432-4a2c-a21a-6b000849eb1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457593484 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.i2c_csr_mem_rw_with_rand_reset.457593484
Directory /workspace/14.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_csr_rw.4104004467
Short name T212
Test name
Test status
Simulation time 45727907 ps
CPU time 0.71 seconds
Started Jul 03 05:38:20 PM PDT 24
Finished Jul 03 05:38:21 PM PDT 24
Peak memory 204420 kb
Host smart-5f86079e-2448-493b-a8d4-f35630218ebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104004467 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_csr_rw.4104004467
Directory /workspace/14.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_intr_test.3829487560
Short name T1576
Test name
Test status
Simulation time 16497343 ps
CPU time 0.65 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:19 PM PDT 24
Peak memory 204252 kb
Host smart-8077c7b9-e3f6-4e3e-94e2-ee7ac0acda7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829487560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_intr_test.3829487560
Directory /workspace/14.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_same_csr_outstanding.2751030856
Short name T1605
Test name
Test status
Simulation time 83968792 ps
CPU time 1.17 seconds
Started Jul 03 05:38:18 PM PDT 24
Finished Jul 03 05:38:20 PM PDT 24
Peak memory 204484 kb
Host smart-cb518722-626d-4c48-84e0-e555ad947cb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751030856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_same_csr_o
utstanding.2751030856
Directory /workspace/14.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.i2c_tl_errors.3029943387
Short name T1640
Test name
Test status
Simulation time 273673286 ps
CPU time 1.73 seconds
Started Jul 03 05:38:19 PM PDT 24
Finished Jul 03 05:38:21 PM PDT 24
Peak memory 204640 kb
Host smart-412ee894-9d9e-47ec-8616-3a95801b2013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029943387 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.i2c_tl_errors.3029943387
Directory /workspace/14.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_mem_rw_with_rand_reset.2565275626
Short name T140
Test name
Test status
Simulation time 70536603 ps
CPU time 0.8 seconds
Started Jul 03 05:38:24 PM PDT 24
Finished Jul 03 05:38:26 PM PDT 24
Peak memory 204448 kb
Host smart-e9214c6a-9d2e-43f4-99d1-2ce9a71fddec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565275626 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 15.i2c_csr_mem_rw_with_rand_reset.2565275626
Directory /workspace/15.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_csr_rw.1035950725
Short name T1632
Test name
Test status
Simulation time 23596135 ps
CPU time 0.73 seconds
Started Jul 03 05:38:23 PM PDT 24
Finished Jul 03 05:38:24 PM PDT 24
Peak memory 204412 kb
Host smart-97da07a5-4e01-4cea-868c-2fda61fc0915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035950725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_csr_rw.1035950725
Directory /workspace/15.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_intr_test.178925687
Short name T1568
Test name
Test status
Simulation time 28445530 ps
CPU time 0.68 seconds
Started Jul 03 05:38:22 PM PDT 24
Finished Jul 03 05:38:23 PM PDT 24
Peak memory 204316 kb
Host smart-fe40d706-4586-4007-9276-fb77278e2563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178925687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_intr_test.178925687
Directory /workspace/15.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.i2c_tl_intg_err.197527987
Short name T190
Test name
Test status
Simulation time 245960699 ps
CPU time 1.38 seconds
Started Jul 03 05:38:22 PM PDT 24
Finished Jul 03 05:38:24 PM PDT 24
Peak memory 204556 kb
Host smart-f91611ef-0510-4098-9f11-3fbb8b563f8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197527987 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.i2c_tl_intg_err.197527987
Directory /workspace/15.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_mem_rw_with_rand_reset.517953600
Short name T1635
Test name
Test status
Simulation time 177070706 ps
CPU time 1.31 seconds
Started Jul 03 05:38:22 PM PDT 24
Finished Jul 03 05:38:24 PM PDT 24
Peak memory 212852 kb
Host smart-aa1b54f0-683e-4193-a9bc-14eaab6e3493
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517953600 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.i2c_csr_mem_rw_with_rand_reset.517953600
Directory /workspace/16.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_csr_rw.3066693848
Short name T1556
Test name
Test status
Simulation time 71521750 ps
CPU time 0.69 seconds
Started Jul 03 05:38:25 PM PDT 24
Finished Jul 03 05:38:26 PM PDT 24
Peak memory 204468 kb
Host smart-196a4ebb-6be3-48c5-8871-368f9c6121c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066693848 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_csr_rw.3066693848
Directory /workspace/16.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_intr_test.364343629
Short name T1567
Test name
Test status
Simulation time 21908337 ps
CPU time 0.7 seconds
Started Jul 03 05:38:30 PM PDT 24
Finished Jul 03 05:38:32 PM PDT 24
Peak memory 204348 kb
Host smart-91e56478-9643-438c-bdd4-f82d416de109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364343629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_intr_test.364343629
Directory /workspace/16.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_same_csr_outstanding.1634372415
Short name T225
Test name
Test status
Simulation time 155165459 ps
CPU time 0.84 seconds
Started Jul 03 05:38:28 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204424 kb
Host smart-f796d51e-c576-4e23-b127-31d02981bfaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634372415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_same_csr_o
utstanding.1634372415
Directory /workspace/16.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_errors.1286125732
Short name T196
Test name
Test status
Simulation time 127966592 ps
CPU time 2.35 seconds
Started Jul 03 05:38:24 PM PDT 24
Finished Jul 03 05:38:27 PM PDT 24
Peak memory 204684 kb
Host smart-49f5e4c5-46a8-4f85-aea2-051e7ef0a914
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286125732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_errors.1286125732
Directory /workspace/16.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.i2c_tl_intg_err.1220161880
Short name T1611
Test name
Test status
Simulation time 81318239 ps
CPU time 1.45 seconds
Started Jul 03 05:38:24 PM PDT 24
Finished Jul 03 05:38:26 PM PDT 24
Peak memory 204620 kb
Host smart-1ae33ccb-dafa-40a8-abc0-bef6141d1620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220161880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.i2c_tl_intg_err.1220161880
Directory /workspace/16.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_mem_rw_with_rand_reset.3931691340
Short name T188
Test name
Test status
Simulation time 67949526 ps
CPU time 0.83 seconds
Started Jul 03 05:38:30 PM PDT 24
Finished Jul 03 05:38:32 PM PDT 24
Peak memory 204480 kb
Host smart-38892738-185a-40f3-af1b-fb59afefb400
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931691340 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.i2c_csr_mem_rw_with_rand_reset.3931691340
Directory /workspace/17.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_csr_rw.3102857401
Short name T1609
Test name
Test status
Simulation time 75855698 ps
CPU time 0.76 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:28 PM PDT 24
Peak memory 204456 kb
Host smart-92f41261-7b12-4847-9c76-7e270611e9b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102857401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_csr_rw.3102857401
Directory /workspace/17.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_intr_test.2078615296
Short name T1555
Test name
Test status
Simulation time 41691249 ps
CPU time 0.7 seconds
Started Jul 03 05:38:30 PM PDT 24
Finished Jul 03 05:38:32 PM PDT 24
Peak memory 204364 kb
Host smart-c9ac0fa2-9c07-4adb-9c66-bfe5169d75bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078615296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_intr_test.2078615296
Directory /workspace/17.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_same_csr_outstanding.2560733770
Short name T1615
Test name
Test status
Simulation time 183259815 ps
CPU time 1.19 seconds
Started Jul 03 05:38:22 PM PDT 24
Finished Jul 03 05:38:24 PM PDT 24
Peak memory 204492 kb
Host smart-1679efcb-f813-4373-877d-d269182eeeea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560733770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_same_csr_o
utstanding.2560733770
Directory /workspace/17.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.i2c_tl_errors.3513111913
Short name T1621
Test name
Test status
Simulation time 505502805 ps
CPU time 2.47 seconds
Started Jul 03 05:38:23 PM PDT 24
Finished Jul 03 05:38:26 PM PDT 24
Peak memory 204680 kb
Host smart-e20c3c92-f25a-4d3f-a535-cbb3ca50d9b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513111913 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.i2c_tl_errors.3513111913
Directory /workspace/17.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_mem_rw_with_rand_reset.1750758824
Short name T1618
Test name
Test status
Simulation time 83193987 ps
CPU time 1.06 seconds
Started Jul 03 05:38:29 PM PDT 24
Finished Jul 03 05:38:31 PM PDT 24
Peak memory 204476 kb
Host smart-02890573-9c41-4b45-b261-f9c41f36dd36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750758824 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 18.i2c_csr_mem_rw_with_rand_reset.1750758824
Directory /workspace/18.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_csr_rw.2876563328
Short name T139
Test name
Test status
Simulation time 24583456 ps
CPU time 0.78 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204412 kb
Host smart-6c2d9f4d-7f3a-4cc3-916d-8252aadcc2fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876563328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_csr_rw.2876563328
Directory /workspace/18.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_intr_test.1902847453
Short name T1579
Test name
Test status
Simulation time 22312491 ps
CPU time 0.67 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:28 PM PDT 24
Peak memory 204304 kb
Host smart-27722604-d402-4246-ac93-6a47c76bc55f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902847453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_intr_test.1902847453
Directory /workspace/18.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_same_csr_outstanding.3597375285
Short name T1560
Test name
Test status
Simulation time 318124993 ps
CPU time 1.17 seconds
Started Jul 03 05:38:26 PM PDT 24
Finished Jul 03 05:38:28 PM PDT 24
Peak memory 204564 kb
Host smart-0d7a1cf6-a2ab-4d1c-947e-2ac51c2ead1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597375285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_same_csr_o
utstanding.3597375285
Directory /workspace/18.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_errors.3914226739
Short name T1626
Test name
Test status
Simulation time 60090967 ps
CPU time 1.75 seconds
Started Jul 03 05:38:30 PM PDT 24
Finished Jul 03 05:38:33 PM PDT 24
Peak memory 204636 kb
Host smart-c49b23b7-e9b7-4227-ba02-cac34fc67dce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914226739 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_errors.3914226739
Directory /workspace/18.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.i2c_tl_intg_err.2153792833
Short name T1637
Test name
Test status
Simulation time 54139721 ps
CPU time 1.44 seconds
Started Jul 03 05:38:24 PM PDT 24
Finished Jul 03 05:38:26 PM PDT 24
Peak memory 204576 kb
Host smart-49fe6e0f-8f2b-4536-ac8e-61789689c656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153792833 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.i2c_tl_intg_err.2153792833
Directory /workspace/18.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_mem_rw_with_rand_reset.2143005116
Short name T1619
Test name
Test status
Simulation time 38241548 ps
CPU time 1.14 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204556 kb
Host smart-16431e0f-82c9-4396-a339-70cc59aa090e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143005116 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 19.i2c_csr_mem_rw_with_rand_reset.2143005116
Directory /workspace/19.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_csr_rw.3542504013
Short name T227
Test name
Test status
Simulation time 164851213 ps
CPU time 0.69 seconds
Started Jul 03 05:38:32 PM PDT 24
Finished Jul 03 05:38:34 PM PDT 24
Peak memory 204356 kb
Host smart-8ada146d-38bb-440e-a51b-dd11c5753342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542504013 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_csr_rw.3542504013
Directory /workspace/19.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_intr_test.1627521583
Short name T1603
Test name
Test status
Simulation time 104143652 ps
CPU time 0.68 seconds
Started Jul 03 05:38:28 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204372 kb
Host smart-13bdc237-5ccc-4792-84c7-87e0a2e34dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627521583 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_intr_test.1627521583
Directory /workspace/19.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_same_csr_outstanding.1590038082
Short name T228
Test name
Test status
Simulation time 31342836 ps
CPU time 0.87 seconds
Started Jul 03 05:38:28 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204404 kb
Host smart-0e10141c-991c-469b-a7ab-e1882cf8f8df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590038082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_same_csr_o
utstanding.1590038082
Directory /workspace/19.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_errors.3833049754
Short name T1588
Test name
Test status
Simulation time 150487158 ps
CPU time 2.1 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204596 kb
Host smart-c511d5d3-1f5e-41bd-a342-9eeff30fa545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833049754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_errors.3833049754
Directory /workspace/19.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.i2c_tl_intg_err.378745373
Short name T202
Test name
Test status
Simulation time 1000927262 ps
CPU time 1.42 seconds
Started Jul 03 05:38:26 PM PDT 24
Finished Jul 03 05:38:28 PM PDT 24
Peak memory 204552 kb
Host smart-0515ab1d-0ce8-480b-a882-b85671f256d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378745373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.i2c_tl_intg_err.378745373
Directory /workspace/19.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_aliasing.4265511078
Short name T103
Test name
Test status
Simulation time 133061823 ps
CPU time 1.26 seconds
Started Jul 03 05:38:00 PM PDT 24
Finished Jul 03 05:38:01 PM PDT 24
Peak memory 204544 kb
Host smart-bf0615e8-f347-4aa8-aa9f-cf1f2f5bf0a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265511078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_aliasing.4265511078
Directory /workspace/2.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_bit_bash.329604539
Short name T102
Test name
Test status
Simulation time 2398338138 ps
CPU time 5.2 seconds
Started Jul 03 05:38:02 PM PDT 24
Finished Jul 03 05:38:08 PM PDT 24
Peak memory 204632 kb
Host smart-ccd63495-0563-4ad6-a30d-efc3044feacc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329604539 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_bit_bash.329604539
Directory /workspace/2.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.807125082
Short name T1589
Test name
Test status
Simulation time 46301671 ps
CPU time 1.04 seconds
Started Jul 03 05:38:00 PM PDT 24
Finished Jul 03 05:38:01 PM PDT 24
Peak memory 204512 kb
Host smart-f7521caa-3cc2-4272-a57c-081c9e99dc3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807125082 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.i2c_csr_mem_rw_with_rand_reset.807125082
Directory /workspace/2.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_csr_rw.3823566130
Short name T1587
Test name
Test status
Simulation time 22864183 ps
CPU time 0.71 seconds
Started Jul 03 05:38:01 PM PDT 24
Finished Jul 03 05:38:02 PM PDT 24
Peak memory 204428 kb
Host smart-be1809e8-abe8-413a-b5ac-d5784f9eff4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823566130 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_csr_rw.3823566130
Directory /workspace/2.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_intr_test.554063382
Short name T1572
Test name
Test status
Simulation time 40618260 ps
CPU time 0.65 seconds
Started Jul 03 05:38:00 PM PDT 24
Finished Jul 03 05:38:01 PM PDT 24
Peak memory 204332 kb
Host smart-bdf92116-4c35-4747-b1b3-55d03f6bd0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554063382 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_intr_test.554063382
Directory /workspace/2.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_same_csr_outstanding.2094840279
Short name T1592
Test name
Test status
Simulation time 24743246 ps
CPU time 1.09 seconds
Started Jul 03 05:38:03 PM PDT 24
Finished Jul 03 05:38:04 PM PDT 24
Peak memory 204568 kb
Host smart-dfbf898b-27c4-43a6-94f1-d1c53350f321
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094840279 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_same_csr_ou
tstanding.2094840279
Directory /workspace/2.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_errors.532991373
Short name T195
Test name
Test status
Simulation time 54319165 ps
CPU time 1.71 seconds
Started Jul 03 05:38:01 PM PDT 24
Finished Jul 03 05:38:03 PM PDT 24
Peak memory 204620 kb
Host smart-9a41c8eb-37fc-4d92-8e30-47e7b0ebbc96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532991373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_errors.532991373
Directory /workspace/2.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.i2c_tl_intg_err.1555720293
Short name T201
Test name
Test status
Simulation time 52189321 ps
CPU time 1.42 seconds
Started Jul 03 05:38:02 PM PDT 24
Finished Jul 03 05:38:04 PM PDT 24
Peak memory 204608 kb
Host smart-19eb64ff-c1cd-4645-b084-18ace5f2e08c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555720293 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.i2c_tl_intg_err.1555720293
Directory /workspace/2.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.i2c_intr_test.3389999331
Short name T1599
Test name
Test status
Simulation time 25190242 ps
CPU time 0.69 seconds
Started Jul 03 05:38:26 PM PDT 24
Finished Jul 03 05:38:27 PM PDT 24
Peak memory 204360 kb
Host smart-7e3594d3-48d4-46b9-b685-462ca7f2134c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389999331 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.i2c_intr_test.3389999331
Directory /workspace/20.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.i2c_intr_test.159620473
Short name T1549
Test name
Test status
Simulation time 37198706 ps
CPU time 0.7 seconds
Started Jul 03 05:38:32 PM PDT 24
Finished Jul 03 05:38:34 PM PDT 24
Peak memory 203844 kb
Host smart-d6f7a075-e690-4003-9715-46abd43812cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159620473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.i2c_intr_test.159620473
Directory /workspace/21.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.i2c_intr_test.4097774089
Short name T1541
Test name
Test status
Simulation time 146141271 ps
CPU time 0.71 seconds
Started Jul 03 05:38:28 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204336 kb
Host smart-abf71676-b338-41d9-9653-59712dff5b38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097774089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.i2c_intr_test.4097774089
Directory /workspace/22.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.i2c_intr_test.3260525217
Short name T1553
Test name
Test status
Simulation time 43857139 ps
CPU time 0.68 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:28 PM PDT 24
Peak memory 204332 kb
Host smart-a8485acf-b7ee-4fef-b38d-55ad88dd1b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260525217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.i2c_intr_test.3260525217
Directory /workspace/23.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.i2c_intr_test.431920661
Short name T1641
Test name
Test status
Simulation time 20758361 ps
CPU time 0.65 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:28 PM PDT 24
Peak memory 204348 kb
Host smart-02c3e2c7-b01d-4e7f-b624-b529e0ff6bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431920661 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.i2c_intr_test.431920661
Directory /workspace/24.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.i2c_intr_test.948662078
Short name T1557
Test name
Test status
Simulation time 17366550 ps
CPU time 0.68 seconds
Started Jul 03 05:38:32 PM PDT 24
Finished Jul 03 05:38:34 PM PDT 24
Peak memory 203780 kb
Host smart-6dc28147-cac7-4c02-af3b-61c73b03734f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948662078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.i2c_intr_test.948662078
Directory /workspace/26.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.i2c_intr_test.2433172671
Short name T1594
Test name
Test status
Simulation time 18323060 ps
CPU time 0.69 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204380 kb
Host smart-debcd728-1bfd-4289-9f49-b3bdb97de738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433172671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.i2c_intr_test.2433172671
Directory /workspace/27.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.i2c_intr_test.131187406
Short name T1633
Test name
Test status
Simulation time 41863630 ps
CPU time 0.73 seconds
Started Jul 03 05:38:27 PM PDT 24
Finished Jul 03 05:38:29 PM PDT 24
Peak memory 204316 kb
Host smart-f954b3e4-d186-4278-9b78-4301d7c32e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131187406 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.i2c_intr_test.131187406
Directory /workspace/28.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.i2c_intr_test.4005677188
Short name T1538
Test name
Test status
Simulation time 27782107 ps
CPU time 0.68 seconds
Started Jul 03 05:38:30 PM PDT 24
Finished Jul 03 05:38:31 PM PDT 24
Peak memory 204380 kb
Host smart-f0fe3061-25bf-4d33-96c8-616a03811d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005677188 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.i2c_intr_test.4005677188
Directory /workspace/29.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_aliasing.2706054929
Short name T213
Test name
Test status
Simulation time 66181092 ps
CPU time 1.32 seconds
Started Jul 03 05:38:13 PM PDT 24
Finished Jul 03 05:38:15 PM PDT 24
Peak memory 204620 kb
Host smart-264010b5-73a2-44d2-8f9b-9fc14ef472a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706054929 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_aliasing.2706054929
Directory /workspace/3.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_bit_bash.3694064349
Short name T1616
Test name
Test status
Simulation time 1389653208 ps
CPU time 5.07 seconds
Started Jul 03 05:38:13 PM PDT 24
Finished Jul 03 05:38:18 PM PDT 24
Peak memory 204552 kb
Host smart-549a7dff-914f-4ed0-bb76-9012ab7b9b7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694064349 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_bit_bash.3694064349
Directory /workspace/3.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_hw_reset.2617824138
Short name T214
Test name
Test status
Simulation time 243171517 ps
CPU time 0.73 seconds
Started Jul 03 05:38:02 PM PDT 24
Finished Jul 03 05:38:03 PM PDT 24
Peak memory 204392 kb
Host smart-03bd72dc-3759-4303-a97a-afe4db647414
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617824138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_hw_reset.2617824138
Directory /workspace/3.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.93547551
Short name T1564
Test name
Test status
Simulation time 313575793 ps
CPU time 0.99 seconds
Started Jul 03 05:38:04 PM PDT 24
Finished Jul 03 05:38:05 PM PDT 24
Peak memory 204464 kb
Host smart-112c1bec-4160-4dea-b1db-b4100d92a7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93547551 -assert nopostproc +UVM_TESTNAME=i
2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.i2c_csr_mem_rw_with_rand_reset.93547551
Directory /workspace/3.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_csr_rw.3955181730
Short name T222
Test name
Test status
Simulation time 29679954 ps
CPU time 0.75 seconds
Started Jul 03 05:38:05 PM PDT 24
Finished Jul 03 05:38:06 PM PDT 24
Peak memory 204400 kb
Host smart-61b816df-a236-4ebe-a425-ae4662c38f5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955181730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_csr_rw.3955181730
Directory /workspace/3.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_intr_test.383850592
Short name T1614
Test name
Test status
Simulation time 40842228 ps
CPU time 0.67 seconds
Started Jul 03 05:38:02 PM PDT 24
Finished Jul 03 05:38:04 PM PDT 24
Peak memory 204344 kb
Host smart-6eb1779a-ee54-45a8-ba3a-06ac0751d639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383850592 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_intr_test.383850592
Directory /workspace/3.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4137251348
Short name T98
Test name
Test status
Simulation time 44647813 ps
CPU time 0.91 seconds
Started Jul 03 05:38:04 PM PDT 24
Finished Jul 03 05:38:05 PM PDT 24
Peak memory 204460 kb
Host smart-f85ad075-504e-4db7-bd50-5c61407de8f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137251348 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_same_csr_ou
tstanding.4137251348
Directory /workspace/3.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_errors.3581054323
Short name T107
Test name
Test status
Simulation time 351973752 ps
CPU time 2.57 seconds
Started Jul 03 05:38:03 PM PDT 24
Finished Jul 03 05:38:06 PM PDT 24
Peak memory 204588 kb
Host smart-f3064c1e-3fe8-42c9-ba90-8da2d4fb138a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581054323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_errors.3581054323
Directory /workspace/3.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.i2c_tl_intg_err.3269588367
Short name T189
Test name
Test status
Simulation time 241402365 ps
CPU time 1.36 seconds
Started Jul 03 05:38:03 PM PDT 24
Finished Jul 03 05:38:05 PM PDT 24
Peak memory 204552 kb
Host smart-bf70f193-5435-4ae3-be4f-e76573a37393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269588367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.i2c_tl_intg_err.3269588367
Directory /workspace/3.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.i2c_intr_test.992249707
Short name T1627
Test name
Test status
Simulation time 57645558 ps
CPU time 0.67 seconds
Started Jul 03 05:38:30 PM PDT 24
Finished Jul 03 05:38:31 PM PDT 24
Peak memory 204252 kb
Host smart-0f2463cb-690b-42f8-90ce-ad0e391888ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992249707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.i2c_intr_test.992249707
Directory /workspace/30.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.i2c_intr_test.4146920722
Short name T1593
Test name
Test status
Simulation time 27645678 ps
CPU time 0.67 seconds
Started Jul 03 05:38:32 PM PDT 24
Finished Jul 03 05:38:33 PM PDT 24
Peak memory 204356 kb
Host smart-88d4a62e-fad7-4317-b4ae-d065fafd38d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146920722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.i2c_intr_test.4146920722
Directory /workspace/31.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.i2c_intr_test.830510410
Short name T1544
Test name
Test status
Simulation time 18591180 ps
CPU time 0.7 seconds
Started Jul 03 05:38:32 PM PDT 24
Finished Jul 03 05:38:33 PM PDT 24
Peak memory 204360 kb
Host smart-8f70c731-9033-44cc-9c2b-6273fc2d8e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830510410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.i2c_intr_test.830510410
Directory /workspace/32.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.i2c_intr_test.640667472
Short name T1540
Test name
Test status
Simulation time 58779958 ps
CPU time 0.71 seconds
Started Jul 03 05:38:33 PM PDT 24
Finished Jul 03 05:38:34 PM PDT 24
Peak memory 204348 kb
Host smart-5a04b97c-61fa-40b6-9df8-57e169476565
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640667472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.i2c_intr_test.640667472
Directory /workspace/33.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.i2c_intr_test.1174877017
Short name T1606
Test name
Test status
Simulation time 81254936 ps
CPU time 0.68 seconds
Started Jul 03 05:38:33 PM PDT 24
Finished Jul 03 05:38:34 PM PDT 24
Peak memory 204280 kb
Host smart-c08f1b1c-e5dc-4078-8125-7ac998438da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174877017 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.i2c_intr_test.1174877017
Directory /workspace/34.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.i2c_intr_test.2009533424
Short name T1600
Test name
Test status
Simulation time 32956976 ps
CPU time 0.68 seconds
Started Jul 03 05:38:31 PM PDT 24
Finished Jul 03 05:38:32 PM PDT 24
Peak memory 204344 kb
Host smart-06e9a005-b057-4317-a174-f21c019d1c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009533424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.i2c_intr_test.2009533424
Directory /workspace/35.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.i2c_intr_test.3368728903
Short name T1548
Test name
Test status
Simulation time 18887885 ps
CPU time 0.77 seconds
Started Jul 03 05:38:33 PM PDT 24
Finished Jul 03 05:38:34 PM PDT 24
Peak memory 204336 kb
Host smart-e119a53b-1c62-4ed1-9032-6dd8f6d2a1b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368728903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.i2c_intr_test.3368728903
Directory /workspace/36.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.i2c_intr_test.1284251308
Short name T1561
Test name
Test status
Simulation time 88430240 ps
CPU time 0.67 seconds
Started Jul 03 05:38:32 PM PDT 24
Finished Jul 03 05:38:33 PM PDT 24
Peak memory 204368 kb
Host smart-97fa3ac9-9d1b-467d-9969-9b683cedbb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284251308 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.i2c_intr_test.1284251308
Directory /workspace/37.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.i2c_intr_test.2739721055
Short name T1586
Test name
Test status
Simulation time 16582118 ps
CPU time 0.67 seconds
Started Jul 03 05:38:32 PM PDT 24
Finished Jul 03 05:38:33 PM PDT 24
Peak memory 204364 kb
Host smart-306353de-c4aa-467c-86e6-b7f5e7ee1e08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739721055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.i2c_intr_test.2739721055
Directory /workspace/38.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.i2c_intr_test.1179556571
Short name T1625
Test name
Test status
Simulation time 14560593 ps
CPU time 0.67 seconds
Started Jul 03 05:38:33 PM PDT 24
Finished Jul 03 05:38:34 PM PDT 24
Peak memory 204364 kb
Host smart-17a4a5a3-c58a-43bc-9447-53c49b13b4c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179556571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.i2c_intr_test.1179556571
Directory /workspace/39.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_aliasing.2143669417
Short name T211
Test name
Test status
Simulation time 143416399 ps
CPU time 1.79 seconds
Started Jul 03 05:38:06 PM PDT 24
Finished Jul 03 05:38:08 PM PDT 24
Peak memory 204484 kb
Host smart-c16d5511-f616-4820-a2a7-117400293f91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143669417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_aliasing.2143669417
Directory /workspace/4.i2c_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_bit_bash.2294611471
Short name T221
Test name
Test status
Simulation time 1194990697 ps
CPU time 2.96 seconds
Started Jul 03 05:38:06 PM PDT 24
Finished Jul 03 05:38:09 PM PDT 24
Peak memory 204572 kb
Host smart-bc0c0fb9-cdfa-41ba-9937-888122aa9175
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294611471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_bit_bash.2294611471
Directory /workspace/4.i2c_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_hw_reset.290869714
Short name T1644
Test name
Test status
Simulation time 32656325 ps
CPU time 0.68 seconds
Started Jul 03 05:38:05 PM PDT 24
Finished Jul 03 05:38:06 PM PDT 24
Peak memory 204400 kb
Host smart-5cf497f7-11d5-4ac8-bfa0-d8ac3a3304fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290869714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_hw_reset.290869714
Directory /workspace/4.i2c_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3807836128
Short name T1574
Test name
Test status
Simulation time 116797525 ps
CPU time 0.97 seconds
Started Jul 03 05:38:09 PM PDT 24
Finished Jul 03 05:38:11 PM PDT 24
Peak memory 204476 kb
Host smart-55687fa5-8caf-4231-b34a-91db486e0850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807836128 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.i2c_csr_mem_rw_with_rand_reset.3807836128
Directory /workspace/4.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_csr_rw.2195260027
Short name T104
Test name
Test status
Simulation time 45331809 ps
CPU time 0.78 seconds
Started Jul 03 05:38:04 PM PDT 24
Finished Jul 03 05:38:06 PM PDT 24
Peak memory 204416 kb
Host smart-ec3ded6b-5e57-4e49-b4f7-7cd1d3a33df0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195260027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_csr_rw.2195260027
Directory /workspace/4.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_intr_test.2502084413
Short name T1565
Test name
Test status
Simulation time 43406882 ps
CPU time 0.69 seconds
Started Jul 03 05:38:06 PM PDT 24
Finished Jul 03 05:38:07 PM PDT 24
Peak memory 204328 kb
Host smart-6dc983fe-be18-4fa4-bfe6-d8ef347ce789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502084413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_intr_test.2502084413
Directory /workspace/4.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_same_csr_outstanding.2095790073
Short name T1547
Test name
Test status
Simulation time 23558012 ps
CPU time 0.85 seconds
Started Jul 03 05:38:06 PM PDT 24
Finished Jul 03 05:38:07 PM PDT 24
Peak memory 204464 kb
Host smart-bcd0a9b0-d8e9-44c6-b6aa-fc1eb96a9f66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095790073 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_same_csr_ou
tstanding.2095790073
Directory /workspace/4.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_errors.2226562510
Short name T1623
Test name
Test status
Simulation time 130075889 ps
CPU time 2.2 seconds
Started Jul 03 05:38:05 PM PDT 24
Finished Jul 03 05:38:07 PM PDT 24
Peak memory 204656 kb
Host smart-ea502da5-8b70-4734-b67b-c40c4bd96484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226562510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_errors.2226562510
Directory /workspace/4.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.i2c_tl_intg_err.3520600341
Short name T204
Test name
Test status
Simulation time 138853974 ps
CPU time 1.39 seconds
Started Jul 03 05:38:05 PM PDT 24
Finished Jul 03 05:38:06 PM PDT 24
Peak memory 204592 kb
Host smart-c1190f34-48b3-4009-875d-957436774a43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520600341 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.i2c_tl_intg_err.3520600341
Directory /workspace/4.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.i2c_intr_test.2730022910
Short name T1559
Test name
Test status
Simulation time 15899785 ps
CPU time 0.67 seconds
Started Jul 03 05:38:30 PM PDT 24
Finished Jul 03 05:38:32 PM PDT 24
Peak memory 204372 kb
Host smart-1eb9c5cd-5736-4cfd-ae28-3c11e9de2dcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730022910 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.i2c_intr_test.2730022910
Directory /workspace/40.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.i2c_intr_test.2669147764
Short name T1610
Test name
Test status
Simulation time 18357037 ps
CPU time 0.65 seconds
Started Jul 03 05:38:29 PM PDT 24
Finished Jul 03 05:38:30 PM PDT 24
Peak memory 204312 kb
Host smart-99f8bb69-507a-4529-9a1e-f09f138a071a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669147764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.i2c_intr_test.2669147764
Directory /workspace/41.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.i2c_intr_test.2079341691
Short name T1569
Test name
Test status
Simulation time 26801704 ps
CPU time 0.67 seconds
Started Jul 03 05:38:31 PM PDT 24
Finished Jul 03 05:38:32 PM PDT 24
Peak memory 204344 kb
Host smart-fd7a552f-ebab-4b1d-81a0-a68ef2085ee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079341691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.i2c_intr_test.2079341691
Directory /workspace/42.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.i2c_intr_test.3304288392
Short name T1630
Test name
Test status
Simulation time 27043840 ps
CPU time 0.67 seconds
Started Jul 03 05:38:35 PM PDT 24
Finished Jul 03 05:38:36 PM PDT 24
Peak memory 204376 kb
Host smart-0951ad63-55ce-4b01-b473-69ea013fcb90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304288392 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.i2c_intr_test.3304288392
Directory /workspace/43.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.i2c_intr_test.3040257319
Short name T1580
Test name
Test status
Simulation time 42699457 ps
CPU time 0.68 seconds
Started Jul 03 05:38:36 PM PDT 24
Finished Jul 03 05:38:37 PM PDT 24
Peak memory 204376 kb
Host smart-4f7e5cf5-f4a3-4940-b438-ffc228908cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040257319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.i2c_intr_test.3040257319
Directory /workspace/44.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.i2c_intr_test.3132472721
Short name T1537
Test name
Test status
Simulation time 25257985 ps
CPU time 0.68 seconds
Started Jul 03 05:38:34 PM PDT 24
Finished Jul 03 05:38:35 PM PDT 24
Peak memory 204332 kb
Host smart-0963895b-0420-4cd2-9d50-b4295052d946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132472721 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.i2c_intr_test.3132472721
Directory /workspace/45.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.i2c_intr_test.1844627297
Short name T1562
Test name
Test status
Simulation time 14519331 ps
CPU time 0.68 seconds
Started Jul 03 05:38:33 PM PDT 24
Finished Jul 03 05:38:34 PM PDT 24
Peak memory 204368 kb
Host smart-7ab0e0d1-d30c-4835-8638-4c2b08411b2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844627297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.i2c_intr_test.1844627297
Directory /workspace/46.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.i2c_intr_test.2853952426
Short name T1577
Test name
Test status
Simulation time 32758513 ps
CPU time 0.69 seconds
Started Jul 03 05:38:36 PM PDT 24
Finished Jul 03 05:38:36 PM PDT 24
Peak memory 204348 kb
Host smart-653e771d-da3a-4d5a-8ede-12660189fe26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853952426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.i2c_intr_test.2853952426
Directory /workspace/47.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.i2c_intr_test.2087838880
Short name T1620
Test name
Test status
Simulation time 19065430 ps
CPU time 0.68 seconds
Started Jul 03 05:38:37 PM PDT 24
Finished Jul 03 05:38:38 PM PDT 24
Peak memory 204336 kb
Host smart-5b6aa5eb-2b8d-48a4-923e-cfa9b1100b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087838880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.i2c_intr_test.2087838880
Directory /workspace/48.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.i2c_intr_test.371025723
Short name T1550
Test name
Test status
Simulation time 51027824 ps
CPU time 0.71 seconds
Started Jul 03 05:38:35 PM PDT 24
Finished Jul 03 05:38:36 PM PDT 24
Peak memory 204364 kb
Host smart-5e96ba21-b9c4-4eea-bd05-708eca3aa549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371025723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.i2c_intr_test.371025723
Directory /workspace/49.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.3346183773
Short name T1563
Test name
Test status
Simulation time 320724903 ps
CPU time 1.05 seconds
Started Jul 03 05:38:08 PM PDT 24
Finished Jul 03 05:38:09 PM PDT 24
Peak memory 204424 kb
Host smart-53591d7f-8357-44be-afaf-7a2ef5e9bc1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346183773 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.i2c_csr_mem_rw_with_rand_reset.3346183773
Directory /workspace/5.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_csr_rw.3786784918
Short name T1546
Test name
Test status
Simulation time 19815177 ps
CPU time 0.72 seconds
Started Jul 03 05:38:08 PM PDT 24
Finished Jul 03 05:38:09 PM PDT 24
Peak memory 204408 kb
Host smart-d3d934f0-e6e4-4a26-887f-2819de7f47fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786784918 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_csr_rw.3786784918
Directory /workspace/5.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_intr_test.3844751765
Short name T1534
Test name
Test status
Simulation time 17196353 ps
CPU time 0.67 seconds
Started Jul 03 05:38:08 PM PDT 24
Finished Jul 03 05:38:09 PM PDT 24
Peak memory 204352 kb
Host smart-f63de2b7-4d4e-4ca7-b572-4c9f12c27aed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844751765 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_intr_test.3844751765
Directory /workspace/5.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_same_csr_outstanding.2514666469
Short name T105
Test name
Test status
Simulation time 220065978 ps
CPU time 1.18 seconds
Started Jul 03 05:38:09 PM PDT 24
Finished Jul 03 05:38:11 PM PDT 24
Peak memory 204524 kb
Host smart-d78069e2-ddb9-46e1-a124-08b8d9a90386
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514666469 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_same_csr_ou
tstanding.2514666469
Directory /workspace/5.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.i2c_tl_errors.16751560
Short name T1638
Test name
Test status
Simulation time 413609453 ps
CPU time 2.09 seconds
Started Jul 03 05:38:05 PM PDT 24
Finished Jul 03 05:38:07 PM PDT 24
Peak memory 204652 kb
Host smart-40d14d95-8416-4dd9-bd29-c77d72426f79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16751560 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.i2c_tl_errors.16751560
Directory /workspace/5.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.670908632
Short name T1558
Test name
Test status
Simulation time 57961145 ps
CPU time 0.9 seconds
Started Jul 03 05:38:09 PM PDT 24
Finished Jul 03 05:38:10 PM PDT 24
Peak memory 204492 kb
Host smart-2dec6a46-02af-4d7f-913e-4b5fedf7bafb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670908632 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.i2c_csr_mem_rw_with_rand_reset.670908632
Directory /workspace/6.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_csr_rw.919824790
Short name T1552
Test name
Test status
Simulation time 20748613 ps
CPU time 0.73 seconds
Started Jul 03 05:38:07 PM PDT 24
Finished Jul 03 05:38:08 PM PDT 24
Peak memory 204384 kb
Host smart-5492af3c-3f2d-42d0-bf27-394ba27a6b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919824790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_csr_rw.919824790
Directory /workspace/6.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_intr_test.1078948543
Short name T1631
Test name
Test status
Simulation time 33665863 ps
CPU time 0.79 seconds
Started Jul 03 05:38:09 PM PDT 24
Finished Jul 03 05:38:10 PM PDT 24
Peak memory 204356 kb
Host smart-2affbbb9-8292-4102-be0a-c6631b50ed08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078948543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_intr_test.1078948543
Directory /workspace/6.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_errors.2979028302
Short name T1629
Test name
Test status
Simulation time 499387738 ps
CPU time 2.32 seconds
Started Jul 03 05:38:08 PM PDT 24
Finished Jul 03 05:38:11 PM PDT 24
Peak memory 212844 kb
Host smart-18eccffe-7361-4cf1-8141-4ce2c5f52570
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979028302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_errors.2979028302
Directory /workspace/6.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.i2c_tl_intg_err.2453003630
Short name T198
Test name
Test status
Simulation time 262019310 ps
CPU time 1.5 seconds
Started Jul 03 05:38:09 PM PDT 24
Finished Jul 03 05:38:11 PM PDT 24
Peak memory 204468 kb
Host smart-4275131b-9ccb-44be-9f52-3782a56e58a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453003630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.i2c_tl_intg_err.2453003630
Directory /workspace/6.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.3655965105
Short name T1602
Test name
Test status
Simulation time 53936830 ps
CPU time 0.93 seconds
Started Jul 03 05:38:09 PM PDT 24
Finished Jul 03 05:38:10 PM PDT 24
Peak memory 204500 kb
Host smart-4cc4e8a6-3a7e-4306-8b61-553fda5c3ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655965105 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.i2c_csr_mem_rw_with_rand_reset.3655965105
Directory /workspace/7.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_csr_rw.399727265
Short name T218
Test name
Test status
Simulation time 47511712 ps
CPU time 0.76 seconds
Started Jul 03 05:38:08 PM PDT 24
Finished Jul 03 05:38:09 PM PDT 24
Peak memory 204456 kb
Host smart-5262fef4-4335-4fc0-b4dc-c23833419064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399727265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_csr_rw.399727265
Directory /workspace/7.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_intr_test.4276125962
Short name T1539
Test name
Test status
Simulation time 43415084 ps
CPU time 0.66 seconds
Started Jul 03 05:38:13 PM PDT 24
Finished Jul 03 05:38:15 PM PDT 24
Peak memory 204368 kb
Host smart-fb923a89-3f32-4c86-901a-01565a340257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276125962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_intr_test.4276125962
Directory /workspace/7.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_same_csr_outstanding.3426127015
Short name T100
Test name
Test status
Simulation time 58512722 ps
CPU time 0.88 seconds
Started Jul 03 05:38:10 PM PDT 24
Finished Jul 03 05:38:11 PM PDT 24
Peak memory 204400 kb
Host smart-d0079b92-47b2-4dd5-854b-b9b9bf96f2be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426127015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_same_csr_ou
tstanding.3426127015
Directory /workspace/7.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.i2c_tl_errors.3260646380
Short name T197
Test name
Test status
Simulation time 78543837 ps
CPU time 1.56 seconds
Started Jul 03 05:38:13 PM PDT 24
Finished Jul 03 05:38:15 PM PDT 24
Peak memory 204624 kb
Host smart-0dad082a-a591-4c59-b15d-4ec6246329c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260646380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.i2c_tl_errors.3260646380
Directory /workspace/7.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_mem_rw_with_rand_reset.3589791392
Short name T1604
Test name
Test status
Simulation time 58218017 ps
CPU time 1.01 seconds
Started Jul 03 05:38:12 PM PDT 24
Finished Jul 03 05:38:13 PM PDT 24
Peak memory 204680 kb
Host smart-f84f88ee-44b1-4fe1-95a4-0ee51dcbdcb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589791392 -assert nopostproc +UVM_TESTNAME
=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.i2c_csr_mem_rw_with_rand_reset.3589791392
Directory /workspace/8.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_csr_rw.1331352483
Short name T1584
Test name
Test status
Simulation time 131867979 ps
CPU time 0.72 seconds
Started Jul 03 05:38:12 PM PDT 24
Finished Jul 03 05:38:13 PM PDT 24
Peak memory 204332 kb
Host smart-86873a67-2c28-405c-b586-6715538d94c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331352483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_csr_rw.1331352483
Directory /workspace/8.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_intr_test.4038195535
Short name T1608
Test name
Test status
Simulation time 19272767 ps
CPU time 0.71 seconds
Started Jul 03 05:38:09 PM PDT 24
Finished Jul 03 05:38:10 PM PDT 24
Peak memory 204388 kb
Host smart-e0ba0505-bfed-4d92-ab82-fe758c9d5132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038195535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_intr_test.4038195535
Directory /workspace/8.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_same_csr_outstanding.2375480270
Short name T1624
Test name
Test status
Simulation time 58722765 ps
CPU time 1.18 seconds
Started Jul 03 05:38:13 PM PDT 24
Finished Jul 03 05:38:14 PM PDT 24
Peak memory 204624 kb
Host smart-cda1a1cd-e250-4d0a-944a-698a0bba1c9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375480270 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_same_csr_ou
tstanding.2375480270
Directory /workspace/8.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_errors.1117655198
Short name T1598
Test name
Test status
Simulation time 674247463 ps
CPU time 1.55 seconds
Started Jul 03 05:38:11 PM PDT 24
Finished Jul 03 05:38:13 PM PDT 24
Peak memory 204572 kb
Host smart-02385e28-1080-4d87-a9a7-e7d28dba68be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117655198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_errors.1117655198
Directory /workspace/8.i2c_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.i2c_tl_intg_err.4250965991
Short name T192
Test name
Test status
Simulation time 73701325 ps
CPU time 1.42 seconds
Started Jul 03 05:38:12 PM PDT 24
Finished Jul 03 05:38:13 PM PDT 24
Peak memory 204556 kb
Host smart-d440a008-1b89-4131-b4ed-00a9a42c0883
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250965991 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.i2c_tl_intg_err.4250965991
Directory /workspace/8.i2c_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_mem_rw_with_rand_reset.631986039
Short name T1582
Test name
Test status
Simulation time 25088664 ps
CPU time 0.84 seconds
Started Jul 03 05:38:11 PM PDT 24
Finished Jul 03 05:38:12 PM PDT 24
Peak memory 204520 kb
Host smart-9ecc3611-f460-4126-9a09-23631f14c986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631986039 -assert nopostproc +UVM_TESTNAME=
i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.i2c_csr_mem_rw_with_rand_reset.631986039
Directory /workspace/9.i2c_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_csr_rw.862425296
Short name T1585
Test name
Test status
Simulation time 25967161 ps
CPU time 0.7 seconds
Started Jul 03 05:38:13 PM PDT 24
Finished Jul 03 05:38:14 PM PDT 24
Peak memory 204444 kb
Host smart-ba9b52d5-eaaf-451b-b6ac-e8f6c956b092
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862425296 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_csr_rw.862425296
Directory /workspace/9.i2c_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_intr_test.3694788805
Short name T1535
Test name
Test status
Simulation time 18942595 ps
CPU time 0.71 seconds
Started Jul 03 05:38:12 PM PDT 24
Finished Jul 03 05:38:13 PM PDT 24
Peak memory 204332 kb
Host smart-d6607eca-fe3a-4622-b165-9555c1f89ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694788805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_intr_test.3694788805
Directory /workspace/9.i2c_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_same_csr_outstanding.1027234674
Short name T224
Test name
Test status
Simulation time 31246944 ps
CPU time 0.86 seconds
Started Jul 03 05:38:13 PM PDT 24
Finished Jul 03 05:38:15 PM PDT 24
Peak memory 204400 kb
Host smart-83fdaf82-b433-49be-828d-2d25c947f4b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027234674 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_same_csr_ou
tstanding.1027234674
Directory /workspace/9.i2c_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.i2c_tl_intg_err.3729884054
Short name T194
Test name
Test status
Simulation time 150888257 ps
CPU time 2.13 seconds
Started Jul 03 05:38:13 PM PDT 24
Finished Jul 03 05:38:16 PM PDT 24
Peak memory 204504 kb
Host smart-06bcaf4a-0291-41c5-ab23-3ce88f0bad9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729884054 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.i2c_tl_intg_err.3729884054
Directory /workspace/9.i2c_tl_intg_err/latest

Test location /workspace/coverage/default/0.i2c_alert_test.1054089066
Short name T1369
Test name
Test status
Simulation time 18450734 ps
CPU time 0.66 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:04 PM PDT 24
Peak memory 204512 kb
Host smart-2a9b1159-241e-4971-832f-01427a2706b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054089066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_alert_test.1054089066
Directory /workspace/0.i2c_alert_test/latest

Test location /workspace/coverage/default/0.i2c_host_error_intr.1463256494
Short name T49
Test name
Test status
Simulation time 984292242 ps
CPU time 9.18 seconds
Started Jul 03 05:24:55 PM PDT 24
Finished Jul 03 05:25:04 PM PDT 24
Peak memory 230384 kb
Host smart-3143f6f4-5643-44cf-9c76-8639d4d655e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463256494 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_error_intr.1463256494
Directory /workspace/0.i2c_host_error_intr/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_fmt_empty.828662891
Short name T1493
Test name
Test status
Simulation time 222928872 ps
CPU time 11.4 seconds
Started Jul 03 05:24:49 PM PDT 24
Finished Jul 03 05:25:02 PM PDT 24
Peak memory 247004 kb
Host smart-798b25b2-3050-4cff-8542-05943646ec51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828662891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_fmt_empty
.828662891
Directory /workspace/0.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_overflow.382556023
Short name T1298
Test name
Test status
Simulation time 4304665027 ps
CPU time 111.89 seconds
Started Jul 03 05:25:01 PM PDT 24
Finished Jul 03 05:26:54 PM PDT 24
Peak memory 621176 kb
Host smart-3928a1a3-48c9-47ac-9aa0-75c85682116b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382556023 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_overflow.382556023
Directory /workspace/0.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_fmt.989198982
Short name T236
Test name
Test status
Simulation time 676175122 ps
CPU time 1.04 seconds
Started Jul 03 05:24:53 PM PDT 24
Finished Jul 03 05:24:55 PM PDT 24
Peak memory 204424 kb
Host smart-ca606e16-1a36-4437-9b73-91d3ca53d849
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989198982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_fmt
.989198982
Directory /workspace/0.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/0.i2c_host_fifo_reset_rx.1902434333
Short name T1310
Test name
Test status
Simulation time 668119969 ps
CPU time 4.74 seconds
Started Jul 03 05:24:53 PM PDT 24
Finished Jul 03 05:24:58 PM PDT 24
Peak memory 233212 kb
Host smart-cc51c4a3-903a-4960-ba47-1c3b182dbeb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902434333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_fifo_reset_rx.
1902434333
Directory /workspace/0.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/0.i2c_host_mode_toggle.3600375372
Short name T1113
Test name
Test status
Simulation time 7160121091 ps
CPU time 63.74 seconds
Started Jul 03 05:24:58 PM PDT 24
Finished Jul 03 05:26:02 PM PDT 24
Peak memory 285796 kb
Host smart-e42817f2-18e5-4989-a359-1e78b79d1f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600375372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_mode_toggle.3600375372
Directory /workspace/0.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/0.i2c_host_override.1897119150
Short name T1128
Test name
Test status
Simulation time 28740169 ps
CPU time 0.7 seconds
Started Jul 03 05:24:53 PM PDT 24
Finished Jul 03 05:24:55 PM PDT 24
Peak memory 204552 kb
Host smart-b260f69f-ddb3-47bd-a830-541398f1ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897119150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_override.1897119150
Directory /workspace/0.i2c_host_override/latest

Test location /workspace/coverage/default/0.i2c_host_perf.4013685866
Short name T31
Test name
Test status
Simulation time 48399467183 ps
CPU time 335.93 seconds
Started Jul 03 05:24:57 PM PDT 24
Finished Jul 03 05:30:34 PM PDT 24
Peak memory 204912 kb
Host smart-4efc97cb-c5b2-4e1a-89cf-d71870c52746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013685866 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf.4013685866
Directory /workspace/0.i2c_host_perf/latest

Test location /workspace/coverage/default/0.i2c_host_perf_precise.48681042
Short name T554
Test name
Test status
Simulation time 322733762 ps
CPU time 1.83 seconds
Started Jul 03 05:24:58 PM PDT 24
Finished Jul 03 05:25:00 PM PDT 24
Peak memory 220656 kb
Host smart-87588532-f167-4e4f-abc0-cf1d35bc8ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48681042 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_perf_precise.48681042
Directory /workspace/0.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/0.i2c_host_smoke.1406293517
Short name T1455
Test name
Test status
Simulation time 3372104658 ps
CPU time 28.13 seconds
Started Jul 03 05:24:52 PM PDT 24
Finished Jul 03 05:25:21 PM PDT 24
Peak memory 354688 kb
Host smart-1ad81ec7-3ca5-47c5-960a-b28645c63cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406293517 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_smoke.1406293517
Directory /workspace/0.i2c_host_smoke/latest

Test location /workspace/coverage/default/0.i2c_host_stretch_timeout.152129258
Short name T92
Test name
Test status
Simulation time 568249648 ps
CPU time 9.95 seconds
Started Jul 03 05:24:55 PM PDT 24
Finished Jul 03 05:25:05 PM PDT 24
Peak memory 221236 kb
Host smart-57389d72-5ab9-4ad4-aba1-ab1848403570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152129258 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_host_stretch_timeout.152129258
Directory /workspace/0.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/0.i2c_sec_cm.3614674386
Short name T184
Test name
Test status
Simulation time 126068804 ps
CPU time 0.96 seconds
Started Jul 03 05:24:59 PM PDT 24
Finished Jul 03 05:25:00 PM PDT 24
Peak memory 223352 kb
Host smart-ad16c8fa-d123-49e9-819e-21f67fb9c884
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614674386 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_sec_cm.3614674386
Directory /workspace/0.i2c_sec_cm/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_acq.2685572641
Short name T1386
Test name
Test status
Simulation time 323185534 ps
CPU time 1.47 seconds
Started Jul 03 05:24:58 PM PDT 24
Finished Jul 03 05:25:00 PM PDT 24
Peak memory 204872 kb
Host smart-46ef2272-9d5e-4354-b0f9-c99acb0d4430
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685572641 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_fifo_reset_acq.2685572641
Directory /workspace/0.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_reset_tx.861745902
Short name T403
Test name
Test status
Simulation time 189597944 ps
CPU time 1.15 seconds
Started Jul 03 05:25:02 PM PDT 24
Finished Jul 03 05:25:04 PM PDT 24
Peak memory 204636 kb
Host smart-129c703f-3c0b-4e3d-894b-6c7ac9b51eea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861745902 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.i2c_target_fifo_reset_tx.861745902
Directory /workspace/0.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_acq.2347250839
Short name T936
Test name
Test status
Simulation time 5177193552 ps
CPU time 2.45 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:06 PM PDT 24
Peak memory 204948 kb
Host smart-7368a639-32d9-4c8a-8218-6cd51f7d79f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347250839 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.i2c_target_fifo_watermarks_acq.2347250839
Directory /workspace/0.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/0.i2c_target_fifo_watermarks_tx.1579139005
Short name T1022
Test name
Test status
Simulation time 104607821 ps
CPU time 1.08 seconds
Started Jul 03 05:25:01 PM PDT 24
Finished Jul 03 05:25:03 PM PDT 24
Peak memory 204652 kb
Host smart-93df6c92-4e7f-45da-87d9-a6164ab64661
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579139005 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.i2c_target_fifo_watermarks_tx.1579139005
Directory /workspace/0.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/0.i2c_target_glitch.3013880064
Short name T15
Test name
Test status
Simulation time 32896738016 ps
CPU time 10.06 seconds
Started Jul 03 05:24:52 PM PDT 24
Finished Jul 03 05:25:03 PM PDT 24
Peak memory 213672 kb
Host smart-83bf8daf-fbdb-404e-8d2f-b03dd4618487
User root
Command /workspace/default/simv +i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013880064 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_target_glitch.3013880064
Directory /workspace/0.i2c_target_glitch/latest

Test location /workspace/coverage/default/0.i2c_target_hrst.1486620009
Short name T249
Test name
Test status
Simulation time 310190256 ps
CPU time 4.07 seconds
Started Jul 03 05:24:59 PM PDT 24
Finished Jul 03 05:25:04 PM PDT 24
Peak memory 204852 kb
Host smart-6d5fd38e-6bed-4f0b-98e8-558671540688
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486620009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 0.i2c_target_hrst.1486620009
Directory /workspace/0.i2c_target_hrst/latest

Test location /workspace/coverage/default/0.i2c_target_intr_smoke.4021185349
Short name T348
Test name
Test status
Simulation time 6661979200 ps
CPU time 6.63 seconds
Started Jul 03 05:25:08 PM PDT 24
Finished Jul 03 05:25:15 PM PDT 24
Peak memory 220976 kb
Host smart-016835b5-3487-4e78-9f04-7290a6eb6aeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021185349 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 0.i2c_target_intr_smoke.4021185349
Directory /workspace/0.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_intr_stress_wr.3713221579
Short name T754
Test name
Test status
Simulation time 22842129946 ps
CPU time 57.69 seconds
Started Jul 03 05:24:59 PM PDT 24
Finished Jul 03 05:25:57 PM PDT 24
Peak memory 1239056 kb
Host smart-23df2c3e-cd6d-4ac7-86ec-141f6ce0349b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713221579 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.i2c_target_intr_stress_wr.3713221579
Directory /workspace/0.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_smoke.1996653125
Short name T146
Test name
Test status
Simulation time 4165598149 ps
CPU time 15.09 seconds
Started Jul 03 05:25:04 PM PDT 24
Finished Jul 03 05:25:20 PM PDT 24
Peak memory 204724 kb
Host smart-7ecd2853-3bd6-47c6-a3f7-4a469d40d215
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996653125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_tar
get_smoke.1996653125
Directory /workspace/0.i2c_target_smoke/latest

Test location /workspace/coverage/default/0.i2c_target_stress_rd.215128615
Short name T568
Test name
Test status
Simulation time 1535592110 ps
CPU time 26.54 seconds
Started Jul 03 05:25:02 PM PDT 24
Finished Jul 03 05:25:29 PM PDT 24
Peak memory 227748 kb
Host smart-4c8faef9-baff-439e-8bb4-b0934938f303
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215128615 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_
target_stress_rd.215128615
Directory /workspace/0.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/0.i2c_target_stress_wr.3802490363
Short name T1436
Test name
Test status
Simulation time 25157410778 ps
CPU time 89.81 seconds
Started Jul 03 05:24:59 PM PDT 24
Finished Jul 03 05:26:30 PM PDT 24
Peak memory 1290152 kb
Host smart-a5972d14-5ff7-425b-a488-a8393654cac3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802490363 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c
_target_stress_wr.3802490363
Directory /workspace/0.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/0.i2c_target_stretch.464538792
Short name T1409
Test name
Test status
Simulation time 39058795716 ps
CPU time 224.13 seconds
Started Jul 03 05:25:07 PM PDT 24
Finished Jul 03 05:28:51 PM PDT 24
Peak memory 871392 kb
Host smart-e0df4235-8f63-4dcd-a205-bcfa4fdf143f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464538792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.i2c_ta
rget_stretch.464538792
Directory /workspace/0.i2c_target_stretch/latest

Test location /workspace/coverage/default/0.i2c_target_timeout.1007663127
Short name T411
Test name
Test status
Simulation time 5094060397 ps
CPU time 7.24 seconds
Started Jul 03 05:25:02 PM PDT 24
Finished Jul 03 05:25:10 PM PDT 24
Peak memory 217264 kb
Host smart-7d0c15f6-61b0-4225-82e0-f521026e276f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007663127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.i2c_target_timeout.1007663127
Directory /workspace/0.i2c_target_timeout/latest

Test location /workspace/coverage/default/0.i2c_target_tx_stretch_ctrl.3008777048
Short name T1271
Test name
Test status
Simulation time 130518163 ps
CPU time 2.79 seconds
Started Jul 03 05:24:52 PM PDT 24
Finished Jul 03 05:24:55 PM PDT 24
Peak memory 204880 kb
Host smart-857a6d8c-a36c-4efd-8d2d-9b5f304ad8ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008777048 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.i2c_target_tx_stretch_ctrl.3008777048
Directory /workspace/0.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/1.i2c_alert_test.2692579020
Short name T165
Test name
Test status
Simulation time 47841360 ps
CPU time 0.62 seconds
Started Jul 03 05:25:07 PM PDT 24
Finished Jul 03 05:25:08 PM PDT 24
Peak memory 204432 kb
Host smart-23fa6070-de51-47f7-ba39-2da06b3dd035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692579020 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_alert_test.2692579020
Directory /workspace/1.i2c_alert_test/latest

Test location /workspace/coverage/default/1.i2c_host_error_intr.2074827531
Short name T809
Test name
Test status
Simulation time 106937493 ps
CPU time 1.82 seconds
Started Jul 03 05:25:02 PM PDT 24
Finished Jul 03 05:25:05 PM PDT 24
Peak memory 213040 kb
Host smart-8342de5b-667f-40b4-b898-abef680f8ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074827531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_error_intr.2074827531
Directory /workspace/1.i2c_host_error_intr/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_fmt_empty.474974891
Short name T392
Test name
Test status
Simulation time 1220077129 ps
CPU time 14.5 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:18 PM PDT 24
Peak memory 258976 kb
Host smart-7a17aa74-3b2c-43da-80c5-c11552edce34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474974891 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_fmt_empty
.474974891
Directory /workspace/1.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_full.1379583497
Short name T260
Test name
Test status
Simulation time 3046640579 ps
CPU time 82.85 seconds
Started Jul 03 05:24:57 PM PDT 24
Finished Jul 03 05:26:21 PM PDT 24
Peak memory 728300 kb
Host smart-c17acbbf-0e3d-47c5-b7d4-33b18a1c0c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379583497 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_full.1379583497
Directory /workspace/1.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_overflow.1356427226
Short name T1043
Test name
Test status
Simulation time 6709857465 ps
CPU time 108.51 seconds
Started Jul 03 05:24:56 PM PDT 24
Finished Jul 03 05:26:45 PM PDT 24
Peak memory 578404 kb
Host smart-d8008faf-b048-4931-a1d2-7fbd1b34005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356427226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_overflow.1356427226
Directory /workspace/1.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_fmt.2313515801
Short name T1513
Test name
Test status
Simulation time 460826430 ps
CPU time 1.01 seconds
Started Jul 03 05:24:56 PM PDT 24
Finished Jul 03 05:24:57 PM PDT 24
Peak memory 204472 kb
Host smart-059c3d3f-30c7-4833-91d7-09c7015d9b02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313515801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_fm
t.2313515801
Directory /workspace/1.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_reset_rx.484684856
Short name T1250
Test name
Test status
Simulation time 574313343 ps
CPU time 7.3 seconds
Started Jul 03 05:25:00 PM PDT 24
Finished Jul 03 05:25:07 PM PDT 24
Peak memory 204820 kb
Host smart-97947ec0-3542-4080-a3d7-0e8b7fc4e86b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484684856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_reset_rx.484684856
Directory /workspace/1.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/1.i2c_host_fifo_watermark.2734278198
Short name T262
Test name
Test status
Simulation time 3845732991 ps
CPU time 104.96 seconds
Started Jul 03 05:24:59 PM PDT 24
Finished Jul 03 05:26:44 PM PDT 24
Peak memory 1112844 kb
Host smart-c6b7fcdb-833a-46d2-a756-9cb744abe3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734278198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_fifo_watermark.2734278198
Directory /workspace/1.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/1.i2c_host_may_nack.1094168907
Short name T91
Test name
Test status
Simulation time 1735403184 ps
CPU time 17.76 seconds
Started Jul 03 05:25:01 PM PDT 24
Finished Jul 03 05:25:19 PM PDT 24
Peak memory 204824 kb
Host smart-80a67ca4-ed5c-40ba-970f-90ab63d2157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094168907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_may_nack.1094168907
Directory /workspace/1.i2c_host_may_nack/latest

Test location /workspace/coverage/default/1.i2c_host_override.1368985813
Short name T362
Test name
Test status
Simulation time 63935578 ps
CPU time 0.66 seconds
Started Jul 03 05:24:58 PM PDT 24
Finished Jul 03 05:24:59 PM PDT 24
Peak memory 204300 kb
Host smart-f8831c19-2a19-486f-8a3c-c0770c3117f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368985813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_override.1368985813
Directory /workspace/1.i2c_host_override/latest

Test location /workspace/coverage/default/1.i2c_host_perf_precise.2067056302
Short name T960
Test name
Test status
Simulation time 98566238 ps
CPU time 1.43 seconds
Started Jul 03 05:25:06 PM PDT 24
Finished Jul 03 05:25:08 PM PDT 24
Peak memory 222628 kb
Host smart-8ba05c74-9185-4948-a665-843394f1cead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067056302 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_perf_precise.2067056302
Directory /workspace/1.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/1.i2c_host_smoke.2967401242
Short name T455
Test name
Test status
Simulation time 4026732978 ps
CPU time 101.24 seconds
Started Jul 03 05:24:58 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 406284 kb
Host smart-43778af2-d005-48f8-88c4-9eec57e7cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967401242 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_smoke.2967401242
Directory /workspace/1.i2c_host_smoke/latest

Test location /workspace/coverage/default/1.i2c_host_stress_all.3850905789
Short name T1184
Test name
Test status
Simulation time 79332503344 ps
CPU time 1001.8 seconds
Started Jul 03 05:24:58 PM PDT 24
Finished Jul 03 05:41:41 PM PDT 24
Peak memory 3938260 kb
Host smart-b19f59da-924a-425d-a1f5-07e93fc4eda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850905789 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stress_all.3850905789
Directory /workspace/1.i2c_host_stress_all/latest

Test location /workspace/coverage/default/1.i2c_host_stretch_timeout.2136635027
Short name T1251
Test name
Test status
Simulation time 3853662240 ps
CPU time 42.39 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 213124 kb
Host smart-002042a0-1267-443c-99f3-bf7a9ddf2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136635027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_host_stretch_timeout.2136635027
Directory /workspace/1.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/1.i2c_sec_cm.255317912
Short name T181
Test name
Test status
Simulation time 65153423 ps
CPU time 0.95 seconds
Started Jul 03 05:25:06 PM PDT 24
Finished Jul 03 05:25:12 PM PDT 24
Peak memory 223200 kb
Host smart-5871b320-4b11-4b0f-b537-a72b204f70a7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255317912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_sec_cm.255317912
Directory /workspace/1.i2c_sec_cm/latest

Test location /workspace/coverage/default/1.i2c_target_bad_addr.1577748605
Short name T764
Test name
Test status
Simulation time 11448827495 ps
CPU time 4.2 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:08 PM PDT 24
Peak memory 204972 kb
Host smart-101af39e-af95-4655-a9e2-61e815880492
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577748605 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.i2c_target_bad_addr.1577748605
Directory /workspace/1.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_acq.2370936341
Short name T1055
Test name
Test status
Simulation time 399532285 ps
CPU time 1.06 seconds
Started Jul 03 05:25:06 PM PDT 24
Finished Jul 03 05:25:07 PM PDT 24
Peak memory 204800 kb
Host smart-4994891d-8867-4950-a8a1-1ca07cfe627f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370936341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_fifo_reset_acq.2370936341
Directory /workspace/1.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_reset_tx.1316364840
Short name T769
Test name
Test status
Simulation time 147809124 ps
CPU time 0.83 seconds
Started Jul 03 05:25:00 PM PDT 24
Finished Jul 03 05:25:02 PM PDT 24
Peak memory 204584 kb
Host smart-a8f9ec4c-39b1-4b72-9186-06fdd51653e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316364840 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.i2c_target_fifo_reset_tx.1316364840
Directory /workspace/1.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_acq.1702761414
Short name T252
Test name
Test status
Simulation time 1610060750 ps
CPU time 2.13 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:06 PM PDT 24
Peak memory 204792 kb
Host smart-9f751218-0ecf-4235-a2bf-0463d253007f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702761414 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.i2c_target_fifo_watermarks_acq.1702761414
Directory /workspace/1.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/1.i2c_target_fifo_watermarks_tx.1983096427
Short name T284
Test name
Test status
Simulation time 489371179 ps
CPU time 1.05 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:05 PM PDT 24
Peak memory 204632 kb
Host smart-b8644e92-23db-46ee-9c52-dfd4f9644676
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983096427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.i2c_target_fifo_watermarks_tx.1983096427
Directory /workspace/1.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/1.i2c_target_hrst.3837872206
Short name T1470
Test name
Test status
Simulation time 679905930 ps
CPU time 2.85 seconds
Started Jul 03 05:25:04 PM PDT 24
Finished Jul 03 05:25:07 PM PDT 24
Peak memory 204800 kb
Host smart-7f13fc61-eb7c-4df9-b41a-3987a810a4d1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837872206 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 1.i2c_target_hrst.3837872206
Directory /workspace/1.i2c_target_hrst/latest

Test location /workspace/coverage/default/1.i2c_target_intr_smoke.2412497468
Short name T462
Test name
Test status
Simulation time 2792163582 ps
CPU time 5.92 seconds
Started Jul 03 05:24:56 PM PDT 24
Finished Jul 03 05:25:02 PM PDT 24
Peak memory 217744 kb
Host smart-48556f9c-348c-45bd-a52a-5a3cadc6492d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412497468 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 1.i2c_target_intr_smoke.2412497468
Directory /workspace/1.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_intr_stress_wr.2020849642
Short name T501
Test name
Test status
Simulation time 23283680217 ps
CPU time 209.81 seconds
Started Jul 03 05:25:07 PM PDT 24
Finished Jul 03 05:28:37 PM PDT 24
Peak memory 2130308 kb
Host smart-a3f02ac2-0a3a-489e-b1ef-0666d5529486
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020849642 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.i2c_target_intr_stress_wr.2020849642
Directory /workspace/1.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_smoke.726125723
Short name T168
Test name
Test status
Simulation time 1436767964 ps
CPU time 49.14 seconds
Started Jul 03 05:24:58 PM PDT 24
Finished Jul 03 05:25:48 PM PDT 24
Peak memory 204832 kb
Host smart-c0358e4e-02c2-449c-9b5e-fbab9a123f69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726125723 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_targ
et_smoke.726125723
Directory /workspace/1.i2c_target_smoke/latest

Test location /workspace/coverage/default/1.i2c_target_stress_rd.3255174479
Short name T719
Test name
Test status
Simulation time 3562893550 ps
CPU time 28.01 seconds
Started Jul 03 05:25:07 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 226112 kb
Host smart-e11f8e73-9450-42e9-ba03-bc5a31fb5c1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255174479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_rd.3255174479
Directory /workspace/1.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/1.i2c_target_stress_wr.1614043577
Short name T820
Test name
Test status
Simulation time 23832431913 ps
CPU time 5.14 seconds
Started Jul 03 05:25:01 PM PDT 24
Finished Jul 03 05:25:07 PM PDT 24
Peak memory 204904 kb
Host smart-467855b5-34aa-4876-bec7-903cb1b7ac06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614043577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c
_target_stress_wr.1614043577
Directory /workspace/1.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/1.i2c_target_stretch.3988946524
Short name T1507
Test name
Test status
Simulation time 34863392441 ps
CPU time 1341.92 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:47:26 PM PDT 24
Peak memory 3198352 kb
Host smart-221d03e9-dbc4-4edd-a9af-0fd25380980c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988946524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.i2c_t
arget_stretch.3988946524
Directory /workspace/1.i2c_target_stretch/latest

Test location /workspace/coverage/default/1.i2c_target_timeout.2856158596
Short name T1186
Test name
Test status
Simulation time 5717372840 ps
CPU time 7.42 seconds
Started Jul 03 05:25:01 PM PDT 24
Finished Jul 03 05:25:10 PM PDT 24
Peak memory 219492 kb
Host smart-09f5e527-e387-4026-9bc7-466519276e6b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856158596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.i2c_target_timeout.2856158596
Directory /workspace/1.i2c_target_timeout/latest

Test location /workspace/coverage/default/1.i2c_target_tx_stretch_ctrl.1034461830
Short name T1503
Test name
Test status
Simulation time 467010177 ps
CPU time 6.21 seconds
Started Jul 03 05:25:03 PM PDT 24
Finished Jul 03 05:25:10 PM PDT 24
Peak memory 204860 kb
Host smart-886ddd78-d262-440f-92fa-744a91bfab31
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034461830 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.i2c_target_tx_stretch_ctrl.1034461830
Directory /workspace/1.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/10.i2c_alert_test.1470180906
Short name T1484
Test name
Test status
Simulation time 23799845 ps
CPU time 0.62 seconds
Started Jul 03 05:25:48 PM PDT 24
Finished Jul 03 05:25:49 PM PDT 24
Peak memory 204452 kb
Host smart-c832192d-0797-4fc6-8fc6-87a1352b5831
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470180906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_alert_test.1470180906
Directory /workspace/10.i2c_alert_test/latest

Test location /workspace/coverage/default/10.i2c_host_error_intr.1062852250
Short name T1418
Test name
Test status
Simulation time 728366761 ps
CPU time 1.99 seconds
Started Jul 03 05:25:54 PM PDT 24
Finished Jul 03 05:25:56 PM PDT 24
Peak memory 221216 kb
Host smart-cfe84b06-e3be-4f5f-8a4d-d7d0b61ac0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062852250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_error_intr.1062852250
Directory /workspace/10.i2c_host_error_intr/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_fmt_empty.2438105492
Short name T694
Test name
Test status
Simulation time 588236070 ps
CPU time 5.96 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:25:49 PM PDT 24
Peak memory 245996 kb
Host smart-724f0e91-9baa-4aaa-8176-7eea10a501c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438105492 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_fmt_emp
ty.2438105492
Directory /workspace/10.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_full.1345217418
Short name T1531
Test name
Test status
Simulation time 2642270398 ps
CPU time 85.29 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:27:10 PM PDT 24
Peak memory 529112 kb
Host smart-fea7a459-f9a6-42d7-9b22-0ab029a175b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345217418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_full.1345217418
Directory /workspace/10.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_overflow.4255316519
Short name T760
Test name
Test status
Simulation time 2517717032 ps
CPU time 169.81 seconds
Started Jul 03 05:25:48 PM PDT 24
Finished Jul 03 05:28:39 PM PDT 24
Peak memory 761624 kb
Host smart-ceaf6c44-b4f8-4cad-9347-a17b02d94292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255316519 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_overflow.4255316519
Directory /workspace/10.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_fmt.351866851
Short name T1121
Test name
Test status
Simulation time 186477333 ps
CPU time 0.88 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:43 PM PDT 24
Peak memory 204492 kb
Host smart-133f586b-6db7-4b02-95da-5ba6055bcb02
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351866851 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_fm
t.351866851
Directory /workspace/10.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_reset_rx.2047529940
Short name T317
Test name
Test status
Simulation time 164597711 ps
CPU time 4.42 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:25:58 PM PDT 24
Peak memory 233412 kb
Host smart-f3082d72-df83-441c-a5db-7b8062e30a62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047529940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_reset_rx
.2047529940
Directory /workspace/10.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/10.i2c_host_fifo_watermark.2044655237
Short name T1221
Test name
Test status
Simulation time 19737841955 ps
CPU time 130.84 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:27:56 PM PDT 24
Peak memory 1401436 kb
Host smart-41a8b9db-1be6-46a9-aeb0-bfebe0d97ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044655237 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_fifo_watermark.2044655237
Directory /workspace/10.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/10.i2c_host_may_nack.2822904570
Short name T1264
Test name
Test status
Simulation time 632530738 ps
CPU time 4.45 seconds
Started Jul 03 05:25:49 PM PDT 24
Finished Jul 03 05:25:54 PM PDT 24
Peak memory 204868 kb
Host smart-e7054ea5-2ecd-4275-914a-33586cf966c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822904570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_may_nack.2822904570
Directory /workspace/10.i2c_host_may_nack/latest

Test location /workspace/coverage/default/10.i2c_host_mode_toggle.740265232
Short name T33
Test name
Test status
Simulation time 3991585987 ps
CPU time 30.89 seconds
Started Jul 03 05:25:56 PM PDT 24
Finished Jul 03 05:26:28 PM PDT 24
Peak memory 409168 kb
Host smart-5348f41e-9bca-4be4-8cef-10108c3692d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740265232 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_mode_toggle.740265232
Directory /workspace/10.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/10.i2c_host_override.2223288949
Short name T678
Test name
Test status
Simulation time 41543007 ps
CPU time 0.65 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 204484 kb
Host smart-2982f66b-2d4c-46fa-837a-32d79ecf07f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223288949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_override.2223288949
Directory /workspace/10.i2c_host_override/latest

Test location /workspace/coverage/default/10.i2c_host_perf.4043904869
Short name T435
Test name
Test status
Simulation time 7021728430 ps
CPU time 36.15 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:26:30 PM PDT 24
Peak memory 502684 kb
Host smart-1a487a23-dcae-4709-9f54-0f67325330f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043904869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf.4043904869
Directory /workspace/10.i2c_host_perf/latest

Test location /workspace/coverage/default/10.i2c_host_perf_precise.3296902413
Short name T531
Test name
Test status
Simulation time 96771786 ps
CPU time 1.29 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 212900 kb
Host smart-c296746e-0aa0-4106-a720-59733cf31709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296902413 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_perf_precise.3296902413
Directory /workspace/10.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/10.i2c_host_smoke.2682779448
Short name T765
Test name
Test status
Simulation time 1441601980 ps
CPU time 21.51 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:26:05 PM PDT 24
Peak memory 334468 kb
Host smart-b3f1f48a-b2f2-4eb4-86e7-2bbe18266044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682779448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_smoke.2682779448
Directory /workspace/10.i2c_host_smoke/latest

Test location /workspace/coverage/default/10.i2c_host_stretch_timeout.3769773732
Short name T1164
Test name
Test status
Simulation time 851802784 ps
CPU time 13.04 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:25:57 PM PDT 24
Peak memory 221160 kb
Host smart-e9c95935-f3f6-41f2-9bdf-d1fa3afbfea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769773732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_host_stretch_timeout.3769773732
Directory /workspace/10.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_bad_addr.2545388688
Short name T1506
Test name
Test status
Simulation time 687454346 ps
CPU time 3.19 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:26:00 PM PDT 24
Peak memory 213076 kb
Host smart-2fd89f28-752c-4dce-ac4f-a3dad41972e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545388688 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.i2c_target_bad_addr.2545388688
Directory /workspace/10.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_acq.3992079425
Short name T663
Test name
Test status
Simulation time 134440352 ps
CPU time 0.89 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 204628 kb
Host smart-a8aac98b-9f25-4020-89e8-eef4bb92686d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992079425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_fifo_reset_acq.3992079425
Directory /workspace/10.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_reset_tx.2960422341
Short name T869
Test name
Test status
Simulation time 461442892 ps
CPU time 0.94 seconds
Started Jul 03 05:25:56 PM PDT 24
Finished Jul 03 05:25:58 PM PDT 24
Peak memory 204592 kb
Host smart-c4dfcce2-3754-4b7d-8f82-8c36480a02dc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960422341 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.i2c_target_fifo_reset_tx.2960422341
Directory /workspace/10.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_acq.529639279
Short name T324
Test name
Test status
Simulation time 135482366 ps
CPU time 1.11 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:25:57 PM PDT 24
Peak memory 204640 kb
Host smart-3580bdc5-17a3-4f91-b395-da6ec616922e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529639279 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_acq.529639279
Directory /workspace/10.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/10.i2c_target_fifo_watermarks_tx.2146985404
Short name T524
Test name
Test status
Simulation time 360213563 ps
CPU time 1.16 seconds
Started Jul 03 05:25:46 PM PDT 24
Finished Jul 03 05:25:47 PM PDT 24
Peak memory 204544 kb
Host smart-827b0a54-8809-44b0-a859-11850e965915
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146985404 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.i2c_target_fifo_watermarks_tx.2146985404
Directory /workspace/10.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/10.i2c_target_hrst.99073243
Short name T1228
Test name
Test status
Simulation time 376104862 ps
CPU time 2.91 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:26:01 PM PDT 24
Peak memory 204820 kb
Host smart-17af8c97-6a71-4ca8-9d81-8c7f2079dc32
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99073243 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.i2c_target_hrst.99073243
Directory /workspace/10.i2c_target_hrst/latest

Test location /workspace/coverage/default/10.i2c_target_intr_smoke.2931918470
Short name T1494
Test name
Test status
Simulation time 4705225738 ps
CPU time 5.48 seconds
Started Jul 03 05:25:41 PM PDT 24
Finished Jul 03 05:25:47 PM PDT 24
Peak memory 213160 kb
Host smart-92ee152e-2c90-45e2-a559-567c67e4a7c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931918470 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.i2c_target_intr_smoke.2931918470
Directory /workspace/10.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_intr_stress_wr.986437217
Short name T209
Test name
Test status
Simulation time 3923187788 ps
CPU time 3.25 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 204868 kb
Host smart-5d4f5a5c-f5b4-4644-9076-5007e1227681
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986437217 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.i2c_target_intr_stress_wr.986437217
Directory /workspace/10.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_smoke.1330722984
Short name T1509
Test name
Test status
Simulation time 2491481120 ps
CPU time 44.43 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:26:29 PM PDT 24
Peak memory 204856 kb
Host smart-fa76c59b-56d6-483f-88ae-341f228ad94a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330722984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_ta
rget_smoke.1330722984
Directory /workspace/10.i2c_target_smoke/latest

Test location /workspace/coverage/default/10.i2c_target_stress_rd.294370602
Short name T1031
Test name
Test status
Simulation time 1615201276 ps
CPU time 29.78 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:26:14 PM PDT 24
Peak memory 226928 kb
Host smart-208d5e99-26e6-47da-8cca-aa7a03d2ea67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294370602 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c
_target_stress_rd.294370602
Directory /workspace/10.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/10.i2c_target_stress_wr.92031746
Short name T320
Test name
Test status
Simulation time 8404934155 ps
CPU time 14.89 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:25:56 PM PDT 24
Peak memory 204964 kb
Host smart-2435662c-5137-4d20-9620-4057d1d18866
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92031746 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stress_wr.92031746
Directory /workspace/10.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/10.i2c_target_stretch.2226859200
Short name T626
Test name
Test status
Simulation time 20845342458 ps
CPU time 766.66 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:38:32 PM PDT 24
Peak memory 4347112 kb
Host smart-ddd571a2-eec0-4e5e-90f5-b20d302cf295
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226859200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.i2c_
target_stretch.2226859200
Directory /workspace/10.i2c_target_stretch/latest

Test location /workspace/coverage/default/10.i2c_target_timeout.3375959864
Short name T88
Test name
Test status
Simulation time 1410926855 ps
CPU time 8.05 seconds
Started Jul 03 05:25:48 PM PDT 24
Finished Jul 03 05:25:57 PM PDT 24
Peak memory 221148 kb
Host smart-24e92908-9689-45c0-b688-ecb88bc70e35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375959864 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.i2c_target_timeout.3375959864
Directory /workspace/10.i2c_target_timeout/latest

Test location /workspace/coverage/default/10.i2c_target_tx_stretch_ctrl.817958408
Short name T549
Test name
Test status
Simulation time 145442694 ps
CPU time 2.12 seconds
Started Jul 03 05:25:50 PM PDT 24
Finished Jul 03 05:25:53 PM PDT 24
Peak memory 204800 kb
Host smart-3629b388-cb38-4544-89db-55740ce47f37
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817958408 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.i2c_target_tx_stretch_ctrl.817958408
Directory /workspace/10.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/11.i2c_alert_test.1893597072
Short name T364
Test name
Test status
Simulation time 20542830 ps
CPU time 0.63 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:25:54 PM PDT 24
Peak memory 204344 kb
Host smart-0fac1736-cfa7-460c-81aa-8c175f17d925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893597072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_alert_test.1893597072
Directory /workspace/11.i2c_alert_test/latest

Test location /workspace/coverage/default/11.i2c_host_error_intr.3243146962
Short name T1412
Test name
Test status
Simulation time 327026214 ps
CPU time 1.8 seconds
Started Jul 03 05:25:52 PM PDT 24
Finished Jul 03 05:25:54 PM PDT 24
Peak memory 213096 kb
Host smart-94146efa-6b9c-475c-b7be-a7df8b0a98ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243146962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_error_intr.3243146962
Directory /workspace/11.i2c_host_error_intr/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_fmt_empty.589819906
Short name T373
Test name
Test status
Simulation time 2173631545 ps
CPU time 8.21 seconds
Started Jul 03 05:25:52 PM PDT 24
Finished Jul 03 05:26:00 PM PDT 24
Peak memory 298696 kb
Host smart-0c1d79ab-4149-42ad-b802-d961d3ae9f80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589819906 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_fmt_empt
y.589819906
Directory /workspace/11.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_full.1745308608
Short name T618
Test name
Test status
Simulation time 2837864829 ps
CPU time 91.77 seconds
Started Jul 03 05:25:56 PM PDT 24
Finished Jul 03 05:27:28 PM PDT 24
Peak memory 556412 kb
Host smart-8eab0fb4-a190-4c27-8923-a534a5cc6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745308608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_full.1745308608
Directory /workspace/11.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_overflow.3666819857
Short name T1423
Test name
Test status
Simulation time 7661074035 ps
CPU time 58.51 seconds
Started Jul 03 05:25:56 PM PDT 24
Finished Jul 03 05:26:55 PM PDT 24
Peak memory 599812 kb
Host smart-ad4ba578-199c-4db3-96d6-5d3c0913ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666819857 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_overflow.3666819857
Directory /workspace/11.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_fmt.1427986466
Short name T380
Test name
Test status
Simulation time 157696208 ps
CPU time 1.25 seconds
Started Jul 03 05:25:50 PM PDT 24
Finished Jul 03 05:25:51 PM PDT 24
Peak memory 204644 kb
Host smart-c82cb3be-a6f9-4303-9eb4-1243ed3b6237
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427986466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_f
mt.1427986466
Directory /workspace/11.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_reset_rx.1682952571
Short name T695
Test name
Test status
Simulation time 921941857 ps
CPU time 6.31 seconds
Started Jul 03 05:25:52 PM PDT 24
Finished Jul 03 05:25:59 PM PDT 24
Peak memory 251176 kb
Host smart-4640152e-9592-4111-ac70-7be3fe299bc6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682952571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_reset_rx
.1682952571
Directory /workspace/11.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/11.i2c_host_fifo_watermark.1848161722
Short name T1122
Test name
Test status
Simulation time 20338154559 ps
CPU time 125.66 seconds
Started Jul 03 05:25:49 PM PDT 24
Finished Jul 03 05:27:55 PM PDT 24
Peak memory 1451376 kb
Host smart-24b8e835-e9fa-494a-a2d3-69ef59918991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848161722 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_fifo_watermark.1848161722
Directory /workspace/11.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/11.i2c_host_may_nack.2187107514
Short name T721
Test name
Test status
Simulation time 442738724 ps
CPU time 6.88 seconds
Started Jul 03 05:25:58 PM PDT 24
Finished Jul 03 05:26:10 PM PDT 24
Peak memory 204820 kb
Host smart-514d0b3f-3342-46f6-895d-cdbf825c30de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187107514 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_may_nack.2187107514
Directory /workspace/11.i2c_host_may_nack/latest

Test location /workspace/coverage/default/11.i2c_host_mode_toggle.390969069
Short name T916
Test name
Test status
Simulation time 1965676674 ps
CPU time 84.06 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 266020 kb
Host smart-9bac808e-90f5-4e6c-9618-b9fbb54ccf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390969069 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_mode_toggle.390969069
Directory /workspace/11.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/11.i2c_host_override.2947984532
Short name T93
Test name
Test status
Simulation time 35491688 ps
CPU time 0.71 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:25:52 PM PDT 24
Peak memory 204532 kb
Host smart-695987c1-ef8c-465f-b980-2da9f7a0215e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947984532 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_override.2947984532
Directory /workspace/11.i2c_host_override/latest

Test location /workspace/coverage/default/11.i2c_host_perf.161417014
Short name T427
Test name
Test status
Simulation time 52679890082 ps
CPU time 1612.64 seconds
Started Jul 03 05:25:59 PM PDT 24
Finished Jul 03 05:52:53 PM PDT 24
Peak memory 1910448 kb
Host smart-6cd63fde-2b01-4ab4-90d1-ec8841ea370d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161417014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf.161417014
Directory /workspace/11.i2c_host_perf/latest

Test location /workspace/coverage/default/11.i2c_host_perf_precise.1180768491
Short name T1066
Test name
Test status
Simulation time 320890537 ps
CPU time 4.5 seconds
Started Jul 03 05:25:56 PM PDT 24
Finished Jul 03 05:26:01 PM PDT 24
Peak memory 204664 kb
Host smart-733d5890-144c-4603-9976-b5eaacf05aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180768491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_perf_precise.1180768491
Directory /workspace/11.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/11.i2c_host_smoke.1057659220
Short name T1279
Test name
Test status
Simulation time 2435734717 ps
CPU time 93.28 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 375696 kb
Host smart-7936f50b-fc44-4fe4-b055-db578fed52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057659220 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_smoke.1057659220
Directory /workspace/11.i2c_host_smoke/latest

Test location /workspace/coverage/default/11.i2c_host_stress_all.387712573
Short name T166
Test name
Test status
Simulation time 19434029399 ps
CPU time 284.82 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:30:40 PM PDT 24
Peak memory 1373520 kb
Host smart-170cc651-805e-4dc4-9523-2893e9a0b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387712573 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stress_all.387712573
Directory /workspace/11.i2c_host_stress_all/latest

Test location /workspace/coverage/default/11.i2c_host_stretch_timeout.3938474828
Short name T471
Test name
Test status
Simulation time 5404935787 ps
CPU time 24.65 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:26:16 PM PDT 24
Peak memory 213156 kb
Host smart-19d920b2-1c40-4c42-b0f3-5541cb2efc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938474828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_host_stretch_timeout.3938474828
Directory /workspace/11.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_acq.3398001274
Short name T638
Test name
Test status
Simulation time 213603361 ps
CPU time 1 seconds
Started Jul 03 05:25:58 PM PDT 24
Finished Jul 03 05:25:59 PM PDT 24
Peak memory 204500 kb
Host smart-debe7de0-db4f-46a9-814d-c050127702f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398001274 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.i2c_target_fifo_reset_acq.3398001274
Directory /workspace/11.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_reset_tx.1193084522
Short name T1306
Test name
Test status
Simulation time 186950109 ps
CPU time 1.21 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:25:53 PM PDT 24
Peak memory 204596 kb
Host smart-86604232-f005-47ee-b4e6-1e166b0e82f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193084522 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.i2c_target_fifo_reset_tx.1193084522
Directory /workspace/11.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/11.i2c_target_fifo_watermarks_tx.1491587468
Short name T658
Test name
Test status
Simulation time 256263776 ps
CPU time 0.87 seconds
Started Jul 03 05:26:01 PM PDT 24
Finished Jul 03 05:26:03 PM PDT 24
Peak memory 204604 kb
Host smart-674b56d1-2e63-4659-8a13-b627ede960a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491587468 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 11.i2c_target_fifo_watermarks_tx.1491587468
Directory /workspace/11.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/11.i2c_target_hrst.3878167655
Short name T972
Test name
Test status
Simulation time 2496530069 ps
CPU time 3.26 seconds
Started Jul 03 05:25:52 PM PDT 24
Finished Jul 03 05:25:56 PM PDT 24
Peak memory 204896 kb
Host smart-d372823c-1def-4692-859c-dd832cf7524f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878167655 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 11.i2c_target_hrst.3878167655
Directory /workspace/11.i2c_target_hrst/latest

Test location /workspace/coverage/default/11.i2c_target_intr_smoke.3012516074
Short name T30
Test name
Test status
Simulation time 1023495375 ps
CPU time 5.78 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:26:02 PM PDT 24
Peak memory 221084 kb
Host smart-9069375b-a546-43b1-8b9b-3d5b22133db5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012516074 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 11.i2c_target_intr_smoke.3012516074
Directory /workspace/11.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_intr_stress_wr.289198401
Short name T360
Test name
Test status
Simulation time 5501708611 ps
CPU time 10.08 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:26:01 PM PDT 24
Peak memory 204912 kb
Host smart-e594968a-0dd2-4c3a-8860-52e79335b1a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289198401 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.i2c_target_intr_stress_wr.289198401
Directory /workspace/11.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_smoke.3516154087
Short name T585
Test name
Test status
Simulation time 1252920953 ps
CPU time 22.01 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:26:18 PM PDT 24
Peak memory 204804 kb
Host smart-b56d8bae-ef39-419e-9ca8-03b59977bde0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516154087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_ta
rget_smoke.3516154087
Directory /workspace/11.i2c_target_smoke/latest

Test location /workspace/coverage/default/11.i2c_target_stress_rd.2268591973
Short name T945
Test name
Test status
Simulation time 5417381508 ps
CPU time 20.69 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:26:12 PM PDT 24
Peak memory 227492 kb
Host smart-6e681dcf-8539-484a-9487-774de62c0111
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268591973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2
c_target_stress_rd.2268591973
Directory /workspace/11.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/11.i2c_target_stress_wr.57646518
Short name T167
Test name
Test status
Simulation time 10383630516 ps
CPU time 19.17 seconds
Started Jul 03 05:25:59 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 204904 kb
Host smart-0f819647-c685-4920-b2e1-96351b07b264
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57646518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stress_wr.57646518
Directory /workspace/11.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/11.i2c_target_stretch.4026635085
Short name T906
Test name
Test status
Simulation time 18203655360 ps
CPU time 58.62 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:26:56 PM PDT 24
Peak memory 384960 kb
Host smart-c8e51014-26da-4973-800b-a47ba8af9e90
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026635085 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.i2c_
target_stretch.4026635085
Directory /workspace/11.i2c_target_stretch/latest

Test location /workspace/coverage/default/11.i2c_target_timeout.1349251697
Short name T356
Test name
Test status
Simulation time 6893781931 ps
CPU time 6.31 seconds
Started Jul 03 05:25:56 PM PDT 24
Finished Jul 03 05:26:03 PM PDT 24
Peak memory 213152 kb
Host smart-95851c63-9476-4ea2-9719-054db03180b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349251697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.i2c_target_timeout.1349251697
Directory /workspace/11.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_alert_test.2445610766
Short name T1007
Test name
Test status
Simulation time 32100741 ps
CPU time 0.62 seconds
Started Jul 03 05:26:00 PM PDT 24
Finished Jul 03 05:26:01 PM PDT 24
Peak memory 204432 kb
Host smart-82da3a30-144b-4bef-b96e-d59b257b768d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445610766 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_alert_test.2445610766
Directory /workspace/12.i2c_alert_test/latest

Test location /workspace/coverage/default/12.i2c_host_error_intr.2488204530
Short name T44
Test name
Test status
Simulation time 342563424 ps
CPU time 6.58 seconds
Started Jul 03 05:25:58 PM PDT 24
Finished Jul 03 05:26:05 PM PDT 24
Peak memory 232064 kb
Host smart-6e7cec2f-db64-44f8-ae9f-b8078b75f925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488204530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_error_intr.2488204530
Directory /workspace/12.i2c_host_error_intr/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_fmt_empty.2792820016
Short name T709
Test name
Test status
Simulation time 1671148430 ps
CPU time 9.38 seconds
Started Jul 03 05:25:52 PM PDT 24
Finished Jul 03 05:26:01 PM PDT 24
Peak memory 294308 kb
Host smart-ff032076-32da-403c-82ac-b2b1fdcb86a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792820016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_fmt_emp
ty.2792820016
Directory /workspace/12.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_full.3019426625
Short name T1393
Test name
Test status
Simulation time 9259414361 ps
CPU time 121.06 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:27:57 PM PDT 24
Peak memory 643336 kb
Host smart-2cbe5f62-b115-4490-aabc-c526a43f064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019426625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_full.3019426625
Directory /workspace/12.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_overflow.1303883276
Short name T1068
Test name
Test status
Simulation time 10102708681 ps
CPU time 168.69 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:28:43 PM PDT 24
Peak memory 760228 kb
Host smart-4072db6b-6894-497f-a94f-88e7326ad1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303883276 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_overflow.1303883276
Directory /workspace/12.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/12.i2c_host_fifo_reset_rx.1128291582
Short name T1353
Test name
Test status
Simulation time 530370643 ps
CPU time 3.74 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:26:01 PM PDT 24
Peak memory 204836 kb
Host smart-bd37fb6c-894f-4a93-a9a4-3315a6da7770
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128291582 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_fifo_reset_rx
.1128291582
Directory /workspace/12.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/12.i2c_host_may_nack.1590497976
Short name T254
Test name
Test status
Simulation time 373135280 ps
CPU time 15.46 seconds
Started Jul 03 05:25:59 PM PDT 24
Finished Jul 03 05:26:15 PM PDT 24
Peak memory 204880 kb
Host smart-b0ecc91a-693e-4def-8a35-bda4a86b50b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590497976 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_may_nack.1590497976
Directory /workspace/12.i2c_host_may_nack/latest

Test location /workspace/coverage/default/12.i2c_host_mode_toggle.4129353902
Short name T64
Test name
Test status
Simulation time 4610656464 ps
CPU time 19.26 seconds
Started Jul 03 05:26:04 PM PDT 24
Finished Jul 03 05:26:24 PM PDT 24
Peak memory 270260 kb
Host smart-b572253f-639a-4569-8e32-4e1249527e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129353902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_mode_toggle.4129353902
Directory /workspace/12.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/12.i2c_host_override.2514125853
Short name T523
Test name
Test status
Simulation time 32370183 ps
CPU time 0.65 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:25:56 PM PDT 24
Peak memory 204424 kb
Host smart-84def7c8-e852-4044-ba90-006530f85a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514125853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_override.2514125853
Directory /workspace/12.i2c_host_override/latest

Test location /workspace/coverage/default/12.i2c_host_perf.260323095
Short name T210
Test name
Test status
Simulation time 24394204817 ps
CPU time 2535.08 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 06:08:09 PM PDT 24
Peak memory 3292468 kb
Host smart-f4aa115d-b28b-4976-838c-91c503d77a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260323095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf.260323095
Directory /workspace/12.i2c_host_perf/latest

Test location /workspace/coverage/default/12.i2c_host_perf_precise.2554853724
Short name T395
Test name
Test status
Simulation time 2526736108 ps
CPU time 63.62 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:26:59 PM PDT 24
Peak memory 461508 kb
Host smart-57bc1e7f-2df3-4548-942a-e731cf8842ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554853724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_perf_precise.2554853724
Directory /workspace/12.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/12.i2c_host_smoke.1856720332
Short name T1468
Test name
Test status
Simulation time 1132173001 ps
CPU time 15.71 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:26:14 PM PDT 24
Peak memory 278884 kb
Host smart-ffb2b3d8-084e-438b-9fed-72b37bc094ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856720332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_smoke.1856720332
Directory /workspace/12.i2c_host_smoke/latest

Test location /workspace/coverage/default/12.i2c_host_stress_all.2742512892
Short name T113
Test name
Test status
Simulation time 44078557237 ps
CPU time 1406.48 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:49:25 PM PDT 24
Peak memory 4371452 kb
Host smart-37a91096-daf8-468e-ad1f-5913a684453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742512892 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stress_all.2742512892
Directory /workspace/12.i2c_host_stress_all/latest

Test location /workspace/coverage/default/12.i2c_host_stretch_timeout.3951852031
Short name T889
Test name
Test status
Simulation time 743524276 ps
CPU time 11.79 seconds
Started Jul 03 05:25:52 PM PDT 24
Finished Jul 03 05:26:04 PM PDT 24
Peak memory 214300 kb
Host smart-8c2aa9f9-d540-40f3-b81c-58ea6c3d8ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951852031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_host_stretch_timeout.3951852031
Directory /workspace/12.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_bad_addr.1677787966
Short name T978
Test name
Test status
Simulation time 1142384312 ps
CPU time 5.6 seconds
Started Jul 03 05:26:04 PM PDT 24
Finished Jul 03 05:26:10 PM PDT 24
Peak memory 213076 kb
Host smart-f1711fee-2d05-4a4e-a266-1209d3541477
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677787966 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.i2c_target_bad_addr.1677787966
Directory /workspace/12.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_acq.571784621
Short name T278
Test name
Test status
Simulation time 243922903 ps
CPU time 1.38 seconds
Started Jul 03 05:26:00 PM PDT 24
Finished Jul 03 05:26:02 PM PDT 24
Peak memory 204856 kb
Host smart-b9f44b71-ea48-47d1-8670-4790db7d54c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571784621 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_acq.571784621
Directory /workspace/12.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_reset_tx.4250522955
Short name T277
Test name
Test status
Simulation time 207865897 ps
CPU time 1.45 seconds
Started Jul 03 05:26:01 PM PDT 24
Finished Jul 03 05:26:02 PM PDT 24
Peak memory 212980 kb
Host smart-6c421ece-cb71-4384-bc23-591c7a896c87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250522955 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.i2c_target_fifo_reset_tx.4250522955
Directory /workspace/12.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_acq.4254947672
Short name T1385
Test name
Test status
Simulation time 665346912 ps
CPU time 1.96 seconds
Started Jul 03 05:26:02 PM PDT 24
Finished Jul 03 05:26:04 PM PDT 24
Peak memory 204828 kb
Host smart-b8501cc7-61ff-410a-bd8a-d64d8d9cd653
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254947672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.i2c_target_fifo_watermarks_acq.4254947672
Directory /workspace/12.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/12.i2c_target_fifo_watermarks_tx.2614045546
Short name T789
Test name
Test status
Simulation time 155178847 ps
CPU time 1.33 seconds
Started Jul 03 05:26:02 PM PDT 24
Finished Jul 03 05:26:04 PM PDT 24
Peak memory 204588 kb
Host smart-2d239591-b6ea-4456-9e8d-09b8fae1a553
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614045546 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 12.i2c_target_fifo_watermarks_tx.2614045546
Directory /workspace/12.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/12.i2c_target_intr_smoke.923705323
Short name T1343
Test name
Test status
Simulation time 751990644 ps
CPU time 4.48 seconds
Started Jul 03 05:25:54 PM PDT 24
Finished Jul 03 05:25:59 PM PDT 24
Peak memory 213052 kb
Host smart-fa3f0fde-e163-4679-9401-ad880b86d23f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923705323 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 12.i2c_target_intr_smoke.923705323
Directory /workspace/12.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_intr_stress_wr.1975555498
Short name T1408
Test name
Test status
Simulation time 19938624278 ps
CPU time 51.23 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:26:46 PM PDT 24
Peak memory 1171908 kb
Host smart-55b6bcff-9d70-433c-9ef7-26b6c4a84d5b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975555498 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.i2c_target_intr_stress_wr.1975555498
Directory /workspace/12.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_smoke.2099132252
Short name T699
Test name
Test status
Simulation time 2528936826 ps
CPU time 49.47 seconds
Started Jul 03 05:25:58 PM PDT 24
Finished Jul 03 05:26:48 PM PDT 24
Peak memory 204872 kb
Host smart-fc78e7c9-0e23-4864-af63-9804cd367384
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099132252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_ta
rget_smoke.2099132252
Directory /workspace/12.i2c_target_smoke/latest

Test location /workspace/coverage/default/12.i2c_target_stress_rd.3982039476
Short name T480
Test name
Test status
Simulation time 4074076913 ps
CPU time 14.91 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:26:13 PM PDT 24
Peak memory 219140 kb
Host smart-58c4b9d5-5914-4b93-adf0-c472dc9cd9a8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982039476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_rd.3982039476
Directory /workspace/12.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/12.i2c_target_stress_wr.2477365460
Short name T931
Test name
Test status
Simulation time 43704769265 ps
CPU time 738.97 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:38:15 PM PDT 24
Peak memory 5930576 kb
Host smart-4bf58bc3-67b7-4b3d-aeec-8282d5c56ce2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477365460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2
c_target_stress_wr.2477365460
Directory /workspace/12.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/12.i2c_target_stretch.160865011
Short name T1443
Test name
Test status
Simulation time 20762801801 ps
CPU time 1248.96 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:46:45 PM PDT 24
Peak memory 5047212 kb
Host smart-9aeab6aa-4fb5-46df-a1a0-fec98e335a17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160865011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.i2c_t
arget_stretch.160865011
Directory /workspace/12.i2c_target_stretch/latest

Test location /workspace/coverage/default/12.i2c_target_timeout.3381889575
Short name T1338
Test name
Test status
Simulation time 3009340893 ps
CPU time 7.59 seconds
Started Jul 03 05:25:55 PM PDT 24
Finished Jul 03 05:26:03 PM PDT 24
Peak memory 213096 kb
Host smart-500b3b08-8797-4863-b599-439ca4f79cd2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381889575 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.i2c_target_timeout.3381889575
Directory /workspace/12.i2c_target_timeout/latest

Test location /workspace/coverage/default/12.i2c_target_tx_stretch_ctrl.3892636357
Short name T971
Test name
Test status
Simulation time 84137777 ps
CPU time 1.83 seconds
Started Jul 03 05:26:02 PM PDT 24
Finished Jul 03 05:26:04 PM PDT 24
Peak memory 204860 kb
Host smart-9f57c405-aaa1-4adc-864e-a5d69fb3eaab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892636357 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.i2c_target_tx_stretch_ctrl.3892636357
Directory /workspace/12.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/13.i2c_host_error_intr.3577676434
Short name T1424
Test name
Test status
Simulation time 120036834 ps
CPU time 1.66 seconds
Started Jul 03 05:26:08 PM PDT 24
Finished Jul 03 05:26:10 PM PDT 24
Peak memory 213160 kb
Host smart-1c7a50c2-d87b-41dd-b9c7-3f47000fc627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577676434 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_error_intr.3577676434
Directory /workspace/13.i2c_host_error_intr/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_fmt_empty.943188399
Short name T774
Test name
Test status
Simulation time 802941719 ps
CPU time 8.34 seconds
Started Jul 03 05:26:04 PM PDT 24
Finished Jul 03 05:26:13 PM PDT 24
Peak memory 269524 kb
Host smart-cecf0271-bf66-4790-a49a-b052511fa141
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943188399 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_fmt_empt
y.943188399
Directory /workspace/13.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_full.3543042762
Short name T143
Test name
Test status
Simulation time 11051802258 ps
CPU time 107.52 seconds
Started Jul 03 05:26:13 PM PDT 24
Finished Jul 03 05:28:01 PM PDT 24
Peak memory 923844 kb
Host smart-79695e14-4a9f-43b0-9c7e-c757cd144a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543042762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_full.3543042762
Directory /workspace/13.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_overflow.3475311068
Short name T1088
Test name
Test status
Simulation time 14210550664 ps
CPU time 89.79 seconds
Started Jul 03 05:26:01 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 882604 kb
Host smart-ed395f3f-4ac2-48ec-9dfe-e446b22b7a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475311068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_overflow.3475311068
Directory /workspace/13.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_fmt.2526785431
Short name T893
Test name
Test status
Simulation time 314125695 ps
CPU time 1.08 seconds
Started Jul 03 05:26:05 PM PDT 24
Finished Jul 03 05:26:06 PM PDT 24
Peak memory 204424 kb
Host smart-8a28ee0b-2cb3-4459-9424-aef164dacbd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526785431 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_f
mt.2526785431
Directory /workspace/13.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_reset_rx.1457396240
Short name T861
Test name
Test status
Simulation time 161173328 ps
CPU time 8.02 seconds
Started Jul 03 05:26:01 PM PDT 24
Finished Jul 03 05:26:10 PM PDT 24
Peak memory 204692 kb
Host smart-6dec40a7-212c-4039-a76e-a572610f8220
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457396240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_reset_rx
.1457396240
Directory /workspace/13.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/13.i2c_host_fifo_watermark.2868343193
Short name T954
Test name
Test status
Simulation time 11333607100 ps
CPU time 166.86 seconds
Started Jul 03 05:25:59 PM PDT 24
Finished Jul 03 05:28:46 PM PDT 24
Peak memory 853592 kb
Host smart-393c6867-23f1-446e-ad49-69cc8bd03917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868343193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_fifo_watermark.2868343193
Directory /workspace/13.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/13.i2c_host_may_nack.2071794156
Short name T61
Test name
Test status
Simulation time 328702253 ps
CPU time 2.82 seconds
Started Jul 03 05:26:02 PM PDT 24
Finished Jul 03 05:26:06 PM PDT 24
Peak memory 204816 kb
Host smart-461e7123-99ae-4bda-abb7-4c3bd43dff65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071794156 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_may_nack.2071794156
Directory /workspace/13.i2c_host_may_nack/latest

Test location /workspace/coverage/default/13.i2c_host_override.220586016
Short name T433
Test name
Test status
Simulation time 21109792 ps
CPU time 0.7 seconds
Started Jul 03 05:26:06 PM PDT 24
Finished Jul 03 05:26:07 PM PDT 24
Peak memory 204572 kb
Host smart-ce08abd2-11ed-4051-a197-fb3c049c4df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220586016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_override.220586016
Directory /workspace/13.i2c_host_override/latest

Test location /workspace/coverage/default/13.i2c_host_perf.751637688
Short name T1467
Test name
Test status
Simulation time 26720176236 ps
CPU time 705.1 seconds
Started Jul 03 05:26:04 PM PDT 24
Finished Jul 03 05:37:49 PM PDT 24
Peak memory 873476 kb
Host smart-3f615d97-5f07-40b8-9803-aa24f2003b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751637688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf.751637688
Directory /workspace/13.i2c_host_perf/latest

Test location /workspace/coverage/default/13.i2c_host_perf_precise.2968393917
Short name T417
Test name
Test status
Simulation time 74356273 ps
CPU time 1.12 seconds
Started Jul 03 05:26:06 PM PDT 24
Finished Jul 03 05:26:08 PM PDT 24
Peak memory 205024 kb
Host smart-aa9eef2b-e227-4775-8464-af03f133b19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968393917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_perf_precise.2968393917
Directory /workspace/13.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/13.i2c_host_smoke.1843479265
Short name T117
Test name
Test status
Simulation time 1801453432 ps
CPU time 71.76 seconds
Started Jul 03 05:26:05 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 301104 kb
Host smart-e2b8126b-8637-47fa-b0ff-8767d42aa697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843479265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_smoke.1843479265
Directory /workspace/13.i2c_host_smoke/latest

Test location /workspace/coverage/default/13.i2c_host_stretch_timeout.2174757565
Short name T301
Test name
Test status
Simulation time 9516457179 ps
CPU time 14.26 seconds
Started Jul 03 05:26:04 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 220260 kb
Host smart-9050efa3-05d6-4ead-b78d-df84ff0e7f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174757565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_host_stretch_timeout.2174757565
Directory /workspace/13.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_bad_addr.3889379425
Short name T1110
Test name
Test status
Simulation time 3751991839 ps
CPU time 5.03 seconds
Started Jul 03 05:26:01 PM PDT 24
Finished Jul 03 05:26:06 PM PDT 24
Peak memory 214500 kb
Host smart-300ee0bd-52ec-4a0b-ab0b-691e8e6698aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889379425 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.i2c_target_bad_addr.3889379425
Directory /workspace/13.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_acq.1836282485
Short name T464
Test name
Test status
Simulation time 203769669 ps
CPU time 1.07 seconds
Started Jul 03 05:26:10 PM PDT 24
Finished Jul 03 05:26:11 PM PDT 24
Peak memory 204580 kb
Host smart-c2789463-932b-4576-bbac-1aa79786c988
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836282485 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_fifo_reset_acq.1836282485
Directory /workspace/13.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_reset_tx.891551443
Short name T1283
Test name
Test status
Simulation time 116875311 ps
CPU time 0.92 seconds
Started Jul 03 05:26:02 PM PDT 24
Finished Jul 03 05:26:03 PM PDT 24
Peak memory 204624 kb
Host smart-40d9ef50-1dd8-4a79-9671-03fd397c3c69
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891551443 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.i2c_target_fifo_reset_tx.891551443
Directory /workspace/13.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_acq.3059671503
Short name T1344
Test name
Test status
Simulation time 934893000 ps
CPU time 2.3 seconds
Started Jul 03 05:26:03 PM PDT 24
Finished Jul 03 05:26:05 PM PDT 24
Peak memory 204872 kb
Host smart-08d9ae53-dd96-4339-8bbf-ea32f03e9630
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059671503 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.i2c_target_fifo_watermarks_acq.3059671503
Directory /workspace/13.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/13.i2c_target_fifo_watermarks_tx.2040482240
Short name T1488
Test name
Test status
Simulation time 255169637 ps
CPU time 1.21 seconds
Started Jul 03 05:26:05 PM PDT 24
Finished Jul 03 05:26:07 PM PDT 24
Peak memory 204544 kb
Host smart-b72df9f0-1318-4517-aafd-cbd49c49905e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040482240 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 13.i2c_target_fifo_watermarks_tx.2040482240
Directory /workspace/13.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/13.i2c_target_intr_smoke.2143843400
Short name T341
Test name
Test status
Simulation time 3673610464 ps
CPU time 5.78 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:21 PM PDT 24
Peak memory 204876 kb
Host smart-27115f54-e82e-499d-8ec2-2c14bdb40e26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143843400 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 13.i2c_target_intr_smoke.2143843400
Directory /workspace/13.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_intr_stress_wr.2804513962
Short name T939
Test name
Test status
Simulation time 22669427097 ps
CPU time 168.15 seconds
Started Jul 03 05:26:07 PM PDT 24
Finished Jul 03 05:28:55 PM PDT 24
Peak memory 1987436 kb
Host smart-bfd568c9-dbc5-4241-b71a-67ce6d08774c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804513962 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.i2c_target_intr_stress_wr.2804513962
Directory /workspace/13.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_smoke.2790208614
Short name T463
Test name
Test status
Simulation time 626987152 ps
CPU time 22.44 seconds
Started Jul 03 05:26:08 PM PDT 24
Finished Jul 03 05:26:31 PM PDT 24
Peak memory 204792 kb
Host smart-7c79da2c-d2a3-4f52-8375-917d4f27fc55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790208614 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_ta
rget_smoke.2790208614
Directory /workspace/13.i2c_target_smoke/latest

Test location /workspace/coverage/default/13.i2c_target_stress_rd.2276035043
Short name T518
Test name
Test status
Simulation time 1720150145 ps
CPU time 29.13 seconds
Started Jul 03 05:26:07 PM PDT 24
Finished Jul 03 05:26:36 PM PDT 24
Peak memory 227756 kb
Host smart-19147391-cca9-48bd-9d03-7cda55de76cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276035043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_rd.2276035043
Directory /workspace/13.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/13.i2c_target_stress_wr.1858953995
Short name T1366
Test name
Test status
Simulation time 43996172350 ps
CPU time 302.91 seconds
Started Jul 03 05:26:11 PM PDT 24
Finished Jul 03 05:31:14 PM PDT 24
Peak memory 3053804 kb
Host smart-3bee22b7-efce-4f5d-880b-19ca67ca9223
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858953995 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2
c_target_stress_wr.1858953995
Directory /workspace/13.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/13.i2c_target_stretch.661436223
Short name T912
Test name
Test status
Simulation time 10505127622 ps
CPU time 347.16 seconds
Started Jul 03 05:26:07 PM PDT 24
Finished Jul 03 05:31:55 PM PDT 24
Peak memory 2738420 kb
Host smart-7ee6cf1c-ce50-4a06-a19a-576a36d69a63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661436223 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.i2c_t
arget_stretch.661436223
Directory /workspace/13.i2c_target_stretch/latest

Test location /workspace/coverage/default/13.i2c_target_timeout.1936035113
Short name T1158
Test name
Test status
Simulation time 5824476457 ps
CPU time 7.03 seconds
Started Jul 03 05:26:12 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 204868 kb
Host smart-c87f19ec-13d8-493c-867c-acb73bebd050
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936035113 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.i2c_target_timeout.1936035113
Directory /workspace/13.i2c_target_timeout/latest

Test location /workspace/coverage/default/13.i2c_target_tx_stretch_ctrl.3720739137
Short name T354
Test name
Test status
Simulation time 268006420 ps
CPU time 4.33 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:22 PM PDT 24
Peak memory 204840 kb
Host smart-3e7b35a9-ad51-4b9b-baae-11c1916ae6fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720739137 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.i2c_target_tx_stretch_ctrl.3720739137
Directory /workspace/13.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/14.i2c_alert_test.3010594812
Short name T858
Test name
Test status
Simulation time 39244397 ps
CPU time 0.63 seconds
Started Jul 03 05:26:26 PM PDT 24
Finished Jul 03 05:26:27 PM PDT 24
Peak memory 204452 kb
Host smart-93b96d21-4adb-44a0-b9de-92390a171857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010594812 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_alert_test.3010594812
Directory /workspace/14.i2c_alert_test/latest

Test location /workspace/coverage/default/14.i2c_host_error_intr.263708426
Short name T833
Test name
Test status
Simulation time 632150585 ps
CPU time 1.65 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 213140 kb
Host smart-a87127d9-c89a-43fc-8ab1-e5cc1e941b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263708426 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_error_intr.263708426
Directory /workspace/14.i2c_host_error_intr/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_fmt_empty.2614567904
Short name T937
Test name
Test status
Simulation time 903953348 ps
CPU time 11.6 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:27 PM PDT 24
Peak memory 244976 kb
Host smart-d5fb31d6-25e8-4f86-b122-e8c18d1238f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614567904 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_fmt_emp
ty.2614567904
Directory /workspace/14.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_full.2668738707
Short name T996
Test name
Test status
Simulation time 4196931700 ps
CPU time 73.96 seconds
Started Jul 03 05:26:07 PM PDT 24
Finished Jul 03 05:27:21 PM PDT 24
Peak memory 703956 kb
Host smart-aa4a00a4-39e8-4143-aeba-eee26b8dae92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668738707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_full.2668738707
Directory /workspace/14.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_overflow.87834480
Short name T1119
Test name
Test status
Simulation time 10672867332 ps
CPU time 97.87 seconds
Started Jul 03 05:26:21 PM PDT 24
Finished Jul 03 05:27:59 PM PDT 24
Peak memory 845276 kb
Host smart-941e4ed8-6426-4527-9085-d208d32ed40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87834480 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_overflow.87834480
Directory /workspace/14.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_fmt.2158809983
Short name T1505
Test name
Test status
Simulation time 204695600 ps
CPU time 1.13 seconds
Started Jul 03 05:26:07 PM PDT 24
Finished Jul 03 05:26:09 PM PDT 24
Peak memory 204484 kb
Host smart-201a89fa-e58c-4497-a440-7c5c8b8f2e07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158809983 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_f
mt.2158809983
Directory /workspace/14.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_reset_rx.2378551376
Short name T159
Test name
Test status
Simulation time 130778992 ps
CPU time 6.52 seconds
Started Jul 03 05:26:13 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 204836 kb
Host smart-c0f104c0-dbeb-43cf-a290-6149ab21fed1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378551376 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_reset_rx
.2378551376
Directory /workspace/14.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/14.i2c_host_fifo_watermark.4232661438
Short name T371
Test name
Test status
Simulation time 2717420827 ps
CPU time 170.93 seconds
Started Jul 03 05:26:07 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 849048 kb
Host smart-9f0085f1-670d-4a23-b9be-b49da0abb578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232661438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_fifo_watermark.4232661438
Directory /workspace/14.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/14.i2c_host_may_nack.3067420653
Short name T521
Test name
Test status
Simulation time 1186036424 ps
CPU time 12.18 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:28 PM PDT 24
Peak memory 204844 kb
Host smart-36d8aae7-b178-4658-92c6-12db9475f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067420653 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_may_nack.3067420653
Directory /workspace/14.i2c_host_may_nack/latest

Test location /workspace/coverage/default/14.i2c_host_mode_toggle.862215465
Short name T344
Test name
Test status
Simulation time 1725107546 ps
CPU time 31.96 seconds
Started Jul 03 05:26:19 PM PDT 24
Finished Jul 03 05:26:51 PM PDT 24
Peak memory 352996 kb
Host smart-9828b095-f0b0-4870-bb86-0024d92b001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862215465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_mode_toggle.862215465
Directory /workspace/14.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/14.i2c_host_override.3555787333
Short name T134
Test name
Test status
Simulation time 88655250 ps
CPU time 0.69 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 204536 kb
Host smart-c7a03bd0-ee61-4b9c-bc5e-4840e2df9d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555787333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_override.3555787333
Directory /workspace/14.i2c_host_override/latest

Test location /workspace/coverage/default/14.i2c_host_perf.1023471471
Short name T763
Test name
Test status
Simulation time 48078560505 ps
CPU time 1297.37 seconds
Started Jul 03 05:26:06 PM PDT 24
Finished Jul 03 05:47:44 PM PDT 24
Peak memory 2832880 kb
Host smart-f12ddee3-4f83-4175-abc6-27fc22b6667d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023471471 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf.1023471471
Directory /workspace/14.i2c_host_perf/latest

Test location /workspace/coverage/default/14.i2c_host_perf_precise.3172217604
Short name T527
Test name
Test status
Simulation time 138117046 ps
CPU time 1.59 seconds
Started Jul 03 05:26:07 PM PDT 24
Finished Jul 03 05:26:09 PM PDT 24
Peak memory 204684 kb
Host smart-c913a122-2c64-4822-b554-59bd58284bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172217604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_perf_precise.3172217604
Directory /workspace/14.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/14.i2c_host_smoke.3038052890
Short name T667
Test name
Test status
Simulation time 1471441799 ps
CPU time 21.45 seconds
Started Jul 03 05:26:10 PM PDT 24
Finished Jul 03 05:26:32 PM PDT 24
Peak memory 305648 kb
Host smart-18c2e1ea-c169-4a66-aa60-4423208ac62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038052890 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_smoke.3038052890
Directory /workspace/14.i2c_host_smoke/latest

Test location /workspace/coverage/default/14.i2c_host_stretch_timeout.1774228505
Short name T574
Test name
Test status
Simulation time 3662353799 ps
CPU time 40.46 seconds
Started Jul 03 05:26:06 PM PDT 24
Finished Jul 03 05:26:47 PM PDT 24
Peak memory 221280 kb
Host smart-61dc1be5-dbb3-4346-8808-c2b58ce34998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774228505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_host_stretch_timeout.1774228505
Directory /workspace/14.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_bad_addr.1625596681
Short name T662
Test name
Test status
Simulation time 816483360 ps
CPU time 3.99 seconds
Started Jul 03 05:26:11 PM PDT 24
Finished Jul 03 05:26:15 PM PDT 24
Peak memory 204784 kb
Host smart-0ebfc607-6aa4-4453-b9ef-4802aa073d98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625596681 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.i2c_target_bad_addr.1625596681
Directory /workspace/14.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_acq.2738111374
Short name T603
Test name
Test status
Simulation time 815141627 ps
CPU time 0.92 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 204612 kb
Host smart-256f84c4-f664-46c8-b33b-ff350a7b18ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738111374 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_fifo_reset_acq.2738111374
Directory /workspace/14.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_reset_tx.300286314
Short name T29
Test name
Test status
Simulation time 276233684 ps
CPU time 1.07 seconds
Started Jul 03 05:26:12 PM PDT 24
Finished Jul 03 05:26:13 PM PDT 24
Peak memory 204456 kb
Host smart-330df024-837f-432e-b74e-76dfa06e6c82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300286314 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.i2c_target_fifo_reset_tx.300286314
Directory /workspace/14.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_acq.3388691944
Short name T1058
Test name
Test status
Simulation time 4838777715 ps
CPU time 2.59 seconds
Started Jul 03 05:26:13 PM PDT 24
Finished Jul 03 05:26:16 PM PDT 24
Peak memory 204944 kb
Host smart-4d5a57dc-a188-48f5-ab15-33993c9aef06
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388691944 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.i2c_target_fifo_watermarks_acq.3388691944
Directory /workspace/14.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/14.i2c_target_fifo_watermarks_tx.2778908543
Short name T1076
Test name
Test status
Simulation time 132141303 ps
CPU time 1.18 seconds
Started Jul 03 05:26:14 PM PDT 24
Finished Jul 03 05:26:15 PM PDT 24
Peak memory 204600 kb
Host smart-8dd3e578-8266-492a-b7b7-266a481f82cd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778908543 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 14.i2c_target_fifo_watermarks_tx.2778908543
Directory /workspace/14.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/14.i2c_target_hrst.2695326707
Short name T423
Test name
Test status
Simulation time 1290520076 ps
CPU time 3.05 seconds
Started Jul 03 05:26:13 PM PDT 24
Finished Jul 03 05:26:16 PM PDT 24
Peak memory 204820 kb
Host smart-6a792816-7808-4005-a490-dd78edeeaa33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695326707 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_hrst.2695326707
Directory /workspace/14.i2c_target_hrst/latest

Test location /workspace/coverage/default/14.i2c_target_intr_smoke.973461539
Short name T1086
Test name
Test status
Simulation time 5105163315 ps
CPU time 6.12 seconds
Started Jul 03 05:26:24 PM PDT 24
Finished Jul 03 05:26:31 PM PDT 24
Peak memory 220476 kb
Host smart-fbf0254e-b73e-4ca3-9fd7-9e6b560545bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973461539 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 14.i2c_target_intr_smoke.973461539
Directory /workspace/14.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_intr_stress_wr.898595848
Short name T895
Test name
Test status
Simulation time 20522079153 ps
CPU time 418.39 seconds
Started Jul 03 05:26:11 PM PDT 24
Finished Jul 03 05:33:10 PM PDT 24
Peak memory 4951344 kb
Host smart-2361114c-1e1f-447c-aa4d-c352ac272b33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898595848 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.i2c_target_intr_stress_wr.898595848
Directory /workspace/14.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_smoke.353361121
Short name T1442
Test name
Test status
Simulation time 15749760935 ps
CPU time 37.39 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:55 PM PDT 24
Peak memory 204948 kb
Host smart-6d0fba76-df77-4314-b468-8e3b1e568bbe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353361121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_tar
get_smoke.353361121
Directory /workspace/14.i2c_target_smoke/latest

Test location /workspace/coverage/default/14.i2c_target_stress_rd.316145185
Short name T424
Test name
Test status
Simulation time 866186410 ps
CPU time 37.87 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:56 PM PDT 24
Peak memory 204780 kb
Host smart-4fe1ef8f-4830-4f63-a76e-acf2c1f3cbf4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316145185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c
_target_stress_rd.316145185
Directory /workspace/14.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/14.i2c_target_stress_wr.1141930858
Short name T1280
Test name
Test status
Simulation time 22438659254 ps
CPU time 13.74 seconds
Started Jul 03 05:26:05 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 256084 kb
Host smart-7ccab88c-8eda-44e4-9f8e-cf0505aceb54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141930858 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2
c_target_stress_wr.1141930858
Directory /workspace/14.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/14.i2c_target_stretch.1693229886
Short name T1357
Test name
Test status
Simulation time 23806718883 ps
CPU time 1419.77 seconds
Started Jul 03 05:26:06 PM PDT 24
Finished Jul 03 05:49:46 PM PDT 24
Peak memory 5718316 kb
Host smart-9f4fa96f-3e2c-4e83-baa2-7700eef47c3b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693229886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.i2c_
target_stretch.1693229886
Directory /workspace/14.i2c_target_stretch/latest

Test location /workspace/coverage/default/14.i2c_target_timeout.1498227653
Short name T1530
Test name
Test status
Simulation time 1369345593 ps
CPU time 6.99 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:23 PM PDT 24
Peak memory 204844 kb
Host smart-e3d98562-b1ae-4792-a4bc-1aa8e04db79e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498227653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.i2c_target_timeout.1498227653
Directory /workspace/14.i2c_target_timeout/latest

Test location /workspace/coverage/default/14.i2c_target_tx_stretch_ctrl.2400851264
Short name T1103
Test name
Test status
Simulation time 49690217 ps
CPU time 1.23 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 204720 kb
Host smart-e81263e1-3f87-40c2-ac5b-916b60b2d7a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400851264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.i2c_target_tx_stretch_ctrl.2400851264
Directory /workspace/14.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/15.i2c_alert_test.114229916
Short name T870
Test name
Test status
Simulation time 50856527 ps
CPU time 0.61 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:16 PM PDT 24
Peak memory 204500 kb
Host smart-b64b0768-623d-4458-858a-48688ff9a5d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114229916 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_alert_test.114229916
Directory /workspace/15.i2c_alert_test/latest

Test location /workspace/coverage/default/15.i2c_host_error_intr.2582104217
Short name T1388
Test name
Test status
Simulation time 406600336 ps
CPU time 7.6 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:23 PM PDT 24
Peak memory 277680 kb
Host smart-79d8d0c1-897f-4087-bf87-4a614a1114c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582104217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_error_intr.2582104217
Directory /workspace/15.i2c_host_error_intr/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_fmt_empty.2857412772
Short name T1206
Test name
Test status
Simulation time 526285256 ps
CPU time 13.48 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:31 PM PDT 24
Peak memory 258348 kb
Host smart-1866912f-c998-4545-aff7-d60bf5f49ad3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857412772 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_fmt_emp
ty.2857412772
Directory /workspace/15.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_overflow.999260036
Short name T649
Test name
Test status
Simulation time 2431076412 ps
CPU time 183.43 seconds
Started Jul 03 05:26:14 PM PDT 24
Finished Jul 03 05:29:18 PM PDT 24
Peak memory 792280 kb
Host smart-f4f452c7-630b-4ceb-8874-290c65ab4ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999260036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_overflow.999260036
Directory /workspace/15.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_fmt.1726743473
Short name T921
Test name
Test status
Simulation time 110252293 ps
CPU time 1.01 seconds
Started Jul 03 05:26:16 PM PDT 24
Finished Jul 03 05:26:18 PM PDT 24
Peak memory 204448 kb
Host smart-454b28c4-fe36-4e52-8a09-11532613d7c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726743473 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_f
mt.1726743473
Directory /workspace/15.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_reset_rx.326538005
Short name T66
Test name
Test status
Simulation time 972913679 ps
CPU time 4.46 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 236564 kb
Host smart-34017728-8112-4cc8-b074-4802dd5c884e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326538005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_reset_rx.
326538005
Directory /workspace/15.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/15.i2c_host_fifo_watermark.3860895973
Short name T617
Test name
Test status
Simulation time 2896588266 ps
CPU time 68.52 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:27:27 PM PDT 24
Peak memory 852560 kb
Host smart-b090306e-415d-4f22-a6ad-92df7e72e5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860895973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_fifo_watermark.3860895973
Directory /workspace/15.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/15.i2c_host_may_nack.1824131509
Short name T734
Test name
Test status
Simulation time 514199290 ps
CPU time 6.33 seconds
Started Jul 03 05:26:24 PM PDT 24
Finished Jul 03 05:26:30 PM PDT 24
Peak memory 204820 kb
Host smart-e2adf256-1a18-446f-aa3f-8170d313e855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824131509 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_may_nack.1824131509
Directory /workspace/15.i2c_host_may_nack/latest

Test location /workspace/coverage/default/15.i2c_host_override.328217730
Short name T1075
Test name
Test status
Simulation time 51571042 ps
CPU time 0.71 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:18 PM PDT 24
Peak memory 204524 kb
Host smart-74d4d78c-0b9b-476a-8033-6c2270cdabc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328217730 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_override.328217730
Directory /workspace/15.i2c_host_override/latest

Test location /workspace/coverage/default/15.i2c_host_perf.2553142150
Short name T930
Test name
Test status
Simulation time 2714728713 ps
CPU time 15.69 seconds
Started Jul 03 05:26:12 PM PDT 24
Finished Jul 03 05:26:28 PM PDT 24
Peak memory 219796 kb
Host smart-3f702201-c210-447e-a432-e6ec50ed9a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553142150 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf.2553142150
Directory /workspace/15.i2c_host_perf/latest

Test location /workspace/coverage/default/15.i2c_host_perf_precise.1085316959
Short name T36
Test name
Test status
Simulation time 2389834581 ps
CPU time 149.81 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:28:45 PM PDT 24
Peak memory 766064 kb
Host smart-d301eda8-278c-4a71-a20d-b28a653a38bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085316959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_perf_precise.1085316959
Directory /workspace/15.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/15.i2c_host_smoke.952019865
Short name T597
Test name
Test status
Simulation time 14420660240 ps
CPU time 20.25 seconds
Started Jul 03 05:26:19 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 318460 kb
Host smart-d936d9e8-b056-4ac3-b5ae-684b8e7ee3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952019865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_smoke.952019865
Directory /workspace/15.i2c_host_smoke/latest

Test location /workspace/coverage/default/15.i2c_host_stress_all.4172583280
Short name T1003
Test name
Test status
Simulation time 24369874573 ps
CPU time 1410.45 seconds
Started Jul 03 05:26:14 PM PDT 24
Finished Jul 03 05:49:45 PM PDT 24
Peak memory 2561536 kb
Host smart-51de0e9a-3bf9-4226-9d66-1adfd2b4850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172583280 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stress_all.4172583280
Directory /workspace/15.i2c_host_stress_all/latest

Test location /workspace/coverage/default/15.i2c_host_stretch_timeout.1246771694
Short name T605
Test name
Test status
Simulation time 886728451 ps
CPU time 8.56 seconds
Started Jul 03 05:26:13 PM PDT 24
Finished Jul 03 05:26:22 PM PDT 24
Peak memory 212984 kb
Host smart-f68f074b-921c-4cfa-8308-957b5f169c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246771694 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_host_stretch_timeout.1246771694
Directory /workspace/15.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_bad_addr.3015736908
Short name T1201
Test name
Test status
Simulation time 1125570870 ps
CPU time 5.32 seconds
Started Jul 03 05:26:19 PM PDT 24
Finished Jul 03 05:26:25 PM PDT 24
Peak memory 213076 kb
Host smart-d39e5ad7-fe67-4677-8da9-4f3978e3c8e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015736908 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.i2c_target_bad_addr.3015736908
Directory /workspace/15.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_acq.34768958
Short name T883
Test name
Test status
Simulation time 573628352 ps
CPU time 1.19 seconds
Started Jul 03 05:26:16 PM PDT 24
Finished Jul 03 05:26:18 PM PDT 24
Peak memory 204656 kb
Host smart-9685b316-4ce5-4482-ab38-cfeb6b0dcff3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34768958 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_acq.34768958
Directory /workspace/15.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_reset_tx.245453673
Short name T514
Test name
Test status
Simulation time 181371915 ps
CPU time 0.94 seconds
Started Jul 03 05:26:16 PM PDT 24
Finished Jul 03 05:26:17 PM PDT 24
Peak memory 204608 kb
Host smart-1c4d1f29-5cd3-41c8-82cb-0a2e78d29b17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245453673 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.i2c_target_fifo_reset_tx.245453673
Directory /workspace/15.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_acq.1947945287
Short name T297
Test name
Test status
Simulation time 4017166873 ps
CPU time 2.13 seconds
Started Jul 03 05:26:20 PM PDT 24
Finished Jul 03 05:26:23 PM PDT 24
Peak memory 204876 kb
Host smart-ded61b06-4e25-4b13-a137-aff68bba518b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947945287 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.i2c_target_fifo_watermarks_acq.1947945287
Directory /workspace/15.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/15.i2c_target_fifo_watermarks_tx.1633673158
Short name T850
Test name
Test status
Simulation time 675378592 ps
CPU time 1.35 seconds
Started Jul 03 05:26:24 PM PDT 24
Finished Jul 03 05:26:25 PM PDT 24
Peak memory 204612 kb
Host smart-b143b08c-9d89-46e2-820e-1b8f79bab3b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633673158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 15.i2c_target_fifo_watermarks_tx.1633673158
Directory /workspace/15.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/15.i2c_target_hrst.118731000
Short name T823
Test name
Test status
Simulation time 257483159 ps
CPU time 2.53 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:26:21 PM PDT 24
Peak memory 204716 kb
Host smart-97b7009c-9768-47d9-9b64-accaa0b3d35a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118731000 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.i2c_target_hrst.118731000
Directory /workspace/15.i2c_target_hrst/latest

Test location /workspace/coverage/default/15.i2c_target_intr_smoke.377410650
Short name T1389
Test name
Test status
Simulation time 2816168613 ps
CPU time 5.09 seconds
Started Jul 03 05:26:16 PM PDT 24
Finished Jul 03 05:26:21 PM PDT 24
Peak memory 213060 kb
Host smart-b0651fa3-9c4f-4a32-9937-44c9944fc53f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377410650 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 15.i2c_target_intr_smoke.377410650
Directory /workspace/15.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_intr_stress_wr.997069729
Short name T1289
Test name
Test status
Simulation time 4743352434 ps
CPU time 6.22 seconds
Started Jul 03 05:26:10 PM PDT 24
Finished Jul 03 05:26:16 PM PDT 24
Peak memory 204760 kb
Host smart-8afd7b6d-9f80-4edf-b595-2ce7789f93be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997069729 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.i2c_target_intr_stress_wr.997069729
Directory /workspace/15.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_smoke.4205212291
Short name T1178
Test name
Test status
Simulation time 735383161 ps
CPU time 12.09 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:26:31 PM PDT 24
Peak memory 204660 kb
Host smart-99f819a9-0a04-4b11-bb85-8db273a07d76
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205212291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_ta
rget_smoke.4205212291
Directory /workspace/15.i2c_target_smoke/latest

Test location /workspace/coverage/default/15.i2c_target_stress_rd.2281450598
Short name T414
Test name
Test status
Simulation time 714696223 ps
CPU time 11.19 seconds
Started Jul 03 05:26:22 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 209836 kb
Host smart-2c10df83-d66e-4744-8d92-c84e33d1422b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281450598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_rd.2281450598
Directory /workspace/15.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/15.i2c_target_stress_wr.1292691125
Short name T1281
Test name
Test status
Simulation time 17029653873 ps
CPU time 4.22 seconds
Started Jul 03 05:26:12 PM PDT 24
Finished Jul 03 05:26:16 PM PDT 24
Peak memory 204880 kb
Host smart-df380816-7c91-4a02-aabc-24bfc7686ce5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292691125 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2
c_target_stress_wr.1292691125
Directory /workspace/15.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/15.i2c_target_stretch.2328911525
Short name T1131
Test name
Test status
Simulation time 15669372123 ps
CPU time 896.6 seconds
Started Jul 03 05:26:16 PM PDT 24
Finished Jul 03 05:41:13 PM PDT 24
Peak memory 3938384 kb
Host smart-f8f2b195-3b77-4e5b-94d2-d701e175a639
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328911525 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.i2c_
target_stretch.2328911525
Directory /workspace/15.i2c_target_stretch/latest

Test location /workspace/coverage/default/15.i2c_target_timeout.2990185968
Short name T269
Test name
Test status
Simulation time 5526917718 ps
CPU time 8.42 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:26:27 PM PDT 24
Peak memory 221260 kb
Host smart-66f3b66a-ad5e-4ee1-a0fb-908c567a0a13
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990185968 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 15.i2c_target_timeout.2990185968
Directory /workspace/15.i2c_target_timeout/latest

Test location /workspace/coverage/default/15.i2c_target_tx_stretch_ctrl.54075677
Short name T304
Test name
Test status
Simulation time 605838021 ps
CPU time 8.03 seconds
Started Jul 03 05:26:21 PM PDT 24
Finished Jul 03 05:26:30 PM PDT 24
Peak memory 204836 kb
Host smart-bfa7cd9a-4dc4-4c89-816d-095e2c225779
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54075677 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.i2c_target_tx_stretch_ctrl.54075677
Directory /workspace/15.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/16.i2c_alert_test.1066121831
Short name T634
Test name
Test status
Simulation time 33731039 ps
CPU time 0.62 seconds
Started Jul 03 05:26:32 PM PDT 24
Finished Jul 03 05:26:33 PM PDT 24
Peak memory 204460 kb
Host smart-a91a246f-5577-4196-9da6-b5aee5741d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066121831 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_alert_test.1066121831
Directory /workspace/16.i2c_alert_test/latest

Test location /workspace/coverage/default/16.i2c_host_error_intr.1682156610
Short name T534
Test name
Test status
Simulation time 271318989 ps
CPU time 9.4 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:25 PM PDT 24
Peak memory 217408 kb
Host smart-8ba23a50-e62a-4099-95af-782cf6fa3f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682156610 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_error_intr.1682156610
Directory /workspace/16.i2c_host_error_intr/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_fmt_empty.345233127
Short name T288
Test name
Test status
Simulation time 5000252178 ps
CPU time 15.26 seconds
Started Jul 03 05:26:21 PM PDT 24
Finished Jul 03 05:26:36 PM PDT 24
Peak memory 264232 kb
Host smart-f5e9fee8-0594-4dae-8666-50f3d7f63fac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345233127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_fmt_empt
y.345233127
Directory /workspace/16.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_full.3208435533
Short name T1321
Test name
Test status
Simulation time 31772051969 ps
CPU time 127.09 seconds
Started Jul 03 05:26:26 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 587676 kb
Host smart-6956d87c-d5d3-463e-a618-d780e4b9a907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208435533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_full.3208435533
Directory /workspace/16.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_overflow.390210133
Short name T476
Test name
Test status
Simulation time 2193934087 ps
CPU time 148.74 seconds
Started Jul 03 05:26:24 PM PDT 24
Finished Jul 03 05:28:53 PM PDT 24
Peak memory 699060 kb
Host smart-1dc62e79-51ad-49a2-bd4b-63a42362e2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390210133 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_overflow.390210133
Directory /workspace/16.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_fmt.3762107644
Short name T725
Test name
Test status
Simulation time 303456153 ps
CPU time 0.84 seconds
Started Jul 03 05:26:16 PM PDT 24
Finished Jul 03 05:26:18 PM PDT 24
Peak memory 204448 kb
Host smart-9da9e0a5-f702-44fc-b048-1ad264e0c9c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762107644 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_f
mt.3762107644
Directory /workspace/16.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_reset_rx.2410963172
Short name T1274
Test name
Test status
Simulation time 152465615 ps
CPU time 3.61 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 204796 kb
Host smart-75a0218c-4a5c-43af-8a5d-6fafd893dc43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410963172 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_reset_rx
.2410963172
Directory /workspace/16.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/16.i2c_host_fifo_watermark.4076415679
Short name T1352
Test name
Test status
Simulation time 11517337238 ps
CPU time 173.25 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:29:10 PM PDT 24
Peak memory 1586600 kb
Host smart-7dd0a437-536d-481f-9333-2d94390f350d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076415679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_fifo_watermark.4076415679
Directory /workspace/16.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/16.i2c_host_mode_toggle.2266695304
Short name T1004
Test name
Test status
Simulation time 1933787192 ps
CPU time 41.54 seconds
Started Jul 03 05:26:31 PM PDT 24
Finished Jul 03 05:27:13 PM PDT 24
Peak memory 289184 kb
Host smart-cf8de71c-7b66-4dd5-b8ce-f0bd70b1d493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266695304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_mode_toggle.2266695304
Directory /workspace/16.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/16.i2c_host_perf.2057618082
Short name T32
Test name
Test status
Simulation time 7204803194 ps
CPU time 623.23 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:36:39 PM PDT 24
Peak memory 1695156 kb
Host smart-6bf0dce1-129c-476d-bda9-9c0e203199cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057618082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf.2057618082
Directory /workspace/16.i2c_host_perf/latest

Test location /workspace/coverage/default/16.i2c_host_perf_precise.1092244629
Short name T1287
Test name
Test status
Simulation time 6344011567 ps
CPU time 58.26 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:27:16 PM PDT 24
Peak memory 204832 kb
Host smart-d53fc43a-a76c-44f7-a630-1a5249fb29db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092244629 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_perf_precise.1092244629
Directory /workspace/16.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/16.i2c_host_smoke.1375410423
Short name T468
Test name
Test status
Simulation time 1309995122 ps
CPU time 26.18 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 362664 kb
Host smart-d6c408fb-84be-4599-9b78-ad298af13a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375410423 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_smoke.1375410423
Directory /workspace/16.i2c_host_smoke/latest

Test location /workspace/coverage/default/16.i2c_host_stress_all.2897210754
Short name T51
Test name
Test status
Simulation time 26125163413 ps
CPU time 674.18 seconds
Started Jul 03 05:26:14 PM PDT 24
Finished Jul 03 05:37:29 PM PDT 24
Peak memory 1528152 kb
Host smart-6ecdf845-f67e-41e4-b941-922c7cec6979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897210754 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stress_all.2897210754
Directory /workspace/16.i2c_host_stress_all/latest

Test location /workspace/coverage/default/16.i2c_host_stretch_timeout.304888930
Short name T1045
Test name
Test status
Simulation time 1002385973 ps
CPU time 41.37 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 212928 kb
Host smart-b2f9b608-147f-47d5-9893-083e4f64525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304888930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_host_stretch_timeout.304888930
Directory /workspace/16.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_bad_addr.1410989623
Short name T516
Test name
Test status
Simulation time 631478145 ps
CPU time 3.45 seconds
Started Jul 03 05:26:16 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 204800 kb
Host smart-bd63bb2b-25fc-4db2-bc66-24634cd69a7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410989623 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.i2c_target_bad_addr.1410989623
Directory /workspace/16.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_acq.2647113606
Short name T1147
Test name
Test status
Simulation time 189385972 ps
CPU time 1.28 seconds
Started Jul 03 05:26:30 PM PDT 24
Finished Jul 03 05:26:32 PM PDT 24
Peak memory 204668 kb
Host smart-e91e0763-3007-4b9d-aed9-8cb40c82fd22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647113606 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_fifo_reset_acq.2647113606
Directory /workspace/16.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_reset_tx.4121480660
Short name T973
Test name
Test status
Simulation time 182532411 ps
CPU time 1.14 seconds
Started Jul 03 05:26:26 PM PDT 24
Finished Jul 03 05:26:27 PM PDT 24
Peak memory 204812 kb
Host smart-0581a2f1-e04f-46b3-84c8-4a46e7981a60
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121480660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.i2c_target_fifo_reset_tx.4121480660
Directory /workspace/16.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_acq.1668408654
Short name T1368
Test name
Test status
Simulation time 2702530448 ps
CPU time 2.86 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 204904 kb
Host smart-33f431e5-817f-4c9b-a716-205f520fc0e5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668408654 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.i2c_target_fifo_watermarks_acq.1668408654
Directory /workspace/16.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/16.i2c_target_fifo_watermarks_tx.3116349956
Short name T840
Test name
Test status
Simulation time 173367705 ps
CPU time 1.05 seconds
Started Jul 03 05:26:24 PM PDT 24
Finished Jul 03 05:26:25 PM PDT 24
Peak memory 204616 kb
Host smart-b9084c92-c57e-4cc7-9be7-61c8e9d9e18b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116349956 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.i2c_target_fifo_watermarks_tx.3116349956
Directory /workspace/16.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/16.i2c_target_hrst.3918677339
Short name T650
Test name
Test status
Simulation time 760861212 ps
CPU time 2.81 seconds
Started Jul 03 05:26:19 PM PDT 24
Finished Jul 03 05:26:22 PM PDT 24
Peak memory 204816 kb
Host smart-e1d7689e-788e-4a7a-8f72-d72440374bcf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918677339 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 16.i2c_target_hrst.3918677339
Directory /workspace/16.i2c_target_hrst/latest

Test location /workspace/coverage/default/16.i2c_target_intr_smoke.2722292446
Short name T119
Test name
Test status
Simulation time 1023072580 ps
CPU time 5.24 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:23 PM PDT 24
Peak memory 213080 kb
Host smart-f54f644d-0e78-4936-9e88-022ca82a0975
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722292446 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 16.i2c_target_intr_smoke.2722292446
Directory /workspace/16.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_intr_stress_wr.32824751
Short name T1225
Test name
Test status
Simulation time 18938720936 ps
CPU time 9.12 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:26:46 PM PDT 24
Peak memory 242552 kb
Host smart-504bf1a7-9a04-4041-8712-1269970ac003
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824751 -assert nopostproc +UVM_TESTN
AME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.i2c_target_intr_stress_wr.32824751
Directory /workspace/16.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_smoke.254423882
Short name T1214
Test name
Test status
Simulation time 6492660437 ps
CPU time 22.56 seconds
Started Jul 03 05:26:24 PM PDT 24
Finished Jul 03 05:26:47 PM PDT 24
Peak memory 204912 kb
Host smart-93a8d32b-d037-4310-b7c4-0dcd7a3bf7d3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254423882 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_tar
get_smoke.254423882
Directory /workspace/16.i2c_target_smoke/latest

Test location /workspace/coverage/default/16.i2c_target_stress_rd.1824526940
Short name T970
Test name
Test status
Simulation time 5057040123 ps
CPU time 57.73 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 05:27:13 PM PDT 24
Peak memory 208000 kb
Host smart-3741de27-3fa7-467c-8da2-7ded79c05cd4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824526940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_rd.1824526940
Directory /workspace/16.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/16.i2c_target_stress_wr.1814380260
Short name T815
Test name
Test status
Simulation time 65943973559 ps
CPU time 2599.03 seconds
Started Jul 03 05:26:15 PM PDT 24
Finished Jul 03 06:09:35 PM PDT 24
Peak memory 11402524 kb
Host smart-36afbe4d-ba19-47d2-b0ba-3ef45db3b4fb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814380260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2
c_target_stress_wr.1814380260
Directory /workspace/16.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/16.i2c_target_stretch.3769190089
Short name T1048
Test name
Test status
Simulation time 3979946271 ps
CPU time 34.68 seconds
Started Jul 03 05:26:19 PM PDT 24
Finished Jul 03 05:26:54 PM PDT 24
Peak memory 343768 kb
Host smart-e2a28607-dd1a-4207-96e5-a29984d5c008
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769190089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.i2c_
target_stretch.3769190089
Directory /workspace/16.i2c_target_stretch/latest

Test location /workspace/coverage/default/16.i2c_target_timeout.2425009784
Short name T1474
Test name
Test status
Simulation time 3307526292 ps
CPU time 8.69 seconds
Started Jul 03 05:26:22 PM PDT 24
Finished Jul 03 05:26:31 PM PDT 24
Peak memory 221172 kb
Host smart-4a9fc2aa-360c-4933-b8bc-e1712f824697
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425009784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.i2c_target_timeout.2425009784
Directory /workspace/16.i2c_target_timeout/latest

Test location /workspace/coverage/default/16.i2c_target_tx_stretch_ctrl.2893784141
Short name T641
Test name
Test status
Simulation time 184117821 ps
CPU time 3.4 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:37 PM PDT 24
Peak memory 204840 kb
Host smart-e55cf7f3-edcd-4c7b-a402-b8aaa1d90c29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893784141 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.i2c_target_tx_stretch_ctrl.2893784141
Directory /workspace/16.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/17.i2c_alert_test.2827067065
Short name T343
Test name
Test status
Simulation time 40135298 ps
CPU time 0.62 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:36 PM PDT 24
Peak memory 204440 kb
Host smart-0f99a174-5ae8-493a-845c-a8a53d72e9a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827067065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_alert_test.2827067065
Directory /workspace/17.i2c_alert_test/latest

Test location /workspace/coverage/default/17.i2c_host_error_intr.2042944885
Short name T986
Test name
Test status
Simulation time 290390381 ps
CPU time 1.55 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 216852 kb
Host smart-3c3a74bd-7c9d-4932-aaad-a368676d49e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042944885 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_error_intr.2042944885
Directory /workspace/17.i2c_host_error_intr/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_fmt_empty.119558108
Short name T1355
Test name
Test status
Simulation time 3508217981 ps
CPU time 16.6 seconds
Started Jul 03 05:26:30 PM PDT 24
Finished Jul 03 05:26:47 PM PDT 24
Peak memory 253064 kb
Host smart-3953797a-a0ba-471a-bdc2-7d1588e03ae2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119558108 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_fmt_empt
y.119558108
Directory /workspace/17.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_full.3185247990
Short name T878
Test name
Test status
Simulation time 4269730122 ps
CPU time 125.09 seconds
Started Jul 03 05:26:27 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 653148 kb
Host smart-c4abc062-9f3a-404d-9c76-0ddc6e9b73be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185247990 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_full.3185247990
Directory /workspace/17.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_overflow.3300391542
Short name T1192
Test name
Test status
Simulation time 11052818344 ps
CPU time 176.22 seconds
Started Jul 03 05:26:36 PM PDT 24
Finished Jul 03 05:29:34 PM PDT 24
Peak memory 782980 kb
Host smart-7bbf9f94-2109-483d-a71b-19ac817dd04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300391542 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_overflow.3300391542
Directory /workspace/17.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_fmt.1401824430
Short name T1241
Test name
Test status
Simulation time 500180656 ps
CPU time 1.06 seconds
Started Jul 03 05:26:29 PM PDT 24
Finished Jul 03 05:26:31 PM PDT 24
Peak memory 204428 kb
Host smart-07ae116b-8b0e-4780-b96a-0da5f9c2ed1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401824430 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_f
mt.1401824430
Directory /workspace/17.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_reset_rx.4127244319
Short name T987
Test name
Test status
Simulation time 824720920 ps
CPU time 4.52 seconds
Started Jul 03 05:26:19 PM PDT 24
Finished Jul 03 05:26:24 PM PDT 24
Peak memory 204812 kb
Host smart-8ca2611d-7dd9-4801-b113-da73a865fa85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127244319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_reset_rx
.4127244319
Directory /workspace/17.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/17.i2c_host_fifo_watermark.237463021
Short name T48
Test name
Test status
Simulation time 15974016141 ps
CPU time 151.1 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:29:04 PM PDT 24
Peak memory 1380572 kb
Host smart-a7737a09-2ca4-490f-aa2d-f5a17df25569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237463021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_fifo_watermark.237463021
Directory /workspace/17.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/17.i2c_host_may_nack.1555974700
Short name T1290
Test name
Test status
Simulation time 1098844540 ps
CPU time 11.24 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:44 PM PDT 24
Peak memory 204820 kb
Host smart-df1cb2c9-2057-4cbd-814e-ceae27a73113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555974700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_may_nack.1555974700
Directory /workspace/17.i2c_host_may_nack/latest

Test location /workspace/coverage/default/17.i2c_host_mode_toggle.2567030001
Short name T1265
Test name
Test status
Simulation time 1443433586 ps
CPU time 68.35 seconds
Started Jul 03 05:26:28 PM PDT 24
Finished Jul 03 05:27:36 PM PDT 24
Peak memory 354600 kb
Host smart-85ffa4e9-f1fe-4422-9e3e-de0ab6ca0564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567030001 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_mode_toggle.2567030001
Directory /workspace/17.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/17.i2c_host_override.1209769799
Short name T1415
Test name
Test status
Simulation time 45669980 ps
CPU time 0.66 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 204472 kb
Host smart-12a41e1e-4be6-4c06-bb20-6b87795bbb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209769799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_override.1209769799
Directory /workspace/17.i2c_host_override/latest

Test location /workspace/coverage/default/17.i2c_host_perf.852990477
Short name T1269
Test name
Test status
Simulation time 29510159690 ps
CPU time 308.13 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:31:26 PM PDT 24
Peak memory 684568 kb
Host smart-46b6def9-73e6-4bb4-9ae5-13bcb37ac858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852990477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf.852990477
Directory /workspace/17.i2c_host_perf/latest

Test location /workspace/coverage/default/17.i2c_host_perf_precise.3592180677
Short name T724
Test name
Test status
Simulation time 236392641 ps
CPU time 3.07 seconds
Started Jul 03 05:26:19 PM PDT 24
Finished Jul 03 05:26:23 PM PDT 24
Peak memory 204648 kb
Host smart-af464159-6fab-4d76-a8cf-c0dde9a79bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592180677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_perf_precise.3592180677
Directory /workspace/17.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/17.i2c_host_smoke.3903133865
Short name T1090
Test name
Test status
Simulation time 15211158683 ps
CPU time 29.86 seconds
Started Jul 03 05:26:25 PM PDT 24
Finished Jul 03 05:26:55 PM PDT 24
Peak memory 328760 kb
Host smart-2d4673bc-eaee-4e8d-b7c4-2d6f27f88b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903133865 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_smoke.3903133865
Directory /workspace/17.i2c_host_smoke/latest

Test location /workspace/coverage/default/17.i2c_host_stretch_timeout.2484062565
Short name T1323
Test name
Test status
Simulation time 651654836 ps
CPU time 28.89 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:27:04 PM PDT 24
Peak memory 213060 kb
Host smart-a0d9f378-048b-46ad-8e3a-9331850c7377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484062565 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_host_stretch_timeout.2484062565
Directory /workspace/17.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_bad_addr.3090796121
Short name T1060
Test name
Test status
Simulation time 4529731541 ps
CPU time 5.97 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:41 PM PDT 24
Peak memory 216504 kb
Host smart-beeff1b0-ae02-4910-93e7-12fbe1e95ae6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090796121 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.i2c_target_bad_addr.3090796121
Directory /workspace/17.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_acq.2587590082
Short name T562
Test name
Test status
Simulation time 227892325 ps
CPU time 1.37 seconds
Started Jul 03 05:26:18 PM PDT 24
Finished Jul 03 05:26:20 PM PDT 24
Peak memory 204876 kb
Host smart-49c91f83-8404-4c32-9a36-4fd857f7b7c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587590082 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_fifo_reset_acq.2587590082
Directory /workspace/17.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_reset_tx.408878670
Short name T82
Test name
Test status
Simulation time 585334081 ps
CPU time 1.31 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 204808 kb
Host smart-d8058e8c-d422-4aeb-918a-1ef908671bb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408878670 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.i2c_target_fifo_reset_tx.408878670
Directory /workspace/17.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_acq.2243954175
Short name T778
Test name
Test status
Simulation time 2702428998 ps
CPU time 2.63 seconds
Started Jul 03 05:26:31 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 204888 kb
Host smart-12b02f40-45ff-4981-b75c-242c5cafe39c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243954175 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.i2c_target_fifo_watermarks_acq.2243954175
Directory /workspace/17.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/17.i2c_target_fifo_watermarks_tx.4139004783
Short name T1487
Test name
Test status
Simulation time 103973436 ps
CPU time 0.88 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 204608 kb
Host smart-2ada4906-9601-492b-97c0-47706722e605
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139004783 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 17.i2c_target_fifo_watermarks_tx.4139004783
Directory /workspace/17.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/17.i2c_target_hrst.829385166
Short name T479
Test name
Test status
Simulation time 2468459230 ps
CPU time 2.16 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:38 PM PDT 24
Peak memory 204920 kb
Host smart-3ee8ce38-2547-4bbe-b46a-6f30b74c7151
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829385166 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.i2c_target_hrst.829385166
Directory /workspace/17.i2c_target_hrst/latest

Test location /workspace/coverage/default/17.i2c_target_intr_smoke.2071690395
Short name T798
Test name
Test status
Simulation time 1063204942 ps
CPU time 5.5 seconds
Started Jul 03 05:26:20 PM PDT 24
Finished Jul 03 05:26:26 PM PDT 24
Peak memory 210788 kb
Host smart-4027dd7b-b297-474d-8373-b3c7d2df6b3c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071690395 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 17.i2c_target_intr_smoke.2071690395
Directory /workspace/17.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_intr_stress_wr.2762147284
Short name T1328
Test name
Test status
Simulation time 13975073689 ps
CPU time 20.21 seconds
Started Jul 03 05:26:19 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 480000 kb
Host smart-662da5b9-e6dd-4cb2-be0e-f922a47d932f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762147284 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.i2c_target_intr_stress_wr.2762147284
Directory /workspace/17.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_smoke.3218290832
Short name T644
Test name
Test status
Simulation time 564044775 ps
CPU time 15.09 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:26:33 PM PDT 24
Peak memory 204788 kb
Host smart-1fc3a493-ba49-462a-9ceb-1655d290e4ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218290832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_ta
rget_smoke.3218290832
Directory /workspace/17.i2c_target_smoke/latest

Test location /workspace/coverage/default/17.i2c_target_stress_rd.2926037948
Short name T308
Test name
Test status
Simulation time 4719376398 ps
CPU time 21.62 seconds
Started Jul 03 05:26:29 PM PDT 24
Finished Jul 03 05:26:51 PM PDT 24
Peak memory 216360 kb
Host smart-41c64d71-5927-46a8-b355-4ce41d4229f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926037948 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_rd.2926037948
Directory /workspace/17.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/17.i2c_target_stress_wr.4235634207
Short name T884
Test name
Test status
Simulation time 53306060218 ps
CPU time 210.24 seconds
Started Jul 03 05:26:17 PM PDT 24
Finished Jul 03 05:29:48 PM PDT 24
Peak memory 2499004 kb
Host smart-31f5332b-f7c4-4c53-bd42-28281e254c24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235634207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2
c_target_stress_wr.4235634207
Directory /workspace/17.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/17.i2c_target_stretch.1751393513
Short name T1348
Test name
Test status
Simulation time 29221527043 ps
CPU time 1909.69 seconds
Started Jul 03 05:26:28 PM PDT 24
Finished Jul 03 05:58:19 PM PDT 24
Peak memory 6916436 kb
Host smart-4294e9d7-c5c6-44b3-91bb-0b66f6b3d4bf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751393513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.i2c_
target_stretch.1751393513
Directory /workspace/17.i2c_target_stretch/latest

Test location /workspace/coverage/default/17.i2c_target_timeout.1197601128
Short name T1411
Test name
Test status
Simulation time 11646677257 ps
CPU time 6.69 seconds
Started Jul 03 05:26:27 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 204976 kb
Host smart-bcc3ec96-c0dc-4f1f-baec-c082875549a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197601128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.i2c_target_timeout.1197601128
Directory /workspace/17.i2c_target_timeout/latest

Test location /workspace/coverage/default/17.i2c_target_tx_stretch_ctrl.2300032591
Short name T1142
Test name
Test status
Simulation time 471412592 ps
CPU time 6.71 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 204812 kb
Host smart-881a08ff-9ed7-417b-9fc1-e11ca2de1542
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300032591 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.i2c_target_tx_stretch_ctrl.2300032591
Directory /workspace/17.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/18.i2c_alert_test.3356293805
Short name T1501
Test name
Test status
Simulation time 18168406 ps
CPU time 0.64 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:39 PM PDT 24
Peak memory 204480 kb
Host smart-ed8644c8-6cca-41bb-8856-b31fd90e2ccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356293805 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_alert_test.3356293805
Directory /workspace/18.i2c_alert_test/latest

Test location /workspace/coverage/default/18.i2c_host_error_intr.3296917570
Short name T922
Test name
Test status
Simulation time 109462477 ps
CPU time 2.96 seconds
Started Jul 03 05:26:25 PM PDT 24
Finished Jul 03 05:26:29 PM PDT 24
Peak memory 213068 kb
Host smart-16486912-5e39-40ed-8ef7-3e1cf46d55a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296917570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_error_intr.3296917570
Directory /workspace/18.i2c_host_error_intr/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_fmt_empty.954854797
Short name T533
Test name
Test status
Simulation time 766739207 ps
CPU time 9.27 seconds
Started Jul 03 05:26:36 PM PDT 24
Finished Jul 03 05:26:46 PM PDT 24
Peak memory 291428 kb
Host smart-4737a629-e987-4295-a4c1-ad9f6ecf1b8e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954854797 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_fmt_empt
y.954854797
Directory /workspace/18.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_full.2456393969
Short name T690
Test name
Test status
Simulation time 2486702799 ps
CPU time 172.2 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:29:30 PM PDT 24
Peak memory 737680 kb
Host smart-20a5d91d-50b4-4b10-a236-aa448926befc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456393969 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_full.2456393969
Directory /workspace/18.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_overflow.2711375736
Short name T1428
Test name
Test status
Simulation time 1437414248 ps
CPU time 74.85 seconds
Started Jul 03 05:26:25 PM PDT 24
Finished Jul 03 05:27:41 PM PDT 24
Peak memory 438576 kb
Host smart-f6de007f-b73f-4ca1-b5be-a89ab2b3cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711375736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_overflow.2711375736
Directory /workspace/18.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_fmt.2381828621
Short name T493
Test name
Test status
Simulation time 1921444537 ps
CPU time 1.17 seconds
Started Jul 03 05:26:36 PM PDT 24
Finished Jul 03 05:26:38 PM PDT 24
Peak memory 204684 kb
Host smart-8d10dde5-ffa3-4020-b5f2-c5b7a181ad6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381828621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_f
mt.2381828621
Directory /workspace/18.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_reset_rx.3416421332
Short name T157
Test name
Test status
Simulation time 138759156 ps
CPU time 3.42 seconds
Started Jul 03 05:26:30 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 204812 kb
Host smart-272400df-2f7f-47b5-8626-65a3bb09dce7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416421332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_reset_rx
.3416421332
Directory /workspace/18.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/18.i2c_host_fifo_watermark.1067711465
Short name T817
Test name
Test status
Simulation time 18783159931 ps
CPU time 203.07 seconds
Started Jul 03 05:26:26 PM PDT 24
Finished Jul 03 05:29:50 PM PDT 24
Peak memory 886320 kb
Host smart-47a07bdb-d99f-423e-b6e0-ed0b08f286c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067711465 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_fifo_watermark.1067711465
Directory /workspace/18.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/18.i2c_host_may_nack.3619918589
Short name T1256
Test name
Test status
Simulation time 385023459 ps
CPU time 5.82 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:41 PM PDT 24
Peak memory 204784 kb
Host smart-e2e62834-75b3-48b3-b846-c57d1a4d1a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619918589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_may_nack.3619918589
Directory /workspace/18.i2c_host_may_nack/latest

Test location /workspace/coverage/default/18.i2c_host_mode_toggle.485865051
Short name T849
Test name
Test status
Simulation time 6715243241 ps
CPU time 22.07 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 285300 kb
Host smart-b33bfde9-6d96-4410-89d0-a594d16b0644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485865051 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_mode_toggle.485865051
Directory /workspace/18.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/18.i2c_host_override.4202524917
Short name T1450
Test name
Test status
Simulation time 22988639 ps
CPU time 0.62 seconds
Started Jul 03 05:26:28 PM PDT 24
Finished Jul 03 05:26:29 PM PDT 24
Peak memory 204508 kb
Host smart-532d2fac-3b28-467d-91da-f3289a4fab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202524917 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_override.4202524917
Directory /workspace/18.i2c_host_override/latest

Test location /workspace/coverage/default/18.i2c_host_perf.863119940
Short name T1093
Test name
Test status
Simulation time 7558670650 ps
CPU time 46.17 seconds
Started Jul 03 05:26:31 PM PDT 24
Finished Jul 03 05:27:18 PM PDT 24
Peak memory 602624 kb
Host smart-01913a9e-5ed8-400c-a1db-1a82538e00a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863119940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf.863119940
Directory /workspace/18.i2c_host_perf/latest

Test location /workspace/coverage/default/18.i2c_host_perf_precise.994613828
Short name T434
Test name
Test status
Simulation time 72537903 ps
CPU time 1.65 seconds
Started Jul 03 05:26:36 PM PDT 24
Finished Jul 03 05:26:39 PM PDT 24
Peak memory 204712 kb
Host smart-83f21601-e132-43db-8ffb-8f0aecd7aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994613828 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_perf_precise.994613828
Directory /workspace/18.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/18.i2c_host_smoke.2791467537
Short name T851
Test name
Test status
Simulation time 13441525182 ps
CPU time 70.19 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:27:47 PM PDT 24
Peak memory 379252 kb
Host smart-07ee4700-9aad-4581-a4f6-56c1cd8bed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791467537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_smoke.2791467537
Directory /workspace/18.i2c_host_smoke/latest

Test location /workspace/coverage/default/18.i2c_host_stress_all.1295673213
Short name T1266
Test name
Test status
Simulation time 235098810356 ps
CPU time 682.1 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:37:56 PM PDT 24
Peak memory 2635584 kb
Host smart-c3c9f209-f14b-4428-9e42-fd0eb852f0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295673213 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stress_all.1295673213
Directory /workspace/18.i2c_host_stress_all/latest

Test location /workspace/coverage/default/18.i2c_host_stretch_timeout.3119383578
Short name T1073
Test name
Test status
Simulation time 806123569 ps
CPU time 14.92 seconds
Started Jul 03 05:26:36 PM PDT 24
Finished Jul 03 05:26:52 PM PDT 24
Peak memory 215528 kb
Host smart-6d57fcfd-d5bf-49ec-94b1-0575ea1d3b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119383578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_host_stretch_timeout.3119383578
Directory /workspace/18.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_bad_addr.596439846
Short name T1446
Test name
Test status
Simulation time 860327987 ps
CPU time 4.67 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 213176 kb
Host smart-a731cca8-1b25-4470-bcd3-8f8fd6bef2a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596439846 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 18.i2c_target_bad_addr.596439846
Directory /workspace/18.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_reset_tx.3340807343
Short name T342
Test name
Test status
Simulation time 511272998 ps
CPU time 1.06 seconds
Started Jul 03 05:26:31 PM PDT 24
Finished Jul 03 05:26:32 PM PDT 24
Peak memory 204640 kb
Host smart-020689ae-a011-44cd-9f31-51e5a76cd672
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340807343 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.i2c_target_fifo_reset_tx.3340807343
Directory /workspace/18.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_acq.3377770022
Short name T256
Test name
Test status
Simulation time 943848662 ps
CPU time 2.76 seconds
Started Jul 03 05:26:43 PM PDT 24
Finished Jul 03 05:26:46 PM PDT 24
Peak memory 204820 kb
Host smart-eb50022d-3e58-4410-ad32-8b4511b8189d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377770022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.i2c_target_fifo_watermarks_acq.3377770022
Directory /workspace/18.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/18.i2c_target_fifo_watermarks_tx.1763178649
Short name T924
Test name
Test status
Simulation time 999190688 ps
CPU time 1.14 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:37 PM PDT 24
Peak memory 204584 kb
Host smart-92df0a3e-6aea-4de2-9460-4b6abd9794db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763178649 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 18.i2c_target_fifo_watermarks_tx.1763178649
Directory /workspace/18.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/18.i2c_target_hrst.2981916389
Short name T1237
Test name
Test status
Simulation time 518089593 ps
CPU time 3.23 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:37 PM PDT 24
Peak memory 204376 kb
Host smart-9fd4dbd8-503d-4cd5-90dd-b602004e8150
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981916389 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_hrst.2981916389
Directory /workspace/18.i2c_target_hrst/latest

Test location /workspace/coverage/default/18.i2c_target_intr_smoke.39259491
Short name T1329
Test name
Test status
Simulation time 3682105305 ps
CPU time 5.48 seconds
Started Jul 03 05:26:42 PM PDT 24
Finished Jul 03 05:26:48 PM PDT 24
Peak memory 204868 kb
Host smart-35d9d568-cbfe-4a11-b05f-853164941a28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39259491 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 18.i2c_target_intr_smoke.39259491
Directory /workspace/18.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_intr_stress_wr.2439259903
Short name T702
Test name
Test status
Simulation time 8367026610 ps
CPU time 6.44 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:41 PM PDT 24
Peak memory 204984 kb
Host smart-aed8a905-fb3e-4724-a0d9-adf2956f9002
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439259903 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.i2c_target_intr_stress_wr.2439259903
Directory /workspace/18.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_smoke.3047922267
Short name T1163
Test name
Test status
Simulation time 4342473471 ps
CPU time 41.42 seconds
Started Jul 03 05:26:27 PM PDT 24
Finished Jul 03 05:27:11 PM PDT 24
Peak memory 204924 kb
Host smart-a275b44d-ad7a-4c33-9d2e-b3eb5e9e4f28
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047922267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_ta
rget_smoke.3047922267
Directory /workspace/18.i2c_target_smoke/latest

Test location /workspace/coverage/default/18.i2c_target_stress_rd.712694662
Short name T350
Test name
Test status
Simulation time 863594240 ps
CPU time 14.79 seconds
Started Jul 03 05:26:32 PM PDT 24
Finished Jul 03 05:26:47 PM PDT 24
Peak memory 215232 kb
Host smart-979610d7-a281-42cf-9f54-88931f20f4ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712694662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c
_target_stress_rd.712694662
Directory /workspace/18.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/18.i2c_target_stress_wr.1829023388
Short name T888
Test name
Test status
Simulation time 24822402716 ps
CPU time 6.24 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 204788 kb
Host smart-47d3f583-3904-45fa-a5d5-d02ded023407
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829023388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2
c_target_stress_wr.1829023388
Directory /workspace/18.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/18.i2c_target_stretch.1097745590
Short name T1202
Test name
Test status
Simulation time 14784598237 ps
CPU time 1473.71 seconds
Started Jul 03 05:26:30 PM PDT 24
Finished Jul 03 05:51:04 PM PDT 24
Peak memory 3042864 kb
Host smart-8cae9bcd-091c-46fc-8052-6e6b660b6e4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097745590 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.i2c_
target_stretch.1097745590
Directory /workspace/18.i2c_target_stretch/latest

Test location /workspace/coverage/default/18.i2c_target_timeout.4011534478
Short name T1317
Test name
Test status
Simulation time 10753455802 ps
CPU time 6.66 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:47 PM PDT 24
Peak memory 216196 kb
Host smart-972cbb04-dae3-415e-97df-7f6f263b127f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011534478 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.i2c_target_timeout.4011534478
Directory /workspace/18.i2c_target_timeout/latest

Test location /workspace/coverage/default/18.i2c_target_tx_stretch_ctrl.2462114422
Short name T944
Test name
Test status
Simulation time 87993221 ps
CPU time 1.93 seconds
Started Jul 03 05:26:31 PM PDT 24
Finished Jul 03 05:26:33 PM PDT 24
Peak memory 204840 kb
Host smart-013afdac-c410-4ac2-9768-fd2ee98dfe18
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462114422 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.i2c_target_tx_stretch_ctrl.2462114422
Directory /workspace/18.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/19.i2c_alert_test.3312621351
Short name T370
Test name
Test status
Simulation time 18266444 ps
CPU time 0.68 seconds
Started Jul 03 05:26:41 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 204508 kb
Host smart-5efa3877-9c2a-4afd-a679-1e39a730e7f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312621351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_alert_test.3312621351
Directory /workspace/19.i2c_alert_test/latest

Test location /workspace/coverage/default/19.i2c_host_error_intr.787762419
Short name T543
Test name
Test status
Simulation time 173201866 ps
CPU time 1.38 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:39 PM PDT 24
Peak memory 213088 kb
Host smart-87bd72d0-3d11-4dfc-a710-146ecb8c828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787762419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_error_intr.787762419
Directory /workspace/19.i2c_host_error_intr/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_fmt_empty.1652365063
Short name T375
Test name
Test status
Simulation time 347983748 ps
CPU time 8.1 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:26:44 PM PDT 24
Peak memory 281244 kb
Host smart-255c8d35-4db8-410c-96df-77422bc21e91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652365063 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_fmt_emp
ty.1652365063
Directory /workspace/19.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_full.1531728667
Short name T1377
Test name
Test status
Simulation time 8380044698 ps
CPU time 136.26 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:28:50 PM PDT 24
Peak memory 688372 kb
Host smart-1e20cfc3-bc61-40cb-8051-1af1f07bd27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531728667 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_full.1531728667
Directory /workspace/19.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_overflow.2761649409
Short name T1479
Test name
Test status
Simulation time 1982688665 ps
CPU time 139.13 seconds
Started Jul 03 05:26:41 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 678016 kb
Host smart-ff4f8b56-6c2e-4d9c-9d2f-dc7889df7522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761649409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_overflow.2761649409
Directory /workspace/19.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_fmt.1807119091
Short name T238
Test name
Test status
Simulation time 424497237 ps
CPU time 0.97 seconds
Started Jul 03 05:26:36 PM PDT 24
Finished Jul 03 05:26:38 PM PDT 24
Peak memory 204508 kb
Host smart-ae88f113-9df5-49c7-a648-35398cedc9be
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807119091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_f
mt.1807119091
Directory /workspace/19.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/19.i2c_host_fifo_reset_rx.191014193
Short name T976
Test name
Test status
Simulation time 411991611 ps
CPU time 5.09 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:39 PM PDT 24
Peak memory 243464 kb
Host smart-570cb4fd-7f80-4173-baea-4bb82491c16a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191014193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_fifo_reset_rx.
191014193
Directory /workspace/19.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/19.i2c_host_may_nack.416234946
Short name T39
Test name
Test status
Simulation time 674767454 ps
CPU time 27.19 seconds
Started Jul 03 05:26:32 PM PDT 24
Finished Jul 03 05:27:05 PM PDT 24
Peak memory 204828 kb
Host smart-09a234d6-1400-44a7-aba6-c0f8a3cf1323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416234946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_may_nack.416234946
Directory /workspace/19.i2c_host_may_nack/latest

Test location /workspace/coverage/default/19.i2c_host_mode_toggle.1564516707
Short name T35
Test name
Test status
Simulation time 6507002466 ps
CPU time 33.18 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:27:09 PM PDT 24
Peak memory 405536 kb
Host smart-9aeea602-e2c8-4e5a-9159-946f463cc047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564516707 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_mode_toggle.1564516707
Directory /workspace/19.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/19.i2c_host_override.227912295
Short name T137
Test name
Test status
Simulation time 55334600 ps
CPU time 0.66 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:35 PM PDT 24
Peak memory 204508 kb
Host smart-7568bfd8-90dc-4ebd-8e11-246d15f8f808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227912295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_override.227912295
Directory /workspace/19.i2c_host_override/latest

Test location /workspace/coverage/default/19.i2c_host_perf.639739543
Short name T1365
Test name
Test status
Simulation time 7601812017 ps
CPU time 50.2 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 668448 kb
Host smart-2da487fa-b091-4b7c-a266-7928f76cc880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639739543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf.639739543
Directory /workspace/19.i2c_host_perf/latest

Test location /workspace/coverage/default/19.i2c_host_perf_precise.2833684231
Short name T1171
Test name
Test status
Simulation time 5829906472 ps
CPU time 233.36 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:30:30 PM PDT 24
Peak memory 204792 kb
Host smart-cfd221f8-de4c-4054-8508-813d3e80fb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833684231 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_perf_precise.2833684231
Directory /workspace/19.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/19.i2c_host_smoke.2495310086
Short name T1500
Test name
Test status
Simulation time 2036065995 ps
CPU time 32.23 seconds
Started Jul 03 05:26:40 PM PDT 24
Finished Jul 03 05:27:12 PM PDT 24
Peak memory 371528 kb
Host smart-81cf29f0-e4b4-401b-8a39-5fc1bd1f908a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495310086 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_smoke.2495310086
Directory /workspace/19.i2c_host_smoke/latest

Test location /workspace/coverage/default/19.i2c_host_stretch_timeout.3380157014
Short name T841
Test name
Test status
Simulation time 640624285 ps
CPU time 10.09 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:26:49 PM PDT 24
Peak memory 215780 kb
Host smart-bd3b0ce0-7187-48f7-babb-1367c728987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380157014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_host_stretch_timeout.3380157014
Directory /workspace/19.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_bad_addr.1722684684
Short name T1485
Test name
Test status
Simulation time 2241419186 ps
CPU time 4.6 seconds
Started Jul 03 05:26:36 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 213092 kb
Host smart-4fc84f0c-9f82-4ccc-bddb-5aba18270f8b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722684684 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 19.i2c_target_bad_addr.1722684684
Directory /workspace/19.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_acq.376254288
Short name T602
Test name
Test status
Simulation time 532948139 ps
CPU time 1.25 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:39 PM PDT 24
Peak memory 204860 kb
Host smart-4796e266-c79e-467e-8394-83f6f7b67ad9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376254288 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_acq.376254288
Directory /workspace/19.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_reset_tx.4197335309
Short name T853
Test name
Test status
Simulation time 175146821 ps
CPU time 0.86 seconds
Started Jul 03 05:26:36 PM PDT 24
Finished Jul 03 05:26:38 PM PDT 24
Peak memory 204604 kb
Host smart-44b40167-5684-4e59-8495-e1c1cea022c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197335309 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.i2c_target_fifo_reset_tx.4197335309
Directory /workspace/19.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_acq.637189929
Short name T1126
Test name
Test status
Simulation time 2978672527 ps
CPU time 2.84 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:41 PM PDT 24
Peak memory 204876 kb
Host smart-20d08428-f938-48c0-aa66-94abbc299fe8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637189929 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.i2c_target_fifo_watermarks_acq.637189929
Directory /workspace/19.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/19.i2c_target_fifo_watermarks_tx.898952631
Short name T1205
Test name
Test status
Simulation time 555341897 ps
CPU time 1.34 seconds
Started Jul 03 05:26:32 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 204584 kb
Host smart-a75ea0e0-ceeb-409c-8833-f880d75a86af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898952631 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.i2c_target_fifo_watermarks_tx.898952631
Directory /workspace/19.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/19.i2c_target_intr_smoke.682059191
Short name T1100
Test name
Test status
Simulation time 1083246796 ps
CPU time 3.17 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:41 PM PDT 24
Peak memory 204836 kb
Host smart-b9836e58-94d8-42c1-91d4-60a7ffe12976
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682059191 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 19.i2c_target_intr_smoke.682059191
Directory /workspace/19.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_intr_stress_wr.3971256382
Short name T982
Test name
Test status
Simulation time 18278922293 ps
CPU time 40.94 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 759336 kb
Host smart-e682a3c3-5908-4ffd-b425-81461bff31d6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971256382 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.i2c_target_intr_stress_wr.3971256382
Directory /workspace/19.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_smoke.4114449115
Short name T1151
Test name
Test status
Simulation time 1881927145 ps
CPU time 14.3 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:26:50 PM PDT 24
Peak memory 204688 kb
Host smart-4e793693-3e61-499b-9fe8-029854390538
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114449115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_ta
rget_smoke.4114449115
Directory /workspace/19.i2c_target_smoke/latest

Test location /workspace/coverage/default/19.i2c_target_stress_rd.440784775
Short name T1491
Test name
Test status
Simulation time 822236849 ps
CPU time 4.33 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 204784 kb
Host smart-476d60e0-a9c0-48bd-9844-60dc144ed1c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440784775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c
_target_stress_rd.440784775
Directory /workspace/19.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/19.i2c_target_stress_wr.3155380543
Short name T1301
Test name
Test status
Simulation time 55891149491 ps
CPU time 1341.65 seconds
Started Jul 03 05:26:44 PM PDT 24
Finished Jul 03 05:49:06 PM PDT 24
Peak memory 8803120 kb
Host smart-d00a4109-e1aa-4b0c-ac3e-e125ea42c1c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155380543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2
c_target_stress_wr.3155380543
Directory /workspace/19.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/19.i2c_target_stretch.489301829
Short name T276
Test name
Test status
Simulation time 36678616365 ps
CPU time 317.77 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:31:54 PM PDT 24
Peak memory 2117772 kb
Host smart-3c09624a-2df4-4aab-9684-d0e1a2123e95
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489301829 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.i2c_t
arget_stretch.489301829
Directory /workspace/19.i2c_target_stretch/latest

Test location /workspace/coverage/default/19.i2c_target_timeout.2985293790
Short name T864
Test name
Test status
Simulation time 1273822847 ps
CPU time 6.85 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:26:45 PM PDT 24
Peak memory 204856 kb
Host smart-72afa7c9-a205-407e-9545-116e03fd29fe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985293790 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.i2c_target_timeout.2985293790
Directory /workspace/19.i2c_target_timeout/latest

Test location /workspace/coverage/default/19.i2c_target_tx_stretch_ctrl.1477703596
Short name T1463
Test name
Test status
Simulation time 33052442 ps
CPU time 0.92 seconds
Started Jul 03 05:26:32 PM PDT 24
Finished Jul 03 05:26:33 PM PDT 24
Peak memory 204856 kb
Host smart-85c2f5b9-0322-42a1-8a1e-3b87817c22ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477703596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.i2c_target_tx_stretch_ctrl.1477703596
Directory /workspace/19.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/2.i2c_alert_test.1319249450
Short name T1097
Test name
Test status
Simulation time 23159597 ps
CPU time 0.67 seconds
Started Jul 03 05:25:20 PM PDT 24
Finished Jul 03 05:25:21 PM PDT 24
Peak memory 204440 kb
Host smart-7ea4efe4-cbd7-418a-a486-5eaa0759346d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319249450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_alert_test.1319249450
Directory /workspace/2.i2c_alert_test/latest

Test location /workspace/coverage/default/2.i2c_host_error_intr.3429693121
Short name T449
Test name
Test status
Simulation time 892026034 ps
CPU time 2.4 seconds
Started Jul 03 05:25:04 PM PDT 24
Finished Jul 03 05:25:07 PM PDT 24
Peak memory 213100 kb
Host smart-4608f066-740c-4854-a9c2-8bf9f10d9641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429693121 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_error_intr.3429693121
Directory /workspace/2.i2c_host_error_intr/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_fmt_empty.2188709982
Short name T660
Test name
Test status
Simulation time 442734651 ps
CPU time 8.56 seconds
Started Jul 03 05:25:02 PM PDT 24
Finished Jul 03 05:25:11 PM PDT 24
Peak memory 299064 kb
Host smart-b3ee7803-e3ca-4ba8-934f-c777dde0a757
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188709982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_fmt_empt
y.2188709982
Directory /workspace/2.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_full.2481841441
Short name T1356
Test name
Test status
Simulation time 3028187474 ps
CPU time 47.4 seconds
Started Jul 03 05:25:04 PM PDT 24
Finished Jul 03 05:25:52 PM PDT 24
Peak memory 565940 kb
Host smart-ba3c4d5e-849b-4da0-aa41-a3a51044e7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481841441 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_full.2481841441
Directory /workspace/2.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_overflow.3233680496
Short name T670
Test name
Test status
Simulation time 16395969927 ps
CPU time 128.1 seconds
Started Jul 03 05:25:06 PM PDT 24
Finished Jul 03 05:27:14 PM PDT 24
Peak memory 618948 kb
Host smart-d45bd7f5-57eb-4dfb-bc01-7f40a0b20420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233680496 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_overflow.3233680496
Directory /workspace/2.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_fmt.4013779627
Short name T910
Test name
Test status
Simulation time 1274243961 ps
CPU time 1.01 seconds
Started Jul 03 05:25:05 PM PDT 24
Finished Jul 03 05:25:06 PM PDT 24
Peak memory 204492 kb
Host smart-f0793eac-1ce7-457f-b8dc-7c49249dadf5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013779627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_fm
t.4013779627
Directory /workspace/2.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_reset_rx.3939555295
Short name T812
Test name
Test status
Simulation time 509540189 ps
CPU time 5.83 seconds
Started Jul 03 05:25:22 PM PDT 24
Finished Jul 03 05:25:28 PM PDT 24
Peak memory 253360 kb
Host smart-fc21ead8-ab6f-4b23-8e98-6a2e198ab13b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939555295 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_reset_rx.
3939555295
Directory /workspace/2.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/2.i2c_host_fifo_watermark.306030391
Short name T1259
Test name
Test status
Simulation time 10015401802 ps
CPU time 251.48 seconds
Started Jul 03 05:25:01 PM PDT 24
Finished Jul 03 05:29:14 PM PDT 24
Peak memory 1095748 kb
Host smart-ddf294b8-2aa3-4f11-afd1-57630bb04514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306030391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_fifo_watermark.306030391
Directory /workspace/2.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/2.i2c_host_may_nack.2653970507
Short name T1293
Test name
Test status
Simulation time 1136053467 ps
CPU time 12.42 seconds
Started Jul 03 05:25:14 PM PDT 24
Finished Jul 03 05:25:27 PM PDT 24
Peak memory 204876 kb
Host smart-1ae18e26-f75e-4826-844d-67dc1e021a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653970507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_may_nack.2653970507
Directory /workspace/2.i2c_host_may_nack/latest

Test location /workspace/coverage/default/2.i2c_host_mode_toggle.1060715292
Short name T590
Test name
Test status
Simulation time 1145030384 ps
CPU time 15.59 seconds
Started Jul 03 05:25:21 PM PDT 24
Finished Jul 03 05:25:37 PM PDT 24
Peak memory 253232 kb
Host smart-6d6adefc-b9bb-4eaf-9a6a-578d16319fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060715292 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_mode_toggle.1060715292
Directory /workspace/2.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/2.i2c_host_override.4059544623
Short name T1249
Test name
Test status
Simulation time 30057917 ps
CPU time 0.68 seconds
Started Jul 03 05:25:05 PM PDT 24
Finished Jul 03 05:25:06 PM PDT 24
Peak memory 204560 kb
Host smart-04dbfb29-fa8d-4cb1-8096-723ef3cea1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059544623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_override.4059544623
Directory /workspace/2.i2c_host_override/latest

Test location /workspace/coverage/default/2.i2c_host_perf.2558049160
Short name T857
Test name
Test status
Simulation time 31255070519 ps
CPU time 394.01 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:31:58 PM PDT 24
Peak memory 204984 kb
Host smart-68caa535-8a63-4437-a9a3-00e2051774b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558049160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf.2558049160
Directory /workspace/2.i2c_host_perf/latest

Test location /workspace/coverage/default/2.i2c_host_perf_precise.3035542788
Short name T502
Test name
Test status
Simulation time 1661146274 ps
CPU time 65.86 seconds
Started Jul 03 05:25:08 PM PDT 24
Finished Jul 03 05:26:15 PM PDT 24
Peak memory 212860 kb
Host smart-733fa5a7-c55f-4c49-822a-42774dd7e547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035542788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_perf_precise.3035542788
Directory /workspace/2.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/2.i2c_host_smoke.1472503208
Short name T338
Test name
Test status
Simulation time 28769590478 ps
CPU time 79.02 seconds
Started Jul 03 05:24:59 PM PDT 24
Finished Jul 03 05:26:19 PM PDT 24
Peak memory 276096 kb
Host smart-3af8a0cf-ff04-44d5-908d-385ba7178c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472503208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_smoke.1472503208
Directory /workspace/2.i2c_host_smoke/latest

Test location /workspace/coverage/default/2.i2c_host_stress_all.4094280000
Short name T1275
Test name
Test status
Simulation time 20530915554 ps
CPU time 570.37 seconds
Started Jul 03 05:25:13 PM PDT 24
Finished Jul 03 05:34:45 PM PDT 24
Peak memory 1827516 kb
Host smart-fb195977-6efd-4b2b-a0df-e300146bba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094280000 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stress_all.4094280000
Directory /workspace/2.i2c_host_stress_all/latest

Test location /workspace/coverage/default/2.i2c_host_stretch_timeout.964381460
Short name T1342
Test name
Test status
Simulation time 890811593 ps
CPU time 42.32 seconds
Started Jul 03 05:25:11 PM PDT 24
Finished Jul 03 05:25:54 PM PDT 24
Peak memory 213044 kb
Host smart-a78ccd29-3259-438c-b24a-ed13c4de90cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964381460 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_host_stretch_timeout.964381460
Directory /workspace/2.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_bad_addr.1995005495
Short name T1381
Test name
Test status
Simulation time 6521533183 ps
CPU time 3.62 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:25:27 PM PDT 24
Peak memory 213108 kb
Host smart-f845df89-f69e-45b7-8383-4edf72e5eb1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995005495 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.i2c_target_bad_addr.1995005495
Directory /workspace/2.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_acq.212686610
Short name T512
Test name
Test status
Simulation time 209706166 ps
CPU time 1.38 seconds
Started Jul 03 05:25:08 PM PDT 24
Finished Jul 03 05:25:10 PM PDT 24
Peak memory 204860 kb
Host smart-bba5a301-0e22-4b18-84fc-dc565c1d9f5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212686610 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.i2c_target_fifo_reset_acq.212686610
Directory /workspace/2.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_reset_tx.348383292
Short name T1532
Test name
Test status
Simulation time 498978027 ps
CPU time 1.2 seconds
Started Jul 03 05:25:04 PM PDT 24
Finished Jul 03 05:25:06 PM PDT 24
Peak memory 204812 kb
Host smart-9fc3f5f3-0d1f-43da-995c-e5a4f803bebe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348383292 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.i2c_target_fifo_reset_tx.348383292
Directory /workspace/2.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_acq.3493733720
Short name T808
Test name
Test status
Simulation time 299729682 ps
CPU time 1.8 seconds
Started Jul 03 05:25:13 PM PDT 24
Finished Jul 03 05:25:16 PM PDT 24
Peak memory 204620 kb
Host smart-c45d3c89-ad59-4baa-b841-6f07578f920d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493733720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.i2c_target_fifo_watermarks_acq.3493733720
Directory /workspace/2.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/2.i2c_target_fifo_watermarks_tx.3322370863
Short name T676
Test name
Test status
Simulation time 479967947 ps
CPU time 1.11 seconds
Started Jul 03 05:25:10 PM PDT 24
Finished Jul 03 05:25:12 PM PDT 24
Peak memory 204568 kb
Host smart-17b4525d-97fe-4232-bf5e-a42ac5a79a41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322370863 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.i2c_target_fifo_watermarks_tx.3322370863
Directory /workspace/2.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/2.i2c_target_hrst.3883643418
Short name T437
Test name
Test status
Simulation time 1650922529 ps
CPU time 3.31 seconds
Started Jul 03 05:25:22 PM PDT 24
Finished Jul 03 05:25:26 PM PDT 24
Peak memory 204800 kb
Host smart-8a0a8bd5-0575-4e4f-9183-23228a99c2cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883643418 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 2.i2c_target_hrst.3883643418
Directory /workspace/2.i2c_target_hrst/latest

Test location /workspace/coverage/default/2.i2c_target_intr_smoke.1951895750
Short name T127
Test name
Test status
Simulation time 709107827 ps
CPU time 4.23 seconds
Started Jul 03 05:25:04 PM PDT 24
Finished Jul 03 05:25:14 PM PDT 24
Peak memory 204864 kb
Host smart-70bb76ff-d359-4411-b408-ada6ca0c7a40
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951895750 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 2.i2c_target_intr_smoke.1951895750
Directory /workspace/2.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_intr_stress_wr.3148762088
Short name T89
Test name
Test status
Simulation time 9822364961 ps
CPU time 52.6 seconds
Started Jul 03 05:25:18 PM PDT 24
Finished Jul 03 05:26:11 PM PDT 24
Peak memory 1280736 kb
Host smart-632348bd-df5d-4670-a60c-1ab3e40abfc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148762088 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.i2c_target_intr_stress_wr.3148762088
Directory /workspace/2.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_smoke.1410090662
Short name T1285
Test name
Test status
Simulation time 1323235205 ps
CPU time 32.05 seconds
Started Jul 03 05:25:09 PM PDT 24
Finished Jul 03 05:25:41 PM PDT 24
Peak memory 204644 kb
Host smart-8d6e580e-d3b0-4f02-8a7a-df6bf66d2430
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410090662 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_tar
get_smoke.1410090662
Directory /workspace/2.i2c_target_smoke/latest

Test location /workspace/coverage/default/2.i2c_target_stress_rd.1705368052
Short name T860
Test name
Test status
Simulation time 3242124299 ps
CPU time 33.75 seconds
Started Jul 03 05:25:15 PM PDT 24
Finished Jul 03 05:25:50 PM PDT 24
Peak memory 204896 kb
Host smart-3116b351-8849-45b5-b226-e70d92c0284b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705368052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_rd.1705368052
Directory /workspace/2.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/2.i2c_target_stress_wr.2049510510
Short name T404
Test name
Test status
Simulation time 8388398724 ps
CPU time 5.13 seconds
Started Jul 03 05:25:10 PM PDT 24
Finished Jul 03 05:25:16 PM PDT 24
Peak memory 204896 kb
Host smart-c34dd075-01f2-4461-acdf-cd63c4f8bf53
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049510510 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c
_target_stress_wr.2049510510
Directory /workspace/2.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/2.i2c_target_stretch.3135205862
Short name T436
Test name
Test status
Simulation time 27962496232 ps
CPU time 1276.95 seconds
Started Jul 03 05:25:09 PM PDT 24
Finished Jul 03 05:46:26 PM PDT 24
Peak memory 3162036 kb
Host smart-f2b9641d-d15e-48b6-a9c6-095f893a1aed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135205862 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.i2c_t
arget_stretch.3135205862
Directory /workspace/2.i2c_target_stretch/latest

Test location /workspace/coverage/default/2.i2c_target_timeout.3953366100
Short name T1057
Test name
Test status
Simulation time 5450695361 ps
CPU time 7.29 seconds
Started Jul 03 05:25:29 PM PDT 24
Finished Jul 03 05:25:36 PM PDT 24
Peak memory 221308 kb
Host smart-12a8f917-71cd-4082-a915-f9e5a8434d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953366100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.i2c_target_timeout.3953366100
Directory /workspace/2.i2c_target_timeout/latest

Test location /workspace/coverage/default/2.i2c_target_tx_stretch_ctrl.2901055076
Short name T1460
Test name
Test status
Simulation time 77908654 ps
CPU time 1.81 seconds
Started Jul 03 05:25:11 PM PDT 24
Finished Jul 03 05:25:14 PM PDT 24
Peak memory 204748 kb
Host smart-d3a7fe21-f79b-405c-9275-8a3a8b482b17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901055076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.i2c_target_tx_stretch_ctrl.2901055076
Directory /workspace/2.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/20.i2c_alert_test.1221859326
Short name T126
Test name
Test status
Simulation time 22897088 ps
CPU time 0.62 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:36 PM PDT 24
Peak memory 204480 kb
Host smart-9eeafc8e-7789-4d1b-9995-d22344471b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221859326 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_alert_test.1221859326
Directory /workspace/20.i2c_alert_test/latest

Test location /workspace/coverage/default/20.i2c_host_error_intr.2911666043
Short name T717
Test name
Test status
Simulation time 93657027 ps
CPU time 1.11 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:26:37 PM PDT 24
Peak memory 213032 kb
Host smart-e44945e1-9502-4e99-8a80-7b5240336f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911666043 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_error_intr.2911666043
Directory /workspace/20.i2c_host_error_intr/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_fmt_empty.3407273374
Short name T899
Test name
Test status
Simulation time 369607364 ps
CPU time 6.87 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 281528 kb
Host smart-8e9e4db5-af4a-46a4-8a4e-e2c62078ac8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407273374 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_fmt_emp
ty.3407273374
Directory /workspace/20.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_full.2053614195
Short name T78
Test name
Test status
Simulation time 3164027292 ps
CPU time 79.55 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:27:56 PM PDT 24
Peak memory 214904 kb
Host smart-2fa46465-9103-4d8a-8c83-a50d40a49dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053614195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_full.2053614195
Directory /workspace/20.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_overflow.2592516613
Short name T1150
Test name
Test status
Simulation time 4538574316 ps
CPU time 83.61 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:28:00 PM PDT 24
Peak memory 770712 kb
Host smart-a5243072-b6e2-4de9-bb0b-079ea3231fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592516613 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_overflow.2592516613
Directory /workspace/20.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_fmt.313626450
Short name T1010
Test name
Test status
Simulation time 91521464 ps
CPU time 0.92 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:26:37 PM PDT 24
Peak memory 204440 kb
Host smart-7055273c-e9dd-4512-ab34-a15931614b6f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313626450 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_fm
t.313626450
Directory /workspace/20.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_reset_rx.135356966
Short name T426
Test name
Test status
Simulation time 838058920 ps
CPU time 5.84 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:44 PM PDT 24
Peak memory 244132 kb
Host smart-0e520008-8825-45a8-8805-136c72a7e357
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135356966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_reset_rx.
135356966
Directory /workspace/20.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/20.i2c_host_fifo_watermark.985184018
Short name T110
Test name
Test status
Simulation time 37055968042 ps
CPU time 106.64 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:28:21 PM PDT 24
Peak memory 1236772 kb
Host smart-39b362a6-17a9-4c9a-b99d-ec2c78d734d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985184018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_fifo_watermark.985184018
Directory /workspace/20.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/20.i2c_host_may_nack.409233192
Short name T1394
Test name
Test status
Simulation time 344693913 ps
CPU time 14.83 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:26:51 PM PDT 24
Peak memory 204852 kb
Host smart-ebe8c88e-ade7-458b-ab75-445c2aa84b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409233192 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_may_nack.409233192
Directory /workspace/20.i2c_host_may_nack/latest

Test location /workspace/coverage/default/20.i2c_host_mode_toggle.2606566053
Short name T854
Test name
Test status
Simulation time 9262158824 ps
CPU time 32.27 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:27:11 PM PDT 24
Peak memory 309496 kb
Host smart-2d1149cf-fc63-44e2-9fd8-60ec341ef616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606566053 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_mode_toggle.2606566053
Directory /workspace/20.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/20.i2c_host_override.537338670
Short name T1261
Test name
Test status
Simulation time 32733333 ps
CPU time 0.65 seconds
Started Jul 03 05:26:32 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 204520 kb
Host smart-48db0967-ea98-46af-9ebf-dfed1ffb0e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537338670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_override.537338670
Directory /workspace/20.i2c_host_override/latest

Test location /workspace/coverage/default/20.i2c_host_perf.4279756689
Short name T1471
Test name
Test status
Simulation time 797593325 ps
CPU time 7.67 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:41 PM PDT 24
Peak memory 250252 kb
Host smart-e6f1e8fa-8ff2-44f1-8537-347ba76677d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279756689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf.4279756689
Directory /workspace/20.i2c_host_perf/latest

Test location /workspace/coverage/default/20.i2c_host_perf_precise.2841117068
Short name T385
Test name
Test status
Simulation time 23222852697 ps
CPU time 928.91 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:42:20 PM PDT 24
Peak memory 213104 kb
Host smart-4f834dc5-abc8-45c0-95db-a70c96a96748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841117068 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_perf_precise.2841117068
Directory /workspace/20.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/20.i2c_host_smoke.1795321666
Short name T542
Test name
Test status
Simulation time 2003961455 ps
CPU time 29.1 seconds
Started Jul 03 05:26:31 PM PDT 24
Finished Jul 03 05:27:00 PM PDT 24
Peak memory 337564 kb
Host smart-44580a9f-384a-41e3-8171-670fe3ac2100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795321666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_smoke.1795321666
Directory /workspace/20.i2c_host_smoke/latest

Test location /workspace/coverage/default/20.i2c_host_stress_all.3220150415
Short name T1174
Test name
Test status
Simulation time 86562469391 ps
CPU time 2328.22 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 06:05:24 PM PDT 24
Peak memory 4373388 kb
Host smart-84330024-dcce-400c-a5e0-7ab8948c3c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220150415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_host_stress_all.3220150415
Directory /workspace/20.i2c_host_stress_all/latest

Test location /workspace/coverage/default/20.i2c_target_bad_addr.3800917828
Short name T1398
Test name
Test status
Simulation time 1952603096 ps
CPU time 4.11 seconds
Started Jul 03 05:26:44 PM PDT 24
Finished Jul 03 05:26:48 PM PDT 24
Peak memory 213048 kb
Host smart-77fae28e-236e-4d2e-bc2f-bd5b77f4e0e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800917828 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.i2c_target_bad_addr.3800917828
Directory /workspace/20.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_acq.38733550
Short name T687
Test name
Test status
Simulation time 521804184 ps
CPU time 1.15 seconds
Started Jul 03 05:26:39 PM PDT 24
Finished Jul 03 05:26:41 PM PDT 24
Peak memory 204624 kb
Host smart-a59bbc04-27c8-4d69-acce-f7bd455ac54e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38733550 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.i2c_target_fifo_reset_acq.38733550
Directory /workspace/20.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_reset_tx.3600758597
Short name T1445
Test name
Test status
Simulation time 1415182454 ps
CPU time 1.4 seconds
Started Jul 03 05:26:42 PM PDT 24
Finished Jul 03 05:26:44 PM PDT 24
Peak memory 213060 kb
Host smart-12b8fc69-2d8f-41db-9c52-437e049eba1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600758597 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.i2c_target_fifo_reset_tx.3600758597
Directory /workspace/20.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_acq.520421480
Short name T10
Test name
Test status
Simulation time 2568214678 ps
CPU time 2.52 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:37 PM PDT 24
Peak memory 204884 kb
Host smart-1a04fb40-79b8-4d57-9726-d8db6d7a27dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520421480 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_acq.520421480
Directory /workspace/20.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/20.i2c_target_fifo_watermarks_tx.1374131911
Short name T391
Test name
Test status
Simulation time 913467674 ps
CPU time 1.28 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:26:35 PM PDT 24
Peak memory 204652 kb
Host smart-7730875a-451a-424f-a20f-d45a6dc56eb7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374131911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 20.i2c_target_fifo_watermarks_tx.1374131911
Directory /workspace/20.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/20.i2c_target_hrst.2386356136
Short name T506
Test name
Test status
Simulation time 2072553944 ps
CPU time 3.03 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 204800 kb
Host smart-4b061fa4-ac7e-4524-8551-3a509d8f2eda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386356136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 20.i2c_target_hrst.2386356136
Directory /workspace/20.i2c_target_hrst/latest

Test location /workspace/coverage/default/20.i2c_target_intr_smoke.4156655120
Short name T875
Test name
Test status
Simulation time 1387011155 ps
CPU time 7.18 seconds
Started Jul 03 05:26:43 PM PDT 24
Finished Jul 03 05:26:51 PM PDT 24
Peak memory 219336 kb
Host smart-035963e9-cd77-4d32-aad8-49170559dda5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156655120 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_intr_smoke.4156655120
Directory /workspace/20.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_intr_stress_wr.2932889155
Short name T1197
Test name
Test status
Simulation time 9603652391 ps
CPU time 36.7 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 738816 kb
Host smart-4c9f73bb-7f4d-481a-b08f-03f70160b142
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932889155 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.i2c_target_intr_stress_wr.2932889155
Directory /workspace/20.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_smoke.2141278485
Short name T1481
Test name
Test status
Simulation time 1646331708 ps
CPU time 13.52 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:49 PM PDT 24
Peak memory 204836 kb
Host smart-dcf0e27c-90f6-4318-b5e6-e2c0e873dd97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141278485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_ta
rget_smoke.2141278485
Directory /workspace/20.i2c_target_smoke/latest

Test location /workspace/coverage/default/20.i2c_target_stress_rd.2488186059
Short name T530
Test name
Test status
Simulation time 1233679727 ps
CPU time 11.81 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:26:51 PM PDT 24
Peak memory 207932 kb
Host smart-12aecbac-a3a6-4589-a867-356cf034b0da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488186059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_rd.2488186059
Directory /workspace/20.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/20.i2c_target_stress_wr.2774953083
Short name T1239
Test name
Test status
Simulation time 28578233909 ps
CPU time 24.4 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:27:01 PM PDT 24
Peak memory 562960 kb
Host smart-8924c3ba-b220-45e4-a20e-de59510925b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774953083 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2
c_target_stress_wr.2774953083
Directory /workspace/20.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/20.i2c_target_stretch.239158818
Short name T467
Test name
Test status
Simulation time 33139668818 ps
CPU time 70.53 seconds
Started Jul 03 05:26:33 PM PDT 24
Finished Jul 03 05:27:44 PM PDT 24
Peak memory 835548 kb
Host smart-34d195c6-7394-4187-be5f-7f0410088d15
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239158818 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.i2c_t
arget_stretch.239158818
Directory /workspace/20.i2c_target_stretch/latest

Test location /workspace/coverage/default/20.i2c_target_timeout.519812116
Short name T600
Test name
Test status
Simulation time 24553269973 ps
CPU time 7.72 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:43 PM PDT 24
Peak memory 221248 kb
Host smart-31a6cb5c-6146-440b-9e45-ce9a7725d27b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519812116 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 20.i2c_target_timeout.519812116
Directory /workspace/20.i2c_target_timeout/latest

Test location /workspace/coverage/default/20.i2c_target_tx_stretch_ctrl.2191703231
Short name T1054
Test name
Test status
Simulation time 339328307 ps
CPU time 4.63 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 204868 kb
Host smart-0dec68d9-72dd-49ef-a054-58a8371fe68a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191703231 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.i2c_target_tx_stretch_ctrl.2191703231
Directory /workspace/20.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/21.i2c_alert_test.2551089034
Short name T1042
Test name
Test status
Simulation time 18703878 ps
CPU time 0.65 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 204476 kb
Host smart-8c49ea10-623c-4109-8d9d-b0913e4d6031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551089034 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_alert_test.2551089034
Directory /workspace/21.i2c_alert_test/latest

Test location /workspace/coverage/default/21.i2c_host_error_intr.3190252015
Short name T919
Test name
Test status
Simulation time 762974459 ps
CPU time 4.46 seconds
Started Jul 03 05:26:41 PM PDT 24
Finished Jul 03 05:26:46 PM PDT 24
Peak memory 250964 kb
Host smart-fbf8815b-9c5d-405f-b368-1e9a52240121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190252015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_error_intr.3190252015
Directory /workspace/21.i2c_host_error_intr/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_fmt_empty.1135409620
Short name T129
Test name
Test status
Simulation time 685422623 ps
CPU time 4.07 seconds
Started Jul 03 05:26:39 PM PDT 24
Finished Jul 03 05:26:44 PM PDT 24
Peak memory 242532 kb
Host smart-7e8908fe-cf33-47ce-bb82-e523ac24c1d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135409620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_fmt_emp
ty.1135409620
Directory /workspace/21.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_full.1606733277
Short name T81
Test name
Test status
Simulation time 4653845961 ps
CPU time 74.9 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:27:53 PM PDT 24
Peak memory 717212 kb
Host smart-77ce11d4-7288-4ecf-842e-84ba846991a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606733277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_full.1606733277
Directory /workspace/21.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_overflow.835952245
Short name T544
Test name
Test status
Simulation time 9511728725 ps
CPU time 78.72 seconds
Started Jul 03 05:26:34 PM PDT 24
Finished Jul 03 05:27:53 PM PDT 24
Peak memory 793544 kb
Host smart-f24d70cd-f544-4f5b-abc1-69ee9fec362a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835952245 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_overflow.835952245
Directory /workspace/21.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_fmt.1690184439
Short name T234
Test name
Test status
Simulation time 416705726 ps
CPU time 0.87 seconds
Started Jul 03 05:26:43 PM PDT 24
Finished Jul 03 05:26:44 PM PDT 24
Peak memory 204464 kb
Host smart-831b1632-20b3-49b5-8fec-9acf1f3c4f29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690184439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_f
mt.1690184439
Directory /workspace/21.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_reset_rx.56110075
Short name T490
Test name
Test status
Simulation time 341005931 ps
CPU time 10.04 seconds
Started Jul 03 05:26:51 PM PDT 24
Finished Jul 03 05:27:02 PM PDT 24
Peak memory 235952 kb
Host smart-ab0cdb34-2bc9-4f57-a825-8db0b210c753
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56110075 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_reset_rx.56110075
Directory /workspace/21.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/21.i2c_host_fifo_watermark.778447863
Short name T1070
Test name
Test status
Simulation time 14071948651 ps
CPU time 83.44 seconds
Started Jul 03 05:26:39 PM PDT 24
Finished Jul 03 05:28:03 PM PDT 24
Peak memory 1083920 kb
Host smart-c3cf15c6-4a79-4a7b-a540-bae024c4649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778447863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_fifo_watermark.778447863
Directory /workspace/21.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/21.i2c_host_may_nack.1412317267
Short name T683
Test name
Test status
Simulation time 1400390970 ps
CPU time 5.62 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:43 PM PDT 24
Peak memory 204808 kb
Host smart-a7594075-9082-4c73-a987-c8bafc3f72de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412317267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_may_nack.1412317267
Directory /workspace/21.i2c_host_may_nack/latest

Test location /workspace/coverage/default/21.i2c_host_override.2855322283
Short name T1437
Test name
Test status
Simulation time 29648767 ps
CPU time 0.64 seconds
Started Jul 03 05:26:41 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 204552 kb
Host smart-2ca5b907-7d93-4758-bd69-9d342c70fa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855322283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_override.2855322283
Directory /workspace/21.i2c_host_override/latest

Test location /workspace/coverage/default/21.i2c_host_perf.2057302314
Short name T383
Test name
Test status
Simulation time 8348252002 ps
CPU time 87.29 seconds
Started Jul 03 05:26:53 PM PDT 24
Finished Jul 03 05:28:21 PM PDT 24
Peak memory 213352 kb
Host smart-9981d183-1d3b-459a-ac75-0eaa92c3b9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057302314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf.2057302314
Directory /workspace/21.i2c_host_perf/latest

Test location /workspace/coverage/default/21.i2c_host_perf_precise.3844153902
Short name T723
Test name
Test status
Simulation time 6407078579 ps
CPU time 85.74 seconds
Started Jul 03 05:26:43 PM PDT 24
Finished Jul 03 05:28:10 PM PDT 24
Peak memory 513592 kb
Host smart-9898317f-5893-438f-ab53-81a6fb31b2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844153902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_perf_precise.3844153902
Directory /workspace/21.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/21.i2c_host_smoke.1091662576
Short name T358
Test name
Test status
Simulation time 8210352327 ps
CPU time 96.41 seconds
Started Jul 03 05:26:35 PM PDT 24
Finished Jul 03 05:28:13 PM PDT 24
Peak memory 389956 kb
Host smart-d498284a-1d25-4495-af36-6d5d842e5e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091662576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_smoke.1091662576
Directory /workspace/21.i2c_host_smoke/latest

Test location /workspace/coverage/default/21.i2c_host_stress_all.62858076
Short name T1406
Test name
Test status
Simulation time 48373156492 ps
CPU time 303.15 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:31:42 PM PDT 24
Peak memory 1608872 kb
Host smart-0779644f-3a32-47d4-b6aa-75510244afb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62858076 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stress_all.62858076
Directory /workspace/21.i2c_host_stress_all/latest

Test location /workspace/coverage/default/21.i2c_host_stretch_timeout.3822635475
Short name T803
Test name
Test status
Simulation time 3379252629 ps
CPU time 12.07 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:26:51 PM PDT 24
Peak memory 220900 kb
Host smart-010e0207-5e72-4e8c-814e-653b21275a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822635475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_host_stretch_timeout.3822635475
Directory /workspace/21.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_bad_addr.3080438491
Short name T636
Test name
Test status
Simulation time 1532339448 ps
CPU time 4.01 seconds
Started Jul 03 05:26:49 PM PDT 24
Finished Jul 03 05:26:53 PM PDT 24
Peak memory 213044 kb
Host smart-23365076-5172-4593-901c-bbd7dd17514c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080438491 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.i2c_target_bad_addr.3080438491
Directory /workspace/21.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_acq.1223634127
Short name T1492
Test name
Test status
Simulation time 155583364 ps
CPU time 0.98 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:39 PM PDT 24
Peak memory 212836 kb
Host smart-77b96382-779d-40b9-87db-eb2faf52e3e2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223634127 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.i2c_target_fifo_reset_acq.1223634127
Directory /workspace/21.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_reset_tx.775633681
Short name T397
Test name
Test status
Simulation time 817366931 ps
CPU time 0.81 seconds
Started Jul 03 05:26:38 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 204652 kb
Host smart-971a6ed5-f259-4fc1-b553-013922461609
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775633681 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.i2c_target_fifo_reset_tx.775633681
Directory /workspace/21.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_acq.3981350943
Short name T1014
Test name
Test status
Simulation time 748714226 ps
CPU time 2.3 seconds
Started Jul 03 05:26:54 PM PDT 24
Finished Jul 03 05:26:56 PM PDT 24
Peak memory 204776 kb
Host smart-ef391a40-1e0f-416c-b028-b54041a8e9cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981350943 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.i2c_target_fifo_watermarks_acq.3981350943
Directory /workspace/21.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/21.i2c_target_fifo_watermarks_tx.3569970496
Short name T843
Test name
Test status
Simulation time 101227892 ps
CPU time 1.05 seconds
Started Jul 03 05:26:45 PM PDT 24
Finished Jul 03 05:26:46 PM PDT 24
Peak memory 204580 kb
Host smart-84a491e8-6780-462f-8147-35e15af087c7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569970496 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.i2c_target_fifo_watermarks_tx.3569970496
Directory /workspace/21.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/21.i2c_target_hrst.3613026833
Short name T541
Test name
Test status
Simulation time 1514358286 ps
CPU time 2.43 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 204828 kb
Host smart-a8f1c046-e7ed-4f38-af7d-bf1842b6d386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613026833 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 21.i2c_target_hrst.3613026833
Directory /workspace/21.i2c_target_hrst/latest

Test location /workspace/coverage/default/21.i2c_target_intr_smoke.1566319924
Short name T432
Test name
Test status
Simulation time 1012388141 ps
CPU time 4.92 seconds
Started Jul 03 05:26:39 PM PDT 24
Finished Jul 03 05:26:44 PM PDT 24
Peak memory 204844 kb
Host smart-a3a2da09-ecd2-4c78-89df-de156e129b2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566319924 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 21.i2c_target_intr_smoke.1566319924
Directory /workspace/21.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_intr_stress_wr.2468481598
Short name T1104
Test name
Test status
Simulation time 4742139890 ps
CPU time 10.98 seconds
Started Jul 03 05:26:48 PM PDT 24
Finished Jul 03 05:27:00 PM PDT 24
Peak memory 204976 kb
Host smart-a6827945-c33a-42f6-9bf1-47a99f9aff72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468481598 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.i2c_target_intr_stress_wr.2468481598
Directory /workspace/21.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_smoke.604657734
Short name T1313
Test name
Test status
Simulation time 4346512853 ps
CPU time 37.53 seconds
Started Jul 03 05:26:51 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 204936 kb
Host smart-a7112db5-886a-49c0-bc02-e91015b6ee97
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604657734 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_tar
get_smoke.604657734
Directory /workspace/21.i2c_target_smoke/latest

Test location /workspace/coverage/default/21.i2c_target_stress_rd.603470959
Short name T440
Test name
Test status
Simulation time 1466213194 ps
CPU time 12.07 seconds
Started Jul 03 05:26:46 PM PDT 24
Finished Jul 03 05:26:59 PM PDT 24
Peak memory 212388 kb
Host smart-fd8a60cd-ac07-41b9-9496-13742f12e57b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603470959 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c
_target_stress_rd.603470959
Directory /workspace/21.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/21.i2c_target_stress_wr.1337797153
Short name T553
Test name
Test status
Simulation time 60129736072 ps
CPU time 714.66 seconds
Started Jul 03 05:26:52 PM PDT 24
Finished Jul 03 05:38:47 PM PDT 24
Peak memory 5020440 kb
Host smart-43f096b0-225c-4350-9d8b-9f366c12f42e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337797153 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2
c_target_stress_wr.1337797153
Directory /workspace/21.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/21.i2c_target_stretch.1477744206
Short name T148
Test name
Test status
Simulation time 7962814343 ps
CPU time 9.32 seconds
Started Jul 03 05:26:44 PM PDT 24
Finished Jul 03 05:26:54 PM PDT 24
Peak memory 276732 kb
Host smart-8fca1fb8-5651-4255-be24-37062171388c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477744206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.i2c_
target_stretch.1477744206
Directory /workspace/21.i2c_target_stretch/latest

Test location /workspace/coverage/default/21.i2c_target_timeout.3222497534
Short name T745
Test name
Test status
Simulation time 3167766550 ps
CPU time 7.77 seconds
Started Jul 03 05:26:54 PM PDT 24
Finished Jul 03 05:27:02 PM PDT 24
Peak memory 213360 kb
Host smart-2cd5d72f-7eb9-4cd1-af15-43b35b06da02
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222497534 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 21.i2c_target_timeout.3222497534
Directory /workspace/21.i2c_target_timeout/latest

Test location /workspace/coverage/default/21.i2c_target_tx_stretch_ctrl.26468915
Short name T1299
Test name
Test status
Simulation time 65296446 ps
CPU time 1.59 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 204824 kb
Host smart-1adc6bea-6d44-49ef-b42e-2727acd7c7df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26468915 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.i2c_target_tx_stretch_ctrl.26468915
Directory /workspace/21.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/22.i2c_alert_test.3791590646
Short name T739
Test name
Test status
Simulation time 18687007 ps
CPU time 0.65 seconds
Started Jul 03 05:26:48 PM PDT 24
Finished Jul 03 05:26:49 PM PDT 24
Peak memory 204500 kb
Host smart-3d614647-41c3-48cc-bd39-d121421c3f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791590646 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_alert_test.3791590646
Directory /workspace/22.i2c_alert_test/latest

Test location /workspace/coverage/default/22.i2c_host_error_intr.598793081
Short name T1089
Test name
Test status
Simulation time 40322777 ps
CPU time 1.43 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:26:56 PM PDT 24
Peak memory 213148 kb
Host smart-bd7ccf69-8340-4dff-acbe-3016c2ad9ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598793081 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_error_intr.598793081
Directory /workspace/22.i2c_host_error_intr/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_fmt_empty.1242441193
Short name T783
Test name
Test status
Simulation time 1784017699 ps
CPU time 24.55 seconds
Started Jul 03 05:26:39 PM PDT 24
Finished Jul 03 05:27:04 PM PDT 24
Peak memory 303392 kb
Host smart-669a9b44-7793-4db3-8bba-049048f37717
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242441193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_fmt_emp
ty.1242441193
Directory /workspace/22.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_full.1902033799
Short name T1516
Test name
Test status
Simulation time 6308296726 ps
CPU time 78.91 seconds
Started Jul 03 05:26:43 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 821668 kb
Host smart-c3c24261-c69b-48e0-b619-0831f55af1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902033799 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_full.1902033799
Directory /workspace/22.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_overflow.249063836
Short name T1525
Test name
Test status
Simulation time 9590004725 ps
CPU time 85.61 seconds
Started Jul 03 05:26:39 PM PDT 24
Finished Jul 03 05:28:05 PM PDT 24
Peak memory 781820 kb
Host smart-8531b2b9-6a06-4bce-8d3e-c33ee9e43606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249063836 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_overflow.249063836
Directory /workspace/22.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_fmt.2566202669
Short name T596
Test name
Test status
Simulation time 358471925 ps
CPU time 0.94 seconds
Started Jul 03 05:26:40 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 204444 kb
Host smart-ce494446-68cd-443d-9d21-c4619b8ed443
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566202669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_f
mt.2566202669
Directory /workspace/22.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_reset_rx.1604179079
Short name T821
Test name
Test status
Simulation time 461933073 ps
CPU time 11.61 seconds
Started Jul 03 05:26:43 PM PDT 24
Finished Jul 03 05:26:55 PM PDT 24
Peak memory 204844 kb
Host smart-99f1bf10-e8b4-4513-a940-5eda0232a956
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604179079 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_reset_rx
.1604179079
Directory /workspace/22.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/22.i2c_host_fifo_watermark.2816513160
Short name T1440
Test name
Test status
Simulation time 18182655675 ps
CPU time 225.54 seconds
Started Jul 03 05:26:46 PM PDT 24
Finished Jul 03 05:30:32 PM PDT 24
Peak memory 1030560 kb
Host smart-94c05bdc-ba2d-4857-a2ce-7b89a1d4392a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816513160 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_fifo_watermark.2816513160
Directory /workspace/22.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/22.i2c_host_may_nack.3451226677
Short name T635
Test name
Test status
Simulation time 467212517 ps
CPU time 4 seconds
Started Jul 03 05:26:46 PM PDT 24
Finished Jul 03 05:26:50 PM PDT 24
Peak memory 204868 kb
Host smart-01845942-73f2-4e2a-9d5b-9c581fb21179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451226677 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_may_nack.3451226677
Directory /workspace/22.i2c_host_may_nack/latest

Test location /workspace/coverage/default/22.i2c_host_mode_toggle.2294963056
Short name T323
Test name
Test status
Simulation time 3436537922 ps
CPU time 34.45 seconds
Started Jul 03 05:26:48 PM PDT 24
Finished Jul 03 05:27:23 PM PDT 24
Peak memory 435452 kb
Host smart-9456b084-7a19-4db9-a1ae-f2b060689465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294963056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_mode_toggle.2294963056
Directory /workspace/22.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/22.i2c_host_override.3182927424
Short name T1374
Test name
Test status
Simulation time 58324864 ps
CPU time 0.7 seconds
Started Jul 03 05:26:39 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 204552 kb
Host smart-05a0c987-8247-42c8-b2a2-f857030032a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182927424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_override.3182927424
Directory /workspace/22.i2c_host_override/latest

Test location /workspace/coverage/default/22.i2c_host_perf.4027707291
Short name T682
Test name
Test status
Simulation time 5322862395 ps
CPU time 33.22 seconds
Started Jul 03 05:26:43 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 253356 kb
Host smart-ecd5a1a0-57b5-486a-b63b-06ef741dba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027707291 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf.4027707291
Directory /workspace/22.i2c_host_perf/latest

Test location /workspace/coverage/default/22.i2c_host_perf_precise.1246530636
Short name T313
Test name
Test status
Simulation time 503289627 ps
CPU time 6.06 seconds
Started Jul 03 05:26:48 PM PDT 24
Finished Jul 03 05:26:54 PM PDT 24
Peak memory 225152 kb
Host smart-3fda9d1a-18a0-4af5-b412-9c243cc09b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246530636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_perf_precise.1246530636
Directory /workspace/22.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/22.i2c_host_smoke.3172989482
Short name T281
Test name
Test status
Simulation time 1450244926 ps
CPU time 27.26 seconds
Started Jul 03 05:26:37 PM PDT 24
Finished Jul 03 05:27:05 PM PDT 24
Peak memory 295208 kb
Host smart-e15e59ff-07d9-4545-af0b-4f4e3c61927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172989482 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_smoke.3172989482
Directory /workspace/22.i2c_host_smoke/latest

Test location /workspace/coverage/default/22.i2c_host_stretch_timeout.227390743
Short name T142
Test name
Test status
Simulation time 4224461375 ps
CPU time 7.2 seconds
Started Jul 03 05:26:57 PM PDT 24
Finished Jul 03 05:27:05 PM PDT 24
Peak memory 214664 kb
Host smart-6dd9626e-368e-4986-a517-a5d55b2cddfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227390743 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_host_stretch_timeout.227390743
Directory /workspace/22.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_bad_addr.1339457715
Short name T378
Test name
Test status
Simulation time 659245199 ps
CPU time 2.13 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 204764 kb
Host smart-fa959db1-8b00-4180-920f-4855d524b905
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339457715 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.i2c_target_bad_addr.1339457715
Directory /workspace/22.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_reset_tx.1344043846
Short name T327
Test name
Test status
Simulation time 215293213 ps
CPU time 0.83 seconds
Started Jul 03 05:26:51 PM PDT 24
Finished Jul 03 05:26:52 PM PDT 24
Peak memory 204596 kb
Host smart-fb7d162f-dedd-4c5f-8def-0a6ee26fc5ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344043846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.i2c_target_fifo_reset_tx.1344043846
Directory /workspace/22.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_acq.1793429651
Short name T1391
Test name
Test status
Simulation time 418177437 ps
CPU time 2.05 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:26:53 PM PDT 24
Peak memory 204848 kb
Host smart-14f9e159-99b1-410f-951b-0703efe4635c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793429651 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.i2c_target_fifo_watermarks_acq.1793429651
Directory /workspace/22.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/22.i2c_target_fifo_watermarks_tx.1280810215
Short name T1107
Test name
Test status
Simulation time 190185907 ps
CPU time 1.06 seconds
Started Jul 03 05:26:49 PM PDT 24
Finished Jul 03 05:26:50 PM PDT 24
Peak memory 204480 kb
Host smart-594df8fc-9568-4075-b3fc-f4762b4cd617
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280810215 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.i2c_target_fifo_watermarks_tx.1280810215
Directory /workspace/22.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/22.i2c_target_hrst.221221959
Short name T242
Test name
Test status
Simulation time 1325079123 ps
CPU time 3.64 seconds
Started Jul 03 05:26:49 PM PDT 24
Finished Jul 03 05:26:53 PM PDT 24
Peak memory 204884 kb
Host smart-db1c67d3-86a1-438b-b4d5-b158f81280f0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221221959 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 22.i2c_target_hrst.221221959
Directory /workspace/22.i2c_target_hrst/latest

Test location /workspace/coverage/default/22.i2c_target_intr_smoke.4212388572
Short name T923
Test name
Test status
Simulation time 938423421 ps
CPU time 4.78 seconds
Started Jul 03 05:26:44 PM PDT 24
Finished Jul 03 05:26:49 PM PDT 24
Peak memory 213048 kb
Host smart-dace3b9b-1c73-4712-a4e8-dbad10ad4d49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212388572 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 22.i2c_target_intr_smoke.4212388572
Directory /workspace/22.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_intr_stress_wr.1861453928
Short name T1305
Test name
Test status
Simulation time 5626097134 ps
CPU time 4.02 seconds
Started Jul 03 05:26:48 PM PDT 24
Finished Jul 03 05:26:53 PM PDT 24
Peak memory 204932 kb
Host smart-9670cb18-860a-4837-b50b-59538cdb7840
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861453928 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.i2c_target_intr_stress_wr.1861453928
Directory /workspace/22.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_smoke.602370508
Short name T1322
Test name
Test status
Simulation time 2896209148 ps
CPU time 27.84 seconds
Started Jul 03 05:27:06 PM PDT 24
Finished Jul 03 05:27:34 PM PDT 24
Peak memory 204864 kb
Host smart-04d9c089-dd44-41db-ba1b-d567a33211a6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602370508 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_tar
get_smoke.602370508
Directory /workspace/22.i2c_target_smoke/latest

Test location /workspace/coverage/default/22.i2c_target_stress_rd.1542969557
Short name T737
Test name
Test status
Simulation time 356760284 ps
CPU time 5.11 seconds
Started Jul 03 05:26:46 PM PDT 24
Finished Jul 03 05:26:52 PM PDT 24
Peak memory 204840 kb
Host smart-30bb2200-3516-4937-ae8e-472d5abc69da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542969557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2
c_target_stress_rd.1542969557
Directory /workspace/22.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/22.i2c_target_stress_wr.955186162
Short name T561
Test name
Test status
Simulation time 41539177479 ps
CPU time 223.63 seconds
Started Jul 03 05:26:53 PM PDT 24
Finished Jul 03 05:30:37 PM PDT 24
Peak memory 2765276 kb
Host smart-a2055590-1848-46f4-9b77-6249d1a7891c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955186162 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c
_target_stress_wr.955186162
Directory /workspace/22.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/22.i2c_target_stretch.4114478215
Short name T829
Test name
Test status
Simulation time 14463919154 ps
CPU time 43.24 seconds
Started Jul 03 05:26:51 PM PDT 24
Finished Jul 03 05:27:35 PM PDT 24
Peak memory 726184 kb
Host smart-4368608b-c74c-45e4-bc93-e67ff4b6807d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114478215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.i2c_
target_stretch.4114478215
Directory /workspace/22.i2c_target_stretch/latest

Test location /workspace/coverage/default/22.i2c_target_timeout.1880099530
Short name T500
Test name
Test status
Simulation time 7624022921 ps
CPU time 7.55 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:27:07 PM PDT 24
Peak memory 221136 kb
Host smart-db03733d-4196-4b31-abfb-5325c481909e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880099530 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 22.i2c_target_timeout.1880099530
Directory /workspace/22.i2c_target_timeout/latest

Test location /workspace/coverage/default/22.i2c_target_tx_stretch_ctrl.2465946648
Short name T1326
Test name
Test status
Simulation time 72526582 ps
CPU time 1.74 seconds
Started Jul 03 05:26:51 PM PDT 24
Finished Jul 03 05:26:53 PM PDT 24
Peak memory 204840 kb
Host smart-53f78a5b-8324-4cbc-aa15-aea9a4800a9e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465946648 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.i2c_target_tx_stretch_ctrl.2465946648
Directory /workspace/22.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/23.i2c_alert_test.2387068082
Short name T316
Test name
Test status
Simulation time 77604585 ps
CPU time 0.65 seconds
Started Jul 03 05:26:54 PM PDT 24
Finished Jul 03 05:26:55 PM PDT 24
Peak memory 204460 kb
Host smart-a538f5d1-440e-42ee-b0b7-a1237ab3db08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387068082 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_alert_test.2387068082
Directory /workspace/23.i2c_alert_test/latest

Test location /workspace/coverage/default/23.i2c_host_error_intr.2958254536
Short name T545
Test name
Test status
Simulation time 1887304524 ps
CPU time 1.84 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:27:02 PM PDT 24
Peak memory 213088 kb
Host smart-6f583156-a989-4452-8714-a2746c0c4fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958254536 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_error_intr.2958254536
Directory /workspace/23.i2c_host_error_intr/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_fmt_empty.3739907267
Short name T477
Test name
Test status
Simulation time 544563963 ps
CPU time 12.63 seconds
Started Jul 03 05:26:51 PM PDT 24
Finished Jul 03 05:27:09 PM PDT 24
Peak memory 327460 kb
Host smart-8b7efc78-88f5-4236-b133-59cf3b7b6b55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739907267 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_fmt_emp
ty.3739907267
Directory /workspace/23.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_full.1470224005
Short name T144
Test name
Test status
Simulation time 9583288719 ps
CPU time 51.43 seconds
Started Jul 03 05:26:51 PM PDT 24
Finished Jul 03 05:27:44 PM PDT 24
Peak memory 589236 kb
Host smart-0fe5e8b9-1cd8-414a-a7bf-9ca86f0383cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470224005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_full.1470224005
Directory /workspace/23.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_overflow.857547310
Short name T160
Test name
Test status
Simulation time 1991263019 ps
CPU time 123.05 seconds
Started Jul 03 05:26:54 PM PDT 24
Finished Jul 03 05:28:57 PM PDT 24
Peak memory 630648 kb
Host smart-629f6b72-b0b6-4bed-93c7-b935c4e36ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857547310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_overflow.857547310
Directory /workspace/23.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_fmt.2494423453
Short name T1179
Test name
Test status
Simulation time 454173164 ps
CPU time 0.91 seconds
Started Jul 03 05:26:56 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 204484 kb
Host smart-f8f408c5-f2cd-469d-8c62-0d19cc9565b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494423453 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_f
mt.2494423453
Directory /workspace/23.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_reset_rx.4188980666
Short name T914
Test name
Test status
Simulation time 406189330 ps
CPU time 8 seconds
Started Jul 03 05:26:46 PM PDT 24
Finished Jul 03 05:26:54 PM PDT 24
Peak memory 226768 kb
Host smart-63f89d63-7c44-4b84-930c-65439834ddbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188980666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_reset_rx
.4188980666
Directory /workspace/23.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/23.i2c_host_fifo_watermark.2167396182
Short name T813
Test name
Test status
Simulation time 15137075030 ps
CPU time 244.9 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:30:56 PM PDT 24
Peak memory 1075740 kb
Host smart-540897e2-d5fa-4310-b06c-968a999253ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167396182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_fifo_watermark.2167396182
Directory /workspace/23.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/23.i2c_host_may_nack.1796372234
Short name T1222
Test name
Test status
Simulation time 1294237306 ps
CPU time 26.35 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 204824 kb
Host smart-ed681d91-b9fd-4a22-8dfd-2207dfa4c9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796372234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_may_nack.1796372234
Directory /workspace/23.i2c_host_may_nack/latest

Test location /workspace/coverage/default/23.i2c_host_mode_toggle.3899067214
Short name T1015
Test name
Test status
Simulation time 2412144520 ps
CPU time 34.95 seconds
Started Jul 03 05:26:56 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 367072 kb
Host smart-5cae1166-0d61-41eb-bd91-860e3d5d6a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899067214 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_mode_toggle.3899067214
Directory /workspace/23.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/23.i2c_host_override.2555088377
Short name T1512
Test name
Test status
Simulation time 20991324 ps
CPU time 0.67 seconds
Started Jul 03 05:26:48 PM PDT 24
Finished Jul 03 05:26:49 PM PDT 24
Peak memory 204544 kb
Host smart-f22226e6-522c-4f97-8373-b419bf4e0ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555088377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_override.2555088377
Directory /workspace/23.i2c_host_override/latest

Test location /workspace/coverage/default/23.i2c_host_perf.2457313490
Short name T1156
Test name
Test status
Simulation time 24926115559 ps
CPU time 88.9 seconds
Started Jul 03 05:26:49 PM PDT 24
Finished Jul 03 05:28:18 PM PDT 24
Peak memory 221352 kb
Host smart-de043493-5b1b-4298-baa7-77bdfe8c2f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457313490 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf.2457313490
Directory /workspace/23.i2c_host_perf/latest

Test location /workspace/coverage/default/23.i2c_host_perf_precise.3643559367
Short name T312
Test name
Test status
Simulation time 234525862 ps
CPU time 1.89 seconds
Started Jul 03 05:26:46 PM PDT 24
Finished Jul 03 05:26:48 PM PDT 24
Peak memory 204608 kb
Host smart-d8b45ff2-d06e-4faf-8ae1-08064df94ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643559367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_perf_precise.3643559367
Directory /workspace/23.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/23.i2c_host_smoke.1551336803
Short name T642
Test name
Test status
Simulation time 2487734851 ps
CPU time 19.03 seconds
Started Jul 03 05:26:53 PM PDT 24
Finished Jul 03 05:27:12 PM PDT 24
Peak memory 317704 kb
Host smart-d738480d-8541-4d4e-a516-ed4804454d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551336803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_smoke.1551336803
Directory /workspace/23.i2c_host_smoke/latest

Test location /workspace/coverage/default/23.i2c_host_stress_all.1569322290
Short name T1041
Test name
Test status
Simulation time 57856124580 ps
CPU time 1677.36 seconds
Started Jul 03 05:26:53 PM PDT 24
Finished Jul 03 05:54:51 PM PDT 24
Peak memory 3769516 kb
Host smart-6edc8a84-3789-428b-a3ed-590bac84f161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569322290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stress_all.1569322290
Directory /workspace/23.i2c_host_stress_all/latest

Test location /workspace/coverage/default/23.i2c_host_stretch_timeout.160336531
Short name T546
Test name
Test status
Simulation time 1580395739 ps
CPU time 12.27 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:27:11 PM PDT 24
Peak memory 221236 kb
Host smart-3923f873-281e-43a0-9e5b-4692807f7079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160336531 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_host_stretch_timeout.160336531
Directory /workspace/23.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_bad_addr.1287818405
Short name T1081
Test name
Test status
Simulation time 1217550121 ps
CPU time 3.37 seconds
Started Jul 03 05:26:53 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 204816 kb
Host smart-6b56693f-401f-4cc8-81cc-4a8e04dbdd55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287818405 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.i2c_target_bad_addr.1287818405
Directory /workspace/23.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_reset_tx.2440240514
Short name T1051
Test name
Test status
Simulation time 297506318 ps
CPU time 0.85 seconds
Started Jul 03 05:27:07 PM PDT 24
Finished Jul 03 05:27:08 PM PDT 24
Peak memory 204624 kb
Host smart-fdaaf6b5-8a2c-4f96-99a5-c4a02ca01e11
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440240514 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.i2c_target_fifo_reset_tx.2440240514
Directory /workspace/23.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_acq.1775403653
Short name T293
Test name
Test status
Simulation time 221444392 ps
CPU time 1.61 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 204588 kb
Host smart-3d0cb87e-4bc7-4cc2-bb05-f5474fc16239
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775403653 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.i2c_target_fifo_watermarks_acq.1775403653
Directory /workspace/23.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/23.i2c_target_fifo_watermarks_tx.1970955670
Short name T688
Test name
Test status
Simulation time 136662195 ps
CPU time 1.22 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:26:52 PM PDT 24
Peak memory 204660 kb
Host smart-01de5d57-0ed7-4090-bfb7-a0da15e12b56
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970955670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.i2c_target_fifo_watermarks_tx.1970955670
Directory /workspace/23.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/23.i2c_target_hrst.2494235080
Short name T654
Test name
Test status
Simulation time 295577129 ps
CPU time 2.35 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:26:52 PM PDT 24
Peak memory 204856 kb
Host smart-171a255c-3f0c-404b-97a9-b6e5b14556c6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494235080 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 23.i2c_target_hrst.2494235080
Directory /workspace/23.i2c_target_hrst/latest

Test location /workspace/coverage/default/23.i2c_target_intr_smoke.2857925354
Short name T522
Test name
Test status
Simulation time 936493214 ps
CPU time 4.93 seconds
Started Jul 03 05:27:01 PM PDT 24
Finished Jul 03 05:27:06 PM PDT 24
Peak memory 213072 kb
Host smart-6827c1f8-8e6e-4ce7-853e-18a768797f98
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857925354 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 23.i2c_target_intr_smoke.2857925354
Directory /workspace/23.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_intr_stress_wr.4040281713
Short name T886
Test name
Test status
Simulation time 10320315893 ps
CPU time 156.54 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 2640828 kb
Host smart-b88d1915-8966-4263-b29a-d9e6ea89fcfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040281713 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.i2c_target_intr_stress_wr.4040281713
Directory /workspace/23.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_smoke.2510433421
Short name T125
Test name
Test status
Simulation time 4407899693 ps
CPU time 24.16 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 204924 kb
Host smart-d0f81d84-de64-4d7d-a429-d222d003aa08
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510433421 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_ta
rget_smoke.2510433421
Directory /workspace/23.i2c_target_smoke/latest

Test location /workspace/coverage/default/23.i2c_target_stress_rd.539867417
Short name T1524
Test name
Test status
Simulation time 15720197716 ps
CPU time 20.45 seconds
Started Jul 03 05:26:47 PM PDT 24
Finished Jul 03 05:27:08 PM PDT 24
Peak memory 219088 kb
Host smart-9ff0abc6-986d-4cba-81a3-bbd51a360a91
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539867417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_rd.539867417
Directory /workspace/23.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/23.i2c_target_stress_wr.271623184
Short name T1217
Test name
Test status
Simulation time 65366534235 ps
CPU time 2411.14 seconds
Started Jul 03 05:26:50 PM PDT 24
Finished Jul 03 06:07:03 PM PDT 24
Peak memory 11070348 kb
Host smart-489b89c2-6874-4eae-a0f7-519e0d2a96c2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271623184 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c
_target_stress_wr.271623184
Directory /workspace/23.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/23.i2c_target_stretch.181995233
Short name T822
Test name
Test status
Simulation time 30512681891 ps
CPU time 93.94 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 903924 kb
Host smart-2bda3147-a5e0-445f-88f0-7ace8492c011
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181995233 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.i2c_t
arget_stretch.181995233
Directory /workspace/23.i2c_target_stretch/latest

Test location /workspace/coverage/default/23.i2c_target_timeout.2979774573
Short name T1384
Test name
Test status
Simulation time 6038919054 ps
CPU time 7.22 seconds
Started Jul 03 05:26:51 PM PDT 24
Finished Jul 03 05:26:59 PM PDT 24
Peak memory 212044 kb
Host smart-c1f88ac2-2f12-4e00-a4f3-8db4872d7386
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979774573 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 23.i2c_target_timeout.2979774573
Directory /workspace/23.i2c_target_timeout/latest

Test location /workspace/coverage/default/23.i2c_target_tx_stretch_ctrl.2028153186
Short name T438
Test name
Test status
Simulation time 1139213805 ps
CPU time 13.91 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:27:14 PM PDT 24
Peak memory 204828 kb
Host smart-9e6652f3-e915-465d-959d-5f6e0eaeb319
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028153186 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.i2c_target_tx_stretch_ctrl.2028153186
Directory /workspace/23.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/24.i2c_alert_test.117810143
Short name T557
Test name
Test status
Simulation time 72553719 ps
CPU time 0.62 seconds
Started Jul 03 05:26:57 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 204488 kb
Host smart-24195909-40df-4eaf-9a5a-8220529d747f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117810143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_alert_test.117810143
Directory /workspace/24.i2c_alert_test/latest

Test location /workspace/coverage/default/24.i2c_host_error_intr.449194780
Short name T306
Test name
Test status
Simulation time 285565673 ps
CPU time 4.51 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:27:00 PM PDT 24
Peak memory 245432 kb
Host smart-3d750c3a-8062-4846-9a9c-158d53f5653e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449194780 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_error_intr.449194780
Directory /workspace/24.i2c_host_error_intr/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_fmt_empty.3135526747
Short name T1331
Test name
Test status
Simulation time 1497617615 ps
CPU time 10 seconds
Started Jul 03 05:26:47 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 244360 kb
Host smart-3958328f-4d04-444a-9f68-55642739785f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135526747 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_fmt_emp
ty.3135526747
Directory /workspace/24.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_full.2149889354
Short name T862
Test name
Test status
Simulation time 2667296333 ps
CPU time 72.14 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 373580 kb
Host smart-fc9b876f-b408-4ad3-b58e-9f4eb9f9efbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149889354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_full.2149889354
Directory /workspace/24.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_overflow.599987111
Short name T1109
Test name
Test status
Simulation time 4808426853 ps
CPU time 80.04 seconds
Started Jul 03 05:26:49 PM PDT 24
Finished Jul 03 05:28:10 PM PDT 24
Peak memory 828376 kb
Host smart-639c73dc-a4f7-4ea1-bde9-5c39d01a2b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599987111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_overflow.599987111
Directory /workspace/24.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_fmt.877379630
Short name T1473
Test name
Test status
Simulation time 143098015 ps
CPU time 1.07 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 204484 kb
Host smart-6b5cb1ed-6b5f-49fb-bf03-260930542813
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877379630 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_fm
t.877379630
Directory /workspace/24.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_reset_rx.794828321
Short name T1528
Test name
Test status
Simulation time 247952244 ps
CPU time 3.83 seconds
Started Jul 03 05:27:04 PM PDT 24
Finished Jul 03 05:27:09 PM PDT 24
Peak memory 223092 kb
Host smart-9ec21d52-4700-45e9-aa09-333178c4fe91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794828321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_reset_rx.
794828321
Directory /workspace/24.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/24.i2c_host_fifo_watermark.3864199409
Short name T1144
Test name
Test status
Simulation time 5501282082 ps
CPU time 172.92 seconds
Started Jul 03 05:27:05 PM PDT 24
Finished Jul 03 05:29:58 PM PDT 24
Peak memory 832380 kb
Host smart-22d6d618-547e-40b6-9f11-03d38e542f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864199409 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_fifo_watermark.3864199409
Directory /workspace/24.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/24.i2c_host_may_nack.2905436726
Short name T1403
Test name
Test status
Simulation time 2018793964 ps
CPU time 4.45 seconds
Started Jul 03 05:27:05 PM PDT 24
Finished Jul 03 05:27:10 PM PDT 24
Peak memory 204824 kb
Host smart-fa700f1c-1ba4-45ca-8166-a08e68f8e1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905436726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_may_nack.2905436726
Directory /workspace/24.i2c_host_may_nack/latest

Test location /workspace/coverage/default/24.i2c_host_mode_toggle.3173031145
Short name T698
Test name
Test status
Simulation time 3468725314 ps
CPU time 31.64 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:27:27 PM PDT 24
Peak memory 354184 kb
Host smart-e29da207-97e6-4b26-8f0b-fd554d32cd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173031145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_mode_toggle.3173031145
Directory /workspace/24.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/24.i2c_host_override.2077077712
Short name T691
Test name
Test status
Simulation time 70615399 ps
CPU time 0.67 seconds
Started Jul 03 05:26:53 PM PDT 24
Finished Jul 03 05:26:54 PM PDT 24
Peak memory 204520 kb
Host smart-7c40404a-7051-4c6f-a73e-34c036a77b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077077712 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_override.2077077712
Directory /workspace/24.i2c_host_override/latest

Test location /workspace/coverage/default/24.i2c_host_perf.1316285543
Short name T917
Test name
Test status
Simulation time 25211174322 ps
CPU time 1656.87 seconds
Started Jul 03 05:27:05 PM PDT 24
Finished Jul 03 05:54:42 PM PDT 24
Peak memory 3928476 kb
Host smart-68b0b0a8-679c-4507-bbce-789828bbfebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316285543 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf.1316285543
Directory /workspace/24.i2c_host_perf/latest

Test location /workspace/coverage/default/24.i2c_host_perf_precise.2012146577
Short name T1021
Test name
Test status
Simulation time 105094510 ps
CPU time 1.07 seconds
Started Jul 03 05:27:01 PM PDT 24
Finished Jul 03 05:27:02 PM PDT 24
Peak memory 222416 kb
Host smart-fe28eca8-a4f7-47a6-a027-cbff1dc4f46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012146577 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_perf_precise.2012146577
Directory /workspace/24.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/24.i2c_host_smoke.19848056
Short name T1486
Test name
Test status
Simulation time 1589490890 ps
CPU time 31.04 seconds
Started Jul 03 05:27:07 PM PDT 24
Finished Jul 03 05:27:38 PM PDT 24
Peak memory 333632 kb
Host smart-e7e95c0f-2f77-4c9f-8d14-e3d121880d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19848056 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_smoke.19848056
Directory /workspace/24.i2c_host_smoke/latest

Test location /workspace/coverage/default/24.i2c_host_stress_all.470334924
Short name T52
Test name
Test status
Simulation time 21466393783 ps
CPU time 936.68 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:42:46 PM PDT 24
Peak memory 1736500 kb
Host smart-16767f36-6c22-43f8-aee3-cc501cd8c4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470334924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stress_all.470334924
Directory /workspace/24.i2c_host_stress_all/latest

Test location /workspace/coverage/default/24.i2c_host_stretch_timeout.1466560357
Short name T172
Test name
Test status
Simulation time 491295323 ps
CPU time 7.34 seconds
Started Jul 03 05:26:54 PM PDT 24
Finished Jul 03 05:27:02 PM PDT 24
Peak memory 220380 kb
Host smart-1a1927b0-a948-4c1e-bfee-680d4786eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466560357 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_host_stretch_timeout.1466560357
Directory /workspace/24.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_bad_addr.4140072529
Short name T1047
Test name
Test status
Simulation time 616149951 ps
CPU time 3.53 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:27:02 PM PDT 24
Peak memory 213056 kb
Host smart-1fc5a513-0923-454a-8db4-3501bfad4d9a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140072529 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.i2c_target_bad_addr.4140072529
Directory /workspace/24.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_reset_acq.1679827605
Short name T274
Test name
Test status
Simulation time 175485042 ps
CPU time 1.12 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 204664 kb
Host smart-fe00e787-f138-4946-89b8-22de164c111c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679827605 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_fifo_reset_acq.1679827605
Directory /workspace/24.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_acq.2849724121
Short name T257
Test name
Test status
Simulation time 554974386 ps
CPU time 2.9 seconds
Started Jul 03 05:27:04 PM PDT 24
Finished Jul 03 05:27:07 PM PDT 24
Peak memory 204816 kb
Host smart-1f94c30c-3f1b-4cf6-9760-68e1f85c3c93
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849724121 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.i2c_target_fifo_watermarks_acq.2849724121
Directory /workspace/24.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/24.i2c_target_fifo_watermarks_tx.1990277049
Short name T422
Test name
Test status
Simulation time 157287346 ps
CPU time 1.3 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:27:01 PM PDT 24
Peak memory 204600 kb
Host smart-a8fcd964-80a4-44be-b7c2-f0cba3931d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990277049 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.i2c_target_fifo_watermarks_tx.1990277049
Directory /workspace/24.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/24.i2c_target_intr_smoke.1968628779
Short name T572
Test name
Test status
Simulation time 3145376985 ps
CPU time 5.45 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:27:01 PM PDT 24
Peak memory 220540 kb
Host smart-f142327e-39f0-4bcc-a73b-5b289dfc75dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968628779 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 24.i2c_target_intr_smoke.1968628779
Directory /workspace/24.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_intr_stress_wr.1088879461
Short name T517
Test name
Test status
Simulation time 6309883319 ps
CPU time 13.26 seconds
Started Jul 03 05:26:55 PM PDT 24
Finished Jul 03 05:27:09 PM PDT 24
Peak memory 537456 kb
Host smart-ce93c94b-a4fd-4cc8-ae5a-e8c225f23e8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088879461 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.i2c_target_intr_stress_wr.1088879461
Directory /workspace/24.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/24.i2c_target_smoke.2875939396
Short name T938
Test name
Test status
Simulation time 3495083386 ps
CPU time 34.62 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:27:33 PM PDT 24
Peak memory 204824 kb
Host smart-4c168dee-cf30-48a9-90bf-5a930c74a5b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875939396 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_ta
rget_smoke.2875939396
Directory /workspace/24.i2c_target_smoke/latest

Test location /workspace/coverage/default/24.i2c_target_stress_rd.310506264
Short name T1009
Test name
Test status
Simulation time 9084178741 ps
CPU time 74.5 seconds
Started Jul 03 05:27:02 PM PDT 24
Finished Jul 03 05:28:22 PM PDT 24
Peak memory 210348 kb
Host smart-d22213aa-0300-4a23-8d7b-590e11a1a8cc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310506264 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c
_target_stress_rd.310506264
Directory /workspace/24.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/24.i2c_target_stretch.1952085442
Short name T120
Test name
Test status
Simulation time 38862303574 ps
CPU time 42.39 seconds
Started Jul 03 05:26:57 PM PDT 24
Finished Jul 03 05:27:40 PM PDT 24
Peak memory 592632 kb
Host smart-16b73f10-6ec7-4e2a-912f-57df61906bd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952085442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.i2c_
target_stretch.1952085442
Directory /workspace/24.i2c_target_stretch/latest

Test location /workspace/coverage/default/24.i2c_target_timeout.1148935835
Short name T669
Test name
Test status
Simulation time 2915593909 ps
CPU time 8.02 seconds
Started Jul 03 05:27:02 PM PDT 24
Finished Jul 03 05:27:10 PM PDT 24
Peak memory 221196 kb
Host smart-7dff27ea-db10-4236-a23b-6bc3345a5399
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148935835 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 24.i2c_target_timeout.1148935835
Directory /workspace/24.i2c_target_timeout/latest

Test location /workspace/coverage/default/24.i2c_target_tx_stretch_ctrl.3101402195
Short name T496
Test name
Test status
Simulation time 269616972 ps
CPU time 4.31 seconds
Started Jul 03 05:27:04 PM PDT 24
Finished Jul 03 05:27:08 PM PDT 24
Peak memory 204880 kb
Host smart-484fe0cc-ccd3-4076-95bd-7c0d3c6218bd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101402195 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.i2c_target_tx_stretch_ctrl.3101402195
Directory /workspace/24.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/25.i2c_alert_test.230471332
Short name T388
Test name
Test status
Simulation time 156525309 ps
CPU time 0.62 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:26:59 PM PDT 24
Peak memory 204444 kb
Host smart-320f1355-7292-4384-a595-446b523a0ec5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230471332 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_alert_test.230471332
Directory /workspace/25.i2c_alert_test/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_fmt_empty.1338146146
Short name T431
Test name
Test status
Simulation time 1133589625 ps
CPU time 14.22 seconds
Started Jul 03 05:27:03 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 258304 kb
Host smart-a1e86d5c-2b8d-48b9-86a2-18cecc598b09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338146146 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_fmt_emp
ty.1338146146
Directory /workspace/25.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_full.2317491968
Short name T839
Test name
Test status
Simulation time 1468381432 ps
CPU time 37.52 seconds
Started Jul 03 05:27:00 PM PDT 24
Finished Jul 03 05:27:38 PM PDT 24
Peak memory 459368 kb
Host smart-1d676dee-ec66-413b-ad62-cec329e07755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317491968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_full.2317491968
Directory /workspace/25.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_overflow.1749387129
Short name T503
Test name
Test status
Simulation time 2284310385 ps
CPU time 75.11 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:28:15 PM PDT 24
Peak memory 755188 kb
Host smart-ea2b4456-be27-4b55-8b29-c4c4ce2e95c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749387129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_overflow.1749387129
Directory /workspace/25.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_fmt.2899340351
Short name T56
Test name
Test status
Simulation time 108352762 ps
CPU time 0.92 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:27:00 PM PDT 24
Peak memory 204440 kb
Host smart-960200b6-02ac-4759-9214-9843f37c48d6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899340351 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_f
mt.2899340351
Directory /workspace/25.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_reset_rx.33235717
Short name T1130
Test name
Test status
Simulation time 300310052 ps
CPU time 8.73 seconds
Started Jul 03 05:27:04 PM PDT 24
Finished Jul 03 05:27:13 PM PDT 24
Peak memory 231012 kb
Host smart-76ebedfa-fcee-446e-800e-0aa6e803d071
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33235717 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_reset_rx.33235717
Directory /workspace/25.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/25.i2c_host_fifo_watermark.2103901796
Short name T1209
Test name
Test status
Simulation time 4427502604 ps
CPU time 296.51 seconds
Started Jul 03 05:27:02 PM PDT 24
Finished Jul 03 05:31:59 PM PDT 24
Peak memory 1196064 kb
Host smart-1ce60383-518f-47fd-885f-8591d0e98cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103901796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_fifo_watermark.2103901796
Directory /workspace/25.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/25.i2c_host_may_nack.2418956246
Short name T1270
Test name
Test status
Simulation time 1596017631 ps
CPU time 5.2 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:27:14 PM PDT 24
Peak memory 204784 kb
Host smart-8161a762-d903-4c44-9013-0f5bdce15b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418956246 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_may_nack.2418956246
Directory /workspace/25.i2c_host_may_nack/latest

Test location /workspace/coverage/default/25.i2c_host_mode_toggle.2236841397
Short name T1106
Test name
Test status
Simulation time 1572350888 ps
CPU time 21.76 seconds
Started Jul 03 05:27:02 PM PDT 24
Finished Jul 03 05:27:24 PM PDT 24
Peak memory 286668 kb
Host smart-cfaf3709-c46b-461c-86bd-53300d39c8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236841397 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_mode_toggle.2236841397
Directory /workspace/25.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/25.i2c_host_override.2036151278
Short name T741
Test name
Test status
Simulation time 27696471 ps
CPU time 0.72 seconds
Started Jul 03 05:27:01 PM PDT 24
Finished Jul 03 05:27:03 PM PDT 24
Peak memory 204524 kb
Host smart-cca5a090-e45d-4303-bc25-bca1a3ee89cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036151278 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_override.2036151278
Directory /workspace/25.i2c_host_override/latest

Test location /workspace/coverage/default/25.i2c_host_perf.3903851994
Short name T558
Test name
Test status
Simulation time 30370561577 ps
CPU time 641.07 seconds
Started Jul 03 05:27:01 PM PDT 24
Finished Jul 03 05:37:43 PM PDT 24
Peak memory 2809832 kb
Host smart-b8bf81ee-3bb1-4446-a66c-a8acb664859d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903851994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf.3903851994
Directory /workspace/25.i2c_host_perf/latest

Test location /workspace/coverage/default/25.i2c_host_perf_precise.1958410942
Short name T583
Test name
Test status
Simulation time 55621731 ps
CPU time 1.22 seconds
Started Jul 03 05:26:57 PM PDT 24
Finished Jul 03 05:26:59 PM PDT 24
Peak memory 213356 kb
Host smart-6f773fd6-d381-494c-9dce-a2f1b8b8113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958410942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_perf_precise.1958410942
Directory /workspace/25.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/25.i2c_host_smoke.2011664166
Short name T532
Test name
Test status
Simulation time 2018783837 ps
CPU time 23.75 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:27:24 PM PDT 24
Peak memory 297912 kb
Host smart-0c6f7d7e-c406-46e3-93b7-b11c8c6d49fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011664166 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_smoke.2011664166
Directory /workspace/25.i2c_host_smoke/latest

Test location /workspace/coverage/default/25.i2c_host_stress_all.1160201055
Short name T900
Test name
Test status
Simulation time 75160894145 ps
CPU time 1289.29 seconds
Started Jul 03 05:27:05 PM PDT 24
Finished Jul 03 05:48:35 PM PDT 24
Peak memory 3717720 kb
Host smart-9b5d2e62-7fe9-4a41-8886-56283306f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160201055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stress_all.1160201055
Directory /workspace/25.i2c_host_stress_all/latest

Test location /workspace/coverage/default/25.i2c_host_stretch_timeout.142770207
Short name T632
Test name
Test status
Simulation time 974792782 ps
CPU time 17.59 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:27:26 PM PDT 24
Peak memory 221140 kb
Host smart-6610a588-b790-43b1-91cd-ccc32392f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142770207 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_host_stretch_timeout.142770207
Directory /workspace/25.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_bad_addr.3351216282
Short name T430
Test name
Test status
Simulation time 4820947600 ps
CPU time 6.15 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:27:06 PM PDT 24
Peak memory 217432 kb
Host smart-4aed4217-1284-43b4-bfe7-8b2ab07922b5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351216282 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 25.i2c_target_bad_addr.3351216282
Directory /workspace/25.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_acq.897039234
Short name T587
Test name
Test status
Simulation time 1219383030 ps
CPU time 1.32 seconds
Started Jul 03 05:27:07 PM PDT 24
Finished Jul 03 05:27:09 PM PDT 24
Peak memory 204744 kb
Host smart-90e44be9-0ee6-4d64-9549-e514d6813920
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897039234 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_acq.897039234
Directory /workspace/25.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_reset_tx.1989246580
Short name T816
Test name
Test status
Simulation time 260440111 ps
CPU time 1.5 seconds
Started Jul 03 05:27:07 PM PDT 24
Finished Jul 03 05:27:09 PM PDT 24
Peak memory 207900 kb
Host smart-5064db4d-8963-4146-be94-a89511a4c96a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989246580 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.i2c_target_fifo_reset_tx.1989246580
Directory /workspace/25.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_acq.4137825237
Short name T780
Test name
Test status
Simulation time 2131108315 ps
CPU time 2.84 seconds
Started Jul 03 05:27:03 PM PDT 24
Finished Jul 03 05:27:06 PM PDT 24
Peak memory 204772 kb
Host smart-5ba483ea-bb2e-4186-9edc-db95f14ed8f7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137825237 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.i2c_target_fifo_watermarks_acq.4137825237
Directory /workspace/25.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/25.i2c_target_fifo_watermarks_tx.408285539
Short name T1392
Test name
Test status
Simulation time 252859423 ps
CPU time 0.9 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:26:59 PM PDT 24
Peak memory 204616 kb
Host smart-a44d448c-a199-4ac3-9e3b-02049e663088
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408285539 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.i2c_target_fifo_watermarks_tx.408285539
Directory /workspace/25.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/25.i2c_target_intr_smoke.1165691258
Short name T834
Test name
Test status
Simulation time 4473157200 ps
CPU time 6.35 seconds
Started Jul 03 05:27:13 PM PDT 24
Finished Jul 03 05:27:20 PM PDT 24
Peak memory 221160 kb
Host smart-ffa2e556-d94d-4055-92fa-7f6cb8831d7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165691258 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 25.i2c_target_intr_smoke.1165691258
Directory /workspace/25.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_intr_stress_wr.2683432137
Short name T628
Test name
Test status
Simulation time 3204018231 ps
CPU time 5.16 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:27:14 PM PDT 24
Peak memory 349628 kb
Host smart-a65c73d7-f9d9-483e-ab6e-1f8f6677ce4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683432137 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.i2c_target_intr_stress_wr.2683432137
Directory /workspace/25.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_smoke.755232530
Short name T268
Test name
Test status
Simulation time 1002667414 ps
CPU time 39.63 seconds
Started Jul 03 05:27:06 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 204808 kb
Host smart-8318a08f-ad1c-4c89-8489-ec4df88a2c94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755232530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_tar
get_smoke.755232530
Directory /workspace/25.i2c_target_smoke/latest

Test location /workspace/coverage/default/25.i2c_target_stress_rd.16536100
Short name T458
Test name
Test status
Simulation time 1035681072 ps
CPU time 22.41 seconds
Started Jul 03 05:26:58 PM PDT 24
Finished Jul 03 05:27:21 PM PDT 24
Peak memory 204828 kb
Host smart-e993c14b-4d30-448b-88d8-beffd55ad872
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16536100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stress_rd.16536100
Directory /workspace/25.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/25.i2c_target_stress_wr.4007945109
Short name T359
Test name
Test status
Simulation time 63549122900 ps
CPU time 300.38 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:32:10 PM PDT 24
Peak memory 2710616 kb
Host smart-a1d24d29-a346-43b5-aa6b-3941e701e9c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007945109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2
c_target_stress_wr.4007945109
Directory /workspace/25.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/25.i2c_target_stretch.1634807052
Short name T1380
Test name
Test status
Simulation time 12981803924 ps
CPU time 171.62 seconds
Started Jul 03 05:27:05 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 760376 kb
Host smart-3eeafec5-344d-4a26-b7db-494a4bbe2820
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634807052 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.i2c_
target_stretch.1634807052
Directory /workspace/25.i2c_target_stretch/latest

Test location /workspace/coverage/default/25.i2c_target_timeout.2471730697
Short name T1204
Test name
Test status
Simulation time 5922819095 ps
CPU time 7.25 seconds
Started Jul 03 05:27:03 PM PDT 24
Finished Jul 03 05:27:10 PM PDT 24
Peak memory 211160 kb
Host smart-c365a650-52e0-409a-b5ec-a9f13a8934ff
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471730697 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 25.i2c_target_timeout.2471730697
Directory /workspace/25.i2c_target_timeout/latest

Test location /workspace/coverage/default/25.i2c_target_tx_stretch_ctrl.2699235427
Short name T1456
Test name
Test status
Simulation time 381022545 ps
CPU time 5.13 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 204720 kb
Host smart-be731d5b-05ce-46c0-b7ca-04368d479ad4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699235427 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.i2c_target_tx_stretch_ctrl.2699235427
Directory /workspace/25.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/26.i2c_alert_test.2015412322
Short name T1190
Test name
Test status
Simulation time 63197230 ps
CPU time 0.65 seconds
Started Jul 03 05:27:13 PM PDT 24
Finished Jul 03 05:27:14 PM PDT 24
Peak memory 204468 kb
Host smart-f5bfe705-06c4-4a93-9737-9164dc3a1363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015412322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_alert_test.2015412322
Directory /workspace/26.i2c_alert_test/latest

Test location /workspace/coverage/default/26.i2c_host_error_intr.812699977
Short name T1139
Test name
Test status
Simulation time 75586539 ps
CPU time 1.21 seconds
Started Jul 03 05:27:05 PM PDT 24
Finished Jul 03 05:27:07 PM PDT 24
Peak memory 213116 kb
Host smart-e0c83048-892c-4737-844a-87c0c1df9244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812699977 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_error_intr.812699977
Directory /workspace/26.i2c_host_error_intr/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_fmt_empty.1507888250
Short name T1495
Test name
Test status
Simulation time 850422973 ps
CPU time 9.77 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:27:18 PM PDT 24
Peak memory 297792 kb
Host smart-aa7cffba-b700-4b94-a97c-45d48375a8cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507888250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_fmt_emp
ty.1507888250
Directory /workspace/26.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_full.3081475932
Short name T655
Test name
Test status
Simulation time 30269771225 ps
CPU time 105.48 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:28:56 PM PDT 24
Peak memory 885716 kb
Host smart-18192e5d-0848-410e-9e45-e4d269f3332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081475932 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_full.3081475932
Directory /workspace/26.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_overflow.967435695
Short name T643
Test name
Test status
Simulation time 1916988820 ps
CPU time 56.55 seconds
Started Jul 03 05:27:06 PM PDT 24
Finished Jul 03 05:28:03 PM PDT 24
Peak memory 673528 kb
Host smart-6e90f2b0-6ef8-444c-8c79-83ec0e529008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967435695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_overflow.967435695
Directory /workspace/26.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_fmt.486257319
Short name T1166
Test name
Test status
Simulation time 232700841 ps
CPU time 1.18 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:27:10 PM PDT 24
Peak memory 204472 kb
Host smart-2327de7b-6176-4e70-8c49-8a602b517f09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486257319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_fm
t.486257319
Directory /workspace/26.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_reset_rx.3419111290
Short name T156
Test name
Test status
Simulation time 2879257414 ps
CPU time 3.83 seconds
Started Jul 03 05:27:10 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 204892 kb
Host smart-0c31a9c1-f94a-4a50-98f5-14a270ad0b16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419111290 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_reset_rx
.3419111290
Directory /workspace/26.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/26.i2c_host_fifo_watermark.1119333228
Short name T947
Test name
Test status
Simulation time 2541468901 ps
CPU time 162.94 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:29:51 PM PDT 24
Peak memory 837660 kb
Host smart-112018a5-df34-44f6-93d5-85719b210629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119333228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_fifo_watermark.1119333228
Directory /workspace/26.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/26.i2c_host_may_nack.611794802
Short name T396
Test name
Test status
Simulation time 399567371 ps
CPU time 5.58 seconds
Started Jul 03 05:27:12 PM PDT 24
Finished Jul 03 05:27:18 PM PDT 24
Peak memory 204860 kb
Host smart-22628c80-74ca-499b-b024-428139ed26b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611794802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_may_nack.611794802
Directory /workspace/26.i2c_host_may_nack/latest

Test location /workspace/coverage/default/26.i2c_host_mode_toggle.178024796
Short name T1111
Test name
Test status
Simulation time 2469036811 ps
CPU time 113.74 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 05:29:08 PM PDT 24
Peak memory 386180 kb
Host smart-5201c050-7a00-4608-bf59-37bb1ac635d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178024796 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_mode_toggle.178024796
Directory /workspace/26.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/26.i2c_host_override.3489171367
Short name T133
Test name
Test status
Simulation time 34969258 ps
CPU time 0.74 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:27:00 PM PDT 24
Peak memory 204560 kb
Host smart-fe740b49-75ae-450c-af8a-cca34d255aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489171367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_override.3489171367
Directory /workspace/26.i2c_host_override/latest

Test location /workspace/coverage/default/26.i2c_host_perf.1146324601
Short name T975
Test name
Test status
Simulation time 3172186198 ps
CPU time 11.19 seconds
Started Jul 03 05:27:03 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 222392 kb
Host smart-4c192391-c612-40c8-bbec-5d67be38d308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146324601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf.1146324601
Directory /workspace/26.i2c_host_perf/latest

Test location /workspace/coverage/default/26.i2c_host_perf_precise.3073317811
Short name T782
Test name
Test status
Simulation time 6736429142 ps
CPU time 35.68 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 204760 kb
Host smart-91fb610a-8c4b-418f-8993-064163906d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073317811 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_perf_precise.3073317811
Directory /workspace/26.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/26.i2c_host_smoke.3133750930
Short name T792
Test name
Test status
Simulation time 3126957156 ps
CPU time 24.11 seconds
Started Jul 03 05:26:59 PM PDT 24
Finished Jul 03 05:27:24 PM PDT 24
Peak memory 291016 kb
Host smart-12a038a8-f5eb-4425-86f5-70bafa49ee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133750930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_smoke.3133750930
Directory /workspace/26.i2c_host_smoke/latest

Test location /workspace/coverage/default/26.i2c_host_stress_all.189806570
Short name T124
Test name
Test status
Simulation time 47332285082 ps
CPU time 494.52 seconds
Started Jul 03 05:27:06 PM PDT 24
Finished Jul 03 05:35:21 PM PDT 24
Peak memory 1878012 kb
Host smart-bd6b9d85-438b-42cd-93fc-1ad875c5b97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189806570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stress_all.189806570
Directory /workspace/26.i2c_host_stress_all/latest

Test location /workspace/coverage/default/26.i2c_host_stretch_timeout.547033228
Short name T999
Test name
Test status
Simulation time 943416541 ps
CPU time 20.1 seconds
Started Jul 03 05:27:06 PM PDT 24
Finished Jul 03 05:27:26 PM PDT 24
Peak memory 213044 kb
Host smart-a0a2fc40-02fa-4a9d-8366-8add929e285c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547033228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_host_stretch_timeout.547033228
Directory /workspace/26.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_bad_addr.1396108705
Short name T1136
Test name
Test status
Simulation time 777012766 ps
CPU time 3.91 seconds
Started Jul 03 05:27:05 PM PDT 24
Finished Jul 03 05:27:09 PM PDT 24
Peak memory 213004 kb
Host smart-16d2cef4-78eb-4060-b7da-695619d09d35
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396108705 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.i2c_target_bad_addr.1396108705
Directory /workspace/26.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_reset_tx.4213381660
Short name T901
Test name
Test status
Simulation time 355041844 ps
CPU time 1.31 seconds
Started Jul 03 05:27:10 PM PDT 24
Finished Jul 03 05:27:12 PM PDT 24
Peak memory 204492 kb
Host smart-97ac816e-950e-47ed-aa4a-37b8305e180d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213381660 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.i2c_target_fifo_reset_tx.4213381660
Directory /workspace/26.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_acq.1939345094
Short name T367
Test name
Test status
Simulation time 2493748243 ps
CPU time 2.42 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:14 PM PDT 24
Peak memory 204924 kb
Host smart-32168e8d-f4c2-4dfc-b2ff-9b94cb57e76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939345094 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.i2c_target_fifo_watermarks_acq.1939345094
Directory /workspace/26.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/26.i2c_target_fifo_watermarks_tx.1163328267
Short name T753
Test name
Test status
Simulation time 123257713 ps
CPU time 1.18 seconds
Started Jul 03 05:27:13 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 204620 kb
Host smart-c77d40e1-0065-47e2-8581-fb7871e8118f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163328267 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.i2c_target_fifo_watermarks_tx.1163328267
Directory /workspace/26.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/26.i2c_target_intr_smoke.3525043478
Short name T1336
Test name
Test status
Simulation time 5099433818 ps
CPU time 4.14 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:16 PM PDT 24
Peak memory 213160 kb
Host smart-79131dae-131f-4181-9401-9bdab14b109c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525043478 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 26.i2c_target_intr_smoke.3525043478
Directory /workspace/26.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_intr_stress_wr.3793874115
Short name T1454
Test name
Test status
Simulation time 20761138722 ps
CPU time 414.93 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:34:03 PM PDT 24
Peak memory 4992580 kb
Host smart-9f41a1b6-150d-4bed-bba5-2d4adbebf422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793874115 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.i2c_target_intr_stress_wr.3793874115
Directory /workspace/26.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_smoke.2311456475
Short name T651
Test name
Test status
Simulation time 1292424664 ps
CPU time 47.18 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:27:57 PM PDT 24
Peak memory 204816 kb
Host smart-56d9b286-f54f-468e-af05-40618c2d1060
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311456475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_ta
rget_smoke.2311456475
Directory /workspace/26.i2c_target_smoke/latest

Test location /workspace/coverage/default/26.i2c_target_stress_rd.3254915584
Short name T481
Test name
Test status
Simulation time 924515997 ps
CPU time 38.5 seconds
Started Jul 03 05:27:06 PM PDT 24
Finished Jul 03 05:27:45 PM PDT 24
Peak memory 204840 kb
Host smart-52621933-5323-4fbf-9068-44c86d3940ef
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254915584 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2
c_target_stress_rd.3254915584
Directory /workspace/26.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/26.i2c_target_stress_wr.229260845
Short name T1477
Test name
Test status
Simulation time 36515692405 ps
CPU time 27.73 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:27:36 PM PDT 24
Peak memory 636872 kb
Host smart-de7d1790-0fe1-4e2e-98d5-c1f49aff64ec
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229260845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c
_target_stress_wr.229260845
Directory /workspace/26.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/26.i2c_target_stretch.1811447112
Short name T677
Test name
Test status
Simulation time 8342487995 ps
CPU time 32.85 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:27:42 PM PDT 24
Peak memory 315696 kb
Host smart-5a880c6c-f805-4e0f-b35d-a8d48eb58102
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811447112 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.i2c_
target_stretch.1811447112
Directory /workspace/26.i2c_target_stretch/latest

Test location /workspace/coverage/default/26.i2c_target_timeout.4149941136
Short name T1232
Test name
Test status
Simulation time 3080524893 ps
CPU time 8.16 seconds
Started Jul 03 05:27:08 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 213164 kb
Host smart-ff01d7f3-c072-4496-a296-a1ede2ce6075
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149941136 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 26.i2c_target_timeout.4149941136
Directory /workspace/26.i2c_target_timeout/latest

Test location /workspace/coverage/default/26.i2c_target_tx_stretch_ctrl.318199449
Short name T1052
Test name
Test status
Simulation time 267250973 ps
CPU time 4.42 seconds
Started Jul 03 05:27:07 PM PDT 24
Finished Jul 03 05:27:12 PM PDT 24
Peak memory 204808 kb
Host smart-92faaf46-7fd8-4bac-86fb-0cbd4f9686aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318199449 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.i2c_target_tx_stretch_ctrl.318199449
Directory /workspace/26.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/27.i2c_alert_test.920785951
Short name T177
Test name
Test status
Simulation time 22105610 ps
CPU time 0.65 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 204460 kb
Host smart-3d0d0dd7-8187-436f-b598-f8608c0b20dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920785951 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_alert_test.920785951
Directory /workspace/27.i2c_alert_test/latest

Test location /workspace/coverage/default/27.i2c_host_error_intr.2611133022
Short name T612
Test name
Test status
Simulation time 190474871 ps
CPU time 4.28 seconds
Started Jul 03 05:27:13 PM PDT 24
Finished Jul 03 05:27:18 PM PDT 24
Peak memory 213144 kb
Host smart-bb718f1e-3fd8-4284-908b-c1928a469c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611133022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_error_intr.2611133022
Directory /workspace/27.i2c_host_error_intr/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_fmt_empty.2236606415
Short name T86
Test name
Test status
Simulation time 514800965 ps
CPU time 11.98 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:27:21 PM PDT 24
Peak memory 320512 kb
Host smart-62271b20-bcb4-457c-9d56-0980dad70228
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236606415 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_fmt_emp
ty.2236606415
Directory /workspace/27.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_full.3221971572
Short name T482
Test name
Test status
Simulation time 2899476098 ps
CPU time 109.28 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 567496 kb
Host smart-25daef12-a63f-4c7a-aa94-c92568235497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221971572 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_full.3221971572
Directory /workspace/27.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_overflow.3280895345
Short name T892
Test name
Test status
Simulation time 3431820200 ps
CPU time 46.87 seconds
Started Jul 03 05:27:24 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 625908 kb
Host smart-6c1572ba-8d3c-4570-b28c-72b3ddebcd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280895345 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_overflow.3280895345
Directory /workspace/27.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_fmt.4002581792
Short name T1011
Test name
Test status
Simulation time 86369037 ps
CPU time 0.86 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:12 PM PDT 24
Peak memory 204472 kb
Host smart-9749ac9f-7b34-4a83-a041-d437f0241c9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002581792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_f
mt.4002581792
Directory /workspace/27.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_reset_rx.3887131838
Short name T680
Test name
Test status
Simulation time 346175667 ps
CPU time 9.2 seconds
Started Jul 03 05:27:12 PM PDT 24
Finished Jul 03 05:27:22 PM PDT 24
Peak memory 204788 kb
Host smart-1162cc44-4a53-4ab1-b2e1-434582777117
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887131838 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_reset_rx
.3887131838
Directory /workspace/27.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/27.i2c_host_fifo_watermark.1442939632
Short name T332
Test name
Test status
Simulation time 12197948268 ps
CPU time 77.69 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 05:28:32 PM PDT 24
Peak memory 897928 kb
Host smart-b264a9cb-8f3d-48f8-98fa-71f9dc963721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442939632 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_fifo_watermark.1442939632
Directory /workspace/27.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/27.i2c_host_may_nack.794216163
Short name T357
Test name
Test status
Simulation time 333884912 ps
CPU time 7.39 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:19 PM PDT 24
Peak memory 204852 kb
Host smart-d63bf377-7f34-40da-a756-b705589d4102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794216163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_may_nack.794216163
Directory /workspace/27.i2c_host_may_nack/latest

Test location /workspace/coverage/default/27.i2c_host_mode_toggle.1695268720
Short name T1210
Test name
Test status
Simulation time 5628301896 ps
CPU time 24.28 seconds
Started Jul 03 05:27:23 PM PDT 24
Finished Jul 03 05:27:48 PM PDT 24
Peak memory 296876 kb
Host smart-6b366618-36ed-42b7-a5e4-3198f7da48e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695268720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_mode_toggle.1695268720
Directory /workspace/27.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/27.i2c_host_override.855737221
Short name T608
Test name
Test status
Simulation time 165685178 ps
CPU time 0.66 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:12 PM PDT 24
Peak memory 204552 kb
Host smart-4cd14907-4a84-4dc4-b47c-9957c0ab97cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855737221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_override.855737221
Directory /workspace/27.i2c_host_override/latest

Test location /workspace/coverage/default/27.i2c_host_perf.3321182070
Short name T712
Test name
Test status
Simulation time 1087597508 ps
CPU time 7.04 seconds
Started Jul 03 05:27:10 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 248628 kb
Host smart-7eb1d2ab-3eed-4c21-af15-de067b5cfcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321182070 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf.3321182070
Directory /workspace/27.i2c_host_perf/latest

Test location /workspace/coverage/default/27.i2c_host_perf_precise.848706656
Short name T515
Test name
Test status
Simulation time 5964779987 ps
CPU time 203.89 seconds
Started Jul 03 05:27:12 PM PDT 24
Finished Jul 03 05:30:36 PM PDT 24
Peak memory 1514700 kb
Host smart-172f8576-2bd5-425c-a60e-13baa99e5851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848706656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_perf_precise.848706656
Directory /workspace/27.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/27.i2c_host_smoke.2706464205
Short name T2
Test name
Test status
Simulation time 957434978 ps
CPU time 47.9 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:27:57 PM PDT 24
Peak memory 307192 kb
Host smart-53cde0ba-6618-4711-a428-abcd8f2b5a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706464205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_smoke.2706464205
Directory /workspace/27.i2c_host_smoke/latest

Test location /workspace/coverage/default/27.i2c_host_stress_all.3413813418
Short name T1157
Test name
Test status
Simulation time 5072974959 ps
CPU time 155.73 seconds
Started Jul 03 05:27:10 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 716380 kb
Host smart-de234aac-bd7f-4723-a5d9-5c148b9f3288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413813418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stress_all.3413813418
Directory /workspace/27.i2c_host_stress_all/latest

Test location /workspace/coverage/default/27.i2c_host_stretch_timeout.2508473185
Short name T263
Test name
Test status
Simulation time 1537898822 ps
CPU time 14.9 seconds
Started Jul 03 05:27:12 PM PDT 24
Finished Jul 03 05:27:27 PM PDT 24
Peak memory 229364 kb
Host smart-13a2bdfc-11c0-4db2-83f2-8cb4afc9d0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508473185 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_host_stretch_timeout.2508473185
Directory /workspace/27.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_bad_addr.2234532695
Short name T1363
Test name
Test status
Simulation time 1570849477 ps
CPU time 4.01 seconds
Started Jul 03 05:27:25 PM PDT 24
Finished Jul 03 05:27:29 PM PDT 24
Peak memory 204860 kb
Host smart-72f59e0a-5f9c-430a-aacb-4586a5b773e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234532695 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 27.i2c_target_bad_addr.2234532695
Directory /workspace/27.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_acq.2699541019
Short name T1461
Test name
Test status
Simulation time 188581574 ps
CPU time 1.27 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 05:27:11 PM PDT 24
Peak memory 204640 kb
Host smart-ded75094-31cd-499b-9af7-e65e91f7ca8a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699541019 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_fifo_reset_acq.2699541019
Directory /workspace/27.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_reset_tx.3232442486
Short name T570
Test name
Test status
Simulation time 330747841 ps
CPU time 0.91 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 204848 kb
Host smart-1f634788-57bc-4754-a8a0-2af0e9be1d3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232442486 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.i2c_target_fifo_reset_tx.3232442486
Directory /workspace/27.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_acq.3119981077
Short name T258
Test name
Test status
Simulation time 584067945 ps
CPU time 2.91 seconds
Started Jul 03 05:27:13 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 204800 kb
Host smart-4a439f9b-c0c0-4e96-9ce7-9bc4470825b1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119981077 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.i2c_target_fifo_watermarks_acq.3119981077
Directory /workspace/27.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/27.i2c_target_fifo_watermarks_tx.1197162344
Short name T934
Test name
Test status
Simulation time 609888314 ps
CPU time 1.27 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:13 PM PDT 24
Peak memory 204628 kb
Host smart-4f4e4abb-746b-4421-9ef9-4c3b5a733160
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197162344 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 27.i2c_target_fifo_watermarks_tx.1197162344
Directory /workspace/27.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/27.i2c_target_intr_smoke.2299113883
Short name T270
Test name
Test status
Simulation time 5101130962 ps
CPU time 6.42 seconds
Started Jul 03 05:27:10 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 204976 kb
Host smart-b91b3b47-1b51-48b1-8ee0-e2b560903639
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299113883 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 27.i2c_target_intr_smoke.2299113883
Directory /workspace/27.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_smoke.3434408189
Short name T551
Test name
Test status
Simulation time 734654924 ps
CPU time 10.1 seconds
Started Jul 03 05:27:06 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 204840 kb
Host smart-b45bd689-0888-4f0a-9d73-fd4dfdd161f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434408189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_ta
rget_smoke.3434408189
Directory /workspace/27.i2c_target_smoke/latest

Test location /workspace/coverage/default/27.i2c_target_stress_rd.989174322
Short name T1154
Test name
Test status
Simulation time 691344650 ps
CPU time 12.92 seconds
Started Jul 03 05:27:10 PM PDT 24
Finished Jul 03 05:27:24 PM PDT 24
Peak memory 206480 kb
Host smart-57f69520-47e7-4637-a0d0-0d53b07f1a0a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989174322 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c
_target_stress_rd.989174322
Directory /workspace/27.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/27.i2c_target_stress_wr.3541762228
Short name T946
Test name
Test status
Simulation time 68457075146 ps
CPU time 2368.8 seconds
Started Jul 03 05:27:09 PM PDT 24
Finished Jul 03 06:06:40 PM PDT 24
Peak memory 11344472 kb
Host smart-471b5b97-8d9b-44c9-9992-6e812e2f9be1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541762228 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2
c_target_stress_wr.3541762228
Directory /workspace/27.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/27.i2c_target_stretch.2638201528
Short name T566
Test name
Test status
Simulation time 34994784593 ps
CPU time 618.75 seconds
Started Jul 03 05:27:12 PM PDT 24
Finished Jul 03 05:37:32 PM PDT 24
Peak memory 4056016 kb
Host smart-3464abbd-082e-4c6b-bdff-2c48a68bab3e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638201528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.i2c_
target_stretch.2638201528
Directory /workspace/27.i2c_target_stretch/latest

Test location /workspace/coverage/default/27.i2c_target_timeout.3405347193
Short name T595
Test name
Test status
Simulation time 4118354584 ps
CPU time 7.83 seconds
Started Jul 03 05:27:13 PM PDT 24
Finished Jul 03 05:27:22 PM PDT 24
Peak memory 221104 kb
Host smart-b71f9f7b-5499-4bb4-aa6f-e09f998a9bd3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405347193 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 27.i2c_target_timeout.3405347193
Directory /workspace/27.i2c_target_timeout/latest

Test location /workspace/coverage/default/27.i2c_target_tx_stretch_ctrl.3844798630
Short name T20
Test name
Test status
Simulation time 157882408 ps
CPU time 3.22 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 205072 kb
Host smart-55d25b8f-4e12-4a8a-86f7-843ebdec0be0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844798630 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.i2c_target_tx_stretch_ctrl.3844798630
Directory /workspace/27.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/28.i2c_alert_test.2017833611
Short name T453
Test name
Test status
Simulation time 16373516 ps
CPU time 0.64 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 204460 kb
Host smart-7098800b-7612-4371-b970-5b946ff15cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017833611 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_alert_test.2017833611
Directory /workspace/28.i2c_alert_test/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_fmt_empty.2554755911
Short name T387
Test name
Test status
Simulation time 1289443035 ps
CPU time 5.4 seconds
Started Jul 03 05:27:12 PM PDT 24
Finished Jul 03 05:27:18 PM PDT 24
Peak memory 253688 kb
Host smart-c681b25b-2b05-4937-9c14-5353b2a3bb4a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554755911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_fmt_emp
ty.2554755911
Directory /workspace/28.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_full.3951644528
Short name T1196
Test name
Test status
Simulation time 2007206560 ps
CPU time 63.54 seconds
Started Jul 03 05:27:19 PM PDT 24
Finished Jul 03 05:28:23 PM PDT 24
Peak memory 706152 kb
Host smart-ed7eade1-b13b-48b0-b5d0-fc309ade53b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951644528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_full.3951644528
Directory /workspace/28.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_overflow.594328642
Short name T1417
Test name
Test status
Simulation time 2190130780 ps
CPU time 59.08 seconds
Started Jul 03 05:27:18 PM PDT 24
Finished Jul 03 05:28:18 PM PDT 24
Peak memory 619880 kb
Host smart-879160f5-9428-4dae-a9b3-aa8c0866cbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594328642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_overflow.594328642
Directory /workspace/28.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_fmt.2236456395
Short name T1230
Test name
Test status
Simulation time 219583528 ps
CPU time 0.94 seconds
Started Jul 03 05:27:10 PM PDT 24
Finished Jul 03 05:27:11 PM PDT 24
Peak memory 204456 kb
Host smart-c067db56-ee81-420c-99a8-c5a87ede229c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236456395 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_f
mt.2236456395
Directory /workspace/28.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_reset_rx.604885821
Short name T991
Test name
Test status
Simulation time 128405511 ps
CPU time 2.8 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:15 PM PDT 24
Peak memory 204812 kb
Host smart-c25c020c-ad78-44e0-a01a-f5ddf7d83398
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604885821 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_reset_rx.
604885821
Directory /workspace/28.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/28.i2c_host_fifo_watermark.4240115534
Short name T73
Test name
Test status
Simulation time 18864703704 ps
CPU time 121.59 seconds
Started Jul 03 05:27:25 PM PDT 24
Finished Jul 03 05:29:27 PM PDT 24
Peak memory 1380992 kb
Host smart-cfc6614e-fb64-4ba9-a583-2060bb701454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240115534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_fifo_watermark.4240115534
Directory /workspace/28.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/28.i2c_host_may_nack.1901135360
Short name T1315
Test name
Test status
Simulation time 2034294522 ps
CPU time 18.78 seconds
Started Jul 03 05:27:27 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 204864 kb
Host smart-dd4f91a1-acc5-4dc5-9417-a4ed846621c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901135360 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_may_nack.1901135360
Directory /workspace/28.i2c_host_may_nack/latest

Test location /workspace/coverage/default/28.i2c_host_mode_toggle.1767053764
Short name T1095
Test name
Test status
Simulation time 2569711782 ps
CPU time 48.26 seconds
Started Jul 03 05:27:22 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 269756 kb
Host smart-5c03d691-16e9-41d0-abe2-7ff587816068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767053764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_mode_toggle.1767053764
Directory /workspace/28.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/28.i2c_host_override.1626853968
Short name T1079
Test name
Test status
Simulation time 47731810 ps
CPU time 0.68 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:13 PM PDT 24
Peak memory 204544 kb
Host smart-b92243c5-2897-41bf-beb4-23d12baa9b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626853968 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_override.1626853968
Directory /workspace/28.i2c_host_override/latest

Test location /workspace/coverage/default/28.i2c_host_perf.4251526088
Short name T871
Test name
Test status
Simulation time 12912198442 ps
CPU time 136.34 seconds
Started Jul 03 05:27:12 PM PDT 24
Finished Jul 03 05:29:29 PM PDT 24
Peak memory 218924 kb
Host smart-1e13ccda-4814-4c30-81eb-ec7eecf436be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251526088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf.4251526088
Directory /workspace/28.i2c_host_perf/latest

Test location /workspace/coverage/default/28.i2c_host_perf_precise.3089956479
Short name T689
Test name
Test status
Simulation time 183800151 ps
CPU time 1.08 seconds
Started Jul 03 05:27:15 PM PDT 24
Finished Jul 03 05:27:17 PM PDT 24
Peak memory 222192 kb
Host smart-d23a1aa2-5261-4073-a519-e7c6f2a27856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089956479 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_perf_precise.3089956479
Directory /workspace/28.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/28.i2c_host_smoke.1205044009
Short name T604
Test name
Test status
Simulation time 3198212280 ps
CPU time 23.82 seconds
Started Jul 03 05:27:15 PM PDT 24
Finished Jul 03 05:27:39 PM PDT 24
Peak memory 307888 kb
Host smart-b856f4cc-efd2-4573-97e7-e500fa055dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205044009 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_smoke.1205044009
Directory /workspace/28.i2c_host_smoke/latest

Test location /workspace/coverage/default/28.i2c_host_stress_all.941597310
Short name T109
Test name
Test status
Simulation time 32451554690 ps
CPU time 2070.75 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 06:01:46 PM PDT 24
Peak memory 5362128 kb
Host smart-723cb886-b2a1-41bd-8979-f5efc8681459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941597310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stress_all.941597310
Directory /workspace/28.i2c_host_stress_all/latest

Test location /workspace/coverage/default/28.i2c_host_stretch_timeout.381839815
Short name T1092
Test name
Test status
Simulation time 1075010464 ps
CPU time 19.2 seconds
Started Jul 03 05:27:11 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 219348 kb
Host smart-4baa5a29-78e6-42ff-a2bb-4d23a0ec8b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381839815 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_host_stretch_timeout.381839815
Directory /workspace/28.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_bad_addr.2274429211
Short name T846
Test name
Test status
Simulation time 973576288 ps
CPU time 4.74 seconds
Started Jul 03 05:27:22 PM PDT 24
Finished Jul 03 05:27:27 PM PDT 24
Peak memory 204832 kb
Host smart-91e64103-3cb3-4474-81e9-9cdcd2270552
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274429211 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.i2c_target_bad_addr.2274429211
Directory /workspace/28.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_acq.3003712846
Short name T1032
Test name
Test status
Simulation time 138740230 ps
CPU time 0.96 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204456 kb
Host smart-c0dc1bf6-0ee5-4fbb-bc84-2f5c3658fa7e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003712846 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_fifo_reset_acq.3003712846
Directory /workspace/28.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_reset_tx.712395789
Short name T12
Test name
Test status
Simulation time 221953090 ps
CPU time 1.27 seconds
Started Jul 03 05:27:22 PM PDT 24
Finished Jul 03 05:27:24 PM PDT 24
Peak memory 205008 kb
Host smart-e668f53b-2da0-457c-908c-7c4b3421af67
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712395789 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.i2c_target_fifo_reset_tx.712395789
Directory /workspace/28.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_acq.68054811
Short name T1465
Test name
Test status
Simulation time 1007654950 ps
CPU time 2.59 seconds
Started Jul 03 05:27:15 PM PDT 24
Finished Jul 03 05:27:18 PM PDT 24
Peak memory 204844 kb
Host smart-706d1e33-d38c-464a-93da-ef276cec3df6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68054811 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.i2c_target_fifo_watermarks_acq.68054811
Directory /workspace/28.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/28.i2c_target_fifo_watermarks_tx.2242102972
Short name T686
Test name
Test status
Simulation time 215315545 ps
CPU time 1.06 seconds
Started Jul 03 05:27:20 PM PDT 24
Finished Jul 03 05:27:21 PM PDT 24
Peak memory 204588 kb
Host smart-063b04c6-eb3a-44f0-8e9a-e579aa45a7a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242102972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 28.i2c_target_fifo_watermarks_tx.2242102972
Directory /workspace/28.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/28.i2c_target_hrst.4211648601
Short name T1376
Test name
Test status
Simulation time 681783565 ps
CPU time 4.8 seconds
Started Jul 03 05:27:26 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 204784 kb
Host smart-0ee9e865-937a-40d4-8221-6fc2491b5bab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211648601 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 28.i2c_target_hrst.4211648601
Directory /workspace/28.i2c_target_hrst/latest

Test location /workspace/coverage/default/28.i2c_target_intr_smoke.1423695980
Short name T428
Test name
Test status
Simulation time 5464662091 ps
CPU time 7.05 seconds
Started Jul 03 05:27:21 PM PDT 24
Finished Jul 03 05:27:29 PM PDT 24
Peak memory 204976 kb
Host smart-101ecd1f-f591-4035-9dce-a6686ecbe585
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423695980 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_intr_smoke.1423695980
Directory /workspace/28.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_intr_stress_wr.3580537679
Short name T977
Test name
Test status
Simulation time 19066261614 ps
CPU time 29.92 seconds
Started Jul 03 05:27:16 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 585068 kb
Host smart-0a6509dd-1c07-4988-8364-873a3f3a6d1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580537679 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.i2c_target_intr_stress_wr.3580537679
Directory /workspace/28.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_smoke.1091482344
Short name T1108
Test name
Test status
Simulation time 2308979249 ps
CPU time 16.02 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 204760 kb
Host smart-a9452543-73a1-4ce0-a493-58bbe0d99816
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091482344 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_ta
rget_smoke.1091482344
Directory /workspace/28.i2c_target_smoke/latest

Test location /workspace/coverage/default/28.i2c_target_stress_rd.1132781080
Short name T488
Test name
Test status
Simulation time 5275472564 ps
CPU time 55.42 seconds
Started Jul 03 05:27:10 PM PDT 24
Finished Jul 03 05:28:06 PM PDT 24
Peak memory 206316 kb
Host smart-f2b9fa3a-eae1-4ca3-9574-f17acffa4d17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132781080 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_rd.1132781080
Directory /workspace/28.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/28.i2c_target_stress_wr.3468382294
Short name T376
Test name
Test status
Simulation time 13494425084 ps
CPU time 8.45 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 05:27:23 PM PDT 24
Peak memory 204904 kb
Host smart-c7fd0602-d31b-4f35-8aa7-8dadb59a5844
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468382294 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2
c_target_stress_wr.3468382294
Directory /workspace/28.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/28.i2c_target_stretch.3721661100
Short name T949
Test name
Test status
Simulation time 15044432630 ps
CPU time 2135.11 seconds
Started Jul 03 05:27:13 PM PDT 24
Finished Jul 03 06:02:49 PM PDT 24
Peak memory 3596964 kb
Host smart-6148814a-3de5-496a-b3ad-d20f5877d9a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721661100 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.i2c_
target_stretch.3721661100
Directory /workspace/28.i2c_target_stretch/latest

Test location /workspace/coverage/default/28.i2c_target_timeout.300220957
Short name T773
Test name
Test status
Simulation time 2968486319 ps
CPU time 7.11 seconds
Started Jul 03 05:27:14 PM PDT 24
Finished Jul 03 05:27:22 PM PDT 24
Peak memory 204928 kb
Host smart-47602514-2675-4cbc-bf6f-6802cf783b6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300220957 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 28.i2c_target_timeout.300220957
Directory /workspace/28.i2c_target_timeout/latest

Test location /workspace/coverage/default/28.i2c_target_tx_stretch_ctrl.4025287862
Short name T1464
Test name
Test status
Simulation time 583297627 ps
CPU time 7.39 seconds
Started Jul 03 05:27:22 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 204828 kb
Host smart-f52f7579-4fef-4062-8f21-ea5245628693
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025287862 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.i2c_target_tx_stretch_ctrl.4025287862
Directory /workspace/28.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/29.i2c_alert_test.3053218620
Short name T879
Test name
Test status
Simulation time 18904235 ps
CPU time 0.64 seconds
Started Jul 03 05:27:21 PM PDT 24
Finished Jul 03 05:27:27 PM PDT 24
Peak memory 204460 kb
Host smart-13cc8828-4d38-4d97-bef5-5cc9de151fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053218620 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_alert_test.3053218620
Directory /workspace/29.i2c_alert_test/latest

Test location /workspace/coverage/default/29.i2c_host_error_intr.2847125304
Short name T1316
Test name
Test status
Simulation time 612117533 ps
CPU time 3.44 seconds
Started Jul 03 05:27:24 PM PDT 24
Finished Jul 03 05:27:28 PM PDT 24
Peak memory 213092 kb
Host smart-c126403b-9b26-4109-a241-5f3c08fe8805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847125304 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_error_intr.2847125304
Directory /workspace/29.i2c_host_error_intr/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_fmt_empty.2167763187
Short name T1319
Test name
Test status
Simulation time 1312319828 ps
CPU time 18.25 seconds
Started Jul 03 05:27:23 PM PDT 24
Finished Jul 03 05:27:41 PM PDT 24
Peak memory 278344 kb
Host smart-52c595e7-cbe1-4c9a-b37d-d793dc3d6977
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167763187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_fmt_emp
ty.2167763187
Directory /workspace/29.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_full.4014771823
Short name T1102
Test name
Test status
Simulation time 2066095528 ps
CPU time 48.83 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:28:19 PM PDT 24
Peak memory 355628 kb
Host smart-78de143c-6a84-4ac5-8361-9b80203c38c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014771823 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_full.4014771823
Directory /workspace/29.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_overflow.1898015189
Short name T1034
Test name
Test status
Simulation time 3362034623 ps
CPU time 48.42 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:28:17 PM PDT 24
Peak memory 614660 kb
Host smart-5d6c1364-44fe-4954-8f18-f755c0aaea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898015189 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_overflow.1898015189
Directory /workspace/29.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_fmt.2282153371
Short name T1185
Test name
Test status
Simulation time 511690500 ps
CPU time 0.98 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 204468 kb
Host smart-83e32ff2-dc6d-445e-8ad0-5f4c41ee2c7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282153371 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_f
mt.2282153371
Directory /workspace/29.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_reset_rx.3670736808
Short name T491
Test name
Test status
Simulation time 183186216 ps
CPU time 9.33 seconds
Started Jul 03 05:27:26 PM PDT 24
Finished Jul 03 05:27:35 PM PDT 24
Peak memory 204812 kb
Host smart-ed9b908c-54d5-4d62-8d5e-eac43188c518
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670736808 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_reset_rx
.3670736808
Directory /workspace/29.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/29.i2c_host_fifo_watermark.1364712830
Short name T1255
Test name
Test status
Simulation time 2737140534 ps
CPU time 60.06 seconds
Started Jul 03 05:27:21 PM PDT 24
Finished Jul 03 05:28:21 PM PDT 24
Peak memory 857120 kb
Host smart-a12e405d-6952-4761-9416-5c3b892e627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364712830 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_fifo_watermark.1364712830
Directory /workspace/29.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/29.i2c_host_may_nack.613859286
Short name T1165
Test name
Test status
Simulation time 3819237760 ps
CPU time 9.42 seconds
Started Jul 03 05:27:20 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 204920 kb
Host smart-7dfe4d05-ca0b-4f8f-aaf5-c4ef4de9a55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613859286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_may_nack.613859286
Directory /workspace/29.i2c_host_may_nack/latest

Test location /workspace/coverage/default/29.i2c_host_mode_toggle.3537865912
Short name T34
Test name
Test status
Simulation time 2159363614 ps
CPU time 97.03 seconds
Started Jul 03 05:27:16 PM PDT 24
Finished Jul 03 05:28:54 PM PDT 24
Peak memory 335160 kb
Host smart-acb682b9-0d40-48fd-883e-64022f7dbc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537865912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_mode_toggle.3537865912
Directory /workspace/29.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/29.i2c_host_override.825818924
Short name T1101
Test name
Test status
Simulation time 25100464 ps
CPU time 0.66 seconds
Started Jul 03 05:27:15 PM PDT 24
Finished Jul 03 05:27:16 PM PDT 24
Peak memory 204528 kb
Host smart-804ee0f1-ad12-4264-a896-c826af74925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825818924 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_override.825818924
Directory /workspace/29.i2c_host_override/latest

Test location /workspace/coverage/default/29.i2c_host_perf_precise.3063803286
Short name T1207
Test name
Test status
Simulation time 6929956272 ps
CPU time 27.08 seconds
Started Jul 03 05:27:18 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 204820 kb
Host smart-dc6f17fd-22b0-48da-9da1-0195785e1c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063803286 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_perf_precise.3063803286
Directory /workspace/29.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/29.i2c_host_smoke.3712198949
Short name T1496
Test name
Test status
Simulation time 1340488736 ps
CPU time 59.28 seconds
Started Jul 03 05:27:17 PM PDT 24
Finished Jul 03 05:28:17 PM PDT 24
Peak memory 298600 kb
Host smart-13f2143d-f860-48ab-8117-d3490fd985fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712198949 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_smoke.3712198949
Directory /workspace/29.i2c_host_smoke/latest

Test location /workspace/coverage/default/29.i2c_host_stress_all.2292292994
Short name T123
Test name
Test status
Simulation time 27962859316 ps
CPU time 68.49 seconds
Started Jul 03 05:27:22 PM PDT 24
Finished Jul 03 05:28:30 PM PDT 24
Peak memory 608892 kb
Host smart-49c7ecab-f2ab-41f6-976f-716273db71b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292292994 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stress_all.2292292994
Directory /workspace/29.i2c_host_stress_all/latest

Test location /workspace/coverage/default/29.i2c_host_stretch_timeout.2981101701
Short name T727
Test name
Test status
Simulation time 1380104207 ps
CPU time 29.57 seconds
Started Jul 03 05:27:18 PM PDT 24
Finished Jul 03 05:27:48 PM PDT 24
Peak memory 213016 kb
Host smart-ce218a10-5b91-47ff-98a5-fc39023c8ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981101701 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_host_stretch_timeout.2981101701
Directory /workspace/29.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_bad_addr.1814763498
Short name T1449
Test name
Test status
Simulation time 4254029127 ps
CPU time 5.58 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:27:35 PM PDT 24
Peak memory 214176 kb
Host smart-76ffc3e0-f439-4420-b146-72db2a70fa3f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814763498 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.i2c_target_bad_addr.1814763498
Directory /workspace/29.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_acq.2856166377
Short name T692
Test name
Test status
Simulation time 257004093 ps
CPU time 1.42 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 204820 kb
Host smart-2651897a-3c61-4657-8fad-e6ad2a01f888
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856166377 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_fifo_reset_acq.2856166377
Directory /workspace/29.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_reset_tx.3204529813
Short name T1508
Test name
Test status
Simulation time 299001158 ps
CPU time 1.15 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 204632 kb
Host smart-35c99c3a-3e75-4547-856d-f70389188d5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204529813 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.i2c_target_fifo_reset_tx.3204529813
Directory /workspace/29.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_acq.1689836120
Short name T1402
Test name
Test status
Simulation time 9172613468 ps
CPU time 2.55 seconds
Started Jul 03 05:27:21 PM PDT 24
Finished Jul 03 05:27:24 PM PDT 24
Peak memory 204984 kb
Host smart-6a1828d3-856b-44bd-93ff-01464dad6d83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689836120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.i2c_target_fifo_watermarks_acq.1689836120
Directory /workspace/29.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/29.i2c_target_fifo_watermarks_tx.2643662301
Short name T7
Test name
Test status
Simulation time 664818676 ps
CPU time 1.13 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204588 kb
Host smart-2596c97f-1d1e-4fa1-b041-fc2cd17e0995
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643662301 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.i2c_target_fifo_watermarks_tx.2643662301
Directory /workspace/29.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/29.i2c_target_intr_smoke.351254555
Short name T208
Test name
Test status
Simulation time 1373764990 ps
CPU time 4.21 seconds
Started Jul 03 05:27:27 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 213060 kb
Host smart-f91d0e01-c088-416d-8928-1d5f8d0a106d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351254555 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 29.i2c_target_intr_smoke.351254555
Directory /workspace/29.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_intr_stress_wr.2355329180
Short name T1497
Test name
Test status
Simulation time 2482009298 ps
CPU time 19.23 seconds
Started Jul 03 05:27:17 PM PDT 24
Finished Jul 03 05:27:37 PM PDT 24
Peak memory 762612 kb
Host smart-e980fc32-200f-450b-9d3b-68b44a0ecb1e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355329180 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.i2c_target_intr_stress_wr.2355329180
Directory /workspace/29.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_smoke.852621651
Short name T1361
Test name
Test status
Simulation time 1449260144 ps
CPU time 12.54 seconds
Started Jul 03 05:27:20 PM PDT 24
Finished Jul 03 05:27:33 PM PDT 24
Peak memory 204780 kb
Host smart-8a1c3205-eab9-408a-a69e-e9e2caeb4582
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852621651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_tar
get_smoke.852621651
Directory /workspace/29.i2c_target_smoke/latest

Test location /workspace/coverage/default/29.i2c_target_stress_rd.1599044984
Short name T289
Test name
Test status
Simulation time 779899878 ps
CPU time 4.35 seconds
Started Jul 03 05:27:27 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204776 kb
Host smart-01bcbafe-17ef-4dcb-b467-1453112cd879
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599044984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_rd.1599044984
Directory /workspace/29.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/29.i2c_target_stress_wr.2378407066
Short name T1240
Test name
Test status
Simulation time 29793109042 ps
CPU time 32.38 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 704400 kb
Host smart-7337dfd4-2087-46f9-a453-5262367f4c71
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378407066 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2
c_target_stress_wr.2378407066
Directory /workspace/29.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/29.i2c_target_stretch.1949579074
Short name T173
Test name
Test status
Simulation time 20248920538 ps
CPU time 340.2 seconds
Started Jul 03 05:27:21 PM PDT 24
Finished Jul 03 05:33:01 PM PDT 24
Peak memory 1214936 kb
Host smart-0703b4e3-9e2d-405c-a37d-d3e951f4135f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949579074 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.i2c_
target_stretch.1949579074
Directory /workspace/29.i2c_target_stretch/latest

Test location /workspace/coverage/default/29.i2c_target_timeout.1098901139
Short name T768
Test name
Test status
Simulation time 1299321141 ps
CPU time 6.58 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:27:36 PM PDT 24
Peak memory 213020 kb
Host smart-76f43d9c-dc99-41f5-92eb-7fd5b3e1a9cf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098901139 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 29.i2c_target_timeout.1098901139
Directory /workspace/29.i2c_target_timeout/latest

Test location /workspace/coverage/default/29.i2c_target_tx_stretch_ctrl.3312807784
Short name T1499
Test name
Test status
Simulation time 454778974 ps
CPU time 6.11 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:37 PM PDT 24
Peak memory 204748 kb
Host smart-21bfd24c-f10f-4c56-b8b2-e45a6cae4ab9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312807784 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.i2c_target_tx_stretch_ctrl.3312807784
Directory /workspace/29.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/3.i2c_alert_test.4103345725
Short name T1490
Test name
Test status
Simulation time 24309659 ps
CPU time 0.7 seconds
Started Jul 03 05:25:14 PM PDT 24
Finished Jul 03 05:25:15 PM PDT 24
Peak memory 204348 kb
Host smart-8f7e7e65-c46e-44dc-a366-8f2a4d3f0645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103345725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_alert_test.4103345725
Directory /workspace/3.i2c_alert_test/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_fmt_empty.2789286702
Short name T898
Test name
Test status
Simulation time 475298260 ps
CPU time 23.65 seconds
Started Jul 03 05:25:10 PM PDT 24
Finished Jul 03 05:25:34 PM PDT 24
Peak memory 287856 kb
Host smart-836a1599-139c-4a45-9caf-b77d3f4d6f13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789286702 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_fmt_empt
y.2789286702
Directory /workspace/3.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_full.601652930
Short name T1378
Test name
Test status
Simulation time 10864171735 ps
CPU time 200.39 seconds
Started Jul 03 05:25:12 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 820112 kb
Host smart-1c288107-d1b9-49e9-9281-00304752f65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601652930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_full.601652930
Directory /workspace/3.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_overflow.809785067
Short name T352
Test name
Test status
Simulation time 2140580217 ps
CPU time 70.44 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:26:34 PM PDT 24
Peak memory 708524 kb
Host smart-85868e37-5ea2-40db-b48f-8fcef3fdc5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809785067 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_overflow.809785067
Directory /workspace/3.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_fmt.3960343859
Short name T891
Test name
Test status
Simulation time 1366739794 ps
CPU time 1 seconds
Started Jul 03 05:25:12 PM PDT 24
Finished Jul 03 05:25:13 PM PDT 24
Peak memory 204344 kb
Host smart-17ae232f-482d-4f0d-b429-6a256ca793f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960343859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_fm
t.3960343859
Directory /workspace/3.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_reset_rx.3328240869
Short name T1170
Test name
Test status
Simulation time 395535522 ps
CPU time 5 seconds
Started Jul 03 05:25:10 PM PDT 24
Finished Jul 03 05:25:16 PM PDT 24
Peak memory 204796 kb
Host smart-20288e9a-05a2-47cd-ac59-8809614fc835
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328240869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_reset_rx.
3328240869
Directory /workspace/3.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/3.i2c_host_fifo_watermark.2820227277
Short name T111
Test name
Test status
Simulation time 11221702963 ps
CPU time 158.75 seconds
Started Jul 03 05:25:20 PM PDT 24
Finished Jul 03 05:27:59 PM PDT 24
Peak memory 1608060 kb
Host smart-b07cb85a-6f97-4c8e-8998-3e12aed7fa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820227277 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_fifo_watermark.2820227277
Directory /workspace/3.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/3.i2c_host_may_nack.2199877324
Short name T1091
Test name
Test status
Simulation time 1662170895 ps
CPU time 6.05 seconds
Started Jul 03 05:25:26 PM PDT 24
Finished Jul 03 05:25:32 PM PDT 24
Peak memory 204844 kb
Host smart-3f8de995-073d-4d3e-9458-e12c417b7b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199877324 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_may_nack.2199877324
Directory /workspace/3.i2c_host_may_nack/latest

Test location /workspace/coverage/default/3.i2c_host_mode_toggle.3488854638
Short name T65
Test name
Test status
Simulation time 5426290782 ps
CPU time 28.38 seconds
Started Jul 03 05:25:17 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 383720 kb
Host smart-f8d7853c-74a8-48e2-a051-c784811340fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488854638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_mode_toggle.3488854638
Directory /workspace/3.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/3.i2c_host_override.1337903268
Short name T1067
Test name
Test status
Simulation time 48975638 ps
CPU time 0.66 seconds
Started Jul 03 05:25:16 PM PDT 24
Finished Jul 03 05:25:17 PM PDT 24
Peak memory 204516 kb
Host smart-802422ea-c19b-4b9f-93fc-68988d598c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337903268 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_override.1337903268
Directory /workspace/3.i2c_host_override/latest

Test location /workspace/coverage/default/3.i2c_host_perf_precise.1525290847
Short name T1475
Test name
Test status
Simulation time 24425276222 ps
CPU time 206.51 seconds
Started Jul 03 05:25:22 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 204824 kb
Host smart-bbd2f2db-6de6-4204-87cf-be5db03527a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525290847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_perf_precise.1525290847
Directory /workspace/3.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/3.i2c_host_smoke.596311736
Short name T302
Test name
Test status
Simulation time 4090197716 ps
CPU time 33.08 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:25:56 PM PDT 24
Peak memory 435248 kb
Host smart-84c9d29d-0e9a-468f-9637-e4abc47bc7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596311736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_smoke.596311736
Directory /workspace/3.i2c_host_smoke/latest

Test location /workspace/coverage/default/3.i2c_host_stress_all.4257535307
Short name T941
Test name
Test status
Simulation time 13054105535 ps
CPU time 436.36 seconds
Started Jul 03 05:25:26 PM PDT 24
Finished Jul 03 05:32:43 PM PDT 24
Peak memory 2240572 kb
Host smart-b658df0e-396b-4f67-8e09-a599b9836797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257535307 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stress_all.4257535307
Directory /workspace/3.i2c_host_stress_all/latest

Test location /workspace/coverage/default/3.i2c_host_stretch_timeout.2303308650
Short name T657
Test name
Test status
Simulation time 1230401516 ps
CPU time 25.95 seconds
Started Jul 03 05:25:13 PM PDT 24
Finished Jul 03 05:25:39 PM PDT 24
Peak memory 213040 kb
Host smart-d776092a-3859-4d8c-99a6-84f3f381da3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303308650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_host_stretch_timeout.2303308650
Directory /workspace/3.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/3.i2c_sec_cm.2933041681
Short name T182
Test name
Test status
Simulation time 63124527 ps
CPU time 0.85 seconds
Started Jul 03 05:25:16 PM PDT 24
Finished Jul 03 05:25:17 PM PDT 24
Peak memory 222236 kb
Host smart-c0721a6c-221f-4982-b035-5e3b7d8c4d4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933041681 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_sec_cm.2933041681
Directory /workspace/3.i2c_sec_cm/latest

Test location /workspace/coverage/default/3.i2c_target_bad_addr.319766251
Short name T806
Test name
Test status
Simulation time 1791872954 ps
CPU time 4.69 seconds
Started Jul 03 05:25:14 PM PDT 24
Finished Jul 03 05:25:19 PM PDT 24
Peak memory 213016 kb
Host smart-f44d6f61-cd12-4420-aeab-fb9f4d5018ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319766251 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.i2c_target_bad_addr.319766251
Directory /workspace/3.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_acq.3758291091
Short name T162
Test name
Test status
Simulation time 198139913 ps
CPU time 1.22 seconds
Started Jul 03 05:25:13 PM PDT 24
Finished Jul 03 05:25:15 PM PDT 24
Peak memory 204784 kb
Host smart-d8bdd816-0506-4276-82ac-019bac8914ce
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758291091 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_fifo_reset_acq.3758291091
Directory /workspace/3.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_reset_tx.2079364677
Short name T824
Test name
Test status
Simulation time 745276313 ps
CPU time 1.36 seconds
Started Jul 03 05:25:26 PM PDT 24
Finished Jul 03 05:25:28 PM PDT 24
Peak memory 205824 kb
Host smart-0b1a2b0e-190a-45d6-b102-2fdf99dfc590
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079364677 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.i2c_target_fifo_reset_tx.2079364677
Directory /workspace/3.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_acq.3770999919
Short name T447
Test name
Test status
Simulation time 389956059 ps
CPU time 2.12 seconds
Started Jul 03 05:25:14 PM PDT 24
Finished Jul 03 05:25:17 PM PDT 24
Peak memory 204784 kb
Host smart-529ab070-76de-4fb2-8fd8-dac897704e30
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770999919 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.i2c_target_fifo_watermarks_acq.3770999919
Directory /workspace/3.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/3.i2c_target_fifo_watermarks_tx.3765570683
Short name T1182
Test name
Test status
Simulation time 169512027 ps
CPU time 0.88 seconds
Started Jul 03 05:25:27 PM PDT 24
Finished Jul 03 05:25:28 PM PDT 24
Peak memory 204624 kb
Host smart-c991a989-8612-4f54-8e58-ef599eb59745
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765570683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.i2c_target_fifo_watermarks_tx.3765570683
Directory /workspace/3.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/3.i2c_target_hrst.1885090261
Short name T1472
Test name
Test status
Simulation time 352600158 ps
CPU time 3.87 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:25:28 PM PDT 24
Peak memory 204792 kb
Host smart-5c486b9a-2c05-4be5-9103-13ed64e53df1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885090261 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 3.i2c_target_hrst.1885090261
Directory /workspace/3.i2c_target_hrst/latest

Test location /workspace/coverage/default/3.i2c_target_intr_smoke.2482820761
Short name T1177
Test name
Test status
Simulation time 12942403190 ps
CPU time 6.04 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:25:31 PM PDT 24
Peak memory 204972 kb
Host smart-576d6e5f-66c4-4228-ade8-98b74b261e86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482820761 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 3.i2c_target_intr_smoke.2482820761
Directory /workspace/3.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/3.i2c_target_intr_stress_wr.1162127875
Short name T445
Test name
Test status
Simulation time 2745072694 ps
CPU time 3.85 seconds
Started Jul 03 05:25:18 PM PDT 24
Finished Jul 03 05:25:22 PM PDT 24
Peak memory 204880 kb
Host smart-37c83583-e578-4c3e-a768-d4f3296524bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162127875 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.i2c_target_intr_stress_wr.1162127875
Directory /workspace/3.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stress_rd.783201588
Short name T974
Test name
Test status
Simulation time 5769185356 ps
CPU time 37.35 seconds
Started Jul 03 05:25:12 PM PDT 24
Finished Jul 03 05:25:49 PM PDT 24
Peak memory 205008 kb
Host smart-c219ce52-9253-4f74-93a5-b2b718764b8c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783201588 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_rd.783201588
Directory /workspace/3.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/3.i2c_target_stress_wr.286443930
Short name T413
Test name
Test status
Simulation time 20185696661 ps
CPU time 19.07 seconds
Started Jul 03 05:25:15 PM PDT 24
Finished Jul 03 05:25:34 PM PDT 24
Peak memory 204968 kb
Host smart-13fd2410-bf62-4b5e-836b-819003e09f83
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286443930 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_
target_stress_wr.286443930
Directory /workspace/3.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/3.i2c_target_stretch.2189133955
Short name T811
Test name
Test status
Simulation time 12799977119 ps
CPU time 74.26 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:26:38 PM PDT 24
Peak memory 851636 kb
Host smart-3c6f718a-f454-42a9-add0-102c9b96c6ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189133955 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.i2c_t
arget_stretch.2189133955
Directory /workspace/3.i2c_target_stretch/latest

Test location /workspace/coverage/default/3.i2c_target_timeout.2985417031
Short name T697
Test name
Test status
Simulation time 4322928428 ps
CPU time 6.37 seconds
Started Jul 03 05:25:13 PM PDT 24
Finished Jul 03 05:25:20 PM PDT 24
Peak memory 204984 kb
Host smart-23b0b5c5-8c6e-4044-812f-02d13b09fc4b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985417031 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.i2c_target_timeout.2985417031
Directory /workspace/3.i2c_target_timeout/latest

Test location /workspace/coverage/default/3.i2c_target_tx_stretch_ctrl.3544633158
Short name T582
Test name
Test status
Simulation time 193985417 ps
CPU time 3.23 seconds
Started Jul 03 05:25:14 PM PDT 24
Finished Jul 03 05:25:17 PM PDT 24
Peak memory 204748 kb
Host smart-33ea12a7-5a30-4fee-ae31-3a3c0bc82ea0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544633158 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.i2c_target_tx_stretch_ctrl.3544633158
Directory /workspace/3.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/30.i2c_alert_test.752225262
Short name T1350
Test name
Test status
Simulation time 16991206 ps
CPU time 0.67 seconds
Started Jul 03 05:27:37 PM PDT 24
Finished Jul 03 05:27:38 PM PDT 24
Peak memory 204432 kb
Host smart-afd51a0f-ae8b-4ca9-8092-ab77297688e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752225262 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_alert_test.752225262
Directory /workspace/30.i2c_alert_test/latest

Test location /workspace/coverage/default/30.i2c_host_error_intr.967354380
Short name T1404
Test name
Test status
Simulation time 449639738 ps
CPU time 2.75 seconds
Started Jul 03 05:27:23 PM PDT 24
Finished Jul 03 05:27:26 PM PDT 24
Peak memory 229544 kb
Host smart-81fb8ab5-8d2b-476c-a7bb-534c1508699a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967354380 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_error_intr.967354380
Directory /workspace/30.i2c_host_error_intr/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_fmt_empty.1972345750
Short name T1168
Test name
Test status
Simulation time 1369573766 ps
CPU time 17.46 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 251704 kb
Host smart-ba02bcf6-afd7-422b-8d06-f3ee7d1ee133
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972345750 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_fmt_emp
ty.1972345750
Directory /workspace/30.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_full.49383980
Short name T961
Test name
Test status
Simulation time 23893064833 ps
CPU time 39.92 seconds
Started Jul 03 05:27:20 PM PDT 24
Finished Jul 03 05:28:01 PM PDT 24
Peak memory 437604 kb
Host smart-a1fc55d4-52f8-4edd-8d6f-e2738a0e1866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49383980 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_full.49383980
Directory /workspace/30.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_overflow.3918982209
Short name T1028
Test name
Test status
Simulation time 6348005490 ps
CPU time 40.03 seconds
Started Jul 03 05:27:25 PM PDT 24
Finished Jul 03 05:28:06 PM PDT 24
Peak memory 527928 kb
Host smart-31c40314-717d-49e0-bab0-c72cc6a205ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918982209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_overflow.3918982209
Directory /workspace/30.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_fmt.4285127690
Short name T399
Test name
Test status
Simulation time 142971157 ps
CPU time 1.07 seconds
Started Jul 03 05:27:27 PM PDT 24
Finished Jul 03 05:27:28 PM PDT 24
Peak memory 204448 kb
Host smart-e7f2cdd7-bf8a-4b2c-9d0d-7714c990c6e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285127690 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_f
mt.4285127690
Directory /workspace/30.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_reset_rx.2472450088
Short name T1096
Test name
Test status
Simulation time 1118417565 ps
CPU time 4.29 seconds
Started Jul 03 05:27:20 PM PDT 24
Finished Jul 03 05:27:25 PM PDT 24
Peak memory 233844 kb
Host smart-97ea89c3-fcbd-4f14-9b4c-6ad0d298a1c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472450088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_reset_rx
.2472450088
Directory /workspace/30.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/30.i2c_host_fifo_watermark.109143417
Short name T1515
Test name
Test status
Simulation time 5285484212 ps
CPU time 103.81 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:29:14 PM PDT 24
Peak memory 1141784 kb
Host smart-bb6aebf0-1ac5-4bd0-8ddd-817044642c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109143417 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_fifo_watermark.109143417
Directory /workspace/30.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/30.i2c_host_may_nack.1345547752
Short name T624
Test name
Test status
Simulation time 305026594 ps
CPU time 4.81 seconds
Started Jul 03 05:27:27 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204684 kb
Host smart-3649eb15-bf24-413f-a36d-b5bb1659732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345547752 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_may_nack.1345547752
Directory /workspace/30.i2c_host_may_nack/latest

Test location /workspace/coverage/default/30.i2c_host_override.2855594711
Short name T736
Test name
Test status
Simulation time 25888064 ps
CPU time 0.64 seconds
Started Jul 03 05:27:25 PM PDT 24
Finished Jul 03 05:27:26 PM PDT 24
Peak memory 204512 kb
Host smart-5dd971d2-64ad-4315-aabe-e17ca7343c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855594711 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_override.2855594711
Directory /workspace/30.i2c_host_override/latest

Test location /workspace/coverage/default/30.i2c_host_perf.2448590832
Short name T1458
Test name
Test status
Simulation time 13159023490 ps
CPU time 242.75 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:31:34 PM PDT 24
Peak memory 1595960 kb
Host smart-c8467d5c-5126-4eb4-851f-1d46ebcd5b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448590832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf.2448590832
Directory /workspace/30.i2c_host_perf/latest

Test location /workspace/coverage/default/30.i2c_host_perf_precise.3826369366
Short name T685
Test name
Test status
Simulation time 23205518384 ps
CPU time 951.14 seconds
Started Jul 03 05:27:27 PM PDT 24
Finished Jul 03 05:43:18 PM PDT 24
Peak memory 204768 kb
Host smart-efa28c99-d675-4034-a641-0ed2fbd1bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826369366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_perf_precise.3826369366
Directory /workspace/30.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/30.i2c_host_smoke.1970540964
Short name T1220
Test name
Test status
Simulation time 23462051799 ps
CPU time 36.52 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:28:05 PM PDT 24
Peak memory 334460 kb
Host smart-4531ba16-81c4-46b8-a244-996f7c01fc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970540964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_smoke.1970540964
Directory /workspace/30.i2c_host_smoke/latest

Test location /workspace/coverage/default/30.i2c_host_stress_all.1654099792
Short name T122
Test name
Test status
Simulation time 30164146710 ps
CPU time 184.15 seconds
Started Jul 03 05:27:24 PM PDT 24
Finished Jul 03 05:30:29 PM PDT 24
Peak memory 1075320 kb
Host smart-cd879d3c-d6fc-4f13-a042-67909aadd27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654099792 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stress_all.1654099792
Directory /workspace/30.i2c_host_stress_all/latest

Test location /workspace/coverage/default/30.i2c_host_stretch_timeout.1380818767
Short name T1244
Test name
Test status
Simulation time 4225703750 ps
CPU time 32.88 seconds
Started Jul 03 05:27:20 PM PDT 24
Finished Jul 03 05:27:53 PM PDT 24
Peak memory 213128 kb
Host smart-80a2e2b1-fdf3-4767-91e8-f3a0fc48bd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380818767 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_host_stretch_timeout.1380818767
Directory /workspace/30.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_bad_addr.4072295121
Short name T1420
Test name
Test status
Simulation time 1787528799 ps
CPU time 2.94 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204760 kb
Host smart-edb50a45-b3c4-4cc6-be7c-23b5ee0684bb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072295121 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.i2c_target_bad_addr.4072295121
Directory /workspace/30.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_acq.2010061720
Short name T563
Test name
Test status
Simulation time 238575254 ps
CPU time 1.02 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204588 kb
Host smart-f6ffa116-b4a8-4ab5-b099-4db3f3a2b33b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010061720 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_fifo_reset_acq.2010061720
Directory /workspace/30.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_reset_tx.2457175369
Short name T171
Test name
Test status
Simulation time 351056020 ps
CPU time 1.44 seconds
Started Jul 03 05:27:20 PM PDT 24
Finished Jul 03 05:27:21 PM PDT 24
Peak memory 204508 kb
Host smart-569a71cb-5aa9-4ea9-8148-28c4dbf09279
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457175369 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.i2c_target_fifo_reset_tx.2457175369
Directory /workspace/30.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_acq.4170259313
Short name T1396
Test name
Test status
Simulation time 4887763825 ps
CPU time 2.35 seconds
Started Jul 03 05:27:31 PM PDT 24
Finished Jul 03 05:27:34 PM PDT 24
Peak memory 204968 kb
Host smart-10a8c359-5952-4e7f-8c0b-dfc5ee29f0db
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170259313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.i2c_target_fifo_watermarks_acq.4170259313
Directory /workspace/30.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/30.i2c_target_fifo_watermarks_tx.540363858
Short name T1267
Test name
Test status
Simulation time 174810847 ps
CPU time 1.33 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204644 kb
Host smart-e200f22c-7b6e-4c34-9881-21d1a8beaf1a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540363858 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.i2c_target_fifo_watermarks_tx.540363858
Directory /workspace/30.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/30.i2c_target_hrst.2696226312
Short name T1469
Test name
Test status
Simulation time 497295167 ps
CPU time 3.49 seconds
Started Jul 03 05:27:27 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 204856 kb
Host smart-cd668c71-d0b6-42da-9288-47ffa1695fde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696226312 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 30.i2c_target_hrst.2696226312
Directory /workspace/30.i2c_target_hrst/latest

Test location /workspace/coverage/default/30.i2c_target_intr_smoke.1036452780
Short name T599
Test name
Test status
Simulation time 2332691899 ps
CPU time 5.88 seconds
Started Jul 03 05:27:20 PM PDT 24
Finished Jul 03 05:27:26 PM PDT 24
Peak memory 212016 kb
Host smart-8704c99a-eb2a-4adb-a506-c209a003cfcc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036452780 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 30.i2c_target_intr_smoke.1036452780
Directory /workspace/30.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_intr_stress_wr.1985311015
Short name T421
Test name
Test status
Simulation time 3307889752 ps
CPU time 9.96 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:41 PM PDT 24
Peak memory 505196 kb
Host smart-6b7c361a-29a6-4c22-a420-b7c4fcddf462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985311015 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.i2c_target_intr_stress_wr.1985311015
Directory /workspace/30.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_smoke.2275520720
Short name T495
Test name
Test status
Simulation time 1024129034 ps
CPU time 18.44 seconds
Started Jul 03 05:27:21 PM PDT 24
Finished Jul 03 05:27:40 PM PDT 24
Peak memory 204824 kb
Host smart-b090810f-0639-478f-92a1-e735838a21a9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275520720 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_ta
rget_smoke.2275520720
Directory /workspace/30.i2c_target_smoke/latest

Test location /workspace/coverage/default/30.i2c_target_stress_rd.531034353
Short name T246
Test name
Test status
Simulation time 1437673625 ps
CPU time 24.99 seconds
Started Jul 03 05:27:27 PM PDT 24
Finished Jul 03 05:27:52 PM PDT 24
Peak memory 219272 kb
Host smart-41f5ed0d-5aa1-472c-8cfc-17e12fd64c1f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531034353 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c
_target_stress_rd.531034353
Directory /workspace/30.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/30.i2c_target_stress_wr.2138584964
Short name T728
Test name
Test status
Simulation time 38981579824 ps
CPU time 74.66 seconds
Started Jul 03 05:27:26 PM PDT 24
Finished Jul 03 05:28:41 PM PDT 24
Peak memory 1189176 kb
Host smart-fa7022c2-debb-442d-baba-368f3d1b0046
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138584964 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2
c_target_stress_wr.2138584964
Directory /workspace/30.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/30.i2c_target_stretch.2953773435
Short name T1248
Test name
Test status
Simulation time 21117556469 ps
CPU time 19.68 seconds
Started Jul 03 05:27:23 PM PDT 24
Finished Jul 03 05:27:43 PM PDT 24
Peak memory 384076 kb
Host smart-6d6804ef-fbde-4e61-bceb-99cda078ff92
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953773435 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.i2c_
target_stretch.2953773435
Directory /workspace/30.i2c_target_stretch/latest

Test location /workspace/coverage/default/30.i2c_target_timeout.2954301740
Short name T457
Test name
Test status
Simulation time 2710346639 ps
CPU time 6.72 seconds
Started Jul 03 05:27:24 PM PDT 24
Finished Jul 03 05:27:31 PM PDT 24
Peak memory 213392 kb
Host smart-e6ada445-6fa3-4a72-b7f8-6448244c5818
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954301740 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.i2c_target_timeout.2954301740
Directory /workspace/30.i2c_target_timeout/latest

Test location /workspace/coverage/default/30.i2c_target_tx_stretch_ctrl.1515865289
Short name T885
Test name
Test status
Simulation time 82981188 ps
CPU time 1.77 seconds
Started Jul 03 05:27:31 PM PDT 24
Finished Jul 03 05:27:34 PM PDT 24
Peak memory 204772 kb
Host smart-1b98c7cb-b82f-4f0f-a4e4-587204d6dcfa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515865289 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.i2c_target_tx_stretch_ctrl.1515865289
Directory /workspace/30.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/31.i2c_alert_test.3726978318
Short name T1405
Test name
Test status
Simulation time 52203595 ps
CPU time 0.63 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204436 kb
Host smart-d0a965e8-e575-45eb-90a1-d61a6dc911cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726978318 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_alert_test.3726978318
Directory /workspace/31.i2c_alert_test/latest

Test location /workspace/coverage/default/31.i2c_host_error_intr.2405592505
Short name T1030
Test name
Test status
Simulation time 109397289 ps
CPU time 3 seconds
Started Jul 03 05:27:31 PM PDT 24
Finished Jul 03 05:27:35 PM PDT 24
Peak memory 214084 kb
Host smart-4a8641ac-a51f-4544-8a3a-fda063cf2bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405592505 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_error_intr.2405592505
Directory /workspace/31.i2c_host_error_intr/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_fmt_empty.340800046
Short name T1053
Test name
Test status
Simulation time 2705260305 ps
CPU time 4.41 seconds
Started Jul 03 05:27:32 PM PDT 24
Finished Jul 03 05:27:37 PM PDT 24
Peak memory 241644 kb
Host smart-7acc39fb-5ce4-4da0-8552-0d44a5be5d07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340800046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_fmt_empt
y.340800046
Directory /workspace/31.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_full.3322381832
Short name T1078
Test name
Test status
Simulation time 1532407678 ps
CPU time 47.74 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:28:16 PM PDT 24
Peak memory 579000 kb
Host smart-ec025bdc-9b4f-445b-b6b4-6be362568495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322381832 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_full.3322381832
Directory /workspace/31.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_overflow.1720468491
Short name T1203
Test name
Test status
Simulation time 13816371026 ps
CPU time 59.32 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:28:31 PM PDT 24
Peak memory 690964 kb
Host smart-1c6c7333-ab43-4edb-a6d2-007451a4c42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720468491 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_overflow.1720468491
Directory /workspace/31.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_fmt.2478056715
Short name T1213
Test name
Test status
Simulation time 207249068 ps
CPU time 0.9 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:27:30 PM PDT 24
Peak memory 204428 kb
Host smart-45ce7839-d374-4fe9-9ea1-8b99a1237c1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478056715 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_f
mt.2478056715
Directory /workspace/31.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_reset_rx.1691900368
Short name T804
Test name
Test status
Simulation time 1006028988 ps
CPU time 5.36 seconds
Started Jul 03 05:27:26 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204764 kb
Host smart-95136a48-abc1-47f5-81fe-b70003cc4f9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691900368 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_reset_rx
.1691900368
Directory /workspace/31.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/31.i2c_host_fifo_watermark.2441924379
Short name T259
Test name
Test status
Simulation time 4388767706 ps
CPU time 253.27 seconds
Started Jul 03 05:27:25 PM PDT 24
Finished Jul 03 05:31:39 PM PDT 24
Peak memory 1129024 kb
Host smart-c1f06ab8-dcb0-4862-a15d-da88d34ecc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441924379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_fifo_watermark.2441924379
Directory /workspace/31.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/31.i2c_host_may_nack.2983221621
Short name T1439
Test name
Test status
Simulation time 5580472665 ps
CPU time 23.12 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:27:51 PM PDT 24
Peak memory 204928 kb
Host smart-855436ad-0d33-419b-8928-f099b795a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983221621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_may_nack.2983221621
Directory /workspace/31.i2c_host_may_nack/latest

Test location /workspace/coverage/default/31.i2c_host_mode_toggle.2716464816
Short name T251
Test name
Test status
Simulation time 1430486545 ps
CPU time 21.97 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:27:50 PM PDT 24
Peak memory 337076 kb
Host smart-d05a4e60-e5b7-4b59-a2e1-23e18c7163fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716464816 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_mode_toggle.2716464816
Directory /workspace/31.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/31.i2c_host_override.1298403111
Short name T244
Test name
Test status
Simulation time 30282480 ps
CPU time 0.67 seconds
Started Jul 03 05:27:32 PM PDT 24
Finished Jul 03 05:27:33 PM PDT 24
Peak memory 204536 kb
Host smart-bc093fb0-bb59-43a9-b178-47d8ae3a69c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298403111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_override.1298403111
Directory /workspace/31.i2c_host_override/latest

Test location /workspace/coverage/default/31.i2c_host_perf.1889474391
Short name T1288
Test name
Test status
Simulation time 4583479848 ps
CPU time 37.99 seconds
Started Jul 03 05:27:24 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 507896 kb
Host smart-bd73bf8b-61ad-4d84-a26d-4ae6d5e1980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889474391 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf.1889474391
Directory /workspace/31.i2c_host_perf/latest

Test location /workspace/coverage/default/31.i2c_host_perf_precise.1438919698
Short name T1247
Test name
Test status
Simulation time 5850058810 ps
CPU time 237.79 seconds
Started Jul 03 05:27:32 PM PDT 24
Finished Jul 03 05:31:30 PM PDT 24
Peak memory 213000 kb
Host smart-40672418-1922-48b6-9433-0d6bd9828fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438919698 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_perf_precise.1438919698
Directory /workspace/31.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/31.i2c_host_smoke.17640256
Short name T1254
Test name
Test status
Simulation time 5948282507 ps
CPU time 65.62 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:28:36 PM PDT 24
Peak memory 365968 kb
Host smart-984506ee-0df6-4795-b173-98e12106acfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17640256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_smoke.17640256
Directory /workspace/31.i2c_host_smoke/latest

Test location /workspace/coverage/default/31.i2c_host_stress_all.1354213788
Short name T1414
Test name
Test status
Simulation time 34529235648 ps
CPU time 307.92 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:32:39 PM PDT 24
Peak memory 1597036 kb
Host smart-304d2c84-3566-4006-ae2a-0bd4b8fcd5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354213788 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stress_all.1354213788
Directory /workspace/31.i2c_host_stress_all/latest

Test location /workspace/coverage/default/31.i2c_host_stretch_timeout.785309764
Short name T314
Test name
Test status
Simulation time 576302940 ps
CPU time 25.7 seconds
Started Jul 03 05:27:25 PM PDT 24
Finished Jul 03 05:27:51 PM PDT 24
Peak memory 213004 kb
Host smart-0544747b-b5e0-4ee3-83b0-da317113a5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785309764 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_host_stretch_timeout.785309764
Directory /workspace/31.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_bad_addr.2475708420
Short name T372
Test name
Test status
Simulation time 1090432254 ps
CPU time 5.53 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:27:34 PM PDT 24
Peak memory 215716 kb
Host smart-214d268c-c826-4abb-ada0-6f71408f69fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475708420 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.i2c_target_bad_addr.2475708420
Directory /workspace/31.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_acq.1855944355
Short name T486
Test name
Test status
Simulation time 428354210 ps
CPU time 1.41 seconds
Started Jul 03 05:27:35 PM PDT 24
Finished Jul 03 05:27:37 PM PDT 24
Peak memory 212856 kb
Host smart-f3269988-1ec4-40bc-adf9-493d679bdb64
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855944355 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_fifo_reset_acq.1855944355
Directory /workspace/31.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_reset_tx.3229109128
Short name T478
Test name
Test status
Simulation time 312411590 ps
CPU time 1.04 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:32 PM PDT 24
Peak memory 204596 kb
Host smart-49924820-17c3-4434-a465-0978109c6be9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229109128 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.i2c_target_fifo_reset_tx.3229109128
Directory /workspace/31.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_acq.3223392481
Short name T681
Test name
Test status
Simulation time 767334695 ps
CPU time 2.17 seconds
Started Jul 03 05:27:31 PM PDT 24
Finished Jul 03 05:27:34 PM PDT 24
Peak memory 204764 kb
Host smart-e770af17-5f04-4c68-ba75-066dab41f023
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223392481 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.i2c_target_fifo_watermarks_acq.3223392481
Directory /workspace/31.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/31.i2c_target_fifo_watermarks_tx.985572666
Short name T1069
Test name
Test status
Simulation time 502269545 ps
CPU time 1.22 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:27:29 PM PDT 24
Peak memory 204632 kb
Host smart-8dafacfc-3bcd-4b6c-a271-7e270372294b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985572666 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.i2c_target_fifo_watermarks_tx.985572666
Directory /workspace/31.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/31.i2c_target_intr_smoke.4284886322
Short name T1341
Test name
Test status
Simulation time 471690847 ps
CPU time 3.25 seconds
Started Jul 03 05:27:31 PM PDT 24
Finished Jul 03 05:27:35 PM PDT 24
Peak memory 204788 kb
Host smart-1b7e25ca-3cee-4f90-8885-2491a96a81a7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284886322 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 31.i2c_target_intr_smoke.4284886322
Directory /workspace/31.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_intr_stress_wr.1212115373
Short name T962
Test name
Test status
Simulation time 23319822170 ps
CPU time 185.9 seconds
Started Jul 03 05:27:35 PM PDT 24
Finished Jul 03 05:30:41 PM PDT 24
Peak memory 2864620 kb
Host smart-a2a2eead-b93a-469c-a67e-aaa829eabba1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212115373 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.i2c_target_intr_stress_wr.1212115373
Directory /workspace/31.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_smoke.2957702526
Short name T6
Test name
Test status
Simulation time 1182760989 ps
CPU time 45.38 seconds
Started Jul 03 05:27:33 PM PDT 24
Finished Jul 03 05:28:19 PM PDT 24
Peak memory 204852 kb
Host smart-15d8d8bc-a542-4649-bd0f-1082018314ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957702526 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_ta
rget_smoke.2957702526
Directory /workspace/31.i2c_target_smoke/latest

Test location /workspace/coverage/default/31.i2c_target_stress_wr.3271667201
Short name T366
Test name
Test status
Simulation time 33229449991 ps
CPU time 321.94 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:32:53 PM PDT 24
Peak memory 3425388 kb
Host smart-9acb6bf3-886f-4e5a-8eab-c45f5e4a9bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271667201 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2
c_target_stress_wr.3271667201
Directory /workspace/31.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/31.i2c_target_stretch.2762368607
Short name T245
Test name
Test status
Simulation time 22509454541 ps
CPU time 416.74 seconds
Started Jul 03 05:27:31 PM PDT 24
Finished Jul 03 05:34:29 PM PDT 24
Peak memory 1384660 kb
Host smart-f2f6c12e-d3b4-42ad-8b86-83622d39e0b6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762368607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.i2c_
target_stretch.2762368607
Directory /workspace/31.i2c_target_stretch/latest

Test location /workspace/coverage/default/31.i2c_target_timeout.3273244014
Short name T1390
Test name
Test status
Simulation time 1434999091 ps
CPU time 6.42 seconds
Started Jul 03 05:27:37 PM PDT 24
Finished Jul 03 05:27:44 PM PDT 24
Peak memory 220988 kb
Host smart-f9f926ea-4d5c-4eff-ab83-c8baff504040
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273244014 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 31.i2c_target_timeout.3273244014
Directory /workspace/31.i2c_target_timeout/latest

Test location /workspace/coverage/default/31.i2c_target_tx_stretch_ctrl.2147656957
Short name T637
Test name
Test status
Simulation time 80907697 ps
CPU time 1.79 seconds
Started Jul 03 05:27:31 PM PDT 24
Finished Jul 03 05:27:33 PM PDT 24
Peak memory 204876 kb
Host smart-05d75330-f540-4671-92dc-422e62c83056
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147656957 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.i2c_target_tx_stretch_ctrl.2147656957
Directory /workspace/31.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/32.i2c_alert_test.658787377
Short name T918
Test name
Test status
Simulation time 27630080 ps
CPU time 0.63 seconds
Started Jul 03 05:27:39 PM PDT 24
Finished Jul 03 05:27:40 PM PDT 24
Peak memory 204504 kb
Host smart-01bcf792-5842-4040-bcb3-5eb5853120ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658787377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_alert_test.658787377
Directory /workspace/32.i2c_alert_test/latest

Test location /workspace/coverage/default/32.i2c_host_error_intr.3673772319
Short name T935
Test name
Test status
Simulation time 129979624 ps
CPU time 1.51 seconds
Started Jul 03 05:27:35 PM PDT 24
Finished Jul 03 05:27:37 PM PDT 24
Peak memory 213108 kb
Host smart-1f32e70d-eb77-4e36-a537-1dbc8bc2cd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673772319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_error_intr.3673772319
Directory /workspace/32.i2c_host_error_intr/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_fmt_empty.2662229227
Short name T598
Test name
Test status
Simulation time 3722923256 ps
CPU time 26.6 seconds
Started Jul 03 05:27:33 PM PDT 24
Finished Jul 03 05:28:00 PM PDT 24
Peak memory 317764 kb
Host smart-3fc6c4a6-00d9-4c0d-ae48-1972855cbdaa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662229227 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_fmt_emp
ty.2662229227
Directory /workspace/32.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_full.2107987321
Short name T42
Test name
Test status
Simulation time 2575679519 ps
CPU time 156.17 seconds
Started Jul 03 05:27:29 PM PDT 24
Finished Jul 03 05:30:06 PM PDT 24
Peak memory 582732 kb
Host smart-91840309-11f0-46e2-ad08-a07353376a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107987321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_full.2107987321
Directory /workspace/32.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_overflow.991882872
Short name T1346
Test name
Test status
Simulation time 2134981605 ps
CPU time 156.46 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:30:08 PM PDT 24
Peak memory 705784 kb
Host smart-e7a3cf02-611d-4227-8d35-4219542d76d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991882872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_overflow.991882872
Directory /workspace/32.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_reset_fmt.3990086535
Short name T1198
Test name
Test status
Simulation time 85452690 ps
CPU time 0.93 seconds
Started Jul 03 05:27:35 PM PDT 24
Finished Jul 03 05:27:36 PM PDT 24
Peak memory 204432 kb
Host smart-32b6a562-4e42-45ba-a08a-54b552afc54b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990086535 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_reset_f
mt.3990086535
Directory /workspace/32.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/32.i2c_host_fifo_watermark.630730250
Short name T647
Test name
Test status
Simulation time 4309721272 ps
CPU time 130.97 seconds
Started Jul 03 05:27:41 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 1278044 kb
Host smart-ae9a0077-c7f7-406f-8542-81e4522c12af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630730250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_fifo_watermark.630730250
Directory /workspace/32.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/32.i2c_host_may_nack.1497545608
Short name T1312
Test name
Test status
Simulation time 2568305124 ps
CPU time 8.7 seconds
Started Jul 03 05:27:39 PM PDT 24
Finished Jul 03 05:27:48 PM PDT 24
Peak memory 204948 kb
Host smart-21c5c3d4-463a-4d2f-8991-612f064cd3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497545608 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_may_nack.1497545608
Directory /workspace/32.i2c_host_may_nack/latest

Test location /workspace/coverage/default/32.i2c_host_mode_toggle.115101626
Short name T904
Test name
Test status
Simulation time 2454367967 ps
CPU time 49.2 seconds
Started Jul 03 05:27:38 PM PDT 24
Finished Jul 03 05:28:27 PM PDT 24
Peak memory 412896 kb
Host smart-927a1357-314d-4e17-933b-15680f4b42ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115101626 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_mode_toggle.115101626
Directory /workspace/32.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/32.i2c_host_override.3478879501
Short name T1118
Test name
Test status
Simulation time 24973468 ps
CPU time 0.66 seconds
Started Jul 03 05:27:34 PM PDT 24
Finished Jul 03 05:27:35 PM PDT 24
Peak memory 204480 kb
Host smart-229970ea-ccce-470f-8eac-ee8af29b4b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478879501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_override.3478879501
Directory /workspace/32.i2c_host_override/latest

Test location /workspace/coverage/default/32.i2c_host_perf.1290030197
Short name T60
Test name
Test status
Simulation time 2825273701 ps
CPU time 113.37 seconds
Started Jul 03 05:27:34 PM PDT 24
Finished Jul 03 05:29:28 PM PDT 24
Peak memory 205468 kb
Host smart-5dbcfbbe-2307-4e40-a5a3-bc04f07a5085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290030197 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf.1290030197
Directory /workspace/32.i2c_host_perf/latest

Test location /workspace/coverage/default/32.i2c_host_perf_precise.3059512234
Short name T1511
Test name
Test status
Simulation time 99098824 ps
CPU time 1.26 seconds
Started Jul 03 05:27:36 PM PDT 24
Finished Jul 03 05:27:37 PM PDT 24
Peak memory 204596 kb
Host smart-3c91dfc1-ffa6-434e-a6b5-a1eaab695fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059512234 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_perf_precise.3059512234
Directory /workspace/32.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/32.i2c_host_smoke.2460224381
Short name T1238
Test name
Test status
Simulation time 2440951599 ps
CPU time 38.79 seconds
Started Jul 03 05:27:28 PM PDT 24
Finished Jul 03 05:28:07 PM PDT 24
Peak memory 425672 kb
Host smart-4ff8998b-7461-4de1-9f2f-75b560d92fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460224381 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_smoke.2460224381
Directory /workspace/32.i2c_host_smoke/latest

Test location /workspace/coverage/default/32.i2c_host_stress_all.1343164301
Short name T492
Test name
Test status
Simulation time 99066041718 ps
CPU time 1761.07 seconds
Started Jul 03 05:27:33 PM PDT 24
Finished Jul 03 05:56:55 PM PDT 24
Peak memory 4599964 kb
Host smart-d2ea110d-1576-4615-8212-ef9121174a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343164301 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stress_all.1343164301
Directory /workspace/32.i2c_host_stress_all/latest

Test location /workspace/coverage/default/32.i2c_host_stretch_timeout.2445455181
Short name T1373
Test name
Test status
Simulation time 871670727 ps
CPU time 40.33 seconds
Started Jul 03 05:27:31 PM PDT 24
Finished Jul 03 05:28:12 PM PDT 24
Peak memory 213064 kb
Host smart-19ab858e-07b7-48b8-a6dc-c668cc47a8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445455181 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_host_stretch_timeout.2445455181
Directory /workspace/32.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_bad_addr.566010003
Short name T23
Test name
Test status
Simulation time 7281837620 ps
CPU time 5.28 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:27:48 PM PDT 24
Peak memory 213060 kb
Host smart-17be421e-d7d3-415a-9c3c-5d5379d60ff7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566010003 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 32.i2c_target_bad_addr.566010003
Directory /workspace/32.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_acq.4134003789
Short name T26
Test name
Test status
Simulation time 1077793217 ps
CPU time 1.11 seconds
Started Jul 03 05:27:38 PM PDT 24
Finished Jul 03 05:27:39 PM PDT 24
Peak memory 204552 kb
Host smart-50ccc697-1ab4-41c1-89e8-131a24a08488
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134003789 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_fifo_reset_acq.4134003789
Directory /workspace/32.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_reset_tx.800022348
Short name T1518
Test name
Test status
Simulation time 219148693 ps
CPU time 1.15 seconds
Started Jul 03 05:27:43 PM PDT 24
Finished Jul 03 05:27:45 PM PDT 24
Peak memory 212992 kb
Host smart-03a17c05-91ad-4ad3-a530-9c5f6846a09e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800022348 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.i2c_target_fifo_reset_tx.800022348
Directory /workspace/32.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_acq.4141320563
Short name T248
Test name
Test status
Simulation time 669024292 ps
CPU time 2.49 seconds
Started Jul 03 05:27:36 PM PDT 24
Finished Jul 03 05:27:39 PM PDT 24
Peak memory 204784 kb
Host smart-a9e7b649-603e-4533-b2ed-2cbf0d519db6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141320563 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.i2c_target_fifo_watermarks_acq.4141320563
Directory /workspace/32.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/32.i2c_target_fifo_watermarks_tx.1974957254
Short name T1400
Test name
Test status
Simulation time 708549467 ps
CPU time 1.38 seconds
Started Jul 03 05:27:32 PM PDT 24
Finished Jul 03 05:27:34 PM PDT 24
Peak memory 204624 kb
Host smart-ec3e9557-9716-46dc-89ba-aecb907df942
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974957254 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.i2c_target_fifo_watermarks_tx.1974957254
Directory /workspace/32.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/32.i2c_target_hrst.278509373
Short name T27
Test name
Test status
Simulation time 268057334 ps
CPU time 2.46 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:27:45 PM PDT 24
Peak memory 204860 kb
Host smart-783b7c54-3a22-4164-aa8b-67c2ef8dfe4a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278509373 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 32.i2c_target_hrst.278509373
Directory /workspace/32.i2c_target_hrst/latest

Test location /workspace/coverage/default/32.i2c_target_intr_smoke.4139494616
Short name T560
Test name
Test status
Simulation time 1500061118 ps
CPU time 4.33 seconds
Started Jul 03 05:27:32 PM PDT 24
Finished Jul 03 05:27:37 PM PDT 24
Peak memory 204840 kb
Host smart-4d89028c-829d-4516-9fd5-8f09e2e9fb52
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139494616 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_intr_smoke.4139494616
Directory /workspace/32.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_intr_stress_wr.3975821287
Short name T402
Test name
Test status
Simulation time 23373486614 ps
CPU time 477.89 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:35:40 PM PDT 24
Peak memory 4283664 kb
Host smart-a2d558d1-2b88-489c-a6fc-34bfed002cde
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975821287 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.i2c_target_intr_stress_wr.3975821287
Directory /workspace/32.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_smoke.1486539534
Short name T1023
Test name
Test status
Simulation time 2284459589 ps
CPU time 18.21 seconds
Started Jul 03 05:27:33 PM PDT 24
Finished Jul 03 05:27:52 PM PDT 24
Peak memory 204880 kb
Host smart-ef0c1bff-66ed-4e62-ad8c-8d4b82fc8d70
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486539534 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_ta
rget_smoke.1486539534
Directory /workspace/32.i2c_target_smoke/latest

Test location /workspace/coverage/default/32.i2c_target_stress_rd.3259749926
Short name T1115
Test name
Test status
Simulation time 1443375026 ps
CPU time 23.05 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:27:54 PM PDT 24
Peak memory 226764 kb
Host smart-ed1c8a69-9cca-4e17-8265-09ec625f2ad6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259749926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_rd.3259749926
Directory /workspace/32.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/32.i2c_target_stress_wr.2310533072
Short name T1514
Test name
Test status
Simulation time 38250246380 ps
CPU time 506.48 seconds
Started Jul 03 05:27:30 PM PDT 24
Finished Jul 03 05:35:58 PM PDT 24
Peak memory 4653376 kb
Host smart-84e4ddd0-3292-42c1-b8d4-b29744c579ca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310533072 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2
c_target_stress_wr.2310533072
Directory /workspace/32.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/32.i2c_target_stretch.1777582800
Short name T1253
Test name
Test status
Simulation time 19976355633 ps
CPU time 310.05 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:32:52 PM PDT 24
Peak memory 1160940 kb
Host smart-f29b3b2f-a020-4ba8-bc44-de5eaa62d3ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777582800 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.i2c_
target_stretch.1777582800
Directory /workspace/32.i2c_target_stretch/latest

Test location /workspace/coverage/default/32.i2c_target_timeout.845027512
Short name T855
Test name
Test status
Simulation time 2932148044 ps
CPU time 8.16 seconds
Started Jul 03 05:27:37 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 221204 kb
Host smart-87ea2ce6-ab0c-42a2-8b05-b35e09fbb333
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845027512 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 32.i2c_target_timeout.845027512
Directory /workspace/32.i2c_target_timeout/latest

Test location /workspace/coverage/default/32.i2c_target_tx_stretch_ctrl.3604140852
Short name T1065
Test name
Test status
Simulation time 38254589 ps
CPU time 1.03 seconds
Started Jul 03 05:27:39 PM PDT 24
Finished Jul 03 05:27:40 PM PDT 24
Peak memory 204864 kb
Host smart-3c967ad7-f623-45d6-a070-fbd95e785325
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604140852 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.i2c_target_tx_stretch_ctrl.3604140852
Directory /workspace/32.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/33.i2c_alert_test.4218640884
Short name T307
Test name
Test status
Simulation time 17501082 ps
CPU time 0.65 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:27:43 PM PDT 24
Peak memory 204524 kb
Host smart-fd6d2782-d5ab-4ff8-a872-6940808e24f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218640884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_alert_test.4218640884
Directory /workspace/33.i2c_alert_test/latest

Test location /workspace/coverage/default/33.i2c_host_error_intr.798416656
Short name T1105
Test name
Test status
Simulation time 79235256 ps
CPU time 1.79 seconds
Started Jul 03 05:27:38 PM PDT 24
Finished Jul 03 05:27:40 PM PDT 24
Peak memory 213080 kb
Host smart-87b61602-29fd-4d90-b07b-13a3993b07b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798416656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_error_intr.798416656
Directory /workspace/33.i2c_host_error_intr/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_fmt_empty.1107545861
Short name T856
Test name
Test status
Simulation time 783948624 ps
CPU time 20.82 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:28:04 PM PDT 24
Peak memory 291396 kb
Host smart-66db2e47-f857-49f0-80bc-cb98bf7c3438
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107545861 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_fmt_emp
ty.1107545861
Directory /workspace/33.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_full.207801485
Short name T153
Test name
Test status
Simulation time 7423281978 ps
CPU time 249.42 seconds
Started Jul 03 05:27:34 PM PDT 24
Finished Jul 03 05:31:44 PM PDT 24
Peak memory 949220 kb
Host smart-b82253f0-efda-47ba-904c-7c64db0a6923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207801485 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_full.207801485
Directory /workspace/33.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_overflow.1480938439
Short name T905
Test name
Test status
Simulation time 8645345578 ps
CPU time 39.83 seconds
Started Jul 03 05:27:41 PM PDT 24
Finished Jul 03 05:28:21 PM PDT 24
Peak memory 512352 kb
Host smart-baf5e402-1507-4130-bb31-16b6f4127190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480938439 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_overflow.1480938439
Directory /workspace/33.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_fmt.1773054014
Short name T863
Test name
Test status
Simulation time 286396761 ps
CPU time 1 seconds
Started Jul 03 05:27:32 PM PDT 24
Finished Jul 03 05:27:33 PM PDT 24
Peak memory 204428 kb
Host smart-4b4d60f7-b30d-468c-a049-75fe3ef427a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773054014 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_f
mt.1773054014
Directory /workspace/33.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_reset_rx.2196866751
Short name T1277
Test name
Test status
Simulation time 146409668 ps
CPU time 7.77 seconds
Started Jul 03 05:27:32 PM PDT 24
Finished Jul 03 05:27:40 PM PDT 24
Peak memory 226988 kb
Host smart-30ae9725-0208-4a7c-8d6e-162852f01585
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196866751 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_reset_rx
.2196866751
Directory /workspace/33.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/33.i2c_host_fifo_watermark.2053491736
Short name T466
Test name
Test status
Simulation time 3591985070 ps
CPU time 91.16 seconds
Started Jul 03 05:27:41 PM PDT 24
Finished Jul 03 05:29:13 PM PDT 24
Peak memory 1065316 kb
Host smart-8b118601-b0a7-4dc7-a206-9e2bf308374a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053491736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_fifo_watermark.2053491736
Directory /workspace/33.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/33.i2c_host_may_nack.3646609777
Short name T1520
Test name
Test status
Simulation time 3491138627 ps
CPU time 13 seconds
Started Jul 03 05:27:40 PM PDT 24
Finished Jul 03 05:27:54 PM PDT 24
Peak memory 204900 kb
Host smart-8e359cd3-7998-4c03-9b20-982873e4ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646609777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_may_nack.3646609777
Directory /workspace/33.i2c_host_may_nack/latest

Test location /workspace/coverage/default/33.i2c_host_mode_toggle.4007816537
Short name T241
Test name
Test status
Simulation time 1801950426 ps
CPU time 12.25 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:27:54 PM PDT 24
Peak memory 245424 kb
Host smart-0f4439e1-cd9e-4f31-b41c-d7079f314df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007816537 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_mode_toggle.4007816537
Directory /workspace/33.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/33.i2c_host_override.3101975059
Short name T1339
Test name
Test status
Simulation time 29185894 ps
CPU time 0.7 seconds
Started Jul 03 05:27:40 PM PDT 24
Finished Jul 03 05:27:41 PM PDT 24
Peak memory 204536 kb
Host smart-5c49ed22-01b0-4637-bbab-f0411a5aa1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101975059 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_override.3101975059
Directory /workspace/33.i2c_host_override/latest

Test location /workspace/coverage/default/33.i2c_host_perf.1192435997
Short name T1019
Test name
Test status
Simulation time 3052261374 ps
CPU time 8.53 seconds
Started Jul 03 05:27:38 PM PDT 24
Finished Jul 03 05:27:47 PM PDT 24
Peak memory 222640 kb
Host smart-84c4f0d6-0793-49cc-b489-63f9211b45a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192435997 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf.1192435997
Directory /workspace/33.i2c_host_perf/latest

Test location /workspace/coverage/default/33.i2c_host_perf_precise.1721910414
Short name T311
Test name
Test status
Simulation time 1232309467 ps
CPU time 10.41 seconds
Started Jul 03 05:27:43 PM PDT 24
Finished Jul 03 05:27:54 PM PDT 24
Peak memory 204732 kb
Host smart-b9812e50-42f4-4358-9622-947be3f3585b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721910414 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_perf_precise.1721910414
Directory /workspace/33.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/33.i2c_host_smoke.2824189244
Short name T818
Test name
Test status
Simulation time 1338339807 ps
CPU time 18.44 seconds
Started Jul 03 05:27:32 PM PDT 24
Finished Jul 03 05:27:51 PM PDT 24
Peak memory 308288 kb
Host smart-e7e36def-dbdb-4f3a-bcfe-2641a3722254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824189244 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_smoke.2824189244
Directory /workspace/33.i2c_host_smoke/latest

Test location /workspace/coverage/default/33.i2c_host_stress_all.878954887
Short name T273
Test name
Test status
Simulation time 185502117748 ps
CPU time 1474.11 seconds
Started Jul 03 05:27:38 PM PDT 24
Finished Jul 03 05:52:13 PM PDT 24
Peak memory 2718576 kb
Host smart-0ae38fbd-d951-4ef5-8c0a-44a055987be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878954887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stress_all.878954887
Directory /workspace/33.i2c_host_stress_all/latest

Test location /workspace/coverage/default/33.i2c_host_stretch_timeout.253778860
Short name T730
Test name
Test status
Simulation time 3225269436 ps
CPU time 31.58 seconds
Started Jul 03 05:27:34 PM PDT 24
Finished Jul 03 05:28:06 PM PDT 24
Peak memory 213048 kb
Host smart-ded519ea-d7c7-4523-8139-299d99293679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253778860 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_host_stretch_timeout.253778860
Directory /workspace/33.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_bad_addr.3217577018
Short name T1421
Test name
Test status
Simulation time 989699208 ps
CPU time 2.75 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:27:45 PM PDT 24
Peak memory 204820 kb
Host smart-8e0fbebe-be55-413a-a996-44848b1d657a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217577018 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.i2c_target_bad_addr.3217577018
Directory /workspace/33.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_acq.3958182396
Short name T761
Test name
Test status
Simulation time 417344966 ps
CPU time 1.03 seconds
Started Jul 03 05:27:41 PM PDT 24
Finished Jul 03 05:27:42 PM PDT 24
Peak memory 204592 kb
Host smart-6567b451-e8f8-4166-9144-9044af416d33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958182396 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_fifo_reset_acq.3958182396
Directory /workspace/33.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_reset_tx.3723544243
Short name T1372
Test name
Test status
Simulation time 306372909 ps
CPU time 1.14 seconds
Started Jul 03 05:27:41 PM PDT 24
Finished Jul 03 05:27:43 PM PDT 24
Peak memory 204836 kb
Host smart-8826fa8a-5a06-49d8-86de-d0c83746b0ac
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723544243 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.i2c_target_fifo_reset_tx.3723544243
Directory /workspace/33.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_acq.188685154
Short name T1037
Test name
Test status
Simulation time 2559798931 ps
CPU time 2.16 seconds
Started Jul 03 05:27:48 PM PDT 24
Finished Jul 03 05:27:50 PM PDT 24
Peak memory 204760 kb
Host smart-a4a1a7d8-1576-4e37-800b-7b5b308df8b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188685154 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_acq.188685154
Directory /workspace/33.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/33.i2c_target_fifo_watermarks_tx.2935615858
Short name T1038
Test name
Test status
Simulation time 148168335 ps
CPU time 1.31 seconds
Started Jul 03 05:27:44 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 204632 kb
Host smart-4896947d-99be-4ece-b581-d19b42302186
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935615858 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 33.i2c_target_fifo_watermarks_tx.2935615858
Directory /workspace/33.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/33.i2c_target_hrst.4078174672
Short name T285
Test name
Test status
Simulation time 856510120 ps
CPU time 3.01 seconds
Started Jul 03 05:27:36 PM PDT 24
Finished Jul 03 05:27:39 PM PDT 24
Peak memory 204836 kb
Host smart-06ef49f2-1444-44ac-823b-03c44f5058c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078174672 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_hrst.4078174672
Directory /workspace/33.i2c_target_hrst/latest

Test location /workspace/coverage/default/33.i2c_target_intr_smoke.336856112
Short name T1523
Test name
Test status
Simulation time 2545629860 ps
CPU time 6.17 seconds
Started Jul 03 05:27:38 PM PDT 24
Finished Jul 03 05:27:45 PM PDT 24
Peak memory 204892 kb
Host smart-0d1bb41e-9639-4182-84d1-4eb724f5acd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336856112 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 33.i2c_target_intr_smoke.336856112
Directory /workspace/33.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_intr_stress_wr.639436785
Short name T21
Test name
Test status
Simulation time 11505395932 ps
CPU time 76.11 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:28:59 PM PDT 24
Peak memory 1261784 kb
Host smart-ca1186dc-8335-474a-b7a4-d9c1a04e636b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639436785 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.i2c_target_intr_stress_wr.639436785
Directory /workspace/33.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_smoke.4058488411
Short name T510
Test name
Test status
Simulation time 11081051808 ps
CPU time 46.65 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:28:29 PM PDT 24
Peak memory 204788 kb
Host smart-5fcfc777-b44b-442c-9667-5abbe0229708
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058488411 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_ta
rget_smoke.4058488411
Directory /workspace/33.i2c_target_smoke/latest

Test location /workspace/coverage/default/33.i2c_target_stress_rd.1772798200
Short name T619
Test name
Test status
Simulation time 1382899136 ps
CPU time 24.84 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:28:07 PM PDT 24
Peak memory 219808 kb
Host smart-4d8f2545-4606-413f-a231-12eb5b3c1d1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772798200 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_rd.1772798200
Directory /workspace/33.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/33.i2c_target_stress_wr.1400534912
Short name T732
Test name
Test status
Simulation time 24290242166 ps
CPU time 36.03 seconds
Started Jul 03 05:27:34 PM PDT 24
Finished Jul 03 05:28:10 PM PDT 24
Peak memory 693180 kb
Host smart-d379bdf7-e53c-4654-ac62-cbe6097bfd5d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400534912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2
c_target_stress_wr.1400534912
Directory /workspace/33.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/33.i2c_target_stretch.1503401420
Short name T1435
Test name
Test status
Simulation time 30434991549 ps
CPU time 424.4 seconds
Started Jul 03 05:27:39 PM PDT 24
Finished Jul 03 05:34:43 PM PDT 24
Peak memory 3098680 kb
Host smart-4bc9efdd-c99c-4c79-9d2f-c26d2a388470
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503401420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.i2c_
target_stretch.1503401420
Directory /workspace/33.i2c_target_stretch/latest

Test location /workspace/coverage/default/33.i2c_target_timeout.1332912315
Short name T979
Test name
Test status
Simulation time 1506216181 ps
CPU time 7.13 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:27:49 PM PDT 24
Peak memory 217808 kb
Host smart-26f5c25a-9bf0-42f1-ab30-4742e9df46f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332912315 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 33.i2c_target_timeout.1332912315
Directory /workspace/33.i2c_target_timeout/latest

Test location /workspace/coverage/default/33.i2c_target_tx_stretch_ctrl.4103957843
Short name T1212
Test name
Test status
Simulation time 391353923 ps
CPU time 5.43 seconds
Started Jul 03 05:27:45 PM PDT 24
Finished Jul 03 05:27:51 PM PDT 24
Peak memory 204860 kb
Host smart-5c95e7cd-8a3f-4a71-905d-90e8da7f6fbf
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103957843 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.i2c_target_tx_stretch_ctrl.4103957843
Directory /workspace/33.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/34.i2c_alert_test.2508366804
Short name T880
Test name
Test status
Simulation time 24199055 ps
CPU time 0.68 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:27:52 PM PDT 24
Peak memory 204480 kb
Host smart-3b67446b-108e-4cf7-9c16-ab1e46daa4ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508366804 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_alert_test.2508366804
Directory /workspace/34.i2c_alert_test/latest

Test location /workspace/coverage/default/34.i2c_host_error_intr.3721807095
Short name T1422
Test name
Test status
Simulation time 337656470 ps
CPU time 2.64 seconds
Started Jul 03 05:27:44 PM PDT 24
Finished Jul 03 05:27:47 PM PDT 24
Peak memory 214340 kb
Host smart-16de7f14-81c1-4269-9f46-5a8d1a5472db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721807095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_error_intr.3721807095
Directory /workspace/34.i2c_host_error_intr/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_fmt_empty.530695217
Short name T499
Test name
Test status
Simulation time 3057905793 ps
CPU time 27.69 seconds
Started Jul 03 05:27:40 PM PDT 24
Finished Jul 03 05:28:08 PM PDT 24
Peak memory 304412 kb
Host smart-5ad18632-d6fd-4d99-b712-4746452a63fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530695217 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_fmt_empt
y.530695217
Directory /workspace/34.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_full.2653024693
Short name T969
Test name
Test status
Simulation time 7287156557 ps
CPU time 56.54 seconds
Started Jul 03 05:27:44 PM PDT 24
Finished Jul 03 05:28:42 PM PDT 24
Peak memory 661740 kb
Host smart-8996247e-86cd-4865-ac5d-8734e12f4be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653024693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_full.2653024693
Directory /workspace/34.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_overflow.996695691
Short name T832
Test name
Test status
Simulation time 2295264581 ps
CPU time 50.98 seconds
Started Jul 03 05:27:41 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 545256 kb
Host smart-52dd46fe-1753-42a4-a406-16f4024d4767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996695691 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_overflow.996695691
Directory /workspace/34.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_fmt.3695725886
Short name T802
Test name
Test status
Simulation time 394653992 ps
CPU time 0.94 seconds
Started Jul 03 05:27:43 PM PDT 24
Finished Jul 03 05:27:45 PM PDT 24
Peak memory 204432 kb
Host smart-57a8d853-5c68-437a-b88a-305eddbc5a62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695725886 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_f
mt.3695725886
Directory /workspace/34.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_reset_rx.592080695
Short name T233
Test name
Test status
Simulation time 111135076 ps
CPU time 3.56 seconds
Started Jul 03 05:27:40 PM PDT 24
Finished Jul 03 05:27:44 PM PDT 24
Peak memory 220372 kb
Host smart-4c19d795-91a1-4dac-a856-860e6b997cd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592080695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_reset_rx.
592080695
Directory /workspace/34.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/34.i2c_host_fifo_watermark.1454099946
Short name T1522
Test name
Test status
Simulation time 5122646316 ps
CPU time 366.65 seconds
Started Jul 03 05:27:38 PM PDT 24
Finished Jul 03 05:33:45 PM PDT 24
Peak memory 1397236 kb
Host smart-7d72d9d8-1cb8-4abf-b2fd-d0eee304a0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454099946 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_fifo_watermark.1454099946
Directory /workspace/34.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/34.i2c_host_may_nack.1627591060
Short name T1183
Test name
Test status
Simulation time 3928408600 ps
CPU time 25.49 seconds
Started Jul 03 05:27:53 PM PDT 24
Finished Jul 03 05:28:19 PM PDT 24
Peak memory 204884 kb
Host smart-2a62e73f-7c79-459f-9916-5601d2a833a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627591060 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_may_nack.1627591060
Directory /workspace/34.i2c_host_may_nack/latest

Test location /workspace/coverage/default/34.i2c_host_mode_toggle.2956424448
Short name T67
Test name
Test status
Simulation time 13797119617 ps
CPU time 83.13 seconds
Started Jul 03 05:27:47 PM PDT 24
Finished Jul 03 05:29:10 PM PDT 24
Peak memory 433804 kb
Host smart-0dbf7902-c851-4862-87fa-6d393ed68e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956424448 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_mode_toggle.2956424448
Directory /workspace/34.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/34.i2c_host_override.291465030
Short name T94
Test name
Test status
Simulation time 17860463 ps
CPU time 0.64 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:27:44 PM PDT 24
Peak memory 204532 kb
Host smart-5c95dc84-cf94-41ed-927b-5db67e314cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291465030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_override.291465030
Directory /workspace/34.i2c_host_override/latest

Test location /workspace/coverage/default/34.i2c_host_perf.227538022
Short name T1263
Test name
Test status
Simulation time 7081871507 ps
CPU time 280.9 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:32:24 PM PDT 24
Peak memory 204948 kb
Host smart-7adfa34b-72df-44ef-a2d8-b58a2ff20e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227538022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf.227538022
Directory /workspace/34.i2c_host_perf/latest

Test location /workspace/coverage/default/34.i2c_host_perf_precise.2661926708
Short name T336
Test name
Test status
Simulation time 244233067 ps
CPU time 4.85 seconds
Started Jul 03 05:27:53 PM PDT 24
Finished Jul 03 05:27:59 PM PDT 24
Peak memory 204712 kb
Host smart-ba87d838-ed54-443e-a0c9-406d2c23158f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661926708 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_perf_precise.2661926708
Directory /workspace/34.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/34.i2c_host_smoke.2980002578
Short name T1519
Test name
Test status
Simulation time 3540555400 ps
CPU time 39.67 seconds
Started Jul 03 05:27:35 PM PDT 24
Finished Jul 03 05:28:15 PM PDT 24
Peak memory 296708 kb
Host smart-1a9dbdec-d383-4f8b-a64b-0fe991d90d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980002578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_smoke.2980002578
Directory /workspace/34.i2c_host_smoke/latest

Test location /workspace/coverage/default/34.i2c_host_stress_all.910251215
Short name T1314
Test name
Test status
Simulation time 24857152362 ps
CPU time 1229.85 seconds
Started Jul 03 05:27:44 PM PDT 24
Finished Jul 03 05:48:15 PM PDT 24
Peak memory 3287484 kb
Host smart-c46b4772-39c9-4bf9-b2ac-81f8e4c37aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910251215 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stress_all.910251215
Directory /workspace/34.i2c_host_stress_all/latest

Test location /workspace/coverage/default/34.i2c_host_stretch_timeout.746922470
Short name T1354
Test name
Test status
Simulation time 1778946676 ps
CPU time 16.65 seconds
Started Jul 03 05:27:47 PM PDT 24
Finished Jul 03 05:28:04 PM PDT 24
Peak memory 219124 kb
Host smart-e909650b-aaa7-42ab-acc6-cfda5cf26772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746922470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_host_stretch_timeout.746922470
Directory /workspace/34.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_bad_addr.3937266340
Short name T351
Test name
Test status
Simulation time 671128302 ps
CPU time 3.17 seconds
Started Jul 03 05:27:46 PM PDT 24
Finished Jul 03 05:27:49 PM PDT 24
Peak memory 204784 kb
Host smart-2410b894-e238-428c-9c5c-58e5567523ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937266340 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 34.i2c_target_bad_addr.3937266340
Directory /workspace/34.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_acq.654183584
Short name T442
Test name
Test status
Simulation time 219237040 ps
CPU time 1.37 seconds
Started Jul 03 05:27:45 PM PDT 24
Finished Jul 03 05:27:47 PM PDT 24
Peak memory 213044 kb
Host smart-4e5a9e86-337b-485d-b063-dbd56125db19
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654183584 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 34.i2c_target_fifo_reset_acq.654183584
Directory /workspace/34.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_reset_tx.311341402
Short name T1327
Test name
Test status
Simulation time 219179955 ps
CPU time 1.37 seconds
Started Jul 03 05:27:45 PM PDT 24
Finished Jul 03 05:27:47 PM PDT 24
Peak memory 213000 kb
Host smart-a90c5836-fed2-45ac-9fa7-b799fe9cde5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311341402 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.i2c_target_fifo_reset_tx.311341402
Directory /workspace/34.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_acq.3957253868
Short name T247
Test name
Test status
Simulation time 1399052581 ps
CPU time 2.05 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:27:52 PM PDT 24
Peak memory 204820 kb
Host smart-b0502a78-0428-48cb-81df-e36c655a3bfe
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957253868 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.i2c_target_fifo_watermarks_acq.3957253868
Directory /workspace/34.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/34.i2c_target_fifo_watermarks_tx.1417933325
Short name T9
Test name
Test status
Simulation time 517452811 ps
CPU time 1.12 seconds
Started Jul 03 05:27:45 PM PDT 24
Finished Jul 03 05:27:47 PM PDT 24
Peak memory 204624 kb
Host smart-0005dd36-8ce6-445a-b332-76cb072f3346
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417933325 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.i2c_target_fifo_watermarks_tx.1417933325
Directory /workspace/34.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/34.i2c_target_hrst.1489870109
Short name T1504
Test name
Test status
Simulation time 416876907 ps
CPU time 4.4 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:27:53 PM PDT 24
Peak memory 204848 kb
Host smart-dbe5ae68-3dcc-4c84-aa70-4477cdea6390
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489870109 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_hrst.1489870109
Directory /workspace/34.i2c_target_hrst/latest

Test location /workspace/coverage/default/34.i2c_target_intr_smoke.644115430
Short name T787
Test name
Test status
Simulation time 1066031650 ps
CPU time 5.57 seconds
Started Jul 03 05:27:47 PM PDT 24
Finished Jul 03 05:27:53 PM PDT 24
Peak memory 212992 kb
Host smart-e41d0341-2696-4ba8-9531-acaea20b4832
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644115430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 34.i2c_target_intr_smoke.644115430
Directory /workspace/34.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_intr_stress_wr.2675061449
Short name T810
Test name
Test status
Simulation time 25778323735 ps
CPU time 70.55 seconds
Started Jul 03 05:27:48 PM PDT 24
Finished Jul 03 05:28:59 PM PDT 24
Peak memory 1449816 kb
Host smart-24df4890-22d2-410b-8b3a-e5e624b9db6c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675061449 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.i2c_target_intr_stress_wr.2675061449
Directory /workspace/34.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_smoke.2536528358
Short name T759
Test name
Test status
Simulation time 935517769 ps
CPU time 15.02 seconds
Started Jul 03 05:27:40 PM PDT 24
Finished Jul 03 05:27:56 PM PDT 24
Peak memory 204800 kb
Host smart-8c5efb3f-a311-4e48-a587-ee6212d98c36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536528358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_ta
rget_smoke.2536528358
Directory /workspace/34.i2c_target_smoke/latest

Test location /workspace/coverage/default/34.i2c_target_stress_rd.4174320875
Short name T498
Test name
Test status
Simulation time 1233023925 ps
CPU time 23.91 seconds
Started Jul 03 05:27:48 PM PDT 24
Finished Jul 03 05:28:12 PM PDT 24
Peak memory 219392 kb
Host smart-514b3ce0-4e97-4d6c-86ea-d487bf7597f2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174320875 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2
c_target_stress_rd.4174320875
Directory /workspace/34.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/34.i2c_target_stress_wr.391037442
Short name T1362
Test name
Test status
Simulation time 20517218975 ps
CPU time 44.72 seconds
Started Jul 03 05:27:41 PM PDT 24
Finished Jul 03 05:28:27 PM PDT 24
Peak memory 401476 kb
Host smart-93c753d4-04e2-4aeb-98b9-1f86c5205dee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391037442 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c
_target_stress_wr.391037442
Directory /workspace/34.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/34.i2c_target_stretch.501967926
Short name T943
Test name
Test status
Simulation time 14410705921 ps
CPU time 63 seconds
Started Jul 03 05:27:42 PM PDT 24
Finished Jul 03 05:28:46 PM PDT 24
Peak memory 826032 kb
Host smart-18bb30df-210e-4c6a-82c4-98f889055edc
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501967926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.i2c_t
arget_stretch.501967926
Directory /workspace/34.i2c_target_stretch/latest

Test location /workspace/coverage/default/34.i2c_target_timeout.2714395395
Short name T707
Test name
Test status
Simulation time 2773499083 ps
CPU time 7.15 seconds
Started Jul 03 05:27:43 PM PDT 24
Finished Jul 03 05:27:51 PM PDT 24
Peak memory 213072 kb
Host smart-ffd2026b-4b60-4e45-8147-acfc9eb8e29f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714395395 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 34.i2c_target_timeout.2714395395
Directory /workspace/34.i2c_target_timeout/latest

Test location /workspace/coverage/default/34.i2c_target_tx_stretch_ctrl.1224751176
Short name T762
Test name
Test status
Simulation time 52690582 ps
CPU time 1.3 seconds
Started Jul 03 05:27:47 PM PDT 24
Finished Jul 03 05:27:49 PM PDT 24
Peak memory 204824 kb
Host smart-44d42269-3143-4a40-92f2-ced7c66ae053
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224751176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.i2c_target_tx_stretch_ctrl.1224751176
Directory /workspace/34.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/35.i2c_alert_test.377355089
Short name T185
Test name
Test status
Simulation time 36814404 ps
CPU time 0.62 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:27:52 PM PDT 24
Peak memory 204464 kb
Host smart-5666ede5-1a44-4397-8597-511106a17f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377355089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_alert_test.377355089
Directory /workspace/35.i2c_alert_test/latest

Test location /workspace/coverage/default/35.i2c_host_error_intr.141867503
Short name T1085
Test name
Test status
Simulation time 109903553 ps
CPU time 1.31 seconds
Started Jul 03 05:27:46 PM PDT 24
Finished Jul 03 05:27:48 PM PDT 24
Peak memory 213080 kb
Host smart-c2f1636a-30a5-46ac-b215-9fb17888c337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141867503 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_error_intr.141867503
Directory /workspace/35.i2c_host_error_intr/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_fmt_empty.1459528761
Short name T1294
Test name
Test status
Simulation time 4282907572 ps
CPU time 8.3 seconds
Started Jul 03 05:27:53 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 295616 kb
Host smart-207c2ea9-625a-4643-b767-04139b08b3d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459528761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_fmt_emp
ty.1459528761
Directory /workspace/35.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_full.3507868636
Short name T911
Test name
Test status
Simulation time 1671011547 ps
CPU time 48.06 seconds
Started Jul 03 05:27:48 PM PDT 24
Finished Jul 03 05:28:36 PM PDT 24
Peak memory 527568 kb
Host smart-1da2bbc8-d6d6-466c-a747-6a5e73a315ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507868636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_full.3507868636
Directory /workspace/35.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_overflow.1575723541
Short name T290
Test name
Test status
Simulation time 8020166780 ps
CPU time 136.04 seconds
Started Jul 03 05:27:44 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 628216 kb
Host smart-1e1377da-960d-4ddb-a615-f9b5fd8d5af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575723541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_overflow.1575723541
Directory /workspace/35.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_fmt.159800248
Short name T1426
Test name
Test status
Simulation time 557779175 ps
CPU time 0.97 seconds
Started Jul 03 05:27:43 PM PDT 24
Finished Jul 03 05:27:45 PM PDT 24
Peak memory 204468 kb
Host smart-b1b87168-58e7-4317-9639-0926f4f6c54f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159800248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_fm
t.159800248
Directory /workspace/35.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_reset_rx.3309834260
Short name T729
Test name
Test status
Simulation time 143056351 ps
CPU time 4.1 seconds
Started Jul 03 05:27:54 PM PDT 24
Finished Jul 03 05:27:58 PM PDT 24
Peak memory 225420 kb
Host smart-f41dcb7b-6c66-4f30-9594-be2342cacd85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309834260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_reset_rx
.3309834260
Directory /workspace/35.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/35.i2c_host_fifo_watermark.3093504585
Short name T1029
Test name
Test status
Simulation time 17806048722 ps
CPU time 140.85 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 1296672 kb
Host smart-afd1215e-c2da-48ac-a35a-2a4543ed79fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093504585 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_fifo_watermark.3093504585
Directory /workspace/35.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/35.i2c_host_may_nack.2989068689
Short name T1430
Test name
Test status
Simulation time 254181853 ps
CPU time 4.1 seconds
Started Jul 03 05:27:57 PM PDT 24
Finished Jul 03 05:28:01 PM PDT 24
Peak memory 204732 kb
Host smart-c57d060f-066a-4c78-b9b8-eb5c4cfec46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989068689 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_may_nack.2989068689
Directory /workspace/35.i2c_host_may_nack/latest

Test location /workspace/coverage/default/35.i2c_host_mode_toggle.3585573996
Short name T992
Test name
Test status
Simulation time 5273123304 ps
CPU time 24.81 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:28:16 PM PDT 24
Peak memory 401400 kb
Host smart-bf79561d-f2c9-4aaa-ace8-934edf6271e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585573996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_mode_toggle.3585573996
Directory /workspace/35.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/35.i2c_host_override.3835036625
Short name T130
Test name
Test status
Simulation time 49878554 ps
CPU time 0.67 seconds
Started Jul 03 05:27:45 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 204532 kb
Host smart-6db0ea10-ae88-4055-b69f-7ab961c30ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835036625 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_override.3835036625
Directory /workspace/35.i2c_host_override/latest

Test location /workspace/coverage/default/35.i2c_host_perf.683735880
Short name T845
Test name
Test status
Simulation time 1341562937 ps
CPU time 7.3 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:27:59 PM PDT 24
Peak memory 221064 kb
Host smart-609a55d0-086a-4718-92bc-9b2b0e440200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683735880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf.683735880
Directory /workspace/35.i2c_host_perf/latest

Test location /workspace/coverage/default/35.i2c_host_perf_precise.2799195273
Short name T1149
Test name
Test status
Simulation time 279484795 ps
CPU time 4.21 seconds
Started Jul 03 05:27:46 PM PDT 24
Finished Jul 03 05:27:50 PM PDT 24
Peak memory 225936 kb
Host smart-2cd57ca2-bab1-4ebb-9e3a-3758a774b5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799195273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_perf_precise.2799195273
Directory /workspace/35.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/35.i2c_host_smoke.3566211167
Short name T1273
Test name
Test status
Simulation time 8815639812 ps
CPU time 88.42 seconds
Started Jul 03 05:27:53 PM PDT 24
Finished Jul 03 05:29:22 PM PDT 24
Peak memory 359996 kb
Host smart-4dc60abc-dc28-4abe-9391-dfde08ffbef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566211167 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_smoke.3566211167
Directory /workspace/35.i2c_host_smoke/latest

Test location /workspace/coverage/default/35.i2c_host_stress_all.1284745143
Short name T272
Test name
Test status
Simulation time 88298798219 ps
CPU time 513.14 seconds
Started Jul 03 05:27:44 PM PDT 24
Finished Jul 03 05:36:18 PM PDT 24
Peak memory 2201020 kb
Host smart-9b573569-283f-419e-b0c6-3ff4a65c762e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284745143 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stress_all.1284745143
Directory /workspace/35.i2c_host_stress_all/latest

Test location /workspace/coverage/default/35.i2c_host_stretch_timeout.2495183103
Short name T1227
Test name
Test status
Simulation time 1811519690 ps
CPU time 9.21 seconds
Started Jul 03 05:27:44 PM PDT 24
Finished Jul 03 05:27:54 PM PDT 24
Peak memory 212960 kb
Host smart-0c8035e8-d705-4174-85d0-911c6c0fb2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495183103 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_host_stretch_timeout.2495183103
Directory /workspace/35.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_bad_addr.74968178
Short name T329
Test name
Test status
Simulation time 520322130 ps
CPU time 3.05 seconds
Started Jul 03 05:27:59 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 204884 kb
Host smart-e0df0339-6957-4bb7-85ea-3ced02d1617d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74968178 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.i2c_target_bad_addr.74968178
Directory /workspace/35.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_acq.2523132469
Short name T412
Test name
Test status
Simulation time 309439299 ps
CPU time 1.22 seconds
Started Jul 03 05:27:55 PM PDT 24
Finished Jul 03 05:27:56 PM PDT 24
Peak memory 204776 kb
Host smart-365636e2-fc13-4042-8c54-5d9dd1d53e26
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523132469 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_fifo_reset_acq.2523132469
Directory /workspace/35.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_reset_tx.409784789
Short name T576
Test name
Test status
Simulation time 668206206 ps
CPU time 1.21 seconds
Started Jul 03 05:27:52 PM PDT 24
Finished Jul 03 05:27:54 PM PDT 24
Peak memory 204636 kb
Host smart-661a1395-205f-46bb-85cf-ad4958a31e5c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409784789 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.i2c_target_fifo_reset_tx.409784789
Directory /workspace/35.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_acq.976214692
Short name T310
Test name
Test status
Simulation time 2033069509 ps
CPU time 2.51 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:27:53 PM PDT 24
Peak memory 204812 kb
Host smart-1fe5f3eb-1b7b-4c92-bfc5-13a0c463f089
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976214692 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_acq.976214692
Directory /workspace/35.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/35.i2c_target_fifo_watermarks_tx.1916651626
Short name T487
Test name
Test status
Simulation time 665908344 ps
CPU time 1.01 seconds
Started Jul 03 05:27:50 PM PDT 24
Finished Jul 03 05:27:52 PM PDT 24
Peak memory 204544 kb
Host smart-d6851612-6dcb-4687-bdd9-be1a197c0323
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916651626 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.i2c_target_fifo_watermarks_tx.1916651626
Directory /workspace/35.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/35.i2c_target_intr_smoke.1234265183
Short name T1064
Test name
Test status
Simulation time 1711491912 ps
CPU time 4.94 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:27:57 PM PDT 24
Peak memory 215412 kb
Host smart-bf9a7096-6d3d-4480-bf2f-f76bd9b2c7a1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234265183 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 35.i2c_target_intr_smoke.1234265183
Directory /workspace/35.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_intr_stress_wr.297497420
Short name T631
Test name
Test status
Simulation time 9572515088 ps
CPU time 7.19 seconds
Started Jul 03 05:27:55 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 204956 kb
Host smart-db11ea7f-cc90-416b-9c14-dd556a4fc38d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297497420 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.i2c_target_intr_stress_wr.297497420
Directory /workspace/35.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_smoke.840797373
Short name T932
Test name
Test status
Simulation time 1654660413 ps
CPU time 13.79 seconds
Started Jul 03 05:27:43 PM PDT 24
Finished Jul 03 05:27:57 PM PDT 24
Peak memory 204792 kb
Host smart-29e4e480-1b09-48a4-bbd4-cff1fab0491b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840797373 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_tar
get_smoke.840797373
Directory /workspace/35.i2c_target_smoke/latest

Test location /workspace/coverage/default/35.i2c_target_stress_rd.125320438
Short name T28
Test name
Test status
Simulation time 324677884 ps
CPU time 12.77 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:28:05 PM PDT 24
Peak memory 204800 kb
Host smart-7714da71-c760-4747-a9a6-121c2613cc5e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125320438 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c
_target_stress_rd.125320438
Directory /workspace/35.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/35.i2c_target_stress_wr.2724995379
Short name T981
Test name
Test status
Simulation time 22566849601 ps
CPU time 50.33 seconds
Started Jul 03 05:27:48 PM PDT 24
Finished Jul 03 05:28:39 PM PDT 24
Peak memory 624072 kb
Host smart-146590ed-430d-4e66-a2aa-f4f28583f3b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724995379 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2
c_target_stress_wr.2724995379
Directory /workspace/35.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/35.i2c_target_stretch.382653770
Short name T825
Test name
Test status
Simulation time 9395260022 ps
CPU time 146.05 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 1625040 kb
Host smart-28e4c3d3-751e-483a-9b1b-ca7d8f4ea692
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382653770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.i2c_t
arget_stretch.382653770
Directory /workspace/35.i2c_target_stretch/latest

Test location /workspace/coverage/default/35.i2c_target_timeout.4097041110
Short name T665
Test name
Test status
Simulation time 23624249618 ps
CPU time 7.31 seconds
Started Jul 03 05:27:54 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 220320 kb
Host smart-1b9884ab-0607-4fdb-bc81-52495084116d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097041110 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 35.i2c_target_timeout.4097041110
Directory /workspace/35.i2c_target_timeout/latest

Test location /workspace/coverage/default/35.i2c_target_tx_stretch_ctrl.1632627166
Short name T915
Test name
Test status
Simulation time 491732687 ps
CPU time 5.96 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:27:56 PM PDT 24
Peak memory 204876 kb
Host smart-178b3316-00ea-4460-ab93-d2d225f1cfa4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632627166 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.i2c_target_tx_stretch_ctrl.1632627166
Directory /workspace/35.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/36.i2c_alert_test.2641584559
Short name T1480
Test name
Test status
Simulation time 49324570 ps
CPU time 0.65 seconds
Started Jul 03 05:27:54 PM PDT 24
Finished Jul 03 05:27:55 PM PDT 24
Peak memory 204480 kb
Host smart-c29f24da-e1a4-478a-8acb-de197b288456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641584559 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_alert_test.2641584559
Directory /workspace/36.i2c_alert_test/latest

Test location /workspace/coverage/default/36.i2c_host_error_intr.1433037347
Short name T3
Test name
Test status
Simulation time 190703888 ps
CPU time 3.07 seconds
Started Jul 03 05:28:07 PM PDT 24
Finished Jul 03 05:28:10 PM PDT 24
Peak memory 213068 kb
Host smart-ac55a060-9f26-4599-bc6c-4944b1332069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433037347 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_error_intr.1433037347
Directory /workspace/36.i2c_host_error_intr/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_fmt_empty.76616022
Short name T791
Test name
Test status
Simulation time 310752413 ps
CPU time 6.9 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:27:56 PM PDT 24
Peak memory 266468 kb
Host smart-74bee7e0-9324-48ee-9460-741fcb397d61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76616022 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_fmt_empty
.76616022
Directory /workspace/36.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_full.2395042794
Short name T747
Test name
Test status
Simulation time 3761511992 ps
CPU time 77.36 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:29:07 PM PDT 24
Peak memory 674432 kb
Host smart-c386dd87-90a1-4b3f-8bf7-91552b9e4f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395042794 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_full.2395042794
Directory /workspace/36.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_overflow.377694640
Short name T705
Test name
Test status
Simulation time 9601851022 ps
CPU time 185.14 seconds
Started Jul 03 05:27:47 PM PDT 24
Finished Jul 03 05:30:53 PM PDT 24
Peak memory 804636 kb
Host smart-74911a9c-6e7d-4083-9dcb-d6aa38c60eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377694640 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_overflow.377694640
Directory /workspace/36.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_fmt.3273285265
Short name T1002
Test name
Test status
Simulation time 159442432 ps
CPU time 0.85 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:27:51 PM PDT 24
Peak memory 204440 kb
Host smart-a9fe3a81-a0ac-4677-ad0f-d46c50ce4705
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273285265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_f
mt.3273285265
Directory /workspace/36.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_reset_rx.15322016
Short name T589
Test name
Test status
Simulation time 643558975 ps
CPU time 3.86 seconds
Started Jul 03 05:27:53 PM PDT 24
Finished Jul 03 05:27:57 PM PDT 24
Peak memory 204892 kb
Host smart-ad4308db-dc7a-4cea-b498-fc10d8406d1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15322016 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_reset_rx.15322016
Directory /workspace/36.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/36.i2c_host_fifo_watermark.2118655178
Short name T913
Test name
Test status
Simulation time 4954983663 ps
CPU time 171.2 seconds
Started Jul 03 05:28:00 PM PDT 24
Finished Jul 03 05:30:52 PM PDT 24
Peak memory 1467892 kb
Host smart-13a22ad5-8cd3-4980-9f17-ebb9cac201aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118655178 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_fifo_watermark.2118655178
Directory /workspace/36.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/36.i2c_host_may_nack.1107325451
Short name T828
Test name
Test status
Simulation time 372596472 ps
CPU time 4.91 seconds
Started Jul 03 05:27:50 PM PDT 24
Finished Jul 03 05:27:56 PM PDT 24
Peak memory 204812 kb
Host smart-dbda0063-42c5-4453-bbf2-757cf1ce6ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107325451 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_may_nack.1107325451
Directory /workspace/36.i2c_host_may_nack/latest

Test location /workspace/coverage/default/36.i2c_host_mode_toggle.2053201159
Short name T749
Test name
Test status
Simulation time 1468652591 ps
CPU time 23.62 seconds
Started Jul 03 05:28:04 PM PDT 24
Finished Jul 03 05:28:28 PM PDT 24
Peak memory 331440 kb
Host smart-f0221c07-97c8-4225-b6dc-f8bf08e30bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053201159 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_mode_toggle.2053201159
Directory /workspace/36.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/36.i2c_host_override.1856066973
Short name T1320
Test name
Test status
Simulation time 51801310 ps
CPU time 0.68 seconds
Started Jul 03 05:27:52 PM PDT 24
Finished Jul 03 05:27:53 PM PDT 24
Peak memory 204580 kb
Host smart-eaff43ed-e191-4dc6-a028-5af1fe609a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856066973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_override.1856066973
Directory /workspace/36.i2c_host_override/latest

Test location /workspace/coverage/default/36.i2c_host_perf.1076312907
Short name T613
Test name
Test status
Simulation time 5165157597 ps
CPU time 159.5 seconds
Started Jul 03 05:27:54 PM PDT 24
Finished Jul 03 05:30:34 PM PDT 24
Peak memory 795440 kb
Host smart-27eaeaff-f023-4ac9-8016-17a82f945d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076312907 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf.1076312907
Directory /workspace/36.i2c_host_perf/latest

Test location /workspace/coverage/default/36.i2c_host_perf_precise.3993037926
Short name T1059
Test name
Test status
Simulation time 109681335 ps
CPU time 1.92 seconds
Started Jul 03 05:27:52 PM PDT 24
Finished Jul 03 05:27:55 PM PDT 24
Peak memory 225532 kb
Host smart-e421e167-9fa4-461d-b19e-5d1cb2b6d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993037926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_perf_precise.3993037926
Directory /workspace/36.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/36.i2c_host_smoke.2044266659
Short name T349
Test name
Test status
Simulation time 5819267417 ps
CPU time 66.86 seconds
Started Jul 03 05:27:58 PM PDT 24
Finished Jul 03 05:29:06 PM PDT 24
Peak memory 306388 kb
Host smart-f346623a-9638-4c15-8256-acbc4104cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044266659 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_smoke.2044266659
Directory /workspace/36.i2c_host_smoke/latest

Test location /workspace/coverage/default/36.i2c_host_stress_all.525603518
Short name T1332
Test name
Test status
Simulation time 5947369446 ps
CPU time 109.96 seconds
Started Jul 03 05:27:58 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 515468 kb
Host smart-f2b1bd00-e998-4b5d-8534-6631486194a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525603518 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stress_all.525603518
Directory /workspace/36.i2c_host_stress_all/latest

Test location /workspace/coverage/default/36.i2c_host_stretch_timeout.3819918937
Short name T87
Test name
Test status
Simulation time 2444230474 ps
CPU time 9.51 seconds
Started Jul 03 05:27:48 PM PDT 24
Finished Jul 03 05:27:58 PM PDT 24
Peak memory 221316 kb
Host smart-43648b99-aff1-452b-92e6-27c34aa960e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819918937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_host_stretch_timeout.3819918937
Directory /workspace/36.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/36.i2c_target_bad_addr.1460930152
Short name T547
Test name
Test status
Simulation time 1116131030 ps
CPU time 5.1 seconds
Started Jul 03 05:27:58 PM PDT 24
Finished Jul 03 05:28:04 PM PDT 24
Peak memory 213036 kb
Host smart-da9acc8f-79f4-4e56-93fb-578de627dfc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460930152 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.i2c_target_bad_addr.1460930152
Directory /workspace/36.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_acq.3193904696
Short name T152
Test name
Test status
Simulation time 253155208 ps
CPU time 1.43 seconds
Started Jul 03 05:28:03 PM PDT 24
Finished Jul 03 05:28:05 PM PDT 24
Peak memory 204780 kb
Host smart-939a0d21-5d65-49c5-a907-ee41b38d934c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193904696 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_fifo_reset_acq.3193904696
Directory /workspace/36.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_reset_tx.3030806807
Short name T796
Test name
Test status
Simulation time 447260629 ps
CPU time 1.18 seconds
Started Jul 03 05:28:04 PM PDT 24
Finished Jul 03 05:28:06 PM PDT 24
Peak memory 204832 kb
Host smart-d8d60c5a-a8aa-4f69-b735-b9ecb4a22c74
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030806807 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 36.i2c_target_fifo_reset_tx.3030806807
Directory /workspace/36.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_acq.3455317004
Short name T1431
Test name
Test status
Simulation time 2372159669 ps
CPU time 2.96 seconds
Started Jul 03 05:27:54 PM PDT 24
Finished Jul 03 05:27:57 PM PDT 24
Peak memory 204900 kb
Host smart-15922ffc-6b1d-4548-af09-c5f5455d4d80
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455317004 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.i2c_target_fifo_watermarks_acq.3455317004
Directory /workspace/36.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/36.i2c_target_fifo_watermarks_tx.1873254756
Short name T287
Test name
Test status
Simulation time 111887699 ps
CPU time 1.06 seconds
Started Jul 03 05:27:56 PM PDT 24
Finished Jul 03 05:27:57 PM PDT 24
Peak memory 204616 kb
Host smart-12d6f5fc-8832-4307-af01-312a8ec09f50
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873254756 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 36.i2c_target_fifo_watermarks_tx.1873254756
Directory /workspace/36.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/36.i2c_target_intr_smoke.736290526
Short name T675
Test name
Test status
Simulation time 2687407358 ps
CPU time 4.01 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:27:55 PM PDT 24
Peak memory 204956 kb
Host smart-e324f880-3d69-4f21-8d30-39dc325af440
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736290526 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 36.i2c_target_intr_smoke.736290526
Directory /workspace/36.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_intr_stress_wr.2773911968
Short name T693
Test name
Test status
Simulation time 25088283130 ps
CPU time 92.91 seconds
Started Jul 03 05:27:57 PM PDT 24
Finished Jul 03 05:29:30 PM PDT 24
Peak memory 1115068 kb
Host smart-3e27d052-57d6-4bd5-8c2c-db0227338224
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773911968 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.i2c_target_intr_stress_wr.2773911968
Directory /workspace/36.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_smoke.1350285265
Short name T170
Test name
Test status
Simulation time 3953437098 ps
CPU time 32.96 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:28:24 PM PDT 24
Peak memory 204896 kb
Host smart-49412043-4816-48aa-8ed8-c2ffdb8b94f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350285265 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_ta
rget_smoke.1350285265
Directory /workspace/36.i2c_target_smoke/latest

Test location /workspace/coverage/default/36.i2c_target_stress_rd.661964419
Short name T779
Test name
Test status
Simulation time 6079862658 ps
CPU time 45.39 seconds
Started Jul 03 05:27:51 PM PDT 24
Finished Jul 03 05:28:36 PM PDT 24
Peak memory 204920 kb
Host smart-8c8a891d-7c6a-43f7-8a26-1c70fa7615c4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661964419 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c
_target_stress_rd.661964419
Directory /workspace/36.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/36.i2c_target_stress_wr.2704118115
Short name T22
Test name
Test status
Simulation time 53500760966 ps
CPU time 1403.98 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:51:13 PM PDT 24
Peak memory 8443844 kb
Host smart-a91915db-0672-4015-be2e-bcf81dbf85be
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704118115 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2
c_target_stress_wr.2704118115
Directory /workspace/36.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/36.i2c_target_stretch.3703501154
Short name T722
Test name
Test status
Simulation time 24446284825 ps
CPU time 545.12 seconds
Started Jul 03 05:27:49 PM PDT 24
Finished Jul 03 05:36:55 PM PDT 24
Peak memory 1773160 kb
Host smart-55de6fa3-b44a-4df4-a650-77b6cb4b4da1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703501154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.i2c_
target_stretch.3703501154
Directory /workspace/36.i2c_target_stretch/latest

Test location /workspace/coverage/default/36.i2c_target_tx_stretch_ctrl.3239076145
Short name T940
Test name
Test status
Simulation time 167771467 ps
CPU time 3.01 seconds
Started Jul 03 05:28:01 PM PDT 24
Finished Jul 03 05:28:04 PM PDT 24
Peak memory 204860 kb
Host smart-9eab7368-62d3-4515-aee2-6f03ae13147f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239076145 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.i2c_target_tx_stretch_ctrl.3239076145
Directory /workspace/36.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/37.i2c_alert_test.2741798884
Short name T933
Test name
Test status
Simulation time 26118363 ps
CPU time 0.64 seconds
Started Jul 03 05:28:02 PM PDT 24
Finished Jul 03 05:28:03 PM PDT 24
Peak memory 204508 kb
Host smart-19b3df55-0fdc-464c-9971-852f861932b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741798884 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_alert_test.2741798884
Directory /workspace/37.i2c_alert_test/latest

Test location /workspace/coverage/default/37.i2c_host_error_intr.1376280859
Short name T830
Test name
Test status
Simulation time 105600193 ps
CPU time 2.04 seconds
Started Jul 03 05:28:00 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 220364 kb
Host smart-e44738e8-e05e-446f-ba99-7da05a1b5819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376280859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_error_intr.1376280859
Directory /workspace/37.i2c_host_error_intr/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_fmt_empty.818066250
Short name T1527
Test name
Test status
Simulation time 279626464 ps
CPU time 4.86 seconds
Started Jul 03 05:28:01 PM PDT 24
Finished Jul 03 05:28:07 PM PDT 24
Peak memory 243584 kb
Host smart-b786722e-2bcf-4f7f-80e4-92fbc59f1e06
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818066250 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_fmt_empt
y.818066250
Directory /workspace/37.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_full.1770159091
Short name T756
Test name
Test status
Simulation time 7414041524 ps
CPU time 108.7 seconds
Started Jul 03 05:27:52 PM PDT 24
Finished Jul 03 05:29:41 PM PDT 24
Peak memory 561520 kb
Host smart-5edb6cf4-993d-454b-9b33-26a194fa9b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770159091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_full.1770159091
Directory /workspace/37.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_overflow.360774463
Short name T578
Test name
Test status
Simulation time 5260341769 ps
CPU time 81.36 seconds
Started Jul 03 05:27:57 PM PDT 24
Finished Jul 03 05:29:19 PM PDT 24
Peak memory 507440 kb
Host smart-9661d25d-7149-4d55-ab10-bd1b92f366f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360774463 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_overflow.360774463
Directory /workspace/37.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_fmt.257820328
Short name T1173
Test name
Test status
Simulation time 385736444 ps
CPU time 0.97 seconds
Started Jul 03 05:27:58 PM PDT 24
Finished Jul 03 05:27:59 PM PDT 24
Peak memory 204476 kb
Host smart-fae7c11d-1d4b-455b-bdb1-7af035151170
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257820328 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_fm
t.257820328
Directory /workspace/37.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_reset_rx.1744175462
Short name T882
Test name
Test status
Simulation time 621694568 ps
CPU time 3.83 seconds
Started Jul 03 05:27:58 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 204784 kb
Host smart-f29ac135-d5bf-4a1e-835d-92888920e601
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744175462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_reset_rx
.1744175462
Directory /workspace/37.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/37.i2c_host_fifo_watermark.2610635888
Short name T908
Test name
Test status
Simulation time 2785551607 ps
CPU time 62.45 seconds
Started Jul 03 05:27:59 PM PDT 24
Finished Jul 03 05:29:01 PM PDT 24
Peak memory 896128 kb
Host smart-58960973-354e-4d80-9040-06ffa08c2f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610635888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_fifo_watermark.2610635888
Directory /workspace/37.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/37.i2c_host_may_nack.3088831556
Short name T319
Test name
Test status
Simulation time 1253069806 ps
CPU time 25.47 seconds
Started Jul 03 05:28:01 PM PDT 24
Finished Jul 03 05:28:27 PM PDT 24
Peak memory 204832 kb
Host smart-1771311f-324b-42a4-aabd-a9293e672f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088831556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_may_nack.3088831556
Directory /workspace/37.i2c_host_may_nack/latest

Test location /workspace/coverage/default/37.i2c_host_mode_toggle.578427599
Short name T68
Test name
Test status
Simulation time 17618870141 ps
CPU time 62.38 seconds
Started Jul 03 05:27:57 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 364744 kb
Host smart-f4403a76-a82e-42ad-a955-baee8ebe7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578427599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_mode_toggle.578427599
Directory /workspace/37.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/37.i2c_host_override.415001599
Short name T132
Test name
Test status
Simulation time 119293769 ps
CPU time 0.65 seconds
Started Jul 03 05:28:03 PM PDT 24
Finished Jul 03 05:28:04 PM PDT 24
Peak memory 204536 kb
Host smart-eb6a7f37-a556-4075-8931-cc55b623ee21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415001599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_override.415001599
Directory /workspace/37.i2c_host_override/latest

Test location /workspace/coverage/default/37.i2c_host_perf.3434854225
Short name T571
Test name
Test status
Simulation time 6999128068 ps
CPU time 94.34 seconds
Started Jul 03 05:28:04 PM PDT 24
Finished Jul 03 05:29:39 PM PDT 24
Peak memory 585696 kb
Host smart-9005c5b9-fa85-41e0-9697-02e971661302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434854225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf.3434854225
Directory /workspace/37.i2c_host_perf/latest

Test location /workspace/coverage/default/37.i2c_host_perf_precise.1485993384
Short name T814
Test name
Test status
Simulation time 223471643 ps
CPU time 9.09 seconds
Started Jul 03 05:27:54 PM PDT 24
Finished Jul 03 05:28:03 PM PDT 24
Peak memory 204660 kb
Host smart-b0365475-0ba3-4dae-a714-4ad78e90ba92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485993384 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_perf_precise.1485993384
Directory /workspace/37.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/37.i2c_host_smoke.1031603622
Short name T1351
Test name
Test status
Simulation time 24270910895 ps
CPU time 34.87 seconds
Started Jul 03 05:28:00 PM PDT 24
Finished Jul 03 05:28:36 PM PDT 24
Peak memory 359572 kb
Host smart-e0b07124-8832-47e6-829c-0fb7e100f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031603622 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_smoke.1031603622
Directory /workspace/37.i2c_host_smoke/latest

Test location /workspace/coverage/default/37.i2c_host_stress_all.219926589
Short name T85
Test name
Test status
Simulation time 62191572571 ps
CPU time 505.04 seconds
Started Jul 03 05:27:54 PM PDT 24
Finished Jul 03 05:36:20 PM PDT 24
Peak memory 2184336 kb
Host smart-c8b07005-a78e-483a-bc47-238a9f909ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219926589 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stress_all.219926589
Directory /workspace/37.i2c_host_stress_all/latest

Test location /workspace/coverage/default/37.i2c_host_stretch_timeout.1436513321
Short name T401
Test name
Test status
Simulation time 891825945 ps
CPU time 39.99 seconds
Started Jul 03 05:28:03 PM PDT 24
Finished Jul 03 05:28:43 PM PDT 24
Peak memory 212972 kb
Host smart-758eecfc-5d3f-454c-8a64-c9c7972ca5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436513321 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_host_stretch_timeout.1436513321
Directory /workspace/37.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_bad_addr.1580138793
Short name T326
Test name
Test status
Simulation time 7965403792 ps
CPU time 6.31 seconds
Started Jul 03 05:28:00 PM PDT 24
Finished Jul 03 05:28:07 PM PDT 24
Peak memory 218596 kb
Host smart-6f099673-4bc2-482a-a21d-ba88e1535d4e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580138793 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.i2c_target_bad_addr.1580138793
Directory /workspace/37.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_acq.297830000
Short name T1187
Test name
Test status
Simulation time 263316441 ps
CPU time 1.08 seconds
Started Jul 03 05:27:57 PM PDT 24
Finished Jul 03 05:27:58 PM PDT 24
Peak memory 204816 kb
Host smart-df77bb0b-8226-4ba1-8886-fc232506c2e6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297830000 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_acq.297830000
Directory /workspace/37.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_reset_tx.1671517409
Short name T1005
Test name
Test status
Simulation time 185693065 ps
CPU time 0.99 seconds
Started Jul 03 05:28:06 PM PDT 24
Finished Jul 03 05:28:07 PM PDT 24
Peak memory 204604 kb
Host smart-8fa7651c-f17b-4857-9ebb-da5aea83cf33
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671517409 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 37.i2c_target_fifo_reset_tx.1671517409
Directory /workspace/37.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_acq.3477588771
Short name T1027
Test name
Test status
Simulation time 1359546853 ps
CPU time 2.68 seconds
Started Jul 03 05:28:00 PM PDT 24
Finished Jul 03 05:28:03 PM PDT 24
Peak memory 204808 kb
Host smart-fd65b909-1583-48b5-bef5-7306e7e19de0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477588771 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.i2c_target_fifo_watermarks_acq.3477588771
Directory /workspace/37.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/37.i2c_target_fifo_watermarks_tx.91568819
Short name T1208
Test name
Test status
Simulation time 413372224 ps
CPU time 1.16 seconds
Started Jul 03 05:28:00 PM PDT 24
Finished Jul 03 05:28:02 PM PDT 24
Peak memory 204596 kb
Host smart-67e64fc5-809d-4e81-abc2-84600cc26371
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91568819 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 37.i2c_target_fifo_watermarks_tx.91568819
Directory /workspace/37.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/37.i2c_target_intr_smoke.2555479690
Short name T965
Test name
Test status
Simulation time 846170042 ps
CPU time 5.31 seconds
Started Jul 03 05:28:07 PM PDT 24
Finished Jul 03 05:28:12 PM PDT 24
Peak memory 213024 kb
Host smart-cbc4beb4-0868-4a4a-b52c-c67905e36f1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555479690 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_intr_smoke.2555479690
Directory /workspace/37.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_intr_stress_wr.542010415
Short name T874
Test name
Test status
Simulation time 3300936921 ps
CPU time 5.91 seconds
Started Jul 03 05:28:04 PM PDT 24
Finished Jul 03 05:28:10 PM PDT 24
Peak memory 204896 kb
Host smart-65cc268e-973c-45ca-82b8-df822407676e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542010415 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.i2c_target_intr_stress_wr.542010415
Directory /workspace/37.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_smoke.4239183515
Short name T877
Test name
Test status
Simulation time 752343882 ps
CPU time 11.78 seconds
Started Jul 03 05:27:58 PM PDT 24
Finished Jul 03 05:28:10 PM PDT 24
Peak memory 204856 kb
Host smart-57f20d4e-3381-42ef-8ed8-cb22f4e6636d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239183515 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_ta
rget_smoke.4239183515
Directory /workspace/37.i2c_target_smoke/latest

Test location /workspace/coverage/default/37.i2c_target_stress_rd.3561623984
Short name T1159
Test name
Test status
Simulation time 1722921417 ps
CPU time 21.09 seconds
Started Jul 03 05:28:01 PM PDT 24
Finished Jul 03 05:28:23 PM PDT 24
Peak memory 215160 kb
Host smart-9458c203-8281-49b8-a627-8c27f859d7aa
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561623984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_rd.3561623984
Directory /workspace/37.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/37.i2c_target_stress_wr.3479645855
Short name T1218
Test name
Test status
Simulation time 11824539486 ps
CPU time 24.06 seconds
Started Jul 03 05:28:01 PM PDT 24
Finished Jul 03 05:28:25 PM PDT 24
Peak memory 204892 kb
Host smart-9883cd45-a8c3-48bf-9cd3-ccc6329b77b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479645855 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2
c_target_stress_wr.3479645855
Directory /workspace/37.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/37.i2c_target_stretch.1146339795
Short name T1286
Test name
Test status
Simulation time 34704181096 ps
CPU time 286.8 seconds
Started Jul 03 05:28:05 PM PDT 24
Finished Jul 03 05:32:52 PM PDT 24
Peak memory 2089244 kb
Host smart-de4a7fa2-ab02-498b-919b-d5694d70d183
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146339795 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.i2c_
target_stretch.1146339795
Directory /workspace/37.i2c_target_stretch/latest

Test location /workspace/coverage/default/37.i2c_target_timeout.274741593
Short name T389
Test name
Test status
Simulation time 4903473685 ps
CPU time 7.1 seconds
Started Jul 03 05:28:00 PM PDT 24
Finished Jul 03 05:28:08 PM PDT 24
Peak memory 221228 kb
Host smart-8d11d0fd-478a-4074-9562-dd5ffa6150f3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274741593 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 37.i2c_target_timeout.274741593
Directory /workspace/37.i2c_target_timeout/latest

Test location /workspace/coverage/default/37.i2c_target_tx_stretch_ctrl.3654138747
Short name T1401
Test name
Test status
Simulation time 171913282 ps
CPU time 3.44 seconds
Started Jul 03 05:28:06 PM PDT 24
Finished Jul 03 05:28:09 PM PDT 24
Peak memory 204812 kb
Host smart-5a10f336-8c73-48b1-b91b-a7840b1f7dc9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654138747 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.i2c_target_tx_stretch_ctrl.3654138747
Directory /workspace/37.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/38.i2c_alert_test.2486521742
Short name T795
Test name
Test status
Simulation time 40584891 ps
CPU time 0.6 seconds
Started Jul 03 05:28:07 PM PDT 24
Finished Jul 03 05:28:08 PM PDT 24
Peak memory 204308 kb
Host smart-8eef7d89-96cd-4182-b034-3647cfbce583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486521742 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_alert_test.2486521742
Directory /workspace/38.i2c_alert_test/latest

Test location /workspace/coverage/default/38.i2c_host_error_intr.4259775571
Short name T1324
Test name
Test status
Simulation time 209257267 ps
CPU time 1.46 seconds
Started Jul 03 05:27:59 PM PDT 24
Finished Jul 03 05:28:01 PM PDT 24
Peak memory 213148 kb
Host smart-84bb75ed-10a8-4367-985f-c4fe63a1fc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259775571 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_error_intr.4259775571
Directory /workspace/38.i2c_host_error_intr/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_fmt_empty.1264707876
Short name T720
Test name
Test status
Simulation time 1985270015 ps
CPU time 3.82 seconds
Started Jul 03 05:28:01 PM PDT 24
Finished Jul 03 05:28:06 PM PDT 24
Peak memory 241156 kb
Host smart-af4831ad-ca39-45dc-8ab6-e9488956a52f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264707876 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_fmt_emp
ty.1264707876
Directory /workspace/38.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_full.1317932695
Short name T684
Test name
Test status
Simulation time 1120715757 ps
CPU time 64.65 seconds
Started Jul 03 05:28:01 PM PDT 24
Finished Jul 03 05:29:06 PM PDT 24
Peak memory 400636 kb
Host smart-5f4e6b3c-80ca-456b-bb3a-46e167712644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317932695 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_full.1317932695
Directory /workspace/38.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_overflow.2983828372
Short name T748
Test name
Test status
Simulation time 5589698533 ps
CPU time 32.08 seconds
Started Jul 03 05:28:06 PM PDT 24
Finished Jul 03 05:28:38 PM PDT 24
Peak memory 444808 kb
Host smart-995fe37a-a34f-47c5-9eb1-b292c23cd0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983828372 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_overflow.2983828372
Directory /workspace/38.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_fmt.2789610297
Short name T700
Test name
Test status
Simulation time 118473277 ps
CPU time 0.99 seconds
Started Jul 03 05:28:07 PM PDT 24
Finished Jul 03 05:28:08 PM PDT 24
Peak memory 204484 kb
Host smart-16afe83d-487b-4abb-8668-c33d6e2ff942
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789610297 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_f
mt.2789610297
Directory /workspace/38.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_reset_rx.146863221
Short name T640
Test name
Test status
Simulation time 193764957 ps
CPU time 4.15 seconds
Started Jul 03 05:28:04 PM PDT 24
Finished Jul 03 05:28:08 PM PDT 24
Peak memory 204796 kb
Host smart-ce3d7181-8944-4492-a003-4a0927291aea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146863221 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_reset_rx.
146863221
Directory /workspace/38.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/38.i2c_host_fifo_watermark.423584263
Short name T409
Test name
Test status
Simulation time 3174205491 ps
CPU time 199.29 seconds
Started Jul 03 05:28:07 PM PDT 24
Finished Jul 03 05:31:26 PM PDT 24
Peak memory 885824 kb
Host smart-151494b0-a97c-4d07-b575-a41a4888f96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423584263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_fifo_watermark.423584263
Directory /workspace/38.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/38.i2c_host_may_nack.161648138
Short name T733
Test name
Test status
Simulation time 1245541788 ps
CPU time 12.03 seconds
Started Jul 03 05:28:06 PM PDT 24
Finished Jul 03 05:28:18 PM PDT 24
Peak memory 204880 kb
Host smart-fb72a5b2-d46f-46b0-93a4-4a1267784043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161648138 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_may_nack.161648138
Directory /workspace/38.i2c_host_may_nack/latest

Test location /workspace/coverage/default/38.i2c_host_mode_toggle.4231284961
Short name T1448
Test name
Test status
Simulation time 2105718885 ps
CPU time 28.09 seconds
Started Jul 03 05:28:09 PM PDT 24
Finished Jul 03 05:28:38 PM PDT 24
Peak memory 293020 kb
Host smart-83cc82d5-dd3f-4cd2-82bc-f6d3d49b4fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231284961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_mode_toggle.4231284961
Directory /workspace/38.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/38.i2c_host_override.2994218761
Short name T507
Test name
Test status
Simulation time 20161232 ps
CPU time 0.72 seconds
Started Jul 03 05:28:06 PM PDT 24
Finished Jul 03 05:28:07 PM PDT 24
Peak memory 204488 kb
Host smart-00a6039b-2196-4490-9599-ddc9792860de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994218761 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_override.2994218761
Directory /workspace/38.i2c_host_override/latest

Test location /workspace/coverage/default/38.i2c_host_perf.2753186502
Short name T859
Test name
Test status
Simulation time 12999541888 ps
CPU time 89.07 seconds
Started Jul 03 05:28:07 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 205000 kb
Host smart-10b50651-2e14-40d8-a0f9-23bbd8760f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753186502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf.2753186502
Directory /workspace/38.i2c_host_perf/latest

Test location /workspace/coverage/default/38.i2c_host_perf_precise.2132466822
Short name T470
Test name
Test status
Simulation time 3273300659 ps
CPU time 13.71 seconds
Started Jul 03 05:28:03 PM PDT 24
Finished Jul 03 05:28:18 PM PDT 24
Peak memory 204780 kb
Host smart-b4168de9-14b0-4cab-96dc-823228a11a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132466822 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_perf_precise.2132466822
Directory /workspace/38.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/38.i2c_host_smoke.3854128077
Short name T485
Test name
Test status
Simulation time 9131342955 ps
CPU time 36.96 seconds
Started Jul 03 05:27:56 PM PDT 24
Finished Jul 03 05:28:34 PM PDT 24
Peak memory 383716 kb
Host smart-7a643513-8514-4857-a589-0acccda8eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854128077 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_smoke.3854128077
Directory /workspace/38.i2c_host_smoke/latest

Test location /workspace/coverage/default/38.i2c_host_stress_all.2475876912
Short name T62
Test name
Test status
Simulation time 29491219139 ps
CPU time 661.4 seconds
Started Jul 03 05:28:05 PM PDT 24
Finished Jul 03 05:39:07 PM PDT 24
Peak memory 2739512 kb
Host smart-40c6de86-33ed-459b-9c67-125e7678fbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475876912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stress_all.2475876912
Directory /workspace/38.i2c_host_stress_all/latest

Test location /workspace/coverage/default/38.i2c_host_stretch_timeout.2867785401
Short name T187
Test name
Test status
Simulation time 1844530572 ps
CPU time 43.25 seconds
Started Jul 03 05:28:05 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 213080 kb
Host smart-d08fb70a-edd8-436d-b9fc-530ecf88d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867785401 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_host_stretch_timeout.2867785401
Directory /workspace/38.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_bad_addr.1493151460
Short name T1082
Test name
Test status
Simulation time 1341688058 ps
CPU time 6.2 seconds
Started Jul 03 05:28:08 PM PDT 24
Finished Jul 03 05:28:15 PM PDT 24
Peak memory 214264 kb
Host smart-05686921-9f16-4d14-bca4-4f740821d99f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493151460 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 38.i2c_target_bad_addr.1493151460
Directory /workspace/38.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_acq.2370880165
Short name T475
Test name
Test status
Simulation time 270457624 ps
CPU time 0.85 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 204648 kb
Host smart-38ee71bb-798d-4790-98cc-3ce21b547eb6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370880165 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_fifo_reset_acq.2370880165
Directory /workspace/38.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_reset_tx.2639256588
Short name T659
Test name
Test status
Simulation time 162712374 ps
CPU time 1.09 seconds
Started Jul 03 05:28:05 PM PDT 24
Finished Jul 03 05:28:07 PM PDT 24
Peak memory 212852 kb
Host smart-6e0998bd-c9e6-41d7-b2f6-843263e492f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639256588 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.i2c_target_fifo_reset_tx.2639256588
Directory /workspace/38.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_acq.3664689759
Short name T797
Test name
Test status
Simulation time 2274481305 ps
CPU time 2.74 seconds
Started Jul 03 05:28:08 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 204936 kb
Host smart-9154c8a2-2c87-4100-9437-8ed55d49f2b2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664689759 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.i2c_target_fifo_watermarks_acq.3664689759
Directory /workspace/38.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/38.i2c_target_fifo_watermarks_tx.4067107076
Short name T767
Test name
Test status
Simulation time 624036636 ps
CPU time 1.24 seconds
Started Jul 03 05:28:08 PM PDT 24
Finished Jul 03 05:28:09 PM PDT 24
Peak memory 204580 kb
Host smart-1650ab6d-cc50-49ad-aca9-267158de1f17
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067107076 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.i2c_target_fifo_watermarks_tx.4067107076
Directory /workspace/38.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/38.i2c_target_hrst.1111558368
Short name T406
Test name
Test status
Simulation time 1345578164 ps
CPU time 2.66 seconds
Started Jul 03 05:28:13 PM PDT 24
Finished Jul 03 05:28:16 PM PDT 24
Peak memory 204816 kb
Host smart-6676416f-0869-4232-958f-c2793a9894a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111558368 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_hrst.1111558368
Directory /workspace/38.i2c_target_hrst/latest

Test location /workspace/coverage/default/38.i2c_target_intr_smoke.178467621
Short name T735
Test name
Test status
Simulation time 3963829724 ps
CPU time 4.66 seconds
Started Jul 03 05:28:04 PM PDT 24
Finished Jul 03 05:28:09 PM PDT 24
Peak memory 213052 kb
Host smart-9aa021ab-7c03-4957-917d-c5c2bcc31732
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178467621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 38.i2c_target_intr_smoke.178467621
Directory /workspace/38.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_intr_stress_wr.143152598
Short name T526
Test name
Test status
Simulation time 7567025576 ps
CPU time 9.11 seconds
Started Jul 03 05:28:01 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 204940 kb
Host smart-9d29e1bc-fb86-4e11-b181-47bfec15725f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143152598 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.i2c_target_intr_stress_wr.143152598
Directory /workspace/38.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_smoke.908481824
Short name T1035
Test name
Test status
Simulation time 1033297952 ps
CPU time 15.89 seconds
Started Jul 03 05:28:07 PM PDT 24
Finished Jul 03 05:28:24 PM PDT 24
Peak memory 204816 kb
Host smart-cb3ac633-3efa-4d07-846a-bcb211f514e3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908481824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_tar
get_smoke.908481824
Directory /workspace/38.i2c_target_smoke/latest

Test location /workspace/coverage/default/38.i2c_target_stress_rd.2508919793
Short name T1347
Test name
Test status
Simulation time 1075460533 ps
CPU time 6.81 seconds
Started Jul 03 05:28:08 PM PDT 24
Finished Jul 03 05:28:15 PM PDT 24
Peak memory 204832 kb
Host smart-1a6c3553-ed83-4317-80a0-cafaeb049a99
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508919793 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_rd.2508919793
Directory /workspace/38.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/38.i2c_target_stress_wr.2349435055
Short name T1318
Test name
Test status
Simulation time 59221808269 ps
CPU time 207.3 seconds
Started Jul 03 05:27:59 PM PDT 24
Finished Jul 03 05:31:27 PM PDT 24
Peak memory 2593484 kb
Host smart-bdb96630-03af-4658-b370-20c559003256
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349435055 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2
c_target_stress_wr.2349435055
Directory /workspace/38.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/38.i2c_target_stretch.782290941
Short name T472
Test name
Test status
Simulation time 28192639805 ps
CPU time 1956.65 seconds
Started Jul 03 05:28:00 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 6828140 kb
Host smart-f4986c18-687e-43ee-b49f-8a5026051ef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782290941 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.i2c_t
arget_stretch.782290941
Directory /workspace/38.i2c_target_stretch/latest

Test location /workspace/coverage/default/38.i2c_target_timeout.583364350
Short name T207
Test name
Test status
Simulation time 1050309675 ps
CPU time 6.05 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:28:17 PM PDT 24
Peak memory 219548 kb
Host smart-46aeda9d-5a43-4c06-b47a-9b6d45483af3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583364350 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 38.i2c_target_timeout.583364350
Directory /workspace/38.i2c_target_timeout/latest

Test location /workspace/coverage/default/38.i2c_target_tx_stretch_ctrl.635645769
Short name T894
Test name
Test status
Simulation time 134043640 ps
CPU time 2.28 seconds
Started Jul 03 05:28:03 PM PDT 24
Finished Jul 03 05:28:05 PM PDT 24
Peak memory 204832 kb
Host smart-64f6b5a7-976a-4354-9d6b-f3ee2f793e82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635645769 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.i2c_target_tx_stretch_ctrl.635645769
Directory /workspace/38.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/39.i2c_alert_test.1705697541
Short name T842
Test name
Test status
Simulation time 47582398 ps
CPU time 0.68 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 204492 kb
Host smart-0c52a7b9-ffc7-4d68-944e-e3c30efd6893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705697541 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_alert_test.1705697541
Directory /workspace/39.i2c_alert_test/latest

Test location /workspace/coverage/default/39.i2c_host_error_intr.1696618030
Short name T1026
Test name
Test status
Simulation time 168861350 ps
CPU time 2.13 seconds
Started Jul 03 05:28:08 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 220404 kb
Host smart-722ef658-5faf-4d7c-9f70-561b540e91fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696618030 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_error_intr.1696618030
Directory /workspace/39.i2c_host_error_intr/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_fmt_empty.2349105437
Short name T726
Test name
Test status
Simulation time 373680163 ps
CPU time 8.44 seconds
Started Jul 03 05:28:05 PM PDT 24
Finished Jul 03 05:28:14 PM PDT 24
Peak memory 285048 kb
Host smart-3e629b47-021a-4fdb-aa14-ebf399da9207
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349105437 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_fmt_emp
ty.2349105437
Directory /workspace/39.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_full.304279444
Short name T771
Test name
Test status
Simulation time 2106090871 ps
CPU time 69.6 seconds
Started Jul 03 05:28:07 PM PDT 24
Finished Jul 03 05:29:17 PM PDT 24
Peak memory 712736 kb
Host smart-53e2618b-e436-4a40-ae56-3e607fb24a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304279444 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_full.304279444
Directory /workspace/39.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_overflow.951796018
Short name T382
Test name
Test status
Simulation time 4861904706 ps
CPU time 71.32 seconds
Started Jul 03 05:28:09 PM PDT 24
Finished Jul 03 05:29:21 PM PDT 24
Peak memory 750612 kb
Host smart-8479dcf6-546c-46b9-b37b-4412b0ef3399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951796018 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_overflow.951796018
Directory /workspace/39.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_fmt.747658091
Short name T1260
Test name
Test status
Simulation time 528933018 ps
CPU time 1.04 seconds
Started Jul 03 05:28:09 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 204448 kb
Host smart-55a8053e-76aa-494f-a376-fd8d21a4628c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747658091 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_fm
t.747658091
Directory /workspace/39.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_reset_rx.2583989186
Short name T848
Test name
Test status
Simulation time 501965377 ps
CPU time 2.94 seconds
Started Jul 03 05:28:03 PM PDT 24
Finished Jul 03 05:28:06 PM PDT 24
Peak memory 204708 kb
Host smart-1f76c044-5a47-4d3e-abbe-52d98e44500a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583989186 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_reset_rx
.2583989186
Directory /workspace/39.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/39.i2c_host_fifo_watermark.4211361313
Short name T337
Test name
Test status
Simulation time 20990416481 ps
CPU time 158.87 seconds
Started Jul 03 05:28:11 PM PDT 24
Finished Jul 03 05:30:50 PM PDT 24
Peak memory 1456908 kb
Host smart-7476811d-2f5b-40e1-bff8-5e681d25ec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211361313 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_fifo_watermark.4211361313
Directory /workspace/39.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/39.i2c_host_may_nack.1708909031
Short name T1510
Test name
Test status
Simulation time 345804040 ps
CPU time 13.6 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:28:29 PM PDT 24
Peak memory 204856 kb
Host smart-8c311e8c-30f3-42ac-8407-2fe125569295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708909031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_may_nack.1708909031
Directory /workspace/39.i2c_host_may_nack/latest

Test location /workspace/coverage/default/39.i2c_host_mode_toggle.959061239
Short name T988
Test name
Test status
Simulation time 3315191664 ps
CPU time 80.74 seconds
Started Jul 03 05:28:14 PM PDT 24
Finished Jul 03 05:29:35 PM PDT 24
Peak memory 369180 kb
Host smart-0087fab7-b203-447a-93a0-49a4c7208b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959061239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_mode_toggle.959061239
Directory /workspace/39.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/39.i2c_host_override.2263818206
Short name T71
Test name
Test status
Simulation time 29156730 ps
CPU time 0.7 seconds
Started Jul 03 05:28:05 PM PDT 24
Finished Jul 03 05:28:06 PM PDT 24
Peak memory 204532 kb
Host smart-72dcd6cd-2084-4880-b7e7-892f1b6cd5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263818206 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_override.2263818206
Directory /workspace/39.i2c_host_override/latest

Test location /workspace/coverage/default/39.i2c_host_perf.2211314502
Short name T550
Test name
Test status
Simulation time 26277158797 ps
CPU time 318.49 seconds
Started Jul 03 05:28:09 PM PDT 24
Finished Jul 03 05:33:27 PM PDT 24
Peak memory 499836 kb
Host smart-60d70f6b-4706-49bb-ab18-1f78343616ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211314502 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf.2211314502
Directory /workspace/39.i2c_host_perf/latest

Test location /workspace/coverage/default/39.i2c_host_perf_precise.2014523569
Short name T1117
Test name
Test status
Simulation time 1050080264 ps
CPU time 25.53 seconds
Started Jul 03 05:28:03 PM PDT 24
Finished Jul 03 05:28:29 PM PDT 24
Peak memory 299420 kb
Host smart-31c59e10-d855-4a8f-9ef6-bc63b1fa862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014523569 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_perf_precise.2014523569
Directory /workspace/39.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/39.i2c_host_smoke.1968022346
Short name T1229
Test name
Test status
Simulation time 5225418826 ps
CPU time 19.44 seconds
Started Jul 03 05:28:13 PM PDT 24
Finished Jul 03 05:28:32 PM PDT 24
Peak memory 300368 kb
Host smart-13a235a1-de26-443d-a422-d40db07d77ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968022346 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_smoke.1968022346
Directory /workspace/39.i2c_host_smoke/latest

Test location /workspace/coverage/default/39.i2c_host_stretch_timeout.2614892787
Short name T54
Test name
Test status
Simulation time 1920450983 ps
CPU time 18.41 seconds
Started Jul 03 05:28:08 PM PDT 24
Finished Jul 03 05:28:27 PM PDT 24
Peak memory 212992 kb
Host smart-34d8a9e4-6c4a-4f65-a755-976b2544c69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614892787 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_host_stretch_timeout.2614892787
Directory /workspace/39.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_bad_addr.4251658047
Short name T1278
Test name
Test status
Simulation time 1208236936 ps
CPU time 5.95 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:28:17 PM PDT 24
Peak memory 213060 kb
Host smart-5036ab86-cb5c-4669-a13a-570a1f53c5ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251658047 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 39.i2c_target_bad_addr.4251658047
Directory /workspace/39.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_acq.1572107785
Short name T151
Test name
Test status
Simulation time 606586361 ps
CPU time 1.34 seconds
Started Jul 03 05:28:13 PM PDT 24
Finished Jul 03 05:28:14 PM PDT 24
Peak memory 204588 kb
Host smart-0f8e6609-203c-4887-9eee-fd5348861fc2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572107785 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_fifo_reset_acq.1572107785
Directory /workspace/39.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_reset_tx.4190508434
Short name T315
Test name
Test status
Simulation time 198293702 ps
CPU time 1.25 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:28:12 PM PDT 24
Peak memory 204816 kb
Host smart-2cc2cc33-1aeb-498c-baf8-066fdd30e714
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190508434 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.i2c_target_fifo_reset_tx.4190508434
Directory /workspace/39.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_acq.561840872
Short name T601
Test name
Test status
Simulation time 411673559 ps
CPU time 2.41 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:19 PM PDT 24
Peak memory 204868 kb
Host smart-2e29e907-85f2-40d5-820d-60f251240b1b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561840872 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_acq.561840872
Directory /workspace/39.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/39.i2c_target_fifo_watermarks_tx.3142863299
Short name T1410
Test name
Test status
Simulation time 353188568 ps
CPU time 1.52 seconds
Started Jul 03 05:28:13 PM PDT 24
Finished Jul 03 05:28:15 PM PDT 24
Peak memory 204612 kb
Host smart-5d7d83d1-59ac-4975-a99a-83f3d2597462
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142863299 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 39.i2c_target_fifo_watermarks_tx.3142863299
Directory /workspace/39.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/39.i2c_target_intr_smoke.3869697136
Short name T958
Test name
Test status
Simulation time 1664138959 ps
CPU time 2.96 seconds
Started Jul 03 05:28:12 PM PDT 24
Finished Jul 03 05:28:15 PM PDT 24
Peak memory 204856 kb
Host smart-a0914584-29cb-4358-aae1-b39e1d95ef4f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869697136 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 39.i2c_target_intr_smoke.3869697136
Directory /workspace/39.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_intr_stress_wr.3362179669
Short name T1529
Test name
Test status
Simulation time 12410336767 ps
CPU time 38.15 seconds
Started Jul 03 05:28:13 PM PDT 24
Finished Jul 03 05:28:51 PM PDT 24
Peak memory 999408 kb
Host smart-dc7f73b8-1475-4052-88fb-1d949d7b0f82
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362179669 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.i2c_target_intr_stress_wr.3362179669
Directory /workspace/39.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_smoke.2380479603
Short name T967
Test name
Test status
Simulation time 1506480662 ps
CPU time 9.87 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:28:20 PM PDT 24
Peak memory 204660 kb
Host smart-6703e640-70ba-4c65-8c97-6afe4d67e936
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380479603 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_ta
rget_smoke.2380479603
Directory /workspace/39.i2c_target_smoke/latest

Test location /workspace/coverage/default/39.i2c_target_stress_rd.697225029
Short name T872
Test name
Test status
Simulation time 3183991110 ps
CPU time 6.93 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:28:23 PM PDT 24
Peak memory 207244 kb
Host smart-a683bb56-cab5-4cea-8fe1-f26bf8feb7c9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697225029 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c
_target_stress_rd.697225029
Directory /workspace/39.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/39.i2c_target_stress_wr.1756254045
Short name T593
Test name
Test status
Simulation time 25299647091 ps
CPU time 40.84 seconds
Started Jul 03 05:28:19 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 701960 kb
Host smart-ed2a26e1-d22d-4eef-82e2-7c3fd63af1e1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756254045 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2
c_target_stress_wr.1756254045
Directory /workspace/39.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/39.i2c_target_stretch.3171363556
Short name T606
Test name
Test status
Simulation time 29959445234 ps
CPU time 494.34 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:36:25 PM PDT 24
Peak memory 1703288 kb
Host smart-308f91f1-29df-449a-8247-3b851164c293
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171363556 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.i2c_
target_stretch.3171363556
Directory /workspace/39.i2c_target_stretch/latest

Test location /workspace/coverage/default/39.i2c_target_timeout.3150610430
Short name T164
Test name
Test status
Simulation time 7821131141 ps
CPU time 7.1 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:28:17 PM PDT 24
Peak memory 216500 kb
Host smart-e03fa4dd-be27-4ba0-980b-7f6c363b55a5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150610430 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.i2c_target_timeout.3150610430
Directory /workspace/39.i2c_target_timeout/latest

Test location /workspace/coverage/default/39.i2c_target_tx_stretch_ctrl.1961475881
Short name T1127
Test name
Test status
Simulation time 101160306 ps
CPU time 1.96 seconds
Started Jul 03 05:28:12 PM PDT 24
Finished Jul 03 05:28:15 PM PDT 24
Peak memory 204812 kb
Host smart-556e998a-429b-4e24-9e2a-e21b87f2c856
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961475881 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.i2c_target_tx_stretch_ctrl.1961475881
Directory /workspace/39.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/4.i2c_alert_test.4068843714
Short name T926
Test name
Test status
Simulation time 21901840 ps
CPU time 0.68 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:25:25 PM PDT 24
Peak memory 204432 kb
Host smart-1fbe9d53-656e-4c47-a28b-fe31f770af02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068843714 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_alert_test.4068843714
Directory /workspace/4.i2c_alert_test/latest

Test location /workspace/coverage/default/4.i2c_host_error_intr.1147215863
Short name T1039
Test name
Test status
Simulation time 331121372 ps
CPU time 2.57 seconds
Started Jul 03 05:25:36 PM PDT 24
Finished Jul 03 05:25:39 PM PDT 24
Peak memory 221292 kb
Host smart-6aa8ca0b-b0aa-469d-bb05-d664d216d7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147215863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_error_intr.1147215863
Directory /workspace/4.i2c_host_error_intr/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_fmt_empty.2029414285
Short name T927
Test name
Test status
Simulation time 360609611 ps
CPU time 6.27 seconds
Started Jul 03 05:25:28 PM PDT 24
Finished Jul 03 05:25:34 PM PDT 24
Peak memory 283596 kb
Host smart-a57b2249-7278-4fb7-a094-dbf4c2e63cf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029414285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_fmt_empt
y.2029414285
Directory /workspace/4.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_full.3584634966
Short name T630
Test name
Test status
Simulation time 6223808742 ps
CPU time 50.99 seconds
Started Jul 03 05:25:17 PM PDT 24
Finished Jul 03 05:26:09 PM PDT 24
Peak memory 592796 kb
Host smart-1775baef-f795-4d1b-a085-9d0d7b570217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584634966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_full.3584634966
Directory /workspace/4.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_overflow.1055418424
Short name T708
Test name
Test status
Simulation time 2052808355 ps
CPU time 150.56 seconds
Started Jul 03 05:25:17 PM PDT 24
Finished Jul 03 05:27:47 PM PDT 24
Peak memory 703164 kb
Host smart-c2ab6bf7-8ac9-4868-a4ec-5b379ad37bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055418424 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_overflow.1055418424
Directory /workspace/4.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_fmt.1107849132
Short name T777
Test name
Test status
Simulation time 108259192 ps
CPU time 0.96 seconds
Started Jul 03 05:25:16 PM PDT 24
Finished Jul 03 05:25:18 PM PDT 24
Peak memory 204424 kb
Host smart-932255af-e260-4732-9e99-5fa3645ff382
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107849132 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_fm
t.1107849132
Directory /workspace/4.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_reset_rx.1344831476
Short name T1083
Test name
Test status
Simulation time 463403012 ps
CPU time 4.45 seconds
Started Jul 03 05:25:31 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 204800 kb
Host smart-61476429-ff8a-48b0-8012-3eb19ab4a328
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344831476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_reset_rx.
1344831476
Directory /workspace/4.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/4.i2c_host_fifo_watermark.1336989147
Short name T1062
Test name
Test status
Simulation time 4839741840 ps
CPU time 318.06 seconds
Started Jul 03 05:25:16 PM PDT 24
Finished Jul 03 05:30:34 PM PDT 24
Peak memory 1245856 kb
Host smart-0205b9d2-ad5f-4677-84bd-6487feeeabfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336989147 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_fifo_watermark.1336989147
Directory /workspace/4.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/4.i2c_host_may_nack.3548240477
Short name T525
Test name
Test status
Simulation time 150566177 ps
CPU time 6.21 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:25:30 PM PDT 24
Peak memory 204876 kb
Host smart-560784bb-0850-4a71-9c7a-279c0dde9310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548240477 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_may_nack.3548240477
Directory /workspace/4.i2c_host_may_nack/latest

Test location /workspace/coverage/default/4.i2c_host_mode_toggle.468865202
Short name T1441
Test name
Test status
Simulation time 9917995003 ps
CPU time 29.43 seconds
Started Jul 03 05:25:29 PM PDT 24
Finished Jul 03 05:25:59 PM PDT 24
Peak memory 323896 kb
Host smart-a45214a2-2bcf-4ed1-9e16-c37b718ab846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468865202 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_mode_toggle.468865202
Directory /workspace/4.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/4.i2c_host_override.492243942
Short name T474
Test name
Test status
Simulation time 87088327 ps
CPU time 0.66 seconds
Started Jul 03 05:25:28 PM PDT 24
Finished Jul 03 05:25:30 PM PDT 24
Peak memory 204528 kb
Host smart-0882b2c8-5772-40db-b92d-5c71d3414a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492243942 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_override.492243942
Directory /workspace/4.i2c_host_override/latest

Test location /workspace/coverage/default/4.i2c_host_perf.1110493187
Short name T907
Test name
Test status
Simulation time 8522485491 ps
CPU time 37.59 seconds
Started Jul 03 05:25:22 PM PDT 24
Finished Jul 03 05:25:59 PM PDT 24
Peak memory 376600 kb
Host smart-6532f192-f9af-4dfa-a31d-c9f42ffd8e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110493187 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf.1110493187
Directory /workspace/4.i2c_host_perf/latest

Test location /workspace/coverage/default/4.i2c_host_perf_precise.2825242208
Short name T441
Test name
Test status
Simulation time 2587507257 ps
CPU time 27.53 seconds
Started Jul 03 05:25:20 PM PDT 24
Finished Jul 03 05:25:47 PM PDT 24
Peak memory 319564 kb
Host smart-f8853387-dba0-440d-838a-025b6b77587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825242208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_perf_precise.2825242208
Directory /workspace/4.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/4.i2c_host_smoke.3464434354
Short name T47
Test name
Test status
Simulation time 1620080776 ps
CPU time 26.21 seconds
Started Jul 03 05:25:30 PM PDT 24
Finished Jul 03 05:25:57 PM PDT 24
Peak memory 382272 kb
Host smart-545c124b-9e9f-420b-b06c-fe8da2c69cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464434354 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_smoke.3464434354
Directory /workspace/4.i2c_host_smoke/latest

Test location /workspace/coverage/default/4.i2c_host_stress_all.360567388
Short name T112
Test name
Test status
Simulation time 81586599136 ps
CPU time 770.58 seconds
Started Jul 03 05:25:28 PM PDT 24
Finished Jul 03 05:38:19 PM PDT 24
Peak memory 3318040 kb
Host smart-d5690e54-b4a3-4996-ad6c-24bbad6886a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360567388 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stress_all.360567388
Directory /workspace/4.i2c_host_stress_all/latest

Test location /workspace/coverage/default/4.i2c_host_stretch_timeout.3542583837
Short name T1291
Test name
Test status
Simulation time 623790010 ps
CPU time 11.46 seconds
Started Jul 03 05:25:29 PM PDT 24
Finished Jul 03 05:25:40 PM PDT 24
Peak memory 213028 kb
Host smart-e5b4e75e-3d11-4eda-b013-6b89c0067274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542583837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_host_stretch_timeout.3542583837
Directory /workspace/4.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/4.i2c_sec_cm.1082376225
Short name T183
Test name
Test status
Simulation time 1143207106 ps
CPU time 0.89 seconds
Started Jul 03 05:25:28 PM PDT 24
Finished Jul 03 05:25:29 PM PDT 24
Peak memory 223340 kb
Host smart-28247dfa-4edb-4f86-9790-12a7a27ce9f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082376225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_sec_cm.1082376225
Directory /workspace/4.i2c_sec_cm/latest

Test location /workspace/coverage/default/4.i2c_target_bad_addr.4241822800
Short name T1175
Test name
Test status
Simulation time 6256660890 ps
CPU time 4.78 seconds
Started Jul 03 05:25:27 PM PDT 24
Finished Jul 03 05:25:32 PM PDT 24
Peak memory 213260 kb
Host smart-5a750a1a-46d5-4ade-b6e0-71b0e950af29
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241822800 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.i2c_target_bad_addr.4241822800
Directory /workspace/4.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_acq.300417855
Short name T716
Test name
Test status
Simulation time 378341871 ps
CPU time 0.69 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:25:24 PM PDT 24
Peak memory 204568 kb
Host smart-05a6dd4f-6665-4d8f-8302-bef19cc86fd9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300417855 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_acq.300417855
Directory /workspace/4.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_reset_tx.1734079294
Short name T1292
Test name
Test status
Simulation time 661885990 ps
CPU time 0.73 seconds
Started Jul 03 05:25:16 PM PDT 24
Finished Jul 03 05:25:17 PM PDT 24
Peak memory 204656 kb
Host smart-d1484c34-763b-4c65-b152-9ac1c6833d12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734079294 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.i2c_target_fifo_reset_tx.1734079294
Directory /workspace/4.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_acq.1731511497
Short name T17
Test name
Test status
Simulation time 1037527847 ps
CPU time 2.68 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:25:40 PM PDT 24
Peak memory 204884 kb
Host smart-0c633daa-6616-49df-85f1-153dbe3440a0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731511497 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.i2c_target_fifo_watermarks_acq.1731511497
Directory /workspace/4.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/4.i2c_target_fifo_watermarks_tx.3227684902
Short name T1134
Test name
Test status
Simulation time 554858341 ps
CPU time 1.1 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:25:25 PM PDT 24
Peak memory 204620 kb
Host smart-295712bc-8ae0-4592-a5f6-31e6b4a6f657
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227684902 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.i2c_target_fifo_watermarks_tx.3227684902
Directory /workspace/4.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/4.i2c_target_hrst.475197581
Short name T1257
Test name
Test status
Simulation time 1705106716 ps
CPU time 2.55 seconds
Started Jul 03 05:25:29 PM PDT 24
Finished Jul 03 05:25:32 PM PDT 24
Peak memory 204840 kb
Host smart-a39300ac-b704-4485-9f24-45fa3d4d2a24
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475197581 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.i2c_target_hrst.475197581
Directory /workspace/4.i2c_target_hrst/latest

Test location /workspace/coverage/default/4.i2c_target_intr_smoke.952706985
Short name T852
Test name
Test status
Simulation time 2463518376 ps
CPU time 6.35 seconds
Started Jul 03 05:25:17 PM PDT 24
Finished Jul 03 05:25:24 PM PDT 24
Peak memory 218008 kb
Host smart-9ecd9d2a-f400-4006-bf46-8f25b2baf3f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952706985 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 4.i2c_target_intr_smoke.952706985
Directory /workspace/4.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_intr_stress_wr.1471578147
Short name T623
Test name
Test status
Simulation time 17605135312 ps
CPU time 95.34 seconds
Started Jul 03 05:25:21 PM PDT 24
Finished Jul 03 05:26:57 PM PDT 24
Peak memory 1310664 kb
Host smart-ae62e571-641f-47e9-873c-e1158a3048d9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471578147 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.i2c_target_intr_stress_wr.1471578147
Directory /workspace/4.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_smoke.438279557
Short name T484
Test name
Test status
Simulation time 984394622 ps
CPU time 41.66 seconds
Started Jul 03 05:25:20 PM PDT 24
Finished Jul 03 05:26:02 PM PDT 24
Peak memory 204680 kb
Host smart-4cb4a217-041b-42b3-8df9-3486163e7885
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438279557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_targ
et_smoke.438279557
Directory /workspace/4.i2c_target_smoke/latest

Test location /workspace/coverage/default/4.i2c_target_stress_rd.582421238
Short name T873
Test name
Test status
Simulation time 1027270232 ps
CPU time 10.68 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 204836 kb
Host smart-ed4554d6-8aa9-45a2-8cb4-1b09c2e8525e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582421238 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_
target_stress_rd.582421238
Directory /workspace/4.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/4.i2c_target_stress_wr.2290887179
Short name T620
Test name
Test status
Simulation time 9740405512 ps
CPU time 2.89 seconds
Started Jul 03 05:25:30 PM PDT 24
Finished Jul 03 05:25:33 PM PDT 24
Peak memory 204932 kb
Host smart-1c95ab1e-e68d-484a-8a32-501af3c8897b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290887179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c
_target_stress_wr.2290887179
Directory /workspace/4.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/4.i2c_target_stretch.487613981
Short name T844
Test name
Test status
Simulation time 21585504279 ps
CPU time 62.17 seconds
Started Jul 03 05:25:28 PM PDT 24
Finished Jul 03 05:26:30 PM PDT 24
Peak memory 818528 kb
Host smart-914806b5-4ce1-47c6-95cb-441cece8631a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487613981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.i2c_ta
rget_stretch.487613981
Directory /workspace/4.i2c_target_stretch/latest

Test location /workspace/coverage/default/4.i2c_target_timeout.4065363239
Short name T788
Test name
Test status
Simulation time 1279000312 ps
CPU time 6.83 seconds
Started Jul 03 05:25:20 PM PDT 24
Finished Jul 03 05:25:27 PM PDT 24
Peak memory 221052 kb
Host smart-bc4dd432-e13e-4076-a3d2-557b97d07c89
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065363239 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.i2c_target_timeout.4065363239
Directory /workspace/4.i2c_target_timeout/latest

Test location /workspace/coverage/default/4.i2c_target_tx_stretch_ctrl.1682027291
Short name T410
Test name
Test status
Simulation time 618729258 ps
CPU time 8.16 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:25:31 PM PDT 24
Peak memory 204812 kb
Host smart-1a95be23-c835-49c0-b8d5-040be013ca4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682027291 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.i2c_target_tx_stretch_ctrl.1682027291
Directory /workspace/4.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/40.i2c_alert_test.2997854011
Short name T1194
Test name
Test status
Simulation time 94567308 ps
CPU time 0.6 seconds
Started Jul 03 05:28:19 PM PDT 24
Finished Jul 03 05:28:20 PM PDT 24
Peak memory 204412 kb
Host smart-9c3096c7-7a0b-44f2-9622-fab322a5e1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997854011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_alert_test.2997854011
Directory /workspace/40.i2c_alert_test/latest

Test location /workspace/coverage/default/40.i2c_host_error_intr.1033251936
Short name T381
Test name
Test status
Simulation time 201560810 ps
CPU time 6.54 seconds
Started Jul 03 05:28:14 PM PDT 24
Finished Jul 03 05:28:21 PM PDT 24
Peak memory 221248 kb
Host smart-7df49673-ff59-43fc-879e-1fde8ce2ed53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033251936 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_error_intr.1033251936
Directory /workspace/40.i2c_host_error_intr/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_fmt_empty.3058884366
Short name T291
Test name
Test status
Simulation time 1410459694 ps
CPU time 8.82 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:28:24 PM PDT 24
Peak memory 288100 kb
Host smart-c7e269c4-a678-41b9-9c73-52b2ed491c6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058884366 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_fmt_emp
ty.3058884366
Directory /workspace/40.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_full.2135348163
Short name T1020
Test name
Test status
Simulation time 2430374655 ps
CPU time 80.6 seconds
Started Jul 03 05:28:18 PM PDT 24
Finished Jul 03 05:29:38 PM PDT 24
Peak memory 750308 kb
Host smart-bd403e95-693d-4933-86b4-02a15b4401ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135348163 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_full.2135348163
Directory /workspace/40.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_overflow.4070973111
Short name T1044
Test name
Test status
Simulation time 20703058718 ps
CPU time 54.19 seconds
Started Jul 03 05:28:09 PM PDT 24
Finished Jul 03 05:29:04 PM PDT 24
Peak memory 591540 kb
Host smart-1d5149fb-fafc-471c-862f-f2a369167d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070973111 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_overflow.4070973111
Directory /workspace/40.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_fmt.2791567803
Short name T1000
Test name
Test status
Simulation time 169841785 ps
CPU time 1.14 seconds
Started Jul 03 05:28:09 PM PDT 24
Finished Jul 03 05:28:10 PM PDT 24
Peak memory 204436 kb
Host smart-5e9dbb19-d5fa-441d-9bfe-c5739cad0e2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791567803 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_f
mt.2791567803
Directory /workspace/40.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_reset_rx.2727303269
Short name T827
Test name
Test status
Simulation time 830252915 ps
CPU time 3.85 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:20 PM PDT 24
Peak memory 204852 kb
Host smart-a2394eba-53e3-4010-af99-7906dca3e8d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727303269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_reset_rx
.2727303269
Directory /workspace/40.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/40.i2c_host_fifo_watermark.22376323
Short name T331
Test name
Test status
Simulation time 20210545210 ps
CPU time 133.98 seconds
Started Jul 03 05:28:14 PM PDT 24
Finished Jul 03 05:30:29 PM PDT 24
Peak memory 1344492 kb
Host smart-83544c56-d7c3-4ad9-b8ab-4c3959030388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22376323 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_fifo_watermark.22376323
Directory /workspace/40.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/40.i2c_host_may_nack.2495179680
Short name T40
Test name
Test status
Simulation time 857971309 ps
CPU time 17.52 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:34 PM PDT 24
Peak memory 204752 kb
Host smart-f39e7e06-4abe-4dcf-92bf-ca2101c8385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495179680 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_may_nack.2495179680
Directory /workspace/40.i2c_host_may_nack/latest

Test location /workspace/coverage/default/40.i2c_host_mode_toggle.268105165
Short name T1145
Test name
Test status
Simulation time 1711021123 ps
CPU time 40.49 seconds
Started Jul 03 05:28:17 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 503828 kb
Host smart-acd29b77-e4a3-4a67-8a57-a7654c7b44c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268105165 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_mode_toggle.268105165
Directory /workspace/40.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/40.i2c_host_override.2937993889
Short name T299
Test name
Test status
Simulation time 24592400 ps
CPU time 0.7 seconds
Started Jul 03 05:28:09 PM PDT 24
Finished Jul 03 05:28:11 PM PDT 24
Peak memory 204476 kb
Host smart-cc5cc90c-b8f6-4134-8ac0-2c8e4615ba19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937993889 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_override.2937993889
Directory /workspace/40.i2c_host_override/latest

Test location /workspace/coverage/default/40.i2c_host_perf.2953682623
Short name T504
Test name
Test status
Simulation time 52080978045 ps
CPU time 189.16 seconds
Started Jul 03 05:28:10 PM PDT 24
Finished Jul 03 05:31:19 PM PDT 24
Peak memory 1277836 kb
Host smart-5603534c-4a2f-4482-9cf6-b44db36db9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953682623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf.2953682623
Directory /workspace/40.i2c_host_perf/latest

Test location /workspace/coverage/default/40.i2c_host_perf_precise.3728569319
Short name T1146
Test name
Test status
Simulation time 1769377891 ps
CPU time 24.45 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:41 PM PDT 24
Peak memory 212960 kb
Host smart-f38ad3ba-32b9-470d-a0e1-d6b4d1382be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728569319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_perf_precise.3728569319
Directory /workspace/40.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/40.i2c_host_smoke.570509937
Short name T565
Test name
Test status
Simulation time 7208530098 ps
CPU time 63.42 seconds
Started Jul 03 05:28:12 PM PDT 24
Finished Jul 03 05:29:16 PM PDT 24
Peak memory 308104 kb
Host smart-a308dd11-ed3c-435b-9430-433593bbe5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570509937 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_smoke.570509937
Directory /workspace/40.i2c_host_smoke/latest

Test location /workspace/coverage/default/40.i2c_host_stretch_timeout.3535685819
Short name T363
Test name
Test status
Simulation time 986447654 ps
CPU time 42.96 seconds
Started Jul 03 05:28:08 PM PDT 24
Finished Jul 03 05:28:51 PM PDT 24
Peak memory 213000 kb
Host smart-4171b101-042c-46ec-aaba-cc7d86ddd81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535685819 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_host_stretch_timeout.3535685819
Directory /workspace/40.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_bad_addr.36783910
Short name T559
Test name
Test status
Simulation time 3168881549 ps
CPU time 4.45 seconds
Started Jul 03 05:28:11 PM PDT 24
Finished Jul 03 05:28:16 PM PDT 24
Peak memory 213040 kb
Host smart-6d7d7022-11df-48ba-8177-643b3a7974fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36783910 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_bad_addr.36783910
Directory /workspace/40.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_acq.1364995894
Short name T997
Test name
Test status
Simulation time 432445692 ps
CPU time 1.52 seconds
Started Jul 03 05:28:13 PM PDT 24
Finished Jul 03 05:28:14 PM PDT 24
Peak memory 204840 kb
Host smart-cdcc193f-86eb-48e5-9bb5-cd300e31a565
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364995894 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_fifo_reset_acq.1364995894
Directory /workspace/40.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_reset_tx.56103428
Short name T1413
Test name
Test status
Simulation time 167799495 ps
CPU time 1.23 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:28:17 PM PDT 24
Peak memory 212980 kb
Host smart-6af8db01-c4c5-4be3-b6b2-d39813c84ef1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56103428 -assert nopostproc +UVM_TESTNAME=i2c_base_
test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.i2c_target_fifo_reset_tx.56103428
Directory /workspace/40.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_acq.3341858891
Short name T1138
Test name
Test status
Simulation time 1896914099 ps
CPU time 3.37 seconds
Started Jul 03 05:28:12 PM PDT 24
Finished Jul 03 05:28:16 PM PDT 24
Peak memory 204788 kb
Host smart-4ba5316e-bccc-4dd5-b128-d06fe268be2f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341858891 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.i2c_target_fifo_watermarks_acq.3341858891
Directory /workspace/40.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/40.i2c_target_fifo_watermarks_tx.185583473
Short name T740
Test name
Test status
Simulation time 467501697 ps
CPU time 1.22 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:18 PM PDT 24
Peak memory 204588 kb
Host smart-b04fa3fd-4fb8-4f83-abbd-cc5e847d7557
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185583473 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.i2c_target_fifo_watermarks_tx.185583473
Directory /workspace/40.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/40.i2c_target_hrst.3805161425
Short name T652
Test name
Test status
Simulation time 2820599751 ps
CPU time 2.89 seconds
Started Jul 03 05:28:14 PM PDT 24
Finished Jul 03 05:28:17 PM PDT 24
Peak memory 204828 kb
Host smart-a331470f-8e2b-4884-9305-29da7190876c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805161425 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 40.i2c_target_hrst.3805161425
Directory /workspace/40.i2c_target_hrst/latest

Test location /workspace/coverage/default/40.i2c_target_intr_smoke.2253137213
Short name T755
Test name
Test status
Simulation time 843931904 ps
CPU time 4.13 seconds
Started Jul 03 05:28:12 PM PDT 24
Finished Jul 03 05:28:16 PM PDT 24
Peak memory 204856 kb
Host smart-83693a16-0cf3-4475-9097-a087515cf065
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253137213 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 40.i2c_target_intr_smoke.2253137213
Directory /workspace/40.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_intr_stress_wr.3122358988
Short name T303
Test name
Test status
Simulation time 27155057925 ps
CPU time 73.72 seconds
Started Jul 03 05:28:12 PM PDT 24
Finished Jul 03 05:29:26 PM PDT 24
Peak memory 1467692 kb
Host smart-c15635eb-cded-4af9-a88b-0f59e753ad3d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122358988 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.i2c_target_intr_stress_wr.3122358988
Directory /workspace/40.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_smoke.751939507
Short name T1063
Test name
Test status
Simulation time 6600864700 ps
CPU time 41.31 seconds
Started Jul 03 05:28:12 PM PDT 24
Finished Jul 03 05:28:54 PM PDT 24
Peak memory 204964 kb
Host smart-4c8adb68-b943-4d57-a55d-49bff7aab1c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751939507 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_tar
get_smoke.751939507
Directory /workspace/40.i2c_target_smoke/latest

Test location /workspace/coverage/default/40.i2c_target_stress_rd.2570988570
Short name T1017
Test name
Test status
Simulation time 628831818 ps
CPU time 13.59 seconds
Started Jul 03 05:28:13 PM PDT 24
Finished Jul 03 05:28:27 PM PDT 24
Peak memory 204788 kb
Host smart-1c207b3c-7fe5-4c28-9d3e-12f2b6fc2bda
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570988570 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_rd.2570988570
Directory /workspace/40.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/40.i2c_target_stress_wr.4281563005
Short name T420
Test name
Test status
Simulation time 33344881809 ps
CPU time 317.37 seconds
Started Jul 03 05:28:14 PM PDT 24
Finished Jul 03 05:33:31 PM PDT 24
Peak memory 3343324 kb
Host smart-aaf9114e-cad8-4393-8fe1-f58ab3740659
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281563005 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2
c_target_stress_wr.4281563005
Directory /workspace/40.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/40.i2c_target_stretch.1446125633
Short name T983
Test name
Test status
Simulation time 10508685172 ps
CPU time 1006.17 seconds
Started Jul 03 05:28:22 PM PDT 24
Finished Jul 03 05:45:09 PM PDT 24
Peak memory 2734736 kb
Host smart-44d7aa3b-e044-47a7-9bf6-9cd858f438a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446125633 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.i2c_
target_stretch.1446125633
Directory /workspace/40.i2c_target_stretch/latest

Test location /workspace/coverage/default/40.i2c_target_timeout.1472456210
Short name T1482
Test name
Test status
Simulation time 10995115462 ps
CPU time 7.12 seconds
Started Jul 03 05:28:19 PM PDT 24
Finished Jul 03 05:28:26 PM PDT 24
Peak memory 210140 kb
Host smart-4508f68f-2a0e-4c1b-84d1-162d9912bd86
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472456210 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 40.i2c_target_timeout.1472456210
Directory /workspace/40.i2c_target_timeout/latest

Test location /workspace/coverage/default/40.i2c_target_tx_stretch_ctrl.1721895794
Short name T1387
Test name
Test status
Simulation time 542699690 ps
CPU time 7.05 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:23 PM PDT 24
Peak memory 204828 kb
Host smart-8a14b474-9257-4de5-86b1-8a24e678fc43
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721895794 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.i2c_target_tx_stretch_ctrl.1721895794
Directory /workspace/40.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/41.i2c_alert_test.3131726470
Short name T896
Test name
Test status
Simulation time 27093051 ps
CPU time 0.62 seconds
Started Jul 03 05:28:32 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 204428 kb
Host smart-0704b392-7b45-4158-98b5-4758cb50c0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131726470 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_alert_test.3131726470
Directory /workspace/41.i2c_alert_test/latest

Test location /workspace/coverage/default/41.i2c_host_error_intr.2570351182
Short name T511
Test name
Test status
Simulation time 656976466 ps
CPU time 4.64 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:22 PM PDT 24
Peak memory 213068 kb
Host smart-9af0404d-837c-4e60-ad0c-2c643ddecea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570351182 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_error_intr.2570351182
Directory /workspace/41.i2c_host_error_intr/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_fmt_empty.2105755339
Short name T781
Test name
Test status
Simulation time 385547824 ps
CPU time 4.64 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:28:20 PM PDT 24
Peak memory 243652 kb
Host smart-24c6b597-63cf-4dd5-8b6f-4b9a1daecf3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105755339 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_fmt_emp
ty.2105755339
Directory /workspace/41.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_full.2136513926
Short name T673
Test name
Test status
Simulation time 11066556045 ps
CPU time 91.38 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:29:47 PM PDT 24
Peak memory 848716 kb
Host smart-73913981-d4f8-401a-ae4c-f51094b7b945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136513926 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_full.2136513926
Directory /workspace/41.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_overflow.750698894
Short name T799
Test name
Test status
Simulation time 8099000904 ps
CPU time 130.61 seconds
Started Jul 03 05:28:17 PM PDT 24
Finished Jul 03 05:30:28 PM PDT 24
Peak memory 587748 kb
Host smart-8d9849ad-2a57-4f46-91e2-83f5ac78ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750698894 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_overflow.750698894
Directory /workspace/41.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_fmt.2741210939
Short name T459
Test name
Test status
Simulation time 996047568 ps
CPU time 1.2 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:28:17 PM PDT 24
Peak memory 204636 kb
Host smart-1390da76-6dad-4e56-807e-e2a4754e9848
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741210939 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_f
mt.2741210939
Directory /workspace/41.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_reset_rx.610596447
Short name T995
Test name
Test status
Simulation time 1712020595 ps
CPU time 6.16 seconds
Started Jul 03 05:28:17 PM PDT 24
Finished Jul 03 05:28:23 PM PDT 24
Peak memory 243240 kb
Host smart-152e2d1b-aed3-4091-913a-ebfca719b345
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610596447 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_reset_rx.
610596447
Directory /workspace/41.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/41.i2c_host_fifo_watermark.1002194046
Short name T176
Test name
Test status
Simulation time 4090044505 ps
CPU time 298.24 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:33:13 PM PDT 24
Peak memory 1225432 kb
Host smart-07e93895-bf49-4f5c-adc7-3a9a9daea61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002194046 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_fifo_watermark.1002194046
Directory /workspace/41.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/41.i2c_host_may_nack.924422736
Short name T866
Test name
Test status
Simulation time 3627958074 ps
CPU time 7.2 seconds
Started Jul 03 05:28:19 PM PDT 24
Finished Jul 03 05:28:27 PM PDT 24
Peak memory 204924 kb
Host smart-d09ee021-6f06-4dcf-b0b1-915b0bf2f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924422736 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_may_nack.924422736
Directory /workspace/41.i2c_host_may_nack/latest

Test location /workspace/coverage/default/41.i2c_host_mode_toggle.422950285
Short name T473
Test name
Test status
Simulation time 14700152512 ps
CPU time 30.84 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:29:03 PM PDT 24
Peak memory 322980 kb
Host smart-3a738c64-9c74-404f-a4c3-1b576a7b219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422950285 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_mode_toggle.422950285
Directory /workspace/41.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/41.i2c_host_override.3592930400
Short name T1018
Test name
Test status
Simulation time 41500500 ps
CPU time 0.67 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:28:16 PM PDT 24
Peak memory 204476 kb
Host smart-5b5ec044-2601-4421-abb8-984f52dc5fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592930400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_override.3592930400
Directory /workspace/41.i2c_host_override/latest

Test location /workspace/coverage/default/41.i2c_host_perf.3024249856
Short name T398
Test name
Test status
Simulation time 657538360 ps
CPU time 7.79 seconds
Started Jul 03 05:28:15 PM PDT 24
Finished Jul 03 05:28:24 PM PDT 24
Peak memory 222228 kb
Host smart-5e35b7a7-da59-4ddf-8c5a-07ce2eaa84bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024249856 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf.3024249856
Directory /workspace/41.i2c_host_perf/latest

Test location /workspace/coverage/default/41.i2c_host_perf_precise.708455248
Short name T577
Test name
Test status
Simulation time 776823058 ps
CPU time 1.53 seconds
Started Jul 03 05:28:19 PM PDT 24
Finished Jul 03 05:28:20 PM PDT 24
Peak memory 215032 kb
Host smart-0ba6f0b2-1cd9-4d22-8576-7d387f9ded5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708455248 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_perf_precise.708455248
Directory /workspace/41.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/41.i2c_host_smoke.3001935642
Short name T1006
Test name
Test status
Simulation time 2236413910 ps
CPU time 17.27 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:34 PM PDT 24
Peak memory 298140 kb
Host smart-7a5ebf02-f178-4c35-85a1-8452642cec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001935642 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_smoke.3001935642
Directory /workspace/41.i2c_host_smoke/latest

Test location /workspace/coverage/default/41.i2c_host_stress_all.947120638
Short name T175
Test name
Test status
Simulation time 78182937174 ps
CPU time 917.77 seconds
Started Jul 03 05:28:21 PM PDT 24
Finished Jul 03 05:43:40 PM PDT 24
Peak memory 2998940 kb
Host smart-fcec2079-0d41-49f9-af28-a336da2dcc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947120638 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stress_all.947120638
Directory /workspace/41.i2c_host_stress_all/latest

Test location /workspace/coverage/default/41.i2c_host_stretch_timeout.2434436342
Short name T985
Test name
Test status
Simulation time 4120208704 ps
CPU time 10.56 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:28:28 PM PDT 24
Peak memory 213136 kb
Host smart-ff9fa3f6-32b6-4650-a698-ebed5e7d9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434436342 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_host_stretch_timeout.2434436342
Directory /workspace/41.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_bad_addr.2071716844
Short name T1337
Test name
Test status
Simulation time 2139916527 ps
CPU time 3.22 seconds
Started Jul 03 05:28:21 PM PDT 24
Finished Jul 03 05:28:25 PM PDT 24
Peak memory 213044 kb
Host smart-869d03e8-10fa-4474-9c38-c46f8f0d166c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071716844 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.i2c_target_bad_addr.2071716844
Directory /workspace/41.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_acq.467585123
Short name T1330
Test name
Test status
Simulation time 382603641 ps
CPU time 0.96 seconds
Started Jul 03 05:28:22 PM PDT 24
Finished Jul 03 05:28:24 PM PDT 24
Peak memory 204692 kb
Host smart-4f769d1d-f879-4cff-89b5-9448ac44992a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467585123 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_acq.467585123
Directory /workspace/41.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_reset_tx.4285633989
Short name T950
Test name
Test status
Simulation time 151561443 ps
CPU time 0.98 seconds
Started Jul 03 05:28:32 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 204588 kb
Host smart-c26a59c2-4cd5-4a34-9b86-053775f8ea63
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285633989 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 41.i2c_target_fifo_reset_tx.4285633989
Directory /workspace/41.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_acq.3171063105
Short name T528
Test name
Test status
Simulation time 925446280 ps
CPU time 2.68 seconds
Started Jul 03 05:28:22 PM PDT 24
Finished Jul 03 05:28:25 PM PDT 24
Peak memory 204860 kb
Host smart-fc7f8d83-3f99-44f6-8d54-137ee8718f25
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171063105 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.i2c_target_fifo_watermarks_acq.3171063105
Directory /workspace/41.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/41.i2c_target_fifo_watermarks_tx.1123168310
Short name T1200
Test name
Test status
Simulation time 429848861 ps
CPU time 1.34 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:28:32 PM PDT 24
Peak memory 204580 kb
Host smart-c20df859-733b-40aa-a96f-bb7cc0b0a898
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123168310 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.i2c_target_fifo_watermarks_tx.1123168310
Directory /workspace/41.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/41.i2c_target_hrst.2213599893
Short name T345
Test name
Test status
Simulation time 1077600375 ps
CPU time 3.54 seconds
Started Jul 03 05:28:25 PM PDT 24
Finished Jul 03 05:28:29 PM PDT 24
Peak memory 204892 kb
Host smart-da051820-ba3e-46cb-8e14-1387fd7d3702
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213599893 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 41.i2c_target_hrst.2213599893
Directory /workspace/41.i2c_target_hrst/latest

Test location /workspace/coverage/default/41.i2c_target_intr_smoke.2420412863
Short name T653
Test name
Test status
Simulation time 3665178534 ps
CPU time 4.86 seconds
Started Jul 03 05:28:20 PM PDT 24
Finished Jul 03 05:28:25 PM PDT 24
Peak memory 215400 kb
Host smart-6038001e-cd57-4072-807d-75aaf967d368
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420412863 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 41.i2c_target_intr_smoke.2420412863
Directory /workspace/41.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_intr_stress_wr.2843782502
Short name T758
Test name
Test status
Simulation time 14325101667 ps
CPU time 235.98 seconds
Started Jul 03 05:28:25 PM PDT 24
Finished Jul 03 05:32:22 PM PDT 24
Peak memory 3446864 kb
Host smart-6da7f778-ab0c-46aa-a97b-2ee59fe2b562
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843782502 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.i2c_target_intr_stress_wr.2843782502
Directory /workspace/41.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_smoke.3767196538
Short name T1340
Test name
Test status
Simulation time 1020201144 ps
CPU time 36.84 seconds
Started Jul 03 05:28:18 PM PDT 24
Finished Jul 03 05:28:55 PM PDT 24
Peak memory 204784 kb
Host smart-5fdbfcc8-8bd2-45b6-b399-f7062e92ffcd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767196538 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_ta
rget_smoke.3767196538
Directory /workspace/41.i2c_target_smoke/latest

Test location /workspace/coverage/default/41.i2c_target_stress_rd.2905946996
Short name T519
Test name
Test status
Simulation time 6713985017 ps
CPU time 29.41 seconds
Started Jul 03 05:28:20 PM PDT 24
Finished Jul 03 05:28:50 PM PDT 24
Peak memory 204924 kb
Host smart-759f25a9-af1d-463a-a65f-87e680c5f321
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905946996 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_rd.2905946996
Directory /workspace/41.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/41.i2c_target_stress_wr.2595896863
Short name T456
Test name
Test status
Simulation time 41858989415 ps
CPU time 690.63 seconds
Started Jul 03 05:28:16 PM PDT 24
Finished Jul 03 05:39:48 PM PDT 24
Peak memory 5700732 kb
Host smart-14b766c3-337c-4a0d-bbc0-47a52100e9df
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595896863 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2
c_target_stress_wr.2595896863
Directory /workspace/41.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/41.i2c_target_stretch.2381938895
Short name T1245
Test name
Test status
Simulation time 13629016029 ps
CPU time 1521.31 seconds
Started Jul 03 05:28:17 PM PDT 24
Finished Jul 03 05:53:39 PM PDT 24
Peak memory 3318300 kb
Host smart-5056505c-f053-4d9e-8c19-3590a6374602
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381938895 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.i2c_
target_stretch.2381938895
Directory /workspace/41.i2c_target_stretch/latest

Test location /workspace/coverage/default/41.i2c_target_timeout.3746128064
Short name T1453
Test name
Test status
Simulation time 1471664638 ps
CPU time 7.66 seconds
Started Jul 03 05:28:19 PM PDT 24
Finished Jul 03 05:28:27 PM PDT 24
Peak memory 212428 kb
Host smart-6aaf58be-3e9b-461b-9cc2-dd1fa3bd0ec9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746128064 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 41.i2c_target_timeout.3746128064
Directory /workspace/41.i2c_target_timeout/latest

Test location /workspace/coverage/default/41.i2c_target_tx_stretch_ctrl.1846008619
Short name T309
Test name
Test status
Simulation time 416173712 ps
CPU time 5.57 seconds
Started Jul 03 05:28:22 PM PDT 24
Finished Jul 03 05:28:29 PM PDT 24
Peak memory 204824 kb
Host smart-345550b6-d508-4e3a-aa78-5c648a65a361
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846008619 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.i2c_target_tx_stretch_ctrl.1846008619
Directory /workspace/41.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/42.i2c_alert_test.3366192777
Short name T294
Test name
Test status
Simulation time 43900731 ps
CPU time 0.64 seconds
Started Jul 03 05:28:26 PM PDT 24
Finished Jul 03 05:28:27 PM PDT 24
Peak memory 204480 kb
Host smart-93449e4b-76a8-432a-bc39-27807226dccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366192777 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_alert_test.3366192777
Directory /workspace/42.i2c_alert_test/latest

Test location /workspace/coverage/default/42.i2c_host_error_intr.635333670
Short name T5
Test name
Test status
Simulation time 179548041 ps
CPU time 3.04 seconds
Started Jul 03 05:28:21 PM PDT 24
Finished Jul 03 05:28:24 PM PDT 24
Peak memory 214828 kb
Host smart-2ffca4e4-523e-468b-9f3d-bc65f99d3609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635333670 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_error_intr.635333670
Directory /workspace/42.i2c_host_error_intr/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_fmt_empty.344236790
Short name T1375
Test name
Test status
Simulation time 550577071 ps
CPU time 14.98 seconds
Started Jul 03 05:28:21 PM PDT 24
Finished Jul 03 05:28:36 PM PDT 24
Peak memory 267424 kb
Host smart-0cf959cf-3797-4d55-8003-54f66c9bffbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344236790 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_fmt_empt
y.344236790
Directory /workspace/42.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_full.556196902
Short name T489
Test name
Test status
Simulation time 10850551960 ps
CPU time 78.74 seconds
Started Jul 03 05:28:20 PM PDT 24
Finished Jul 03 05:29:39 PM PDT 24
Peak memory 767312 kb
Host smart-e021d3e4-8880-474c-af5f-b61f37da4e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556196902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_full.556196902
Directory /workspace/42.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_overflow.76035617
Short name T609
Test name
Test status
Simulation time 17556625369 ps
CPU time 82.71 seconds
Started Jul 03 05:28:20 PM PDT 24
Finished Jul 03 05:29:43 PM PDT 24
Peak memory 828468 kb
Host smart-32998cd7-2f8c-4dc2-af34-2e4121fc4aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76035617 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_overflow.76035617
Directory /workspace/42.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_reset_rx.3047349648
Short name T452
Test name
Test status
Simulation time 348662041 ps
CPU time 5.36 seconds
Started Jul 03 05:28:18 PM PDT 24
Finished Jul 03 05:28:24 PM PDT 24
Peak memory 242108 kb
Host smart-badd8929-347a-4dc3-a15b-3d7f38d26270
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047349648 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_reset_rx
.3047349648
Directory /workspace/42.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/42.i2c_host_fifo_watermark.2899231117
Short name T108
Test name
Test status
Simulation time 13701066881 ps
CPU time 69.38 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:29:40 PM PDT 24
Peak memory 907924 kb
Host smart-7305a521-1138-4573-a2a9-b6204ce4a037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899231117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_fifo_watermark.2899231117
Directory /workspace/42.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/42.i2c_host_may_nack.388415545
Short name T38
Test name
Test status
Simulation time 477336926 ps
CPU time 9.24 seconds
Started Jul 03 05:28:25 PM PDT 24
Finished Jul 03 05:28:35 PM PDT 24
Peak memory 204860 kb
Host smart-924cb87a-146d-4aaa-ac77-01065c49613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388415545 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_may_nack.388415545
Directory /workspace/42.i2c_host_may_nack/latest

Test location /workspace/coverage/default/42.i2c_host_mode_toggle.1431844769
Short name T819
Test name
Test status
Simulation time 13522798695 ps
CPU time 37.18 seconds
Started Jul 03 05:28:22 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 421892 kb
Host smart-17c7cba3-9b5b-41f6-8bca-0b43979d8189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431844769 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_mode_toggle.1431844769
Directory /workspace/42.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/42.i2c_host_override.3478895289
Short name T837
Test name
Test status
Simulation time 44050026 ps
CPU time 0.7 seconds
Started Jul 03 05:28:20 PM PDT 24
Finished Jul 03 05:28:21 PM PDT 24
Peak memory 204488 kb
Host smart-af7db395-11ba-403a-8052-609b4465bbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478895289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_override.3478895289
Directory /workspace/42.i2c_host_override/latest

Test location /workspace/coverage/default/42.i2c_host_perf.2776547095
Short name T1191
Test name
Test status
Simulation time 30465093415 ps
CPU time 199.5 seconds
Started Jul 03 05:28:23 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 360368 kb
Host smart-c8aa7688-54e0-4093-a616-7910c1043b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776547095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf.2776547095
Directory /workspace/42.i2c_host_perf/latest

Test location /workspace/coverage/default/42.i2c_host_perf_precise.1559021230
Short name T674
Test name
Test status
Simulation time 124639997 ps
CPU time 1.02 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 204652 kb
Host smart-173b4d24-7f67-49e6-8fe9-2a567b41d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559021230 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_perf_precise.1559021230
Directory /workspace/42.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/42.i2c_host_smoke.3346495044
Short name T448
Test name
Test status
Simulation time 1845029522 ps
CPU time 36.96 seconds
Started Jul 03 05:28:20 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 372348 kb
Host smart-a4c0f156-5e07-472c-901b-c47f105798f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346495044 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_smoke.3346495044
Directory /workspace/42.i2c_host_smoke/latest

Test location /workspace/coverage/default/42.i2c_host_stretch_timeout.2155093010
Short name T951
Test name
Test status
Simulation time 555058221 ps
CPU time 17 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 213020 kb
Host smart-5ea7d239-b1a7-4a1e-b17b-5db23eb64025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155093010 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_host_stretch_timeout.2155093010
Directory /workspace/42.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_bad_addr.985651308
Short name T887
Test name
Test status
Simulation time 3604718706 ps
CPU time 3.65 seconds
Started Jul 03 05:28:28 PM PDT 24
Finished Jul 03 05:28:32 PM PDT 24
Peak memory 213056 kb
Host smart-4029aa39-ba18-4257-b804-970cb2cf0b72
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985651308 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 42.i2c_target_bad_addr.985651308
Directory /workspace/42.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_acq.1636522645
Short name T625
Test name
Test status
Simulation time 365264666 ps
CPU time 1.25 seconds
Started Jul 03 05:28:21 PM PDT 24
Finished Jul 03 05:28:22 PM PDT 24
Peak memory 204740 kb
Host smart-14d48dc0-838a-44e3-88a1-e0ab9d506058
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636522645 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_fifo_reset_acq.1636522645
Directory /workspace/42.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_reset_tx.1232967889
Short name T989
Test name
Test status
Simulation time 264794811 ps
CPU time 1.59 seconds
Started Jul 03 05:28:21 PM PDT 24
Finished Jul 03 05:28:23 PM PDT 24
Peak memory 205048 kb
Host smart-c5b7e2d3-8db0-4aa7-8be7-743675efbe22
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232967889 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.i2c_target_fifo_reset_tx.1232967889
Directory /workspace/42.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_acq.123726055
Short name T1349
Test name
Test status
Simulation time 813059220 ps
CPU time 2.3 seconds
Started Jul 03 05:28:28 PM PDT 24
Finished Jul 03 05:28:31 PM PDT 24
Peak memory 204844 kb
Host smart-ebf346c1-4249-4889-807b-859593a3ea7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123726055 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_acq.123726055
Directory /workspace/42.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/42.i2c_target_fifo_watermarks_tx.3799017901
Short name T610
Test name
Test status
Simulation time 874887127 ps
CPU time 1.07 seconds
Started Jul 03 05:28:23 PM PDT 24
Finished Jul 03 05:28:25 PM PDT 24
Peak memory 204628 kb
Host smart-e55702a7-1436-4ab5-9f3e-70858a47e516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799017901 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.i2c_target_fifo_watermarks_tx.3799017901
Directory /workspace/42.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/42.i2c_target_hrst.3963138596
Short name T621
Test name
Test status
Simulation time 2079708063 ps
CPU time 3.08 seconds
Started Jul 03 05:28:23 PM PDT 24
Finished Jul 03 05:28:26 PM PDT 24
Peak memory 204828 kb
Host smart-224c48d8-5ec8-4721-9534-9961f9d173d2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963138596 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 42.i2c_target_hrst.3963138596
Directory /workspace/42.i2c_target_hrst/latest

Test location /workspace/coverage/default/42.i2c_target_intr_smoke.2735623618
Short name T295
Test name
Test status
Simulation time 1292054159 ps
CPU time 7.38 seconds
Started Jul 03 05:28:24 PM PDT 24
Finished Jul 03 05:28:32 PM PDT 24
Peak memory 204804 kb
Host smart-87c0dbea-ca72-42c0-a487-4ace753ed84a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735623618 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 42.i2c_target_intr_smoke.2735623618
Directory /workspace/42.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_intr_stress_wr.4155893459
Short name T794
Test name
Test status
Simulation time 7743555502 ps
CPU time 20.22 seconds
Started Jul 03 05:28:24 PM PDT 24
Finished Jul 03 05:28:44 PM PDT 24
Peak memory 320124 kb
Host smart-15fb8faa-b688-4cab-b385-883809aedbeb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155893459 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.i2c_target_intr_stress_wr.4155893459
Directory /workspace/42.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_smoke.1709786600
Short name T672
Test name
Test status
Simulation time 1209353761 ps
CPU time 48.93 seconds
Started Jul 03 05:28:22 PM PDT 24
Finished Jul 03 05:29:11 PM PDT 24
Peak memory 204816 kb
Host smart-6c195ff7-9b54-4d01-b6cb-15aba2d39f79
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709786600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_ta
rget_smoke.1709786600
Directory /workspace/42.i2c_target_smoke/latest

Test location /workspace/coverage/default/42.i2c_target_stress_rd.2910842501
Short name T163
Test name
Test status
Simulation time 1690653840 ps
CPU time 7.55 seconds
Started Jul 03 05:28:25 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 204836 kb
Host smart-99f313b1-8997-4053-a7cf-226da20eb961
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910842501 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2
c_target_stress_rd.2910842501
Directory /workspace/42.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/42.i2c_target_stress_wr.506971412
Short name T377
Test name
Test status
Simulation time 31202799346 ps
CPU time 99.95 seconds
Started Jul 03 05:28:19 PM PDT 24
Finished Jul 03 05:29:59 PM PDT 24
Peak memory 1542024 kb
Host smart-c78443cc-6907-4b83-af63-c4e8608e7334
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506971412 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c
_target_stress_wr.506971412
Directory /workspace/42.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/42.i2c_target_stretch.2651201912
Short name T347
Test name
Test status
Simulation time 9676578897 ps
CPU time 629.89 seconds
Started Jul 03 05:28:23 PM PDT 24
Finished Jul 03 05:38:53 PM PDT 24
Peak memory 2339640 kb
Host smart-02a02932-3746-4e01-bfd0-58b93f822353
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651201912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.i2c_
target_stretch.2651201912
Directory /workspace/42.i2c_target_stretch/latest

Test location /workspace/coverage/default/42.i2c_target_timeout.2267256264
Short name T1282
Test name
Test status
Simulation time 2637819801 ps
CPU time 7.27 seconds
Started Jul 03 05:28:25 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 213136 kb
Host smart-3a411b35-602d-4400-9599-19f866a1fa12
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267256264 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 42.i2c_target_timeout.2267256264
Directory /workspace/42.i2c_target_timeout/latest

Test location /workspace/coverage/default/42.i2c_target_tx_stretch_ctrl.409951517
Short name T1012
Test name
Test status
Simulation time 57696748 ps
CPU time 1.42 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:28:31 PM PDT 24
Peak memory 204840 kb
Host smart-5935c5aa-f9df-4c1c-894e-2759823a10d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409951517 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.i2c_target_tx_stretch_ctrl.409951517
Directory /workspace/42.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/43.i2c_alert_test.2064215871
Short name T785
Test name
Test status
Simulation time 18092895 ps
CPU time 0.64 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:28:37 PM PDT 24
Peak memory 204480 kb
Host smart-61ea8311-de40-40b8-8128-cffbfa34d011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064215871 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_alert_test.2064215871
Directory /workspace/43.i2c_alert_test/latest

Test location /workspace/coverage/default/43.i2c_host_error_intr.1095733576
Short name T715
Test name
Test status
Simulation time 765565905 ps
CPU time 4.49 seconds
Started Jul 03 05:28:28 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 248488 kb
Host smart-a8e251b8-69ed-4d1b-a40c-42d3aac838a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095733576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_error_intr.1095733576
Directory /workspace/43.i2c_host_error_intr/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_fmt_empty.1769635533
Short name T1533
Test name
Test status
Simulation time 1580422271 ps
CPU time 9.52 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:28:41 PM PDT 24
Peak memory 296452 kb
Host smart-1a4da1cd-73e1-474e-bcb0-86faa00f89a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769635533 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_fmt_emp
ty.1769635533
Directory /workspace/43.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_full.28755745
Short name T611
Test name
Test status
Simulation time 9563845871 ps
CPU time 73.02 seconds
Started Jul 03 05:28:29 PM PDT 24
Finished Jul 03 05:29:43 PM PDT 24
Peak memory 627924 kb
Host smart-000222bf-aed1-4b76-afbe-ae9fe056b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28755745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_full.28755745
Directory /workspace/43.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_overflow.301658575
Short name T483
Test name
Test status
Simulation time 2932533209 ps
CPU time 94.92 seconds
Started Jul 03 05:28:27 PM PDT 24
Finished Jul 03 05:30:03 PM PDT 24
Peak memory 497776 kb
Host smart-42d962a2-dc73-4eb6-8f48-63831ceee5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301658575 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_overflow.301658575
Directory /workspace/43.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_fmt.2547007126
Short name T1234
Test name
Test status
Simulation time 253357317 ps
CPU time 1.02 seconds
Started Jul 03 05:28:28 PM PDT 24
Finished Jul 03 05:28:29 PM PDT 24
Peak memory 204460 kb
Host smart-70fd9775-ec04-4c95-8b22-0c1cb0b21923
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547007126 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_f
mt.2547007126
Directory /workspace/43.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_reset_rx.1108790252
Short name T154
Test name
Test status
Simulation time 514705468 ps
CPU time 3.71 seconds
Started Jul 03 05:28:29 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 227324 kb
Host smart-c2593555-9563-40ac-ae15-2f446c8606a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108790252 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_reset_rx
.1108790252
Directory /workspace/43.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/43.i2c_host_fifo_watermark.2162379256
Short name T592
Test name
Test status
Simulation time 5164246609 ps
CPU time 407.97 seconds
Started Jul 03 05:28:29 PM PDT 24
Finished Jul 03 05:35:18 PM PDT 24
Peak memory 1449748 kb
Host smart-b9cc25ac-6c2a-4f07-a66b-8850300051e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162379256 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_fifo_watermark.2162379256
Directory /workspace/43.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/43.i2c_host_may_nack.3053290449
Short name T607
Test name
Test status
Simulation time 3039072814 ps
CPU time 10.4 seconds
Started Jul 03 05:28:28 PM PDT 24
Finished Jul 03 05:28:39 PM PDT 24
Peak memory 204868 kb
Host smart-b1e5f060-6a11-4720-aecb-3c188f86c0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053290449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_may_nack.3053290449
Directory /workspace/43.i2c_host_may_nack/latest

Test location /workspace/coverage/default/43.i2c_host_mode_toggle.3639260333
Short name T240
Test name
Test status
Simulation time 6966178675 ps
CPU time 76.6 seconds
Started Jul 03 05:28:27 PM PDT 24
Finished Jul 03 05:29:44 PM PDT 24
Peak memory 313072 kb
Host smart-142a3130-f8dd-40b7-a574-e87eaa02db5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639260333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_mode_toggle.3639260333
Directory /workspace/43.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/43.i2c_host_override.2107736760
Short name T710
Test name
Test status
Simulation time 55301224 ps
CPU time 0.65 seconds
Started Jul 03 05:28:24 PM PDT 24
Finished Jul 03 05:28:25 PM PDT 24
Peak memory 204568 kb
Host smart-4d89ae3b-daf7-4ea8-8453-819e56faa81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107736760 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_override.2107736760
Directory /workspace/43.i2c_host_override/latest

Test location /workspace/coverage/default/43.i2c_host_perf.4088106410
Short name T1215
Test name
Test status
Simulation time 12155777771 ps
CPU time 211.74 seconds
Started Jul 03 05:28:27 PM PDT 24
Finished Jul 03 05:31:59 PM PDT 24
Peak memory 1659988 kb
Host smart-75ab293a-9a8d-45e6-ae5a-336feb629a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088106410 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf.4088106410
Directory /workspace/43.i2c_host_perf/latest

Test location /workspace/coverage/default/43.i2c_host_perf_precise.1119330154
Short name T1161
Test name
Test status
Simulation time 610476401 ps
CPU time 6.41 seconds
Started Jul 03 05:28:28 PM PDT 24
Finished Jul 03 05:28:35 PM PDT 24
Peak memory 204648 kb
Host smart-c5531310-ebf3-4884-b437-462bd71b7293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119330154 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_perf_precise.1119330154
Directory /workspace/43.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/43.i2c_host_smoke.958425758
Short name T615
Test name
Test status
Simulation time 1637258974 ps
CPU time 75.04 seconds
Started Jul 03 05:28:25 PM PDT 24
Finished Jul 03 05:29:40 PM PDT 24
Peak memory 345128 kb
Host smart-317e8d57-7944-4a50-8e53-68c41abdc116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958425758 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_smoke.958425758
Directory /workspace/43.i2c_host_smoke/latest

Test location /workspace/coverage/default/43.i2c_host_stress_all.1945732989
Short name T1124
Test name
Test status
Simulation time 13446379177 ps
CPU time 1551.1 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:54:22 PM PDT 24
Peak memory 2243864 kb
Host smart-af91fc48-fe60-4bb1-8b8e-c060ccf07ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945732989 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stress_all.1945732989
Directory /workspace/43.i2c_host_stress_all/latest

Test location /workspace/coverage/default/43.i2c_host_stretch_timeout.778336109
Short name T701
Test name
Test status
Simulation time 1105980918 ps
CPU time 10.61 seconds
Started Jul 03 05:28:27 PM PDT 24
Finished Jul 03 05:28:38 PM PDT 24
Peak memory 213028 kb
Host smart-57fc1d5b-60c4-458c-96d4-4df4dd8e97dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778336109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_host_stretch_timeout.778336109
Directory /workspace/43.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_bad_addr.2002389698
Short name T536
Test name
Test status
Simulation time 687216229 ps
CPU time 3.48 seconds
Started Jul 03 05:28:27 PM PDT 24
Finished Jul 03 05:28:31 PM PDT 24
Peak memory 204732 kb
Host smart-df12fe2d-cb0d-4816-a5cc-50f01205d854
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002389698 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.i2c_target_bad_addr.2002389698
Directory /workspace/43.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_acq.3445596212
Short name T497
Test name
Test status
Simulation time 753919542 ps
CPU time 1.12 seconds
Started Jul 03 05:28:28 PM PDT 24
Finished Jul 03 05:28:30 PM PDT 24
Peak memory 204816 kb
Host smart-466fd84e-1a77-4cbf-9200-db2a230f7628
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445596212 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_fifo_reset_acq.3445596212
Directory /workspace/43.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_reset_tx.2014376972
Short name T1333
Test name
Test status
Simulation time 724999193 ps
CPU time 1.4 seconds
Started Jul 03 05:28:29 PM PDT 24
Finished Jul 03 05:28:31 PM PDT 24
Peak memory 206056 kb
Host smart-fb6710dc-ce1d-4f81-bfba-13542331daab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014376972 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 43.i2c_target_fifo_reset_tx.2014376972
Directory /workspace/43.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_acq.1520238156
Short name T1276
Test name
Test status
Simulation time 1768477699 ps
CPU time 2.58 seconds
Started Jul 03 05:28:25 PM PDT 24
Finished Jul 03 05:28:28 PM PDT 24
Peak memory 204880 kb
Host smart-31da4d5b-d7b0-4c87-96da-1601f95e310e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520238156 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.i2c_target_fifo_watermarks_acq.1520238156
Directory /workspace/43.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/43.i2c_target_fifo_watermarks_tx.2230756009
Short name T807
Test name
Test status
Simulation time 97292054 ps
CPU time 1.01 seconds
Started Jul 03 05:28:33 PM PDT 24
Finished Jul 03 05:28:34 PM PDT 24
Peak memory 204624 kb
Host smart-70824db7-0c48-4123-9461-14e96c173b54
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230756009 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 43.i2c_target_fifo_watermarks_tx.2230756009
Directory /workspace/43.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/43.i2c_target_intr_smoke.692305945
Short name T418
Test name
Test status
Simulation time 896944813 ps
CPU time 5 seconds
Started Jul 03 05:28:27 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 212908 kb
Host smart-fe3f45a3-e48a-406e-b032-5b366bd21712
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692305945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 43.i2c_target_intr_smoke.692305945
Directory /workspace/43.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_intr_stress_wr.458136256
Short name T766
Test name
Test status
Simulation time 13363321100 ps
CPU time 33.68 seconds
Started Jul 03 05:28:28 PM PDT 24
Finished Jul 03 05:29:02 PM PDT 24
Peak memory 923024 kb
Host smart-0eada296-c91e-42c1-ae6b-86bd31c32228
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458136256 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.i2c_target_intr_stress_wr.458136256
Directory /workspace/43.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_smoke.667835179
Short name T838
Test name
Test status
Simulation time 1854729915 ps
CPU time 16.38 seconds
Started Jul 03 05:28:29 PM PDT 24
Finished Jul 03 05:28:45 PM PDT 24
Peak memory 204744 kb
Host smart-b7ffb12a-88b1-4ad8-9b59-6505284c49b9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667835179 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_tar
get_smoke.667835179
Directory /workspace/43.i2c_target_smoke/latest

Test location /workspace/coverage/default/43.i2c_target_stress_rd.3585524902
Short name T283
Test name
Test status
Simulation time 4520006398 ps
CPU time 48.46 seconds
Started Jul 03 05:28:27 PM PDT 24
Finished Jul 03 05:29:15 PM PDT 24
Peak memory 208016 kb
Host smart-76bc59bb-2011-4fea-9a95-aa6b3ea27253
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585524902 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2
c_target_stress_rd.3585524902
Directory /workspace/43.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/43.i2c_target_stress_wr.348044643
Short name T1135
Test name
Test status
Simulation time 12563653353 ps
CPU time 22.94 seconds
Started Jul 03 05:28:27 PM PDT 24
Finished Jul 03 05:28:50 PM PDT 24
Peak memory 204864 kb
Host smart-a08b6ed4-6405-48dc-bc87-c84373060776
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348044643 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c
_target_stress_wr.348044643
Directory /workspace/43.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/43.i2c_target_stretch.2683280205
Short name T925
Test name
Test status
Simulation time 13673766500 ps
CPU time 83.51 seconds
Started Jul 03 05:28:29 PM PDT 24
Finished Jul 03 05:29:53 PM PDT 24
Peak memory 474452 kb
Host smart-d9bb218a-3565-44a3-a313-595fee71efb2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683280205 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.i2c_
target_stretch.2683280205
Directory /workspace/43.i2c_target_stretch/latest

Test location /workspace/coverage/default/43.i2c_target_timeout.609068556
Short name T69
Test name
Test status
Simulation time 2692240102 ps
CPU time 7.36 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:28:37 PM PDT 24
Peak memory 221056 kb
Host smart-6ce20f5b-873d-46c4-8dd9-2d48d9af3fba
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609068556 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 43.i2c_target_timeout.609068556
Directory /workspace/43.i2c_target_timeout/latest

Test location /workspace/coverage/default/43.i2c_target_tx_stretch_ctrl.1211776509
Short name T446
Test name
Test status
Simulation time 58539707 ps
CPU time 1.39 seconds
Started Jul 03 05:28:33 PM PDT 24
Finished Jul 03 05:28:35 PM PDT 24
Peak memory 204828 kb
Host smart-9357af1b-6d7d-40c3-93dc-e1d3a5d77a6d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211776509 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.i2c_target_tx_stretch_ctrl.1211776509
Directory /workspace/43.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/44.i2c_alert_test.2624139089
Short name T1223
Test name
Test status
Simulation time 16010927 ps
CPU time 0.64 seconds
Started Jul 03 05:28:35 PM PDT 24
Finished Jul 03 05:28:36 PM PDT 24
Peak memory 204460 kb
Host smart-00d1ce60-e6a4-4295-bacf-cdd75fd6a620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624139089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_alert_test.2624139089
Directory /workspace/44.i2c_alert_test/latest

Test location /workspace/coverage/default/44.i2c_host_error_intr.231106599
Short name T1407
Test name
Test status
Simulation time 143015890 ps
CPU time 4.72 seconds
Started Jul 03 05:28:29 PM PDT 24
Finished Jul 03 05:28:34 PM PDT 24
Peak memory 212748 kb
Host smart-0c74fec2-8193-4bda-ba03-b15fae05a81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231106599 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_error_intr.231106599
Directory /workspace/44.i2c_host_error_intr/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_fmt_empty.1260564898
Short name T706
Test name
Test status
Simulation time 314924276 ps
CPU time 6.82 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:28:38 PM PDT 24
Peak memory 269964 kb
Host smart-e5abb007-101c-449a-9cd0-d8601113ca58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260564898 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_fmt_emp
ty.1260564898
Directory /workspace/44.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_full.2047660449
Short name T826
Test name
Test status
Simulation time 2651995724 ps
CPU time 190.55 seconds
Started Jul 03 05:28:32 PM PDT 24
Finished Jul 03 05:31:43 PM PDT 24
Peak memory 830788 kb
Host smart-39469370-82ee-4931-aefe-bf53194d8a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047660449 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_full.2047660449
Directory /workspace/44.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_overflow.487936061
Short name T408
Test name
Test status
Simulation time 31650571296 ps
CPU time 107.96 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:30:20 PM PDT 24
Peak memory 597924 kb
Host smart-fab93d65-982c-42a9-8c61-d77c093cc062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487936061 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_overflow.487936061
Directory /workspace/44.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_fmt.4185528483
Short name T1517
Test name
Test status
Simulation time 128017390 ps
CPU time 0.92 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:28:37 PM PDT 24
Peak memory 204440 kb
Host smart-47475235-ce0e-4db8-b882-739d61277520
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185528483 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_f
mt.4185528483
Directory /workspace/44.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_reset_rx.108285195
Short name T1181
Test name
Test status
Simulation time 716702307 ps
CPU time 6.25 seconds
Started Jul 03 05:28:33 PM PDT 24
Finished Jul 03 05:28:39 PM PDT 24
Peak memory 204748 kb
Host smart-fc7e0c7b-26c6-4565-b1e8-98351799ab2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108285195 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_reset_rx.
108285195
Directory /workspace/44.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/44.i2c_host_fifo_watermark.469100688
Short name T1358
Test name
Test status
Simulation time 3036177839 ps
CPU time 77.18 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:29:49 PM PDT 24
Peak memory 914536 kb
Host smart-938dc275-2076-4aee-bf21-17fa8d13f80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469100688 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_fifo_watermark.469100688
Directory /workspace/44.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/44.i2c_host_may_nack.2976536118
Short name T836
Test name
Test status
Simulation time 329767523 ps
CPU time 4.28 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:28:41 PM PDT 24
Peak memory 204860 kb
Host smart-09d3aea3-e82c-4203-833d-f32ea38f0b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976536118 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_may_nack.2976536118
Directory /workspace/44.i2c_host_may_nack/latest

Test location /workspace/coverage/default/44.i2c_host_mode_toggle.743733498
Short name T714
Test name
Test status
Simulation time 1777666913 ps
CPU time 34.67 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:29:11 PM PDT 24
Peak memory 339796 kb
Host smart-4703b931-7c3c-425e-a73f-d5b5809b0331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743733498 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_mode_toggle.743733498
Directory /workspace/44.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/44.i2c_host_override.2594747028
Short name T1268
Test name
Test status
Simulation time 72614981 ps
CPU time 0.7 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:28:37 PM PDT 24
Peak memory 204496 kb
Host smart-ed505ed8-6ef3-4754-a1ce-3aee7bffcbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594747028 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_override.2594747028
Directory /workspace/44.i2c_host_override/latest

Test location /workspace/coverage/default/44.i2c_host_perf.3339329273
Short name T645
Test name
Test status
Simulation time 25257746247 ps
CPU time 1298.5 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:50:10 PM PDT 24
Peak memory 2442172 kb
Host smart-10c414a7-186e-48d1-9ed1-de31a57f84e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339329273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf.3339329273
Directory /workspace/44.i2c_host_perf/latest

Test location /workspace/coverage/default/44.i2c_host_perf_precise.598802970
Short name T1160
Test name
Test status
Simulation time 2121216800 ps
CPU time 82.73 seconds
Started Jul 03 05:28:33 PM PDT 24
Finished Jul 03 05:29:56 PM PDT 24
Peak memory 212940 kb
Host smart-052fc475-7eb1-4387-92bc-6cb9b3b9e627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598802970 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_perf_precise.598802970
Directory /workspace/44.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/44.i2c_host_smoke.815229847
Short name T55
Test name
Test status
Simulation time 6695556587 ps
CPU time 81.3 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:29:52 PM PDT 24
Peak memory 327996 kb
Host smart-cb9822be-f804-434e-810e-c75e7b4ad8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815229847 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_smoke.815229847
Directory /workspace/44.i2c_host_smoke/latest

Test location /workspace/coverage/default/44.i2c_host_stress_all.2035439093
Short name T1189
Test name
Test status
Simulation time 41471353487 ps
CPU time 798.23 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:41:49 PM PDT 24
Peak memory 1646812 kb
Host smart-cd2edf06-14b3-4ef9-b267-0841a3567bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035439093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stress_all.2035439093
Directory /workspace/44.i2c_host_stress_all/latest

Test location /workspace/coverage/default/44.i2c_host_stretch_timeout.1942184834
Short name T1383
Test name
Test status
Simulation time 894888250 ps
CPU time 13.69 seconds
Started Jul 03 05:28:32 PM PDT 24
Finished Jul 03 05:28:46 PM PDT 24
Peak memory 221152 kb
Host smart-a8443072-2730-4c2a-abba-26a6ad51f026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942184834 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_host_stretch_timeout.1942184834
Directory /workspace/44.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_bad_addr.4205008221
Short name T1325
Test name
Test status
Simulation time 15131720576 ps
CPU time 4.39 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:28:40 PM PDT 24
Peak memory 213184 kb
Host smart-5a9cdbbe-7865-4cdc-9b93-94e0d5a73950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205008221 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.i2c_target_bad_addr.4205008221
Directory /workspace/44.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_acq.1040005535
Short name T1025
Test name
Test status
Simulation time 416896635 ps
CPU time 0.98 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:28:33 PM PDT 24
Peak memory 204656 kb
Host smart-4aac177d-6a06-4400-8a91-950a514c6633
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040005535 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_fifo_reset_acq.1040005535
Directory /workspace/44.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_reset_tx.2603031911
Short name T731
Test name
Test status
Simulation time 345138834 ps
CPU time 0.99 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:28:32 PM PDT 24
Peak memory 204600 kb
Host smart-448c36f2-4477-4121-8d06-1386ac76fbe9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603031911 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.i2c_target_fifo_reset_tx.2603031911
Directory /workspace/44.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_acq.476739523
Short name T353
Test name
Test status
Simulation time 595745502 ps
CPU time 2.71 seconds
Started Jul 03 05:28:34 PM PDT 24
Finished Jul 03 05:28:37 PM PDT 24
Peak memory 204808 kb
Host smart-5a65aed3-1166-4e67-9882-53b9522e1189
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476739523 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_acq.476739523
Directory /workspace/44.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/44.i2c_target_fifo_watermarks_tx.3820267775
Short name T1199
Test name
Test status
Simulation time 305026676 ps
CPU time 0.98 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:28:40 PM PDT 24
Peak memory 204628 kb
Host smart-309127ae-57e4-41aa-a736-9924b520514e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820267775 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.i2c_target_fifo_watermarks_tx.3820267775
Directory /workspace/44.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/44.i2c_target_intr_smoke.360354020
Short name T738
Test name
Test status
Simulation time 5554486210 ps
CPU time 6.91 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:28:38 PM PDT 24
Peak memory 221264 kb
Host smart-a8b472d0-fe8b-46bc-878e-111f4c2cd450
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360354020 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 44.i2c_target_intr_smoke.360354020
Directory /workspace/44.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_intr_stress_wr.720069504
Short name T556
Test name
Test status
Simulation time 7905513591 ps
CPU time 38.06 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:29:09 PM PDT 24
Peak memory 1005948 kb
Host smart-14c332d7-6542-4170-8e19-725cdfbbd757
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720069504 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.i2c_target_intr_stress_wr.720069504
Directory /workspace/44.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_smoke.1066609129
Short name T1462
Test name
Test status
Simulation time 2085415386 ps
CPU time 8.39 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:28:40 PM PDT 24
Peak memory 204776 kb
Host smart-faf5d5ce-96ed-481e-8ce0-f704f71f298d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066609129 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_ta
rget_smoke.1066609129
Directory /workspace/44.i2c_target_smoke/latest

Test location /workspace/coverage/default/44.i2c_target_stress_rd.2718616604
Short name T508
Test name
Test status
Simulation time 1753274130 ps
CPU time 7.37 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:28:40 PM PDT 24
Peak memory 209372 kb
Host smart-be6abc13-78ac-4232-87a2-69c5339e57ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718616604 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_rd.2718616604
Directory /workspace/44.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/44.i2c_target_stress_wr.2320307591
Short name T903
Test name
Test status
Simulation time 36928668103 ps
CPU time 59.88 seconds
Started Jul 03 05:28:31 PM PDT 24
Finished Jul 03 05:29:32 PM PDT 24
Peak memory 1084072 kb
Host smart-9ed8601e-2a61-45e9-8291-d46e52c84b6a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320307591 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2
c_target_stress_wr.2320307591
Directory /workspace/44.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/44.i2c_target_stretch.665472495
Short name T147
Test name
Test status
Simulation time 30676090938 ps
CPU time 503.47 seconds
Started Jul 03 05:28:30 PM PDT 24
Finished Jul 03 05:36:54 PM PDT 24
Peak memory 3610408 kb
Host smart-2288081a-0320-4ca2-9a46-a759ce3eaf49
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665472495 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.i2c_t
arget_stretch.665472495
Directory /workspace/44.i2c_target_stretch/latest

Test location /workspace/coverage/default/44.i2c_target_timeout.1935320292
Short name T1416
Test name
Test status
Simulation time 5349415519 ps
CPU time 6.72 seconds
Started Jul 03 05:28:32 PM PDT 24
Finished Jul 03 05:28:39 PM PDT 24
Peak memory 213228 kb
Host smart-1c280355-70d0-4abe-945a-dd053ce68a7d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935320292 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.i2c_target_timeout.1935320292
Directory /workspace/44.i2c_target_timeout/latest

Test location /workspace/coverage/default/44.i2c_target_tx_stretch_ctrl.3764590980
Short name T664
Test name
Test status
Simulation time 551243992 ps
CPU time 7.47 seconds
Started Jul 03 05:28:35 PM PDT 24
Finished Jul 03 05:28:43 PM PDT 24
Peak memory 204812 kb
Host smart-b82fa1f2-ea34-418e-9031-e7e57ddf959f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764590980 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.i2c_target_tx_stretch_ctrl.3764590980
Directory /workspace/44.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/45.i2c_alert_test.3933479356
Short name T1049
Test name
Test status
Simulation time 46076232 ps
CPU time 0.63 seconds
Started Jul 03 05:28:41 PM PDT 24
Finished Jul 03 05:28:42 PM PDT 24
Peak memory 204476 kb
Host smart-fabc8a52-c89a-4dc4-9e9e-a38a39a04dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933479356 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_alert_test.3933479356
Directory /workspace/45.i2c_alert_test/latest

Test location /workspace/coverage/default/45.i2c_host_error_intr.3141336109
Short name T415
Test name
Test status
Simulation time 88244845 ps
CPU time 1.85 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:28:40 PM PDT 24
Peak memory 221232 kb
Host smart-91c0dce9-6790-49de-bfd9-0f3d65334fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141336109 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_error_intr.3141336109
Directory /workspace/45.i2c_host_error_intr/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_fmt_empty.2464636338
Short name T1125
Test name
Test status
Simulation time 1777818584 ps
CPU time 22.38 seconds
Started Jul 03 05:28:33 PM PDT 24
Finished Jul 03 05:28:56 PM PDT 24
Peak memory 297852 kb
Host smart-13f7738f-dedd-421c-926f-ac5975718b7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464636338 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_fmt_emp
ty.2464636338
Directory /workspace/45.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_full.1382690033
Short name T79
Test name
Test status
Simulation time 10313386784 ps
CPU time 101.02 seconds
Started Jul 03 05:28:37 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 345620 kb
Host smart-adee052c-624b-49e2-bc5b-d2469667d347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382690033 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_full.1382690033
Directory /workspace/45.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_overflow.833646263
Short name T1219
Test name
Test status
Simulation time 1610943143 ps
CPU time 41.47 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:29:20 PM PDT 24
Peak memory 590372 kb
Host smart-3e5ed1af-c53e-4fd6-bbe4-33748ac04631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833646263 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_overflow.833646263
Directory /workspace/45.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_fmt.1638425087
Short name T57
Test name
Test status
Simulation time 121066911 ps
CPU time 1.02 seconds
Started Jul 03 05:28:35 PM PDT 24
Finished Jul 03 05:28:36 PM PDT 24
Peak memory 204476 kb
Host smart-1c8ded92-ada1-47e4-ad19-591ee5fc1314
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638425087 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_f
mt.1638425087
Directory /workspace/45.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_reset_rx.3492965623
Short name T750
Test name
Test status
Simulation time 438489246 ps
CPU time 5.26 seconds
Started Jul 03 05:28:35 PM PDT 24
Finished Jul 03 05:28:41 PM PDT 24
Peak memory 204808 kb
Host smart-ed023c51-0b21-498d-b2f7-af00da917e4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492965623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_reset_rx
.3492965623
Directory /workspace/45.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/45.i2c_host_fifo_watermark.1926264621
Short name T520
Test name
Test status
Simulation time 23151649224 ps
CPU time 158.76 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:31:17 PM PDT 24
Peak memory 1504728 kb
Host smart-fd7efb3c-0550-4d03-9c8a-bd326ae605f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926264621 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_fifo_watermark.1926264621
Directory /workspace/45.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/45.i2c_host_may_nack.2012414869
Short name T255
Test name
Test status
Simulation time 1683436622 ps
CPU time 6.59 seconds
Started Jul 03 05:28:44 PM PDT 24
Finished Jul 03 05:28:51 PM PDT 24
Peak memory 204692 kb
Host smart-7e911458-c523-4988-b2cc-97d6238a96ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012414869 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_may_nack.2012414869
Directory /workspace/45.i2c_host_may_nack/latest

Test location /workspace/coverage/default/45.i2c_host_mode_toggle.416774128
Short name T250
Test name
Test status
Simulation time 2694950241 ps
CPU time 21.22 seconds
Started Jul 03 05:28:40 PM PDT 24
Finished Jul 03 05:29:02 PM PDT 24
Peak memory 302000 kb
Host smart-e7df8beb-5c4a-437e-8626-c1cad3b18f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416774128 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_mode_toggle.416774128
Directory /workspace/45.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/45.i2c_host_override.2751311254
Short name T1246
Test name
Test status
Simulation time 87229581 ps
CPU time 0.74 seconds
Started Jul 03 05:28:37 PM PDT 24
Finished Jul 03 05:28:38 PM PDT 24
Peak memory 204552 kb
Host smart-5064890e-c42c-418e-898f-884a43361b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751311254 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_override.2751311254
Directory /workspace/45.i2c_host_override/latest

Test location /workspace/coverage/default/45.i2c_host_perf.2854629666
Short name T573
Test name
Test status
Simulation time 1730378395 ps
CPU time 13.53 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:28:50 PM PDT 24
Peak memory 339276 kb
Host smart-8f93caf0-3aae-43b0-9488-4a75a1d84428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854629666 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf.2854629666
Directory /workspace/45.i2c_host_perf/latest

Test location /workspace/coverage/default/45.i2c_host_perf_precise.1449930400
Short name T128
Test name
Test status
Simulation time 24799163354 ps
CPU time 50.34 seconds
Started Jul 03 05:28:37 PM PDT 24
Finished Jul 03 05:29:28 PM PDT 24
Peak memory 204780 kb
Host smart-57d21937-32ea-4f3d-b276-c1e12f72d4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449930400 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_perf_precise.1449930400
Directory /workspace/45.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/45.i2c_host_smoke.674061607
Short name T386
Test name
Test status
Simulation time 1705512440 ps
CPU time 84.98 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 405008 kb
Host smart-c77d07bb-bb19-4024-8c22-46824bb099fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674061607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_smoke.674061607
Directory /workspace/45.i2c_host_smoke/latest

Test location /workspace/coverage/default/45.i2c_host_stress_all.3501522978
Short name T43
Test name
Test status
Simulation time 49853450243 ps
CPU time 723.3 seconds
Started Jul 03 05:28:36 PM PDT 24
Finished Jul 03 05:40:40 PM PDT 24
Peak memory 2380228 kb
Host smart-77e0ac5f-aadd-4766-8574-5f2cf2c23228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501522978 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stress_all.3501522978
Directory /workspace/45.i2c_host_stress_all/latest

Test location /workspace/coverage/default/45.i2c_host_stretch_timeout.1752929944
Short name T494
Test name
Test status
Simulation time 561273507 ps
CPU time 10.3 seconds
Started Jul 03 05:28:37 PM PDT 24
Finished Jul 03 05:28:47 PM PDT 24
Peak memory 213012 kb
Host smart-15017713-cd12-40c5-bd5b-58d5c7b37ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752929944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_host_stretch_timeout.1752929944
Directory /workspace/45.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_bad_addr.1992621271
Short name T374
Test name
Test status
Simulation time 11514929324 ps
CPU time 4.36 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:28:43 PM PDT 24
Peak memory 213156 kb
Host smart-9251d82f-2bf4-4396-b053-ce83ccccd7c5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992621271 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.i2c_target_bad_addr.1992621271
Directory /workspace/45.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_acq.692830624
Short name T929
Test name
Test status
Simulation time 136872851 ps
CPU time 1.06 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:28:43 PM PDT 24
Peak memory 204416 kb
Host smart-dcc59f35-e40e-4a89-a903-6d3cbaf50112
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692830624 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_acq.692830624
Directory /workspace/45.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_reset_tx.4269651702
Short name T656
Test name
Test status
Simulation time 175970719 ps
CPU time 1.14 seconds
Started Jul 03 05:28:39 PM PDT 24
Finished Jul 03 05:28:41 PM PDT 24
Peak memory 204812 kb
Host smart-0ae799a1-bded-4b3a-bffa-7100efbe05fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269651702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 45.i2c_target_fifo_reset_tx.4269651702
Directory /workspace/45.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_acq.2415496692
Short name T1061
Test name
Test status
Simulation time 326136540 ps
CPU time 1.99 seconds
Started Jul 03 05:28:41 PM PDT 24
Finished Jul 03 05:28:43 PM PDT 24
Peak memory 204736 kb
Host smart-263f920f-8ed6-4203-8af5-a93968dde90c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415496692 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.i2c_target_fifo_watermarks_acq.2415496692
Directory /workspace/45.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/45.i2c_target_fifo_watermarks_tx.949213557
Short name T567
Test name
Test status
Simulation time 365663274 ps
CPU time 1.3 seconds
Started Jul 03 05:28:37 PM PDT 24
Finished Jul 03 05:28:39 PM PDT 24
Peak memory 204624 kb
Host smart-70189563-5584-4b52-b481-cf2606c5ce8f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949213557 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.i2c_target_fifo_watermarks_tx.949213557
Directory /workspace/45.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/45.i2c_target_intr_smoke.4008308780
Short name T145
Test name
Test status
Simulation time 1245584119 ps
CPU time 6.83 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 220988 kb
Host smart-8bf3a513-4f95-4c21-93f9-5178fb1e20b8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008308780 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_intr_smoke.4008308780
Directory /workspace/45.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_intr_stress_wr.3491599738
Short name T1094
Test name
Test status
Simulation time 14257781988 ps
CPU time 11.77 seconds
Started Jul 03 05:28:40 PM PDT 24
Finished Jul 03 05:28:52 PM PDT 24
Peak memory 330100 kb
Host smart-fc0a3f22-8bb5-4973-9fbc-d81b744aa911
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491599738 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.i2c_target_intr_stress_wr.3491599738
Directory /workspace/45.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_smoke.293025880
Short name T509
Test name
Test status
Simulation time 4413503995 ps
CPU time 14.55 seconds
Started Jul 03 05:28:33 PM PDT 24
Finished Jul 03 05:28:48 PM PDT 24
Peak memory 204912 kb
Host smart-d2c9504a-41ec-49a8-957b-18540f038b23
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293025880 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_tar
get_smoke.293025880
Directory /workspace/45.i2c_target_smoke/latest

Test location /workspace/coverage/default/45.i2c_target_stress_rd.3285171874
Short name T1162
Test name
Test status
Simulation time 11288900395 ps
CPU time 26.7 seconds
Started Jul 03 05:28:37 PM PDT 24
Finished Jul 03 05:29:05 PM PDT 24
Peak memory 229268 kb
Host smart-4da152c5-aca3-4d8e-9e3a-29ecdb4f60ab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285171874 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_rd.3285171874
Directory /workspace/45.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/45.i2c_target_stress_wr.2007221209
Short name T1180
Test name
Test status
Simulation time 24166541030 ps
CPU time 13.53 seconds
Started Jul 03 05:28:35 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 304088 kb
Host smart-216b9d2a-7b9f-4130-8bd1-6d0bee8b966b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007221209 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2
c_target_stress_wr.2007221209
Directory /workspace/45.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/45.i2c_target_stretch.1866937801
Short name T711
Test name
Test status
Simulation time 22739894461 ps
CPU time 914.48 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:43:53 PM PDT 24
Peak memory 2417096 kb
Host smart-4664edcf-400e-4736-85db-8518d2c007ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866937801 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.i2c_
target_stretch.1866937801
Directory /workspace/45.i2c_target_stretch/latest

Test location /workspace/coverage/default/45.i2c_target_timeout.334395405
Short name T70
Test name
Test status
Simulation time 3705158160 ps
CPU time 6.88 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:28:46 PM PDT 24
Peak memory 213232 kb
Host smart-e7be64f7-8fed-4a49-a9c0-38fc5c0e72f6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334395405 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 45.i2c_target_timeout.334395405
Directory /workspace/45.i2c_target_timeout/latest

Test location /workspace/coverage/default/45.i2c_target_tx_stretch_ctrl.3696032664
Short name T460
Test name
Test status
Simulation time 128552873 ps
CPU time 2.7 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:28:45 PM PDT 24
Peak memory 204672 kb
Host smart-d575819b-70ca-4dc2-addb-f3ef947134af
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696032664 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.i2c_target_tx_stretch_ctrl.3696032664
Directory /workspace/45.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/46.i2c_alert_test.1956233462
Short name T469
Test name
Test status
Simulation time 15232328 ps
CPU time 0.61 seconds
Started Jul 03 05:28:44 PM PDT 24
Finished Jul 03 05:28:45 PM PDT 24
Peak memory 204476 kb
Host smart-a7bb104e-4096-496d-b18e-e901c0db27d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956233462 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_alert_test.1956233462
Directory /workspace/46.i2c_alert_test/latest

Test location /workspace/coverage/default/46.i2c_host_error_intr.592371408
Short name T1211
Test name
Test status
Simulation time 78123136 ps
CPU time 1.86 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:28:44 PM PDT 24
Peak memory 216760 kb
Host smart-c79e448f-6ea9-4a84-80ee-5e3b2e172ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592371408 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_error_intr.592371408
Directory /workspace/46.i2c_host_error_intr/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_fmt_empty.278257378
Short name T552
Test name
Test status
Simulation time 362095111 ps
CPU time 6.45 seconds
Started Jul 03 05:28:39 PM PDT 24
Finished Jul 03 05:28:45 PM PDT 24
Peak memory 263552 kb
Host smart-88f1e8fa-b3cc-498c-a11b-b218a168fbad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278257378 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_fmt_empt
y.278257378
Directory /workspace/46.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_full.2050268476
Short name T74
Test name
Test status
Simulation time 6974767055 ps
CPU time 115.3 seconds
Started Jul 03 05:28:39 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 642024 kb
Host smart-f0a669de-9d6c-4fbb-9ab5-0570c615db4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050268476 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_full.2050268476
Directory /workspace/46.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_overflow.3132083778
Short name T369
Test name
Test status
Simulation time 4902697289 ps
CPU time 186.56 seconds
Started Jul 03 05:28:44 PM PDT 24
Finished Jul 03 05:31:51 PM PDT 24
Peak memory 783532 kb
Host smart-66fe03d6-1802-479b-8dd7-0871663b6dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132083778 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_overflow.3132083778
Directory /workspace/46.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_fmt.1206845724
Short name T405
Test name
Test status
Simulation time 152295123 ps
CPU time 1.11 seconds
Started Jul 03 05:28:40 PM PDT 24
Finished Jul 03 05:28:42 PM PDT 24
Peak memory 204344 kb
Host smart-537bb2c9-c6fd-4898-9191-8a256ba18a58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206845724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_f
mt.1206845724
Directory /workspace/46.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_reset_rx.1696082527
Short name T1133
Test name
Test status
Simulation time 281045753 ps
CPU time 7.29 seconds
Started Jul 03 05:28:43 PM PDT 24
Finished Jul 03 05:28:51 PM PDT 24
Peak memory 204800 kb
Host smart-45678470-eba8-428a-bcc6-846d68eee84b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696082527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_reset_rx
.1696082527
Directory /workspace/46.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/46.i2c_host_fifo_watermark.1896814269
Short name T114
Test name
Test status
Simulation time 5760679237 ps
CPU time 129.36 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:30:48 PM PDT 24
Peak memory 1369156 kb
Host smart-091ef657-debb-44e8-9da8-4519b47d086a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896814269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_fifo_watermark.1896814269
Directory /workspace/46.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/46.i2c_host_may_nack.692985019
Short name T579
Test name
Test status
Simulation time 759702521 ps
CPU time 8.95 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:28:51 PM PDT 24
Peak memory 204880 kb
Host smart-06bfcb12-391b-4d65-a110-0c58900c78e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692985019 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_may_nack.692985019
Directory /workspace/46.i2c_host_may_nack/latest

Test location /workspace/coverage/default/46.i2c_host_mode_toggle.188995982
Short name T282
Test name
Test status
Simulation time 2442695149 ps
CPU time 61.99 seconds
Started Jul 03 05:28:44 PM PDT 24
Finished Jul 03 05:29:46 PM PDT 24
Peak memory 351688 kb
Host smart-cfb5f193-618c-4a3b-ab43-6a42f17c201d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188995982 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_mode_toggle.188995982
Directory /workspace/46.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/46.i2c_host_override.716673117
Short name T1419
Test name
Test status
Simulation time 47272693 ps
CPU time 0.66 seconds
Started Jul 03 05:28:38 PM PDT 24
Finished Jul 03 05:28:39 PM PDT 24
Peak memory 204572 kb
Host smart-bdf6d0bb-efba-4c9e-b083-4e020b2ee60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716673117 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_override.716673117
Directory /workspace/46.i2c_host_override/latest

Test location /workspace/coverage/default/46.i2c_host_perf.3693893623
Short name T955
Test name
Test status
Simulation time 927013077 ps
CPU time 11.47 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:28:55 PM PDT 24
Peak memory 248896 kb
Host smart-918c99be-b1ee-4c77-aa87-194f4f9545f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693893623 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf.3693893623
Directory /workspace/46.i2c_host_perf/latest

Test location /workspace/coverage/default/46.i2c_host_perf_precise.523832558
Short name T286
Test name
Test status
Simulation time 74021740 ps
CPU time 1.54 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:28:45 PM PDT 24
Peak memory 204684 kb
Host smart-47acf4e9-7ffc-4f5f-8a5f-3786eb38967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523832558 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_perf_precise.523832558
Directory /workspace/46.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/46.i2c_host_smoke.1101481650
Short name T616
Test name
Test status
Simulation time 1742673830 ps
CPU time 75.62 seconds
Started Jul 03 05:28:39 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 277892 kb
Host smart-20f4b71c-f4a9-4866-bf86-40172c4f706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101481650 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_smoke.1101481650
Directory /workspace/46.i2c_host_smoke/latest

Test location /workspace/coverage/default/46.i2c_host_stress_all.1541579446
Short name T53
Test name
Test status
Simulation time 21719987964 ps
CPU time 3541.46 seconds
Started Jul 03 05:28:41 PM PDT 24
Finished Jul 03 06:27:44 PM PDT 24
Peak memory 5084244 kb
Host smart-c7951b59-7855-4839-b2cf-5f12513e4dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541579446 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stress_all.1541579446
Directory /workspace/46.i2c_host_stress_all/latest

Test location /workspace/coverage/default/46.i2c_host_stretch_timeout.785361962
Short name T1148
Test name
Test status
Simulation time 10439466970 ps
CPU time 13.24 seconds
Started Jul 03 05:28:43 PM PDT 24
Finished Jul 03 05:28:57 PM PDT 24
Peak memory 219940 kb
Host smart-74a90e39-3ebd-4333-b89f-8befe505fba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785361962 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_host_stretch_timeout.785361962
Directory /workspace/46.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_bad_addr.250406354
Short name T1399
Test name
Test status
Simulation time 633637107 ps
CPU time 3.25 seconds
Started Jul 03 05:28:45 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 204684 kb
Host smart-9fb725a2-58a2-4031-acc9-ca69556b0eca
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250406354 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 46.i2c_target_bad_addr.250406354
Directory /workspace/46.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_acq.3994199544
Short name T83
Test name
Test status
Simulation time 233609261 ps
CPU time 1.42 seconds
Started Jul 03 05:28:44 PM PDT 24
Finished Jul 03 05:28:46 PM PDT 24
Peak memory 204832 kb
Host smart-9a03895d-4708-43a8-bfd9-842a15a20b36
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994199544 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_fifo_reset_acq.3994199544
Directory /workspace/46.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_reset_tx.500399445
Short name T161
Test name
Test status
Simulation time 179437994 ps
CPU time 1.13 seconds
Started Jul 03 05:28:43 PM PDT 24
Finished Jul 03 05:28:45 PM PDT 24
Peak memory 204616 kb
Host smart-eb42ac5d-b8ad-458d-9ce0-2db8af23cb78
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500399445 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.i2c_target_fifo_reset_tx.500399445
Directory /workspace/46.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_acq.1342611732
Short name T920
Test name
Test status
Simulation time 524978372 ps
CPU time 2.78 seconds
Started Jul 03 05:28:45 PM PDT 24
Finished Jul 03 05:28:48 PM PDT 24
Peak memory 204808 kb
Host smart-2ad8e8bb-3ad3-474e-8d8b-4500cd00e950
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342611732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.i2c_target_fifo_watermarks_acq.1342611732
Directory /workspace/46.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/46.i2c_target_fifo_watermarks_tx.4019887998
Short name T1359
Test name
Test status
Simulation time 129724229 ps
CPU time 1.21 seconds
Started Jul 03 05:28:43 PM PDT 24
Finished Jul 03 05:28:45 PM PDT 24
Peak memory 204656 kb
Host smart-2c2b3bf5-1c6d-4f1f-a216-ec48ec371106
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019887998 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.i2c_target_fifo_watermarks_tx.4019887998
Directory /workspace/46.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/46.i2c_target_hrst.2829953358
Short name T1224
Test name
Test status
Simulation time 1005326348 ps
CPU time 3.18 seconds
Started Jul 03 05:28:44 PM PDT 24
Finished Jul 03 05:28:48 PM PDT 24
Peak memory 204800 kb
Host smart-23186c8e-3954-4096-ae54-c8811f819467
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829953358 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 46.i2c_target_hrst.2829953358
Directory /workspace/46.i2c_target_hrst/latest

Test location /workspace/coverage/default/46.i2c_target_intr_smoke.1303342056
Short name T416
Test name
Test status
Simulation time 826340346 ps
CPU time 4.56 seconds
Started Jul 03 05:28:44 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 214084 kb
Host smart-a86e9282-035b-44a5-b4c8-ec971abfc438
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303342056 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_intr_smoke.1303342056
Directory /workspace/46.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_intr_stress_wr.2530241061
Short name T394
Test name
Test status
Simulation time 4621622016 ps
CPU time 2.6 seconds
Started Jul 03 05:28:41 PM PDT 24
Finished Jul 03 05:28:44 PM PDT 24
Peak memory 204888 kb
Host smart-57ab82e4-4ddd-4e4d-b314-98c7bd1b82fd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530241061 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.i2c_target_intr_stress_wr.2530241061
Directory /workspace/46.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_smoke.1959528513
Short name T1099
Test name
Test status
Simulation time 2189577121 ps
CPU time 9.61 seconds
Started Jul 03 05:28:46 PM PDT 24
Finished Jul 03 05:28:56 PM PDT 24
Peak memory 204748 kb
Host smart-f7734bea-fc1e-4c21-829d-415ef3c46cee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959528513 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2c_ta
rget_smoke.1959528513
Directory /workspace/46.i2c_target_smoke/latest

Test location /workspace/coverage/default/46.i2c_target_stress_rd.2160677872
Short name T1526
Test name
Test status
Simulation time 5132495154 ps
CPU time 51.21 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:29:33 PM PDT 24
Peak memory 205892 kb
Host smart-b19b23b2-3dcd-4693-a308-18ae4bb06667
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160677872 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_rd.2160677872
Directory /workspace/46.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/46.i2c_target_stress_wr.2611786887
Short name T1432
Test name
Test status
Simulation time 20714087872 ps
CPU time 40.47 seconds
Started Jul 03 05:28:43 PM PDT 24
Finished Jul 03 05:29:24 PM PDT 24
Peak memory 288488 kb
Host smart-616a2839-590a-40d3-9314-710c1fbaedea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611786887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.i2
c_target_stress_wr.2611786887
Directory /workspace/46.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/46.i2c_target_timeout.250377904
Short name T776
Test name
Test status
Simulation time 6096864380 ps
CPU time 7.51 seconds
Started Jul 03 05:28:42 PM PDT 24
Finished Jul 03 05:28:51 PM PDT 24
Peak memory 213156 kb
Host smart-9160f206-76d2-4818-9894-7993f82032a4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250377904 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 46.i2c_target_timeout.250377904
Directory /workspace/46.i2c_target_timeout/latest

Test location /workspace/coverage/default/46.i2c_target_tx_stretch_ctrl.3940820690
Short name T1434
Test name
Test status
Simulation time 251413635 ps
CPU time 3.11 seconds
Started Jul 03 05:28:43 PM PDT 24
Finished Jul 03 05:28:47 PM PDT 24
Peak memory 204840 kb
Host smart-18864dde-7eb9-41d8-b323-b11ed1a13414
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940820690 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.i2c_target_tx_stretch_ctrl.3940820690
Directory /workspace/46.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/47.i2c_alert_test.3853195940
Short name T1169
Test name
Test status
Simulation time 19536666 ps
CPU time 0.67 seconds
Started Jul 03 05:28:52 PM PDT 24
Finished Jul 03 05:28:53 PM PDT 24
Peak memory 204444 kb
Host smart-17de24fa-a51a-406f-bbfb-61c9bc79157c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853195940 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_alert_test.3853195940
Directory /workspace/47.i2c_alert_test/latest

Test location /workspace/coverage/default/47.i2c_host_error_intr.2532559791
Short name T1074
Test name
Test status
Simulation time 1894912167 ps
CPU time 7.14 seconds
Started Jul 03 05:28:47 PM PDT 24
Finished Jul 03 05:28:54 PM PDT 24
Peak memory 257544 kb
Host smart-07a187ed-ff02-4e94-9f09-1cbb714209bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532559791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_error_intr.2532559791
Directory /workspace/47.i2c_host_error_intr/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_fmt_empty.747459912
Short name T1382
Test name
Test status
Simulation time 1442278807 ps
CPU time 19.97 seconds
Started Jul 03 05:28:46 PM PDT 24
Finished Jul 03 05:29:06 PM PDT 24
Peak memory 284268 kb
Host smart-7ce70595-15b1-4df7-82fe-da5ba8668874
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747459912 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_fmt_empt
y.747459912
Directory /workspace/47.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_full.1175978289
Short name T639
Test name
Test status
Simulation time 4997305588 ps
CPU time 88.53 seconds
Started Jul 03 05:28:48 PM PDT 24
Finished Jul 03 05:30:18 PM PDT 24
Peak memory 803064 kb
Host smart-7b309fc8-1284-45b8-acdc-1b30a69d8f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175978289 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_full.1175978289
Directory /workspace/47.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_overflow.4161952003
Short name T666
Test name
Test status
Simulation time 1901472745 ps
CPU time 116.21 seconds
Started Jul 03 05:28:45 PM PDT 24
Finished Jul 03 05:30:42 PM PDT 24
Peak memory 600704 kb
Host smart-05e0b885-3ac2-48ee-bb11-304ddc3f4169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161952003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_overflow.4161952003
Directory /workspace/47.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_fmt.1489289966
Short name T443
Test name
Test status
Simulation time 156291837 ps
CPU time 1.15 seconds
Started Jul 03 05:28:45 PM PDT 24
Finished Jul 03 05:28:46 PM PDT 24
Peak memory 204476 kb
Host smart-b8de0dd9-88fe-4992-a754-e90a3b836cf4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489289966 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_f
mt.1489289966
Directory /workspace/47.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_reset_rx.3009649193
Short name T964
Test name
Test status
Simulation time 428171731 ps
CPU time 10.89 seconds
Started Jul 03 05:28:46 PM PDT 24
Finished Jul 03 05:28:57 PM PDT 24
Peak memory 204748 kb
Host smart-9d47a1bb-4f5c-44ad-a5a9-54df30a54ba8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009649193 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_reset_rx
.3009649193
Directory /workspace/47.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/47.i2c_host_fifo_watermark.3103518627
Short name T1360
Test name
Test status
Simulation time 3847598769 ps
CPU time 246.53 seconds
Started Jul 03 05:28:47 PM PDT 24
Finished Jul 03 05:32:54 PM PDT 24
Peak memory 1081724 kb
Host smart-e58f4dff-2ced-41f8-b085-56843300264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103518627 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_fifo_watermark.3103518627
Directory /workspace/47.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/47.i2c_host_may_nack.1448158961
Short name T671
Test name
Test status
Simulation time 1475226527 ps
CPU time 2.36 seconds
Started Jul 03 05:28:50 PM PDT 24
Finished Jul 03 05:28:54 PM PDT 24
Peak memory 204828 kb
Host smart-57b00391-2c6f-4b01-b32d-06cc531b2a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448158961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_may_nack.1448158961
Directory /workspace/47.i2c_host_may_nack/latest

Test location /workspace/coverage/default/47.i2c_host_mode_toggle.2957316021
Short name T865
Test name
Test status
Simulation time 7046165234 ps
CPU time 23.04 seconds
Started Jul 03 05:28:51 PM PDT 24
Finished Jul 03 05:29:14 PM PDT 24
Peak memory 302628 kb
Host smart-14966984-d38d-43db-bd1d-50c8bcc6283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957316021 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_mode_toggle.2957316021
Directory /workspace/47.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/47.i2c_host_override.334347594
Short name T928
Test name
Test status
Simulation time 74119829 ps
CPU time 0.68 seconds
Started Jul 03 05:28:48 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 204508 kb
Host smart-62bef405-cd20-4f71-9ad0-64f2a0de73dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334347594 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_override.334347594
Directory /workspace/47.i2c_host_override/latest

Test location /workspace/coverage/default/47.i2c_host_perf.2534990624
Short name T569
Test name
Test status
Simulation time 202244848 ps
CPU time 2.71 seconds
Started Jul 03 05:28:46 PM PDT 24
Finished Jul 03 05:28:49 PM PDT 24
Peak memory 213212 kb
Host smart-81f16cc4-a15d-4100-ab32-bbace7c0243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534990624 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf.2534990624
Directory /workspace/47.i2c_host_perf/latest

Test location /workspace/coverage/default/47.i2c_host_perf_precise.3807106003
Short name T429
Test name
Test status
Simulation time 26675333837 ps
CPU time 66.52 seconds
Started Jul 03 05:28:47 PM PDT 24
Finished Jul 03 05:29:54 PM PDT 24
Peak memory 473992 kb
Host smart-8f78aa4b-56d4-46dd-b5e6-626edab77891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807106003 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_perf_precise.3807106003
Directory /workspace/47.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/47.i2c_host_smoke.3723750333
Short name T984
Test name
Test status
Simulation time 6689978112 ps
CPU time 72.98 seconds
Started Jul 03 05:28:46 PM PDT 24
Finished Jul 03 05:30:00 PM PDT 24
Peak memory 318044 kb
Host smart-17b8cdab-03ae-4e5d-bae1-dfc8817e3750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723750333 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_smoke.3723750333
Directory /workspace/47.i2c_host_smoke/latest

Test location /workspace/coverage/default/47.i2c_host_stretch_timeout.3521081466
Short name T770
Test name
Test status
Simulation time 463575095 ps
CPU time 21.12 seconds
Started Jul 03 05:28:49 PM PDT 24
Finished Jul 03 05:29:11 PM PDT 24
Peak memory 213016 kb
Host smart-73694257-e5fa-49b2-b296-5f9cfe60232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521081466 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_host_stretch_timeout.3521081466
Directory /workspace/47.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_bad_addr.29210438
Short name T419
Test name
Test status
Simulation time 1690945864 ps
CPU time 4.91 seconds
Started Jul 03 05:28:49 PM PDT 24
Finished Jul 03 05:28:55 PM PDT 24
Peak memory 213040 kb
Host smart-13d2f1ef-4dd4-4bbc-b31b-276f2d6c3cc4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29210438 -assert nopostproc +UV
M_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_bad_addr.29210438
Directory /workspace/47.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_acq.781056976
Short name T1451
Test name
Test status
Simulation time 196683681 ps
CPU time 0.74 seconds
Started Jul 03 05:28:55 PM PDT 24
Finished Jul 03 05:28:56 PM PDT 24
Peak memory 204600 kb
Host smart-26f23f2e-6228-43f8-9ed0-a4f20e7e539c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781056976 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_acq.781056976
Directory /workspace/47.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_reset_tx.2765736991
Short name T535
Test name
Test status
Simulation time 137728568 ps
CPU time 1.07 seconds
Started Jul 03 05:28:55 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 204620 kb
Host smart-1aba1f58-81c5-420a-bca8-4af2f92d0395
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765736991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 47.i2c_target_fifo_reset_tx.2765736991
Directory /workspace/47.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_acq.361810876
Short name T743
Test name
Test status
Simulation time 1675177520 ps
CPU time 1.85 seconds
Started Jul 03 05:28:54 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 204836 kb
Host smart-3bd6afc9-a528-4632-9926-7d34c73b5930
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361810876 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_acq.361810876
Directory /workspace/47.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/47.i2c_target_fifo_watermarks_tx.1604806120
Short name T540
Test name
Test status
Simulation time 364741133 ps
CPU time 1.26 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:28:55 PM PDT 24
Peak memory 204652 kb
Host smart-8e61d470-b558-4564-ac5f-6035c2aaa4d7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604806120 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.i2c_target_fifo_watermarks_tx.1604806120
Directory /workspace/47.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/47.i2c_target_intr_smoke.1030671806
Short name T1489
Test name
Test status
Simulation time 11020354261 ps
CPU time 7.21 seconds
Started Jul 03 05:28:49 PM PDT 24
Finished Jul 03 05:28:57 PM PDT 24
Peak memory 220252 kb
Host smart-23ad4ef9-e88a-47e1-a244-2b6c1aa2d07b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030671806 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_intr_smoke.1030671806
Directory /workspace/47.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_intr_stress_wr.3119719263
Short name T847
Test name
Test status
Simulation time 29614242355 ps
CPU time 78.48 seconds
Started Jul 03 05:28:52 PM PDT 24
Finished Jul 03 05:30:11 PM PDT 24
Peak memory 1566028 kb
Host smart-0e94ac47-e4ed-478a-96a5-890e67c1804a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119719263 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.i2c_target_intr_stress_wr.3119719263
Directory /workspace/47.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_smoke.267520547
Short name T451
Test name
Test status
Simulation time 903726930 ps
CPU time 31.64 seconds
Started Jul 03 05:28:48 PM PDT 24
Finished Jul 03 05:29:20 PM PDT 24
Peak memory 204688 kb
Host smart-437852e9-1d28-4f6b-a657-f5da9a35d491
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267520547 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_tar
get_smoke.267520547
Directory /workspace/47.i2c_target_smoke/latest

Test location /workspace/coverage/default/47.i2c_target_stress_rd.2673060528
Short name T661
Test name
Test status
Simulation time 2007301382 ps
CPU time 43.41 seconds
Started Jul 03 05:28:45 PM PDT 24
Finished Jul 03 05:29:29 PM PDT 24
Peak memory 204848 kb
Host smart-aca9d8e7-83f4-42e8-88ea-de8cb90aa9de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673060528 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_rd.2673060528
Directory /workspace/47.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/47.i2c_target_stress_wr.3919625824
Short name T1114
Test name
Test status
Simulation time 35410329065 ps
CPU time 419.64 seconds
Started Jul 03 05:28:46 PM PDT 24
Finished Jul 03 05:35:46 PM PDT 24
Peak memory 3966732 kb
Host smart-82eed37b-73c7-4a33-b249-6f9a96f7894d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919625824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2
c_target_stress_wr.3919625824
Directory /workspace/47.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/47.i2c_target_stretch.79207226
Short name T1046
Test name
Test status
Simulation time 26843523849 ps
CPU time 16.72 seconds
Started Jul 03 05:28:49 PM PDT 24
Finished Jul 03 05:29:06 PM PDT 24
Peak memory 289284 kb
Host smart-5ca8b2c8-da3a-45fd-b1bf-4659c1ede781
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79207226 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=
i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.i2c_ta
rget_stretch.79207226
Directory /workspace/47.i2c_target_stretch/latest

Test location /workspace/coverage/default/47.i2c_target_timeout.322222660
Short name T594
Test name
Test status
Simulation time 1570720196 ps
CPU time 8.11 seconds
Started Jul 03 05:28:50 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 204876 kb
Host smart-d514d6b2-2b48-45b9-b7bc-8f287d755516
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322222660 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 47.i2c_target_timeout.322222660
Directory /workspace/47.i2c_target_timeout/latest

Test location /workspace/coverage/default/47.i2c_target_tx_stretch_ctrl.4049251117
Short name T876
Test name
Test status
Simulation time 216086578 ps
CPU time 3.08 seconds
Started Jul 03 05:28:50 PM PDT 24
Finished Jul 03 05:28:54 PM PDT 24
Peak memory 204836 kb
Host smart-551c7968-85a5-4fe9-8ddd-d2e4b56d6f47
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049251117 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.i2c_target_tx_stretch_ctrl.4049251117
Directory /workspace/47.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/48.i2c_alert_test.1152590487
Short name T801
Test name
Test status
Simulation time 21385366 ps
CPU time 0.66 seconds
Started Jul 03 05:28:55 PM PDT 24
Finished Jul 03 05:28:57 PM PDT 24
Peak memory 204428 kb
Host smart-1f7dc9f7-a16c-46a3-b0a7-84cf9aebdace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152590487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_alert_test.1152590487
Directory /workspace/48.i2c_alert_test/latest

Test location /workspace/coverage/default/48.i2c_host_error_intr.3915730048
Short name T1120
Test name
Test status
Simulation time 114730693 ps
CPU time 3.15 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:28:57 PM PDT 24
Peak memory 213100 kb
Host smart-e188c694-0935-4fe4-a615-9e5ef2ec1c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915730048 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_error_intr.3915730048
Directory /workspace/48.i2c_host_error_intr/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_fmt_empty.2952477773
Short name T1345
Test name
Test status
Simulation time 378722988 ps
CPU time 7.79 seconds
Started Jul 03 05:28:49 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 278352 kb
Host smart-5749d1cf-73ea-4d79-81f4-1f78cff857d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952477773 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_fmt_emp
ty.2952477773
Directory /workspace/48.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_full.2398651006
Short name T75
Test name
Test status
Simulation time 9067973465 ps
CPU time 73.23 seconds
Started Jul 03 05:28:51 PM PDT 24
Finished Jul 03 05:30:05 PM PDT 24
Peak memory 771092 kb
Host smart-d16dd085-e8a9-42cc-8cd4-2566c34dbad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398651006 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_full.2398651006
Directory /workspace/48.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_overflow.1400619679
Short name T1235
Test name
Test status
Simulation time 4914143305 ps
CPU time 69.52 seconds
Started Jul 03 05:28:51 PM PDT 24
Finished Jul 03 05:30:01 PM PDT 24
Peak memory 732744 kb
Host smart-fa6c74bc-0dc4-4a3d-bd30-7cc34af47591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400619679 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_overflow.1400619679
Directory /workspace/48.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_fmt.575351127
Short name T784
Test name
Test status
Simulation time 65218958 ps
CPU time 0.92 seconds
Started Jul 03 05:28:54 PM PDT 24
Finished Jul 03 05:28:56 PM PDT 24
Peak memory 204072 kb
Host smart-68d93063-946d-4aa3-8b4c-af3ceb6d6345
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575351127 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_fm
t.575351127
Directory /workspace/48.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_reset_rx.699305669
Short name T1304
Test name
Test status
Simulation time 281893273 ps
CPU time 3.64 seconds
Started Jul 03 05:28:51 PM PDT 24
Finished Jul 03 05:28:55 PM PDT 24
Peak memory 204832 kb
Host smart-919de286-9c3c-4f9d-a4f5-bd1f87ee60cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699305669 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_reset_rx.
699305669
Directory /workspace/48.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/48.i2c_host_fifo_watermark.3849056198
Short name T335
Test name
Test status
Simulation time 3530050722 ps
CPU time 95.5 seconds
Started Jul 03 05:28:54 PM PDT 24
Finished Jul 03 05:30:30 PM PDT 24
Peak memory 1023816 kb
Host smart-d4035244-266c-4cb4-a679-8e4ac5b47161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849056198 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_fifo_watermark.3849056198
Directory /workspace/48.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/48.i2c_host_may_nack.518594358
Short name T379
Test name
Test status
Simulation time 1555356005 ps
CPU time 5.05 seconds
Started Jul 03 05:28:54 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 204880 kb
Host smart-b457fdcc-d810-4b44-9a9d-36ef8b6218b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518594358 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_may_nack.518594358
Directory /workspace/48.i2c_host_may_nack/latest

Test location /workspace/coverage/default/48.i2c_host_mode_toggle.3736180475
Short name T703
Test name
Test status
Simulation time 3666264528 ps
CPU time 28.33 seconds
Started Jul 03 05:28:54 PM PDT 24
Finished Jul 03 05:29:23 PM PDT 24
Peak memory 358448 kb
Host smart-7bd59876-504d-4882-8cb9-c56d75bcf07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736180475 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_mode_toggle.3736180475
Directory /workspace/48.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/48.i2c_host_override.2433811963
Short name T368
Test name
Test status
Simulation time 47396102 ps
CPU time 0.64 seconds
Started Jul 03 05:28:50 PM PDT 24
Finished Jul 03 05:28:52 PM PDT 24
Peak memory 204492 kb
Host smart-3647ed36-3d47-405e-b818-c8741ab5afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433811963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_override.2433811963
Directory /workspace/48.i2c_host_override/latest

Test location /workspace/coverage/default/48.i2c_host_perf.2650232984
Short name T1153
Test name
Test status
Simulation time 2260384598 ps
CPU time 100.23 seconds
Started Jul 03 05:28:54 PM PDT 24
Finished Jul 03 05:30:35 PM PDT 24
Peak memory 282268 kb
Host smart-36cb9d4d-dabc-41ea-a96c-9c01cb478c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650232984 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf.2650232984
Directory /workspace/48.i2c_host_perf/latest

Test location /workspace/coverage/default/48.i2c_host_perf_precise.2976727911
Short name T1371
Test name
Test status
Simulation time 137923284 ps
CPU time 2.52 seconds
Started Jul 03 05:28:50 PM PDT 24
Finished Jul 03 05:28:53 PM PDT 24
Peak memory 204708 kb
Host smart-1654f68e-89fa-402c-a67f-3d50fcd417bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976727911 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_perf_precise.2976727911
Directory /workspace/48.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/48.i2c_host_smoke.2157893284
Short name T1425
Test name
Test status
Simulation time 1910619846 ps
CPU time 81.32 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:30:15 PM PDT 24
Peak memory 328336 kb
Host smart-494e3aeb-5630-41a2-911f-494e3c53cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157893284 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_smoke.2157893284
Directory /workspace/48.i2c_host_smoke/latest

Test location /workspace/coverage/default/48.i2c_host_stretch_timeout.3764341879
Short name T318
Test name
Test status
Simulation time 511082336 ps
CPU time 22.22 seconds
Started Jul 03 05:28:51 PM PDT 24
Finished Jul 03 05:29:14 PM PDT 24
Peak memory 213096 kb
Host smart-7b3f13d9-6e26-4f5c-be8b-04655689950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764341879 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_host_stretch_timeout.3764341879
Directory /workspace/48.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_bad_addr.1185822031
Short name T267
Test name
Test status
Simulation time 987817483 ps
CPU time 5.31 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 212980 kb
Host smart-47910a38-90d6-46a1-90b0-359baea88301
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185822031 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.i2c_target_bad_addr.1185822031
Directory /workspace/48.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_acq.2712833363
Short name T1452
Test name
Test status
Simulation time 304529816 ps
CPU time 1.6 seconds
Started Jul 03 05:28:54 PM PDT 24
Finished Jul 03 05:28:57 PM PDT 24
Peak memory 204812 kb
Host smart-19babd2b-441b-475a-bb8e-98aa9100606a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712833363 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_fifo_reset_acq.2712833363
Directory /workspace/48.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_reset_tx.1688217057
Short name T679
Test name
Test status
Simulation time 301458398 ps
CPU time 1.11 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:28:56 PM PDT 24
Peak memory 204584 kb
Host smart-9102ccdc-671a-47b7-b758-1ac232239651
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688217057 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.i2c_target_fifo_reset_tx.1688217057
Directory /workspace/48.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_acq.421915662
Short name T1087
Test name
Test status
Simulation time 335331789 ps
CPU time 1.88 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:28:55 PM PDT 24
Peak memory 204796 kb
Host smart-694dac1f-7dda-4caf-819d-ca157de028b7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421915662 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_acq.421915662
Directory /workspace/48.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/48.i2c_target_fifo_watermarks_tx.3806698602
Short name T1016
Test name
Test status
Simulation time 249008242 ps
CPU time 1.12 seconds
Started Jul 03 05:28:55 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 204656 kb
Host smart-ef9e7ca9-8c20-4c6b-82a4-b05e91de5422
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806698602 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 48.i2c_target_fifo_watermarks_tx.3806698602
Directory /workspace/48.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/48.i2c_target_hrst.1501145176
Short name T627
Test name
Test status
Simulation time 1072389283 ps
CPU time 2.99 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:29:01 PM PDT 24
Peak memory 204792 kb
Host smart-59622fe7-7396-4e34-8191-607b21c02590
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501145176 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_hrst.1501145176
Directory /workspace/48.i2c_target_hrst/latest

Test location /workspace/coverage/default/48.i2c_target_intr_smoke.530117670
Short name T786
Test name
Test status
Simulation time 2148185034 ps
CPU time 6.14 seconds
Started Jul 03 05:28:56 PM PDT 24
Finished Jul 03 05:29:03 PM PDT 24
Peak memory 219032 kb
Host smart-10f93baa-8f40-47f3-83bc-4cbf7ccf3cf9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530117670 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 48.i2c_target_intr_smoke.530117670
Directory /workspace/48.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_intr_stress_wr.4287053792
Short name T1334
Test name
Test status
Simulation time 18084360579 ps
CPU time 363.49 seconds
Started Jul 03 05:28:55 PM PDT 24
Finished Jul 03 05:35:00 PM PDT 24
Peak memory 4052088 kb
Host smart-0264875f-1bd5-46bc-bdf7-5046627cd7c3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287053792 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.i2c_target_intr_stress_wr.4287053792
Directory /workspace/48.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_smoke.2478505813
Short name T96
Test name
Test status
Simulation time 996554932 ps
CPU time 17.47 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:29:12 PM PDT 24
Peak memory 204728 kb
Host smart-6165f212-82f6-4f35-b7da-5e520540d0e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478505813 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_ta
rget_smoke.2478505813
Directory /workspace/48.i2c_target_smoke/latest

Test location /workspace/coverage/default/48.i2c_target_stress_rd.1799190008
Short name T1308
Test name
Test status
Simulation time 2127540846 ps
CPU time 7.52 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:29:02 PM PDT 24
Peak memory 204860 kb
Host smart-78435583-3076-4b6a-b44b-f9ae8b46a998
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799190008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_rd.1799190008
Directory /workspace/48.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/48.i2c_target_stress_wr.3829368887
Short name T1262
Test name
Test status
Simulation time 28940690759 ps
CPU time 30.3 seconds
Started Jul 03 05:28:51 PM PDT 24
Finished Jul 03 05:29:23 PM PDT 24
Peak memory 672800 kb
Host smart-01e0fe73-960b-4ecc-8c34-bf44ba3e7715
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829368887 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2
c_target_stress_wr.3829368887
Directory /workspace/48.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/48.i2c_target_stretch.1540653078
Short name T1216
Test name
Test status
Simulation time 32565657978 ps
CPU time 1941.28 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 06:01:16 PM PDT 24
Peak memory 7873568 kb
Host smart-7bf63b9d-dad1-44af-9de7-9959fd18777f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540653078 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.i2c_
target_stretch.1540653078
Directory /workspace/48.i2c_target_stretch/latest

Test location /workspace/coverage/default/48.i2c_target_timeout.324741245
Short name T1172
Test name
Test status
Simulation time 1301836496 ps
CPU time 6.77 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:29:05 PM PDT 24
Peak memory 213048 kb
Host smart-182355c0-4f86-4283-a4c9-b0d63ff4ecea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324741245 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 48.i2c_target_timeout.324741245
Directory /workspace/48.i2c_target_timeout/latest

Test location /workspace/coverage/default/48.i2c_target_tx_stretch_ctrl.3577138494
Short name T742
Test name
Test status
Simulation time 295564856 ps
CPU time 4.63 seconds
Started Jul 03 05:28:55 PM PDT 24
Finished Jul 03 05:29:01 PM PDT 24
Peak memory 204848 kb
Host smart-bee5a60c-0634-4338-abf6-7a8a56e3eb2e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577138494 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.i2c_target_tx_stretch_ctrl.3577138494
Directory /workspace/48.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/49.i2c_alert_test.418263963
Short name T744
Test name
Test status
Simulation time 25538862 ps
CPU time 0.61 seconds
Started Jul 03 05:29:01 PM PDT 24
Finished Jul 03 05:29:02 PM PDT 24
Peak memory 204424 kb
Host smart-a61cf846-0090-4113-9070-0369e8286d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418263963 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_alert_test.418263963
Directory /workspace/49.i2c_alert_test/latest

Test location /workspace/coverage/default/49.i2c_host_error_intr.3381201239
Short name T998
Test name
Test status
Simulation time 297905731 ps
CPU time 2.16 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 213108 kb
Host smart-e90e5857-05d1-4bba-bf5b-4dd6d39def24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381201239 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_error_intr.3381201239
Directory /workspace/49.i2c_host_error_intr/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_fmt_empty.420610845
Short name T305
Test name
Test status
Simulation time 954388474 ps
CPU time 6.24 seconds
Started Jul 03 05:28:53 PM PDT 24
Finished Jul 03 05:29:01 PM PDT 24
Peak memory 262588 kb
Host smart-66fe54b6-3b52-43a7-b1c8-66d78ef0977e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420610845 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_fmt_empt
y.420610845
Directory /workspace/49.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_full.2056464922
Short name T1370
Test name
Test status
Simulation time 7246476473 ps
CPU time 61.92 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:29:59 PM PDT 24
Peak memory 629840 kb
Host smart-7330ca4e-5ad3-4d2a-adac-f978af575b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056464922 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_full.2056464922
Directory /workspace/49.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_overflow.717661802
Short name T330
Test name
Test status
Simulation time 9148454463 ps
CPU time 176.32 seconds
Started Jul 03 05:28:56 PM PDT 24
Finished Jul 03 05:31:53 PM PDT 24
Peak memory 776344 kb
Host smart-df034e87-e85b-488d-bfe8-6d8b238a17ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717661802 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_overflow.717661802
Directory /workspace/49.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_fmt.189639527
Short name T629
Test name
Test status
Simulation time 504483277 ps
CPU time 1.21 seconds
Started Jul 03 05:28:55 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 204676 kb
Host smart-5f80a33c-9eb4-40f5-97aa-c26695002069
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189639527 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_fm
t.189639527
Directory /workspace/49.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_reset_rx.3264383598
Short name T232
Test name
Test status
Simulation time 148727298 ps
CPU time 4.43 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:29:03 PM PDT 24
Peak memory 229052 kb
Host smart-61360ca1-5a18-4669-b6fc-0570e8743681
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264383598 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_reset_rx
.3264383598
Directory /workspace/49.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/49.i2c_host_fifo_watermark.430009726
Short name T968
Test name
Test status
Simulation time 8479507256 ps
CPU time 272.35 seconds
Started Jul 03 05:28:56 PM PDT 24
Finished Jul 03 05:33:30 PM PDT 24
Peak memory 1185648 kb
Host smart-14741de6-0b4b-4df6-8d61-b8a954bcbf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430009726 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_fifo_watermark.430009726
Directory /workspace/49.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/49.i2c_host_may_nack.2529226418
Short name T948
Test name
Test status
Simulation time 3043868470 ps
CPU time 8.61 seconds
Started Jul 03 05:29:02 PM PDT 24
Finished Jul 03 05:29:11 PM PDT 24
Peak memory 204888 kb
Host smart-d228dbdb-cda2-4e01-8220-76b4d344da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529226418 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_may_nack.2529226418
Directory /workspace/49.i2c_host_may_nack/latest

Test location /workspace/coverage/default/49.i2c_host_mode_toggle.1903646745
Short name T1466
Test name
Test status
Simulation time 1323395938 ps
CPU time 21.22 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:29:19 PM PDT 24
Peak memory 315428 kb
Host smart-28069b74-00d5-4c72-8ec3-972456e61327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903646745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_mode_toggle.1903646745
Directory /workspace/49.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/49.i2c_host_override.3184287253
Short name T136
Test name
Test status
Simulation time 108948377 ps
CPU time 0.7 seconds
Started Jul 03 05:28:54 PM PDT 24
Finished Jul 03 05:28:56 PM PDT 24
Peak memory 204520 kb
Host smart-862fd85d-5d0e-48c2-9a71-b27e5794b907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184287253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_override.3184287253
Directory /workspace/49.i2c_host_override/latest

Test location /workspace/coverage/default/49.i2c_host_perf.3173534944
Short name T1272
Test name
Test status
Simulation time 12724867806 ps
CPU time 138.53 seconds
Started Jul 03 05:29:01 PM PDT 24
Finished Jul 03 05:31:20 PM PDT 24
Peak memory 204984 kb
Host smart-96c46446-2a14-4928-92d3-3a53e8127ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173534944 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf.3173534944
Directory /workspace/49.i2c_host_perf/latest

Test location /workspace/coverage/default/49.i2c_host_perf_precise.947641903
Short name T622
Test name
Test status
Simulation time 103326781 ps
CPU time 1.33 seconds
Started Jul 03 05:28:58 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 222176 kb
Host smart-17a994eb-5cb4-4a1d-ab97-71d848cac3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947641903 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_perf_precise.947641903
Directory /workspace/49.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/49.i2c_host_smoke.1327672724
Short name T696
Test name
Test status
Simulation time 3839573282 ps
CPU time 40.35 seconds
Started Jul 03 05:28:55 PM PDT 24
Finished Jul 03 05:29:36 PM PDT 24
Peak memory 413264 kb
Host smart-1638a048-f1ca-4b67-beb3-c1cc97bfb9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327672724 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_smoke.1327672724
Directory /workspace/49.i2c_host_smoke/latest

Test location /workspace/coverage/default/49.i2c_host_stress_all.1628815824
Short name T45
Test name
Test status
Simulation time 138385500001 ps
CPU time 598.35 seconds
Started Jul 03 05:28:58 PM PDT 24
Finished Jul 03 05:38:57 PM PDT 24
Peak memory 2052172 kb
Host smart-80d3699c-6ce9-45d1-8792-6c7fc33b9ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628815824 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stress_all.1628815824
Directory /workspace/49.i2c_host_stress_all/latest

Test location /workspace/coverage/default/49.i2c_host_stretch_timeout.2337819095
Short name T384
Test name
Test status
Simulation time 1918680385 ps
CPU time 7.37 seconds
Started Jul 03 05:28:58 PM PDT 24
Finished Jul 03 05:29:06 PM PDT 24
Peak memory 213148 kb
Host smart-5a74849f-5fd4-4659-8771-bf58e1cd31da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337819095 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_host_stretch_timeout.2337819095
Directory /workspace/49.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_bad_addr.2278075508
Short name T513
Test name
Test status
Simulation time 1099174651 ps
CPU time 2.95 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:29:01 PM PDT 24
Peak memory 204832 kb
Host smart-108d582f-02c1-416a-a1c7-00d9a141c231
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278075508 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.i2c_target_bad_addr.2278075508
Directory /workspace/49.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_acq.2562509801
Short name T751
Test name
Test status
Simulation time 654963307 ps
CPU time 1.19 seconds
Started Jul 03 05:28:58 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 204780 kb
Host smart-3397d036-de59-4c20-85b9-c1a295919e65
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562509801 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_fifo_reset_acq.2562509801
Directory /workspace/49.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_reset_tx.3136343561
Short name T1397
Test name
Test status
Simulation time 733007985 ps
CPU time 1.13 seconds
Started Jul 03 05:28:59 PM PDT 24
Finished Jul 03 05:29:00 PM PDT 24
Peak memory 204592 kb
Host smart-632110d0-55ab-4fdb-b1f1-6cfc1f4e38da
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136343561 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 49.i2c_target_fifo_reset_tx.3136343561
Directory /workspace/49.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/49.i2c_target_fifo_watermarks_tx.3558583945
Short name T1379
Test name
Test status
Simulation time 138403366 ps
CPU time 1.26 seconds
Started Jul 03 05:29:02 PM PDT 24
Finished Jul 03 05:29:04 PM PDT 24
Peak memory 204544 kb
Host smart-458e8bd0-fc5b-41a1-bae9-e86731ad2c7b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558583945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 49.i2c_target_fifo_watermarks_tx.3558583945
Directory /workspace/49.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/49.i2c_target_hrst.2008767087
Short name T963
Test name
Test status
Simulation time 1581907488 ps
CPU time 3.1 seconds
Started Jul 03 05:28:58 PM PDT 24
Finished Jul 03 05:29:02 PM PDT 24
Peak memory 204816 kb
Host smart-59298a35-b7b5-47cc-9789-3b735a216147
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008767087 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 49.i2c_target_hrst.2008767087
Directory /workspace/49.i2c_target_hrst/latest

Test location /workspace/coverage/default/49.i2c_target_intr_smoke.1575927340
Short name T1309
Test name
Test status
Simulation time 4936111039 ps
CPU time 7.35 seconds
Started Jul 03 05:29:02 PM PDT 24
Finished Jul 03 05:29:10 PM PDT 24
Peak memory 213308 kb
Host smart-8acbdbc6-2a61-4b2d-bc75-82440a2a190f
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575927340 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 49.i2c_target_intr_smoke.1575927340
Directory /workspace/49.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_intr_stress_wr.1280569623
Short name T1129
Test name
Test status
Simulation time 10646442439 ps
CPU time 58.01 seconds
Started Jul 03 05:28:56 PM PDT 24
Finished Jul 03 05:29:55 PM PDT 24
Peak memory 1016080 kb
Host smart-fb01bcaf-5cac-4f2d-a2e7-5b4c3c3048d8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280569623 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.i2c_target_intr_stress_wr.1280569623
Directory /workspace/49.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_smoke.140045208
Short name T169
Test name
Test status
Simulation time 533877149 ps
CPU time 20.43 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:29:18 PM PDT 24
Peak memory 204812 kb
Host smart-e199471e-cf9a-4de2-8112-d7425933657a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140045208 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_tar
get_smoke.140045208
Directory /workspace/49.i2c_target_smoke/latest

Test location /workspace/coverage/default/49.i2c_target_stress_rd.844091097
Short name T529
Test name
Test status
Simulation time 4219203557 ps
CPU time 14.34 seconds
Started Jul 03 05:28:58 PM PDT 24
Finished Jul 03 05:29:13 PM PDT 24
Peak memory 221444 kb
Host smart-f264b6be-e2c1-40aa-a66d-d7b4dd35c48e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844091097 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_rd.844091097
Directory /workspace/49.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/49.i2c_target_stress_wr.211860578
Short name T646
Test name
Test status
Simulation time 14119289375 ps
CPU time 9.05 seconds
Started Jul 03 05:28:59 PM PDT 24
Finished Jul 03 05:29:08 PM PDT 24
Peak memory 204856 kb
Host smart-35b7f755-3b5e-474d-bf6a-8f52e56c77d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211860578 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c
_target_stress_wr.211860578
Directory /workspace/49.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/49.i2c_target_stretch.564008921
Short name T648
Test name
Test status
Simulation time 33894675451 ps
CPU time 247.21 seconds
Started Jul 03 05:28:57 PM PDT 24
Finished Jul 03 05:33:05 PM PDT 24
Peak memory 1949508 kb
Host smart-5ee59c47-2a22-4e9b-a17d-2364a46c5095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564008921 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.i2c_t
arget_stretch.564008921
Directory /workspace/49.i2c_target_stretch/latest

Test location /workspace/coverage/default/49.i2c_target_timeout.3598147732
Short name T322
Test name
Test status
Simulation time 4888915045 ps
CPU time 7.1 seconds
Started Jul 03 05:29:02 PM PDT 24
Finished Jul 03 05:29:09 PM PDT 24
Peak memory 221148 kb
Host smart-d474373e-7081-4761-850a-78225a642240
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598147732 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 49.i2c_target_timeout.3598147732
Directory /workspace/49.i2c_target_timeout/latest

Test location /workspace/coverage/default/49.i2c_target_tx_stretch_ctrl.506277673
Short name T325
Test name
Test status
Simulation time 320854428 ps
CPU time 4.33 seconds
Started Jul 03 05:29:01 PM PDT 24
Finished Jul 03 05:29:05 PM PDT 24
Peak memory 204692 kb
Host smart-10095600-3daa-4152-9ab4-fd5b9984b9f9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506277673 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.i2c_target_tx_stretch_ctrl.506277673
Directory /workspace/49.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/5.i2c_alert_test.1313912031
Short name T465
Test name
Test status
Simulation time 35094062 ps
CPU time 0.61 seconds
Started Jul 03 05:25:34 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 204480 kb
Host smart-d8201b68-8618-4dbb-9078-3fe102ab2dab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313912031 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_alert_test.1313912031
Directory /workspace/5.i2c_alert_test/latest

Test location /workspace/coverage/default/5.i2c_host_error_intr.3193560420
Short name T835
Test name
Test status
Simulation time 383511020 ps
CPU time 4.4 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:25:41 PM PDT 24
Peak memory 213108 kb
Host smart-6bf2d278-de6d-496c-a01e-b3d47a209b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193560420 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_error_intr.3193560420
Directory /workspace/5.i2c_host_error_intr/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_fmt_empty.2807719027
Short name T564
Test name
Test status
Simulation time 329282260 ps
CPU time 16.59 seconds
Started Jul 03 05:25:27 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 272096 kb
Host smart-a6de3109-3637-41ea-a62d-057a857e7915
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807719027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_fmt_empt
y.2807719027
Directory /workspace/5.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_full.2808357461
Short name T80
Test name
Test status
Simulation time 2241921102 ps
CPU time 60.51 seconds
Started Jul 03 05:25:22 PM PDT 24
Finished Jul 03 05:26:23 PM PDT 24
Peak memory 672056 kb
Host smart-a7ced1de-77e8-4b0c-b669-f391e80e678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808357461 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_full.2808357461
Directory /workspace/5.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_overflow.887879487
Short name T902
Test name
Test status
Simulation time 8600531641 ps
CPU time 75.71 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:26:40 PM PDT 24
Peak memory 743716 kb
Host smart-b544a971-5f5a-4965-8891-1c1defff0eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887879487 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_overflow.887879487
Directory /workspace/5.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_fmt.3903345312
Short name T235
Test name
Test status
Simulation time 193203494 ps
CPU time 0.8 seconds
Started Jul 03 05:25:36 PM PDT 24
Finished Jul 03 05:25:37 PM PDT 24
Peak memory 204456 kb
Host smart-3162bbb2-f24e-46d0-9e07-26e4e5d7979f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903345312 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
fmt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_fm
t.3903345312
Directory /workspace/5.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_reset_rx.2583386652
Short name T1433
Test name
Test status
Simulation time 1914307922 ps
CPU time 4.33 seconds
Started Jul 03 05:25:30 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 204632 kb
Host smart-300e3c9f-98c7-46f7-810a-59230a5ec8b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583386652 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_reset_rx.
2583386652
Directory /workspace/5.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/5.i2c_host_fifo_watermark.3296241607
Short name T538
Test name
Test status
Simulation time 9182171280 ps
CPU time 81.3 seconds
Started Jul 03 05:25:36 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 936480 kb
Host smart-c2171d7a-55ae-44ad-bd0a-0a0b54f25e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296241607 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_fifo_watermark.3296241607
Directory /workspace/5.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/5.i2c_host_may_nack.473561748
Short name T1284
Test name
Test status
Simulation time 2282203600 ps
CPU time 7.01 seconds
Started Jul 03 05:25:28 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 204908 kb
Host smart-11f6fc27-091e-425b-99e8-079b1c84278d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473561748 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_may_nack.473561748
Directory /workspace/5.i2c_host_may_nack/latest

Test location /workspace/coverage/default/5.i2c_host_mode_toggle.177638088
Short name T1438
Test name
Test status
Simulation time 13356959906 ps
CPU time 20.76 seconds
Started Jul 03 05:25:32 PM PDT 24
Finished Jul 03 05:25:53 PM PDT 24
Peak memory 268664 kb
Host smart-afa489fd-751e-4856-9a3e-bac92d303633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177638088 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_mode_toggle.177638088
Directory /workspace/5.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/5.i2c_host_override.1771144784
Short name T135
Test name
Test status
Simulation time 20954523 ps
CPU time 0.69 seconds
Started Jul 03 05:25:30 PM PDT 24
Finished Jul 03 05:25:31 PM PDT 24
Peak memory 204560 kb
Host smart-a5cb5e84-bef3-4db4-8a25-267c70a48f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771144784 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_override.1771144784
Directory /workspace/5.i2c_host_override/latest

Test location /workspace/coverage/default/5.i2c_host_perf.1613352260
Short name T1167
Test name
Test status
Simulation time 1793803240 ps
CPU time 5.82 seconds
Started Jul 03 05:25:25 PM PDT 24
Finished Jul 03 05:25:31 PM PDT 24
Peak memory 221236 kb
Host smart-1b926d98-2e82-4b6b-90a2-94f7a671b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613352260 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf.1613352260
Directory /workspace/5.i2c_host_perf/latest

Test location /workspace/coverage/default/5.i2c_host_perf_precise.2150063259
Short name T334
Test name
Test status
Simulation time 281186816 ps
CPU time 1.41 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:25:26 PM PDT 24
Peak memory 204728 kb
Host smart-9f2debec-1e9e-4314-950a-c89be20b52f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150063259 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_perf_precise.2150063259
Directory /workspace/5.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/5.i2c_host_smoke.3965593725
Short name T1140
Test name
Test status
Simulation time 2446630721 ps
CPU time 21.46 seconds
Started Jul 03 05:25:28 PM PDT 24
Finished Jul 03 05:25:50 PM PDT 24
Peak memory 318740 kb
Host smart-f8bb0d69-5421-43c5-ab36-6f373124bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965593725 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_smoke.3965593725
Directory /workspace/5.i2c_host_smoke/latest

Test location /workspace/coverage/default/5.i2c_host_stress_all.1789556521
Short name T1071
Test name
Test status
Simulation time 8769153776 ps
CPU time 696.42 seconds
Started Jul 03 05:25:45 PM PDT 24
Finished Jul 03 05:37:22 PM PDT 24
Peak memory 1316672 kb
Host smart-cd10f993-ee07-4e98-ae84-592bc43a5cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789556521 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stress_all.1789556521
Directory /workspace/5.i2c_host_stress_all/latest

Test location /workspace/coverage/default/5.i2c_host_stretch_timeout.3906231732
Short name T1243
Test name
Test status
Simulation time 2015755643 ps
CPU time 22.09 seconds
Started Jul 03 05:25:27 PM PDT 24
Finished Jul 03 05:25:49 PM PDT 24
Peak memory 213012 kb
Host smart-a2acad42-f511-426c-9693-40f2759944f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906231732 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_host_stretch_timeout.3906231732
Directory /workspace/5.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_bad_addr.2274644420
Short name T24
Test name
Test status
Simulation time 1096209707 ps
CPU time 4.76 seconds
Started Jul 03 05:25:33 PM PDT 24
Finished Jul 03 05:25:38 PM PDT 24
Peak memory 213064 kb
Host smart-e691c39d-8342-45a7-b70b-341d3cfb1cc8
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274644420 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.i2c_target_bad_addr.2274644420
Directory /workspace/5.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_acq.964305992
Short name T425
Test name
Test status
Simulation time 137738221 ps
CPU time 0.87 seconds
Started Jul 03 05:25:25 PM PDT 24
Finished Jul 03 05:25:26 PM PDT 24
Peak memory 204580 kb
Host smart-ae648002-3bcd-438a-b5f6-4c39c9601022
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964305992 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_acq.964305992
Directory /workspace/5.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_reset_tx.2140445167
Short name T328
Test name
Test status
Simulation time 149628261 ps
CPU time 1.08 seconds
Started Jul 03 05:25:30 PM PDT 24
Finished Jul 03 05:25:32 PM PDT 24
Peak memory 204456 kb
Host smart-70e4c12a-2498-45c9-8417-34762cf0ebab
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140445167 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.i2c_target_fifo_reset_tx.2140445167
Directory /workspace/5.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_acq.105319108
Short name T1296
Test name
Test status
Simulation time 1851427712 ps
CPU time 1.83 seconds
Started Jul 03 05:25:33 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 204636 kb
Host smart-b53270d3-0995-4055-8cea-3d55b8698575
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105319108 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_acq.105319108
Directory /workspace/5.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/5.i2c_target_fifo_watermarks_tx.1344587946
Short name T296
Test name
Test status
Simulation time 93567024 ps
CPU time 0.99 seconds
Started Jul 03 05:25:46 PM PDT 24
Finished Jul 03 05:25:47 PM PDT 24
Peak memory 204616 kb
Host smart-e9f06fc4-1a12-4172-8ed2-50334fc94b2b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344587946 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 5.i2c_target_fifo_watermarks_tx.1344587946
Directory /workspace/5.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/5.i2c_target_hrst.3415957691
Short name T1297
Test name
Test status
Simulation time 511728172 ps
CPU time 3.79 seconds
Started Jul 03 05:25:34 PM PDT 24
Finished Jul 03 05:25:38 PM PDT 24
Peak memory 204852 kb
Host smart-3fb632c0-f8e9-41cd-9b02-e99aa65cb32d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415957691 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 5.i2c_target_hrst.3415957691
Directory /workspace/5.i2c_target_hrst/latest

Test location /workspace/coverage/default/5.i2c_target_intr_smoke.2433984868
Short name T116
Test name
Test status
Simulation time 986164837 ps
CPU time 4.68 seconds
Started Jul 03 05:25:26 PM PDT 24
Finished Jul 03 05:25:31 PM PDT 24
Peak memory 212976 kb
Host smart-89bebd22-f0e4-4ce1-ac66-049702a762d0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433984868 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 5.i2c_target_intr_smoke.2433984868
Directory /workspace/5.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_intr_stress_wr.2475407968
Short name T25
Test name
Test status
Simulation time 16250937344 ps
CPU time 179.22 seconds
Started Jul 03 05:25:35 PM PDT 24
Finished Jul 03 05:28:40 PM PDT 24
Peak memory 2302712 kb
Host smart-93e269c0-6518-4c09-b5eb-1d6da04eb819
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475407968 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.i2c_target_intr_stress_wr.2475407968
Directory /workspace/5.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_smoke.3321533377
Short name T1143
Test name
Test status
Simulation time 738722948 ps
CPU time 27.4 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:25:52 PM PDT 24
Peak memory 204816 kb
Host smart-1f05ad57-4eaa-4a6a-92f0-ba89942f7e55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321533377 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_tar
get_smoke.3321533377
Directory /workspace/5.i2c_target_smoke/latest

Test location /workspace/coverage/default/5.i2c_target_stress_rd.3099680576
Short name T444
Test name
Test status
Simulation time 3882452331 ps
CPU time 10.49 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 210816 kb
Host smart-faa20680-5a5d-4cd6-a144-fdd8b1fb762b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099680576 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_rd.3099680576
Directory /workspace/5.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/5.i2c_target_stress_wr.3336921601
Short name T956
Test name
Test status
Simulation time 39301984023 ps
CPU time 600.67 seconds
Started Jul 03 05:25:27 PM PDT 24
Finished Jul 03 05:35:28 PM PDT 24
Peak memory 4917360 kb
Host smart-53788ff0-c6b1-4abb-bf4e-186f454b932b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336921601 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c
_target_stress_wr.3336921601
Directory /workspace/5.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/5.i2c_target_stretch.3115503362
Short name T1427
Test name
Test status
Simulation time 29394755677 ps
CPU time 707.9 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:37:27 PM PDT 24
Peak memory 3869316 kb
Host smart-9621d8a6-0a7d-49b7-80d1-af0215d3b193
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115503362 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.i2c_t
arget_stretch.3115503362
Directory /workspace/5.i2c_target_stretch/latest

Test location /workspace/coverage/default/5.i2c_target_timeout.2165274621
Short name T867
Test name
Test status
Simulation time 1362165124 ps
CPU time 7.45 seconds
Started Jul 03 05:25:25 PM PDT 24
Finished Jul 03 05:25:33 PM PDT 24
Peak memory 217104 kb
Host smart-4e7f803c-285f-423b-b255-ce9c9ad850b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165274621 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.i2c_target_timeout.2165274621
Directory /workspace/5.i2c_target_timeout/latest

Test location /workspace/coverage/default/5.i2c_target_tx_stretch_ctrl.2059125702
Short name T1024
Test name
Test status
Simulation time 108329563 ps
CPU time 1.89 seconds
Started Jul 03 05:25:31 PM PDT 24
Finished Jul 03 05:25:34 PM PDT 24
Peak memory 204792 kb
Host smart-eb816bd0-abc0-4811-a720-6d1bcc20c043
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059125702 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.i2c_target_tx_stretch_ctrl.2059125702
Directory /workspace/5.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/6.i2c_alert_test.2339981367
Short name T959
Test name
Test status
Simulation time 93822069 ps
CPU time 0.65 seconds
Started Jul 03 05:25:41 PM PDT 24
Finished Jul 03 05:25:43 PM PDT 24
Peak memory 204464 kb
Host smart-642e4ea4-f238-4498-acad-0d77f9f837a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339981367 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_alert_test.2339981367
Directory /workspace/6.i2c_alert_test/latest

Test location /workspace/coverage/default/6.i2c_host_error_intr.1066293656
Short name T1193
Test name
Test status
Simulation time 420625850 ps
CPU time 2.5 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:25:41 PM PDT 24
Peak memory 213088 kb
Host smart-b76ddcbd-3c86-41e2-84f6-f001a8d6e39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066293656 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_error_intr.1066293656
Directory /workspace/6.i2c_host_error_intr/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_fmt_empty.23526775
Short name T1188
Test name
Test status
Simulation time 1007625477 ps
CPU time 13.11 seconds
Started Jul 03 05:25:23 PM PDT 24
Finished Jul 03 05:25:37 PM PDT 24
Peak memory 255784 kb
Host smart-586f8cc8-240b-4b47-99ff-2d8f14dfbb58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23526775 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empt
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_fmt_empty.23526775
Directory /workspace/6.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_full.2345883008
Short name T1013
Test name
Test status
Simulation time 1914830666 ps
CPU time 52.74 seconds
Started Jul 03 05:25:32 PM PDT 24
Finished Jul 03 05:26:25 PM PDT 24
Peak memory 632692 kb
Host smart-308c8585-c0b5-4280-b5cb-6120e7518ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345883008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_full.2345883008
Directory /workspace/6.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_overflow.3404885960
Short name T1502
Test name
Test status
Simulation time 20116958992 ps
CPU time 71.13 seconds
Started Jul 03 05:25:27 PM PDT 24
Finished Jul 03 05:26:38 PM PDT 24
Peak memory 741828 kb
Host smart-99dc618c-3d97-444c-b6f7-f799e413debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404885960 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_overflow.3404885960
Directory /workspace/6.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_fmt.763451035
Short name T400
Test name
Test status
Simulation time 188555340 ps
CPU time 1.02 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:41 PM PDT 24
Peak memory 204436 kb
Host smart-91d5446e-9188-4b94-8508-edf6bfdd7535
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763451035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_fmt
.763451035
Directory /workspace/6.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_reset_rx.2177728015
Short name T580
Test name
Test status
Simulation time 994584872 ps
CPU time 12.03 seconds
Started Jul 03 05:25:25 PM PDT 24
Finished Jul 03 05:25:38 PM PDT 24
Peak memory 204744 kb
Host smart-7c5c6c65-dc3c-4c2e-80fc-be6f25c11c9f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177728015 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_reset_rx.
2177728015
Directory /workspace/6.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/6.i2c_host_fifo_watermark.2696882383
Short name T1084
Test name
Test status
Simulation time 10202772227 ps
CPU time 359.94 seconds
Started Jul 03 05:25:29 PM PDT 24
Finished Jul 03 05:31:29 PM PDT 24
Peak memory 1369632 kb
Host smart-2777dbea-491d-4708-ad11-518584fd5178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696882383 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_fifo_watermark.2696882383
Directory /workspace/6.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/6.i2c_host_may_nack.1909745896
Short name T243
Test name
Test status
Simulation time 3967548860 ps
CPU time 20.18 seconds
Started Jul 03 05:25:41 PM PDT 24
Finished Jul 03 05:26:02 PM PDT 24
Peak memory 204904 kb
Host smart-e22c536f-35de-49e7-95d8-bb0292cdef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909745896 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_may_nack.1909745896
Directory /workspace/6.i2c_host_may_nack/latest

Test location /workspace/coverage/default/6.i2c_host_mode_toggle.2245668961
Short name T805
Test name
Test status
Simulation time 2479198519 ps
CPU time 26.33 seconds
Started Jul 03 05:25:47 PM PDT 24
Finished Jul 03 05:26:14 PM PDT 24
Peak memory 304544 kb
Host smart-c8dc6934-7419-46fb-89ac-1a84c04218d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245668961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_mode_toggle.2245668961
Directory /workspace/6.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/6.i2c_host_override.2304800427
Short name T333
Test name
Test status
Simulation time 48106823 ps
CPU time 0.66 seconds
Started Jul 03 05:25:26 PM PDT 24
Finished Jul 03 05:25:27 PM PDT 24
Peak memory 204576 kb
Host smart-807e5d76-ec4f-49b8-9392-b9c9b806cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304800427 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_override.2304800427
Directory /workspace/6.i2c_host_override/latest

Test location /workspace/coverage/default/6.i2c_host_perf.3952960472
Short name T942
Test name
Test status
Simulation time 29100076742 ps
CPU time 183.83 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:28:43 PM PDT 24
Peak memory 328976 kb
Host smart-3e85d04f-aa1a-4f4e-919e-6f97bc5b83d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952960472 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf.3952960472
Directory /workspace/6.i2c_host_perf/latest

Test location /workspace/coverage/default/6.i2c_host_perf_precise.2998752927
Short name T909
Test name
Test status
Simulation time 122108127 ps
CPU time 1.71 seconds
Started Jul 03 05:25:28 PM PDT 24
Finished Jul 03 05:25:30 PM PDT 24
Peak memory 212800 kb
Host smart-4007bbd6-45e2-42ae-8a0b-439831a5e2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998752927 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_perf_precise.2998752927
Directory /workspace/6.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/6.i2c_host_smoke.653360310
Short name T575
Test name
Test status
Simulation time 1582036652 ps
CPU time 68.78 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:26:48 PM PDT 24
Peak memory 294192 kb
Host smart-8250f3db-fb59-49fa-b936-7a27caac9b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653360310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_smoke.653360310
Directory /workspace/6.i2c_host_smoke/latest

Test location /workspace/coverage/default/6.i2c_host_stress_all.1626834288
Short name T1098
Test name
Test status
Simulation time 15123781168 ps
CPU time 226.68 seconds
Started Jul 03 05:25:24 PM PDT 24
Finished Jul 03 05:29:11 PM PDT 24
Peak memory 1615780 kb
Host smart-34288464-e288-4995-a11b-1459cb564d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626834288 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stress_all.1626834288
Directory /workspace/6.i2c_host_stress_all/latest

Test location /workspace/coverage/default/6.i2c_host_stretch_timeout.1133476145
Short name T340
Test name
Test status
Simulation time 1180449176 ps
CPU time 13.18 seconds
Started Jul 03 05:25:34 PM PDT 24
Finished Jul 03 05:25:48 PM PDT 24
Peak memory 221144 kb
Host smart-b3ff869a-66f3-4d28-8bb3-38a99a5410a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133476145 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_host_stretch_timeout.1133476145
Directory /workspace/6.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_bad_addr.1677413371
Short name T586
Test name
Test status
Simulation time 590362445 ps
CPU time 3.11 seconds
Started Jul 03 05:25:32 PM PDT 24
Finished Jul 03 05:25:35 PM PDT 24
Peak memory 204792 kb
Host smart-9ceac75c-96b9-424b-8efb-f444a40f3de3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677413371 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.i2c_target_bad_addr.1677413371
Directory /workspace/6.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_acq.1508918683
Short name T346
Test name
Test status
Simulation time 477842365 ps
CPU time 1.19 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:41 PM PDT 24
Peak memory 204784 kb
Host smart-c5385091-5066-41fb-bbdc-3abbcefe630c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508918683 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_fifo_reset_acq.1508918683
Directory /workspace/6.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_reset_tx.4070933991
Short name T790
Test name
Test status
Simulation time 144633974 ps
CPU time 1.02 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:25:41 PM PDT 24
Peak memory 204664 kb
Host smart-74e523be-241b-497d-8d3d-77d513a82ead
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070933991 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.i2c_target_fifo_reset_tx.4070933991
Directory /workspace/6.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_acq.2425256100
Short name T1444
Test name
Test status
Simulation time 401204330 ps
CPU time 2.27 seconds
Started Jul 03 05:25:34 PM PDT 24
Finished Jul 03 05:25:36 PM PDT 24
Peak memory 204864 kb
Host smart-44ffd6fb-ff01-413a-a5ed-8bcc04add76b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425256100 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.i2c_target_fifo_watermarks_acq.2425256100
Directory /workspace/6.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/6.i2c_target_fifo_watermarks_tx.2654638929
Short name T831
Test name
Test status
Simulation time 82064454 ps
CPU time 0.93 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:25:38 PM PDT 24
Peak memory 204600 kb
Host smart-cc2f728a-c536-4690-9f7e-6a0df0b634e9
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654638929 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 6.i2c_target_fifo_watermarks_tx.2654638929
Directory /workspace/6.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/6.i2c_target_hrst.1202260499
Short name T1155
Test name
Test status
Simulation time 300551337 ps
CPU time 3.54 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:25:42 PM PDT 24
Peak memory 204772 kb
Host smart-c3187cce-97f9-4768-938e-0a56b7f2a478
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202260499 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 6.i2c_target_hrst.1202260499
Directory /workspace/6.i2c_target_hrst/latest

Test location /workspace/coverage/default/6.i2c_target_intr_smoke.1847251212
Short name T1112
Test name
Test status
Simulation time 1469287577 ps
CPU time 7.3 seconds
Started Jul 03 05:25:32 PM PDT 24
Finished Jul 03 05:25:40 PM PDT 24
Peak memory 213524 kb
Host smart-01e71ea2-fefa-4a2b-946a-54823c41aaf7
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847251212 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.i2c_target_intr_smoke.1847251212
Directory /workspace/6.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_intr_stress_wr.4162138172
Short name T584
Test name
Test status
Simulation time 19907235192 ps
CPU time 331.54 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:31:11 PM PDT 24
Peak memory 3303668 kb
Host smart-2fe1e818-ff1f-44ac-aac9-88486acb87de
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162138172 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.i2c_target_intr_stress_wr.4162138172
Directory /workspace/6.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_smoke.2174359350
Short name T990
Test name
Test status
Simulation time 654497824 ps
CPU time 21.67 seconds
Started Jul 03 05:25:27 PM PDT 24
Finished Jul 03 05:25:49 PM PDT 24
Peak memory 204796 kb
Host smart-3a010982-949d-4266-abeb-635b19d7262c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174359350 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_tar
get_smoke.2174359350
Directory /workspace/6.i2c_target_smoke/latest

Test location /workspace/coverage/default/6.i2c_target_stress_rd.2763599203
Short name T1080
Test name
Test status
Simulation time 4995860885 ps
CPU time 6.71 seconds
Started Jul 03 05:25:46 PM PDT 24
Finished Jul 03 05:25:53 PM PDT 24
Peak memory 204980 kb
Host smart-38013506-4d62-478b-aba8-3f17802e84b0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763599203 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_rd.2763599203
Directory /workspace/6.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/6.i2c_target_stress_wr.1262951600
Short name T1258
Test name
Test status
Simulation time 42227688981 ps
CPU time 624.91 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:36:02 PM PDT 24
Peak memory 5355024 kb
Host smart-ee6c3211-ddf7-463f-b0e9-96df5dce9283
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262951600 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c
_target_stress_wr.1262951600
Directory /workspace/6.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/6.i2c_target_stretch.739177981
Short name T897
Test name
Test status
Simulation time 24800248032 ps
CPU time 1152.13 seconds
Started Jul 03 05:25:34 PM PDT 24
Finished Jul 03 05:44:47 PM PDT 24
Peak memory 2882088 kb
Host smart-e891b454-a5cb-4c40-a503-7e24afee1090
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739177981 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.i2c_ta
rget_stretch.739177981
Directory /workspace/6.i2c_target_stretch/latest

Test location /workspace/coverage/default/6.i2c_target_timeout.3385947837
Short name T72
Test name
Test status
Simulation time 5007091314 ps
CPU time 7.83 seconds
Started Jul 03 05:25:32 PM PDT 24
Finished Jul 03 05:25:40 PM PDT 24
Peak memory 219432 kb
Host smart-c6075f8f-b08d-48f5-ac67-0dcf2b2e4893
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385947837 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.i2c_target_timeout.3385947837
Directory /workspace/6.i2c_target_timeout/latest

Test location /workspace/coverage/default/6.i2c_target_tx_stretch_ctrl.365397201
Short name T19
Test name
Test status
Simulation time 242611258 ps
CPU time 3.39 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:43 PM PDT 24
Peak memory 204828 kb
Host smart-4ba88f7a-4a38-4b6b-b996-f46f36fd3860
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365397201 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.i2c_target_tx_stretch_ctrl.365397201
Directory /workspace/6.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/7.i2c_alert_test.1470097993
Short name T115
Test name
Test status
Simulation time 15891690 ps
CPU time 0.65 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:25:42 PM PDT 24
Peak memory 204404 kb
Host smart-1277702b-a0eb-4ef5-bfc1-e3702a48cd58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470097993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_alert_test.1470097993
Directory /workspace/7.i2c_alert_test/latest

Test location /workspace/coverage/default/7.i2c_host_error_intr.2479214557
Short name T1364
Test name
Test status
Simulation time 1287854749 ps
CPU time 2.2 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 213104 kb
Host smart-14ba9419-364a-4fcf-8150-57b971e9c0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479214557 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_error_intr.2479214557
Directory /workspace/7.i2c_host_error_intr/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_fmt_empty.174559762
Short name T537
Test name
Test status
Simulation time 1420848444 ps
CPU time 6.67 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:25:47 PM PDT 24
Peak memory 282616 kb
Host smart-bdee5e3c-123e-4317-a64e-fd27bba856c6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174559762 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_emp
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_fmt_empty
.174559762
Directory /workspace/7.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_full.398075101
Short name T1116
Test name
Test status
Simulation time 25573051982 ps
CPU time 82.42 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:27:00 PM PDT 24
Peak memory 739892 kb
Host smart-fcea25c5-de10-4a0d-afd9-04407ab27f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398075101 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_full.398075101
Directory /workspace/7.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_overflow.3277423008
Short name T757
Test name
Test status
Simulation time 1953218636 ps
CPU time 50.62 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:26:42 PM PDT 24
Peak memory 448572 kb
Host smart-a508499a-66cf-4a17-9a7a-b96eb0c34e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277423008 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_overflow.3277423008
Directory /workspace/7.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_fmt.616418310
Short name T555
Test name
Test status
Simulation time 110148285 ps
CPU time 0.88 seconds
Started Jul 03 05:25:54 PM PDT 24
Finished Jul 03 05:25:55 PM PDT 24
Peak memory 204484 kb
Host smart-521f982f-0f78-42eb-a123-0395fe809168
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616418310 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_fmt
.616418310
Directory /workspace/7.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_reset_rx.343335524
Short name T439
Test name
Test status
Simulation time 879271534 ps
CPU time 4.61 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 204796 kb
Host smart-cb037e08-96ff-4879-92d3-5162c2bba98b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343335524 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_reset_rx.343335524
Directory /workspace/7.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/7.i2c_host_fifo_watermark.3645190240
Short name T1307
Test name
Test status
Simulation time 7625789877 ps
CPU time 127.05 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:27:46 PM PDT 24
Peak memory 1250044 kb
Host smart-ea40b509-2248-4f34-925a-6e75b78d26ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645190240 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_fifo_watermark.3645190240
Directory /workspace/7.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/7.i2c_host_may_nack.3535376657
Short name T1132
Test name
Test status
Simulation time 371608475 ps
CPU time 13.62 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:53 PM PDT 24
Peak memory 204852 kb
Host smart-e115256f-fc81-42d6-a370-10a41a653d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535376657 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_may_nack.3535376657
Directory /workspace/7.i2c_host_may_nack/latest

Test location /workspace/coverage/default/7.i2c_host_mode_toggle.121872225
Short name T1476
Test name
Test status
Simulation time 8020606716 ps
CPU time 28.58 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:26:09 PM PDT 24
Peak memory 314864 kb
Host smart-768037e6-a9e7-44b4-8970-9ac5a6f54487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121872225 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_mode_toggle.121872225
Directory /workspace/7.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/7.i2c_host_override.1561953274
Short name T1077
Test name
Test status
Simulation time 136901236 ps
CPU time 0.69 seconds
Started Jul 03 05:25:33 PM PDT 24
Finished Jul 03 05:25:34 PM PDT 24
Peak memory 204556 kb
Host smart-c4ac8f74-abeb-410e-b801-853c963b43ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561953274 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_override.1561953274
Directory /workspace/7.i2c_host_override/latest

Test location /workspace/coverage/default/7.i2c_host_perf.1052379993
Short name T1252
Test name
Test status
Simulation time 50193774787 ps
CPU time 1200.15 seconds
Started Jul 03 05:25:47 PM PDT 24
Finished Jul 03 05:45:48 PM PDT 24
Peak memory 2118068 kb
Host smart-cf95262b-40fc-42fa-91ee-a6bcff2121e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052379993 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf.1052379993
Directory /workspace/7.i2c_host_perf/latest

Test location /workspace/coverage/default/7.i2c_host_perf_precise.309078628
Short name T1036
Test name
Test status
Simulation time 226611774 ps
CPU time 2.63 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:45 PM PDT 24
Peak memory 229208 kb
Host smart-066c04ca-0b31-4a3a-9a4e-e1eec085a49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309078628 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_perf_precise.309078628
Directory /workspace/7.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/7.i2c_host_smoke.203628651
Short name T1195
Test name
Test status
Simulation time 9824244178 ps
CPU time 48.82 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:26:26 PM PDT 24
Peak memory 269896 kb
Host smart-57fe451e-5d16-4b8e-aee3-679db150621e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203628651 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_smoke.203628651
Directory /workspace/7.i2c_host_smoke/latest

Test location /workspace/coverage/default/7.i2c_host_stress_all.769268553
Short name T881
Test name
Test status
Simulation time 14884196363 ps
CPU time 2259.27 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 06:03:23 PM PDT 24
Peak memory 3276696 kb
Host smart-0b14aadb-b189-4ca0-a108-21a62fea56ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769268553 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stress_all.769268553
Directory /workspace/7.i2c_host_stress_all/latest

Test location /workspace/coverage/default/7.i2c_host_stretch_timeout.1251803273
Short name T118
Test name
Test status
Simulation time 2386642379 ps
CPU time 26.56 seconds
Started Jul 03 05:25:35 PM PDT 24
Finished Jul 03 05:26:02 PM PDT 24
Peak memory 213056 kb
Host smart-5009c473-6f6d-4f79-96ea-387d20302f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251803273 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_host_stretch_timeout.1251803273
Directory /workspace/7.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_bad_addr.3937158899
Short name T361
Test name
Test status
Simulation time 715313589 ps
CPU time 3.73 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 204828 kb
Host smart-c244b6cc-62ac-44e9-bdd1-b2b920f7f78b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937158899 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.i2c_target_bad_addr.3937158899
Directory /workspace/7.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_acq.904552523
Short name T591
Test name
Test status
Simulation time 120819568 ps
CPU time 0.83 seconds
Started Jul 03 05:25:41 PM PDT 24
Finished Jul 03 05:25:43 PM PDT 24
Peak memory 204632 kb
Host smart-2546a99c-200e-4a52-8dec-ef624c77ad41
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904552523 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_acq.904552523
Directory /workspace/7.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_reset_tx.3044458056
Short name T1040
Test name
Test status
Simulation time 1141929480 ps
CPU time 1.1 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 204824 kb
Host smart-929b52dd-bf3a-4d92-b611-c4072a6022ee
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044458056 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.i2c_target_fifo_reset_tx.3044458056
Directory /workspace/7.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_acq.2355227754
Short name T1072
Test name
Test status
Simulation time 2041999912 ps
CPU time 2.52 seconds
Started Jul 03 05:25:48 PM PDT 24
Finished Jul 03 05:25:51 PM PDT 24
Peak memory 204824 kb
Host smart-2ee6dfbd-b48a-447a-b8a9-ba8675421b4d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355227754 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.i2c_target_fifo_watermarks_acq.2355227754
Directory /workspace/7.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/7.i2c_target_fifo_watermarks_tx.4253491838
Short name T298
Test name
Test status
Simulation time 709559643 ps
CPU time 0.99 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:25:38 PM PDT 24
Peak memory 204620 kb
Host smart-4af339eb-6470-4653-8a55-4d8209b7f5a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253491838 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.i2c_target_fifo_watermarks_tx.4253491838
Directory /workspace/7.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/7.i2c_target_hrst.2401072950
Short name T800
Test name
Test status
Simulation time 1379513964 ps
CPU time 3.18 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:25:47 PM PDT 24
Peak memory 204812 kb
Host smart-aa9db509-f368-42bf-ae21-6056c44ec588
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401072950 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 7.i2c_target_hrst.2401072950
Directory /workspace/7.i2c_target_hrst/latest

Test location /workspace/coverage/default/7.i2c_target_intr_smoke.3474552797
Short name T1008
Test name
Test status
Simulation time 881993722 ps
CPU time 4.96 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 204880 kb
Host smart-d1e2ff7b-1a25-468b-b2cb-c4325e93c612
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474552797 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.i2c_target_intr_smoke.3474552797
Directory /workspace/7.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_intr_stress_wr.2255658505
Short name T614
Test name
Test status
Simulation time 3386234887 ps
CPU time 3.26 seconds
Started Jul 03 05:25:31 PM PDT 24
Finished Jul 03 05:25:34 PM PDT 24
Peak memory 204896 kb
Host smart-5084819e-aeff-46d9-a61b-64c9778a7fc1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255658505 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.i2c_target_intr_stress_wr.2255658505
Directory /workspace/7.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_smoke.3543739036
Short name T1033
Test name
Test status
Simulation time 707865322 ps
CPU time 25.17 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:26:06 PM PDT 24
Peak memory 204776 kb
Host smart-c767fffb-8c96-4bb1-b766-4d7bda27276c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543739036 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_tar
get_smoke.3543739036
Directory /workspace/7.i2c_target_smoke/latest

Test location /workspace/coverage/default/7.i2c_target_stress_rd.910697319
Short name T1137
Test name
Test status
Simulation time 1244789404 ps
CPU time 49.96 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:26:28 PM PDT 24
Peak memory 205256 kb
Host smart-5a4b6f4c-976f-48d8-bd8f-effb89dadad2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910697319 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_rd.910697319
Directory /workspace/7.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/7.i2c_target_stress_wr.213430027
Short name T953
Test name
Test status
Simulation time 30497938137 ps
CPU time 79.01 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:26:59 PM PDT 24
Peak memory 1285780 kb
Host smart-5c19895a-021a-4f60-9944-e7f4c1571e1c
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213430027 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_
target_stress_wr.213430027
Directory /workspace/7.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/7.i2c_target_stretch.2875049934
Short name T1429
Test name
Test status
Simulation time 15318010309 ps
CPU time 481.67 seconds
Started Jul 03 05:25:33 PM PDT 24
Finished Jul 03 05:33:35 PM PDT 24
Peak memory 3269436 kb
Host smart-05344104-f0e3-4df4-b751-a2c3448fe3ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875049934 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.i2c_t
arget_stretch.2875049934
Directory /workspace/7.i2c_target_stretch/latest

Test location /workspace/coverage/default/7.i2c_target_timeout.3566444029
Short name T775
Test name
Test status
Simulation time 5681417057 ps
CPU time 6.72 seconds
Started Jul 03 05:25:36 PM PDT 24
Finished Jul 03 05:25:43 PM PDT 24
Peak memory 213428 kb
Host smart-c0378300-60bc-4843-b08c-ae7cba460607
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566444029 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.i2c_target_timeout.3566444029
Directory /workspace/7.i2c_target_timeout/latest

Test location /workspace/coverage/default/7.i2c_target_tx_stretch_ctrl.810961470
Short name T90
Test name
Test status
Simulation time 285631507 ps
CPU time 4.05 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:43 PM PDT 24
Peak memory 204824 kb
Host smart-78340e04-25f7-4ac4-b70d-1674b22b79ed
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810961470 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.i2c_target_tx_stretch_ctrl.810961470
Directory /workspace/7.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/8.i2c_alert_test.3104167579
Short name T1483
Test name
Test status
Simulation time 21411481 ps
CPU time 0.65 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:25:42 PM PDT 24
Peak memory 204508 kb
Host smart-f54ee806-e9fd-4466-90fb-aae8ee141528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104167579 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_alert_test.3104167579
Directory /workspace/8.i2c_alert_test/latest

Test location /workspace/coverage/default/8.i2c_host_error_intr.3206659249
Short name T581
Test name
Test status
Simulation time 144537933 ps
CPU time 2.05 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:25:41 PM PDT 24
Peak memory 213076 kb
Host smart-c95f4095-0087-412f-b77c-f5d6358d0e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206659249 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_error_intr.3206659249
Directory /workspace/8.i2c_host_error_intr/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_fmt_empty.2933812275
Short name T1302
Test name
Test status
Simulation time 1811527371 ps
CPU time 7.53 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 277736 kb
Host smart-84a20f7e-ca7d-43e5-bd9e-4ed93b9671f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933812275 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_fmt_empt
y.2933812275
Directory /workspace/8.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_full.281128664
Short name T1395
Test name
Test status
Simulation time 17052506675 ps
CPU time 49.58 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:26:31 PM PDT 24
Peak memory 632916 kb
Host smart-5a816883-88d0-44c7-9a51-24c118029948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281128664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_full.281128664
Directory /workspace/8.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_overflow.791813065
Short name T994
Test name
Test status
Simulation time 9813811412 ps
CPU time 67.08 seconds
Started Jul 03 05:25:48 PM PDT 24
Finished Jul 03 05:26:55 PM PDT 24
Peak memory 746044 kb
Host smart-fbaf141e-4e66-4361-ada1-8356d4f1714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791813065 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_overflow.791813065
Directory /workspace/8.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_fmt.514046958
Short name T393
Test name
Test status
Simulation time 527978228 ps
CPU time 1.09 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:25:40 PM PDT 24
Peak memory 204440 kb
Host smart-4f329a1b-7b97-4aed-a747-f935c4dcc1e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514046958 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_fmt
.514046958
Directory /workspace/8.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_reset_rx.382775530
Short name T1236
Test name
Test status
Simulation time 149955942 ps
CPU time 3.46 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 204840 kb
Host smart-68b53c42-54df-4f42-8086-5541b858631a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382775530 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_r
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_reset_rx.382775530
Directory /workspace/8.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/8.i2c_host_fifo_watermark.259614211
Short name T868
Test name
Test status
Simulation time 3057846809 ps
CPU time 64.93 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:26:46 PM PDT 24
Peak memory 926276 kb
Host smart-ad7e0d38-1a26-43ea-a384-79d5563c0f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259614211 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_fifo_watermark.259614211
Directory /workspace/8.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/8.i2c_host_may_nack.224933092
Short name T746
Test name
Test status
Simulation time 1137148067 ps
CPU time 6.8 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:25:50 PM PDT 24
Peak memory 204832 kb
Host smart-55b25618-4b05-4a15-b596-ffff329646e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224933092 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_may_nack.224933092
Directory /workspace/8.i2c_host_may_nack/latest

Test location /workspace/coverage/default/8.i2c_host_mode_toggle.4259601529
Short name T1457
Test name
Test status
Simulation time 11423543144 ps
CPU time 18.65 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:26:00 PM PDT 24
Peak memory 295524 kb
Host smart-8a986ba3-277a-4753-867a-266f95d93837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259601529 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_mode_toggle.4259601529
Directory /workspace/8.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/8.i2c_host_override.4012560888
Short name T1300
Test name
Test status
Simulation time 42555608 ps
CPU time 0.62 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 204584 kb
Host smart-c99a0d1c-6ad9-438b-b5e3-45a691e6d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012560888 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_override.4012560888
Directory /workspace/8.i2c_host_override/latest

Test location /workspace/coverage/default/8.i2c_host_perf.1264212745
Short name T339
Test name
Test status
Simulation time 1236598199 ps
CPU time 9.8 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:25:48 PM PDT 24
Peak memory 325148 kb
Host smart-f4ac96c1-f3ee-462d-a68d-7ff08204c5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264212745 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf.1264212745
Directory /workspace/8.i2c_host_perf/latest

Test location /workspace/coverage/default/8.i2c_host_perf_precise.163520938
Short name T752
Test name
Test status
Simulation time 278872922 ps
CPU time 0.88 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:25:45 PM PDT 24
Peak memory 204740 kb
Host smart-56982d1e-e44d-4b27-902a-f80d4e037ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163520938 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_perf_precise.163520938
Directory /workspace/8.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/8.i2c_host_smoke.443404700
Short name T548
Test name
Test status
Simulation time 1159979455 ps
CPU time 18.13 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:26:12 PM PDT 24
Peak memory 291388 kb
Host smart-07383063-605a-49fb-9c26-dcef8204a22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443404700 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_smoke.443404700
Directory /workspace/8.i2c_host_smoke/latest

Test location /workspace/coverage/default/8.i2c_host_stress_all.1430269853
Short name T1056
Test name
Test status
Simulation time 100221929566 ps
CPU time 3104.31 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 06:17:39 PM PDT 24
Peak memory 4244932 kb
Host smart-3f312f5f-4fe8-4e91-9ebc-70689f701546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430269853 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stress_all.1430269853
Directory /workspace/8.i2c_host_stress_all/latest

Test location /workspace/coverage/default/8.i2c_host_stretch_timeout.1094446089
Short name T1141
Test name
Test status
Simulation time 770734506 ps
CPU time 35.01 seconds
Started Jul 03 05:25:41 PM PDT 24
Finished Jul 03 05:26:17 PM PDT 24
Peak memory 213060 kb
Host smart-185e6f9e-f891-4aed-a17e-1241ddbceaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094446089 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_host_stretch_timeout.1094446089
Directory /workspace/8.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_bad_addr.2149805791
Short name T158
Test name
Test status
Simulation time 2923295896 ps
CPU time 4.1 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:25:49 PM PDT 24
Peak memory 205792 kb
Host smart-e976dc37-d218-46c5-bbd3-d7dcb4bdfe87
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149805791 -assert nopostproc +
UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.i2c_target_bad_addr.2149805791
Directory /workspace/8.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_acq.3707526730
Short name T704
Test name
Test status
Simulation time 232713055 ps
CPU time 1.06 seconds
Started Jul 03 05:25:41 PM PDT 24
Finished Jul 03 05:25:43 PM PDT 24
Peak memory 212896 kb
Host smart-379b3b92-224d-4146-9572-b92ce1370eb4
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707526730 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_fifo_reset_acq.3707526730
Directory /workspace/8.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_reset_tx.2362286126
Short name T713
Test name
Test status
Simulation time 198918195 ps
CPU time 1.31 seconds
Started Jul 03 05:25:41 PM PDT 24
Finished Jul 03 05:25:43 PM PDT 24
Peak memory 204692 kb
Host smart-9260a223-7d7f-45ac-bd69-45b5490ed095
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362286126 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.i2c_target_fifo_reset_tx.2362286126
Directory /workspace/8.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_acq.981567859
Short name T1478
Test name
Test status
Simulation time 1040627954 ps
CPU time 2.66 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:25:57 PM PDT 24
Peak memory 204852 kb
Host smart-e4a6b967-903a-42cb-b5b9-6a0f75306564
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981567859 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.i2c_target_fifo_watermarks_acq.981567859
Directory /workspace/8.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/8.i2c_target_fifo_watermarks_tx.432600648
Short name T718
Test name
Test status
Simulation time 363594736 ps
CPU time 1.03 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:25:54 PM PDT 24
Peak memory 204608 kb
Host smart-b25287d1-71ad-4a04-b99c-9e6beb37d0dd
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432600648 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.i2c_target_fifo_watermarks_tx.432600648
Directory /workspace/8.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/8.i2c_target_hrst.2538110768
Short name T890
Test name
Test status
Simulation time 271092011 ps
CPU time 3.18 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:25:48 PM PDT 24
Peak memory 204856 kb
Host smart-38f5ba34-b7c0-4cde-8160-fcdd9d9920ea
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538110768 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 8.i2c_target_hrst.2538110768
Directory /workspace/8.i2c_target_hrst/latest

Test location /workspace/coverage/default/8.i2c_target_intr_smoke.3963332509
Short name T1459
Test name
Test status
Simulation time 812112461 ps
CPU time 5.03 seconds
Started Jul 03 05:25:47 PM PDT 24
Finished Jul 03 05:25:52 PM PDT 24
Peak memory 216308 kb
Host smart-bcd77ea8-d862-4407-a421-b19addac9916
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963332509 -assert nopostproc +UVM_TESTNAME=i2c_ba
se_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 8.i2c_target_intr_smoke.3963332509
Directory /workspace/8.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_intr_stress_wr.802249230
Short name T321
Test name
Test status
Simulation time 1736597443 ps
CPU time 5.33 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:45 PM PDT 24
Peak memory 348372 kb
Host smart-0dc0cc47-230a-4c24-acd0-b61d220eedd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802249230 -assert nopostproc +UVM_TEST
NAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.i2c_target_intr_stress_wr.802249230
Directory /workspace/8.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_smoke.2282137093
Short name T993
Test name
Test status
Simulation time 4000046425 ps
CPU time 14.86 seconds
Started Jul 03 05:25:48 PM PDT 24
Finished Jul 03 05:26:03 PM PDT 24
Peak memory 204828 kb
Host smart-4ef4b492-c660-4e2d-a136-3504d6d8a90b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282137093 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_tar
get_smoke.2282137093
Directory /workspace/8.i2c_target_smoke/latest

Test location /workspace/coverage/default/8.i2c_target_stress_rd.1689806791
Short name T633
Test name
Test status
Simulation time 1975073855 ps
CPU time 33.99 seconds
Started Jul 03 05:25:38 PM PDT 24
Finished Jul 03 05:26:12 PM PDT 24
Peak memory 204856 kb
Host smart-400a0b78-1261-40ae-b12f-9b93b8c6fea6
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689806791 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_rd.1689806791
Directory /workspace/8.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/8.i2c_target_stress_wr.1583088973
Short name T1367
Test name
Test status
Simulation time 51273469368 ps
CPU time 195.46 seconds
Started Jul 03 05:25:51 PM PDT 24
Finished Jul 03 05:29:07 PM PDT 24
Peak memory 2467796 kb
Host smart-fecd7660-6e90-42d8-bf34-938eac2e092a
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583088973 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c
_target_stress_wr.1583088973
Directory /workspace/8.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/8.i2c_target_stretch.2782324314
Short name T280
Test name
Test status
Simulation time 13596190444 ps
CPU time 200.69 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:28:58 PM PDT 24
Peak memory 1673944 kb
Host smart-c80ec6d4-efc0-4b7f-aecf-8072ab25862e
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782324314 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.i2c_t
arget_stretch.2782324314
Directory /workspace/8.i2c_target_stretch/latest

Test location /workspace/coverage/default/8.i2c_target_timeout.1609450022
Short name T1233
Test name
Test status
Simulation time 1234027991 ps
CPU time 6.58 seconds
Started Jul 03 05:25:39 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 213256 kb
Host smart-b2296235-e4a3-4c0d-9ff7-4c949cd25f55
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609450022 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.i2c_target_timeout.1609450022
Directory /workspace/8.i2c_target_timeout/latest

Test location /workspace/coverage/default/8.i2c_target_tx_stretch_ctrl.727266631
Short name T1303
Test name
Test status
Simulation time 88454319 ps
CPU time 1.91 seconds
Started Jul 03 05:25:58 PM PDT 24
Finished Jul 03 05:26:00 PM PDT 24
Peak memory 204840 kb
Host smart-e1033c1f-13c0-43c1-bddf-99472ab0777d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727266631 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.i2c_target_tx_stretch_ctrl.727266631
Directory /workspace/8.i2c_target_tx_stretch_ctrl/latest

Test location /workspace/coverage/default/9.i2c_alert_test.1196452062
Short name T292
Test name
Test status
Simulation time 15949356 ps
CPU time 0.62 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 204408 kb
Host smart-198472fd-22fa-4331-876a-b12ac9a6b5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196452062 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_alert_test.1196452062
Directory /workspace/9.i2c_alert_test/latest

Test location /workspace/coverage/default/9.i2c_host_error_intr.3494482770
Short name T1498
Test name
Test status
Simulation time 144893501 ps
CPU time 2.33 seconds
Started Jul 03 05:25:45 PM PDT 24
Finished Jul 03 05:25:48 PM PDT 24
Peak memory 213936 kb
Host smart-98020ebc-c8c0-4c86-82ae-3876380049f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494482770 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_error_intr.3494482770
Directory /workspace/9.i2c_host_error_intr/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_fmt_empty.3647975269
Short name T461
Test name
Test status
Simulation time 290580884 ps
CPU time 14.51 seconds
Started Jul 03 05:25:52 PM PDT 24
Finished Jul 03 05:26:07 PM PDT 24
Peak memory 262876 kb
Host smart-42469400-049d-47cd-822b-ec1e93c01b54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647975269 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_em
pty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_fmt_empt
y.3647975269
Directory /workspace/9.i2c_host_fifo_fmt_empty/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_full.2582120986
Short name T588
Test name
Test status
Simulation time 9219691963 ps
CPU time 158.79 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:28:23 PM PDT 24
Peak memory 676432 kb
Host smart-7032b7f0-fa1c-4681-a1f5-1fb984924212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582120986 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_full.2582120986
Directory /workspace/9.i2c_host_fifo_full/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_overflow.1457999011
Short name T668
Test name
Test status
Simulation time 2217793195 ps
CPU time 67.65 seconds
Started Jul 03 05:25:41 PM PDT 24
Finished Jul 03 05:26:49 PM PDT 24
Peak memory 756044 kb
Host smart-ee2b1083-0c02-44a3-a8f0-5841989ad8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457999011 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_overflow.1457999011
Directory /workspace/9.i2c_host_fifo_overflow/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_fmt.669986664
Short name T980
Test name
Test status
Simulation time 418928505 ps
CPU time 0.83 seconds
Started Jul 03 05:25:48 PM PDT 24
Finished Jul 03 05:25:49 PM PDT 24
Peak memory 204420 kb
Host smart-b2c68123-b413-43bf-97b6-9181e31840a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669986664 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_f
mt_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_fmt
.669986664
Directory /workspace/9.i2c_host_fifo_reset_fmt/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_reset_rx.3665753370
Short name T1001
Test name
Test status
Simulation time 259451077 ps
CPU time 3.85 seconds
Started Jul 03 05:25:46 PM PDT 24
Finished Jul 03 05:25:50 PM PDT 24
Peak memory 223748 kb
Host smart-827bb4ba-10b6-4889-bda7-ee51fffb5cd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665753370 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_
rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_reset_rx.
3665753370
Directory /workspace/9.i2c_host_fifo_reset_rx/latest

Test location /workspace/coverage/default/9.i2c_host_fifo_watermark.1699145035
Short name T1050
Test name
Test status
Simulation time 5284456674 ps
CPU time 158.53 seconds
Started Jul 03 05:25:46 PM PDT 24
Finished Jul 03 05:28:25 PM PDT 24
Peak memory 816860 kb
Host smart-12fe9bfd-6e1e-49c9-bd3f-02f254e12009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699145035 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_fifo_watermark.1699145035
Directory /workspace/9.i2c_host_fifo_watermark/latest

Test location /workspace/coverage/default/9.i2c_host_may_nack.3561145636
Short name T365
Test name
Test status
Simulation time 289663077 ps
CPU time 12.34 seconds
Started Jul 03 05:25:54 PM PDT 24
Finished Jul 03 05:26:07 PM PDT 24
Peak memory 204884 kb
Host smart-c72ddbad-d8bf-4714-8bda-e32b79d2c8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561145636 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_may_nack.3561145636
Directory /workspace/9.i2c_host_may_nack/latest

Test location /workspace/coverage/default/9.i2c_host_mode_toggle.31280007
Short name T1226
Test name
Test status
Simulation time 4211829187 ps
CPU time 95.15 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:27:18 PM PDT 24
Peak memory 357772 kb
Host smart-07b890c4-c173-4332-9f58-32e5125ce8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31280007 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_mode_toggle.31280007
Directory /workspace/9.i2c_host_mode_toggle/latest

Test location /workspace/coverage/default/9.i2c_host_override.354919687
Short name T1311
Test name
Test status
Simulation time 23776846 ps
CPU time 0.64 seconds
Started Jul 03 05:25:37 PM PDT 24
Finished Jul 03 05:25:39 PM PDT 24
Peak memory 204568 kb
Host smart-213f8f36-2c03-4e8e-8153-95c2e7895134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354919687 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_override.354919687
Directory /workspace/9.i2c_host_override/latest

Test location /workspace/coverage/default/9.i2c_host_perf.299390660
Short name T1231
Test name
Test status
Simulation time 27963310221 ps
CPU time 72.8 seconds
Started Jul 03 05:25:45 PM PDT 24
Finished Jul 03 05:26:58 PM PDT 24
Peak memory 228904 kb
Host smart-ead30ca3-1869-4e1a-9356-5783b5539f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299390660 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf.299390660
Directory /workspace/9.i2c_host_perf/latest

Test location /workspace/coverage/default/9.i2c_host_perf_precise.1513332859
Short name T539
Test name
Test status
Simulation time 79035911 ps
CPU time 1.22 seconds
Started Jul 03 05:25:57 PM PDT 24
Finished Jul 03 05:25:59 PM PDT 24
Peak memory 225156 kb
Host smart-e7733af3-2d63-4803-a0d5-1d226a82fb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513332859 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_perf_precise.1513332859
Directory /workspace/9.i2c_host_perf_precise/latest

Test location /workspace/coverage/default/9.i2c_host_smoke.2126591253
Short name T450
Test name
Test status
Simulation time 1268620484 ps
CPU time 21.52 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:26:07 PM PDT 24
Peak memory 340168 kb
Host smart-12dc6d75-346d-4789-b1eb-8dfaedca77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126591253 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_smoke.2126591253
Directory /workspace/9.i2c_host_smoke/latest

Test location /workspace/coverage/default/9.i2c_host_stress_all.2408954440
Short name T271
Test name
Test status
Simulation time 70577061847 ps
CPU time 1046.39 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:43:08 PM PDT 24
Peak memory 3801500 kb
Host smart-bab34d37-cce4-4145-83c5-3494a56a2b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408954440 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stress_all.2408954440
Directory /workspace/9.i2c_host_stress_all/latest

Test location /workspace/coverage/default/9.i2c_host_stretch_timeout.361253671
Short name T1123
Test name
Test status
Simulation time 1530326450 ps
CPU time 6.97 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:25:52 PM PDT 24
Peak memory 213028 kb
Host smart-8bb826ae-67a6-45a4-845d-7a621f95503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361253671 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_host_stretch_timeout.361253671
Directory /workspace/9.i2c_host_stretch_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_bad_addr.531587323
Short name T793
Test name
Test status
Simulation time 4989131748 ps
CPU time 5.27 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:48 PM PDT 24
Peak memory 207784 kb
Host smart-44d99461-ae8b-4f93-9804-ca06664a4453
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=5 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531587323 -assert nopostproc +U
VM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.i2c_target_bad_addr.531587323
Directory /workspace/9.i2c_target_bad_addr/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_acq.2434361988
Short name T952
Test name
Test status
Simulation time 490989280 ps
CPU time 1.24 seconds
Started Jul 03 05:25:58 PM PDT 24
Finished Jul 03 05:26:00 PM PDT 24
Peak memory 204780 kb
Host smart-e30a68c2-6003-4b38-beec-533331ef9705
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434361988 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_fifo_reset_acq.2434361988
Directory /workspace/9.i2c_target_fifo_reset_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_reset_tx.616404547
Short name T505
Test name
Test status
Simulation time 133724907 ps
CPU time 1.04 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 204504 kb
Host smart-2ba0fc84-6e8e-40cb-bf7e-ec4c26fb3ac1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616404547 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.i2c_target_fifo_reset_tx.616404547
Directory /workspace/9.i2c_target_fifo_reset_tx/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_acq.2222589945
Short name T355
Test name
Test status
Simulation time 1002471664 ps
CPU time 2.5 seconds
Started Jul 03 05:25:56 PM PDT 24
Finished Jul 03 05:25:59 PM PDT 24
Peak memory 204812 kb
Host smart-a76e4f8d-b28d-4270-a32c-1f7f0b798b00
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222589945 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.i2c_target_fifo_watermarks_acq.2222589945
Directory /workspace/9.i2c_target_fifo_watermarks_acq/latest

Test location /workspace/coverage/default/9.i2c_target_fifo_watermarks_tx.586748565
Short name T1447
Test name
Test status
Simulation time 186676226 ps
CPU time 0.81 seconds
Started Jul 03 05:25:42 PM PDT 24
Finished Jul 03 05:25:44 PM PDT 24
Peak memory 204612 kb
Host smart-e3116111-318e-4057-8e7e-b9eee9fcce94
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586748565 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.i2c_target_fifo_watermarks_tx.586748565
Directory /workspace/9.i2c_target_fifo_watermarks_tx/latest

Test location /workspace/coverage/default/9.i2c_target_hrst.1817963188
Short name T275
Test name
Test status
Simulation time 844776363 ps
CPU time 4.32 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 204832 kb
Host smart-945bafe6-fb87-464e-9764-b01d5de0c66b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817963188 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_hrst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_hrst.1817963188
Directory /workspace/9.i2c_target_hrst/latest

Test location /workspace/coverage/default/9.i2c_target_intr_smoke.194917160
Short name T454
Test name
Test status
Simulation time 7813855750 ps
CPU time 7.48 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:25:53 PM PDT 24
Peak memory 223044 kb
Host smart-0b068985-bfdb-42a6-a1b0-e6a6190b68f5
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194917160 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null
-cm_name 9.i2c_target_intr_smoke.194917160
Directory /workspace/9.i2c_target_intr_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_intr_stress_wr.2848507907
Short name T1521
Test name
Test status
Simulation time 10921020528 ps
CPU time 23.7 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:26:09 PM PDT 24
Peak memory 582456 kb
Host smart-8dda8c9d-98b4-4226-9184-3d781f29e1a2
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848507907 -assert nopostproc +UVM_TES
TNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.i2c_target_intr_stress_wr.2848507907
Directory /workspace/9.i2c_target_intr_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_smoke.605714961
Short name T1295
Test name
Test status
Simulation time 2396352125 ps
CPU time 10.41 seconds
Started Jul 03 05:25:47 PM PDT 24
Finished Jul 03 05:25:58 PM PDT 24
Peak memory 204916 kb
Host smart-e08e1832-4351-400f-902e-54502e22607d
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605714961 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_targ
et_smoke.605714961
Directory /workspace/9.i2c_target_smoke/latest

Test location /workspace/coverage/default/9.i2c_target_stress_rd.2746442693
Short name T300
Test name
Test status
Simulation time 604758530 ps
CPU time 26.51 seconds
Started Jul 03 05:25:40 PM PDT 24
Finished Jul 03 05:26:08 PM PDT 24
Peak memory 204812 kb
Host smart-388c0559-b2b3-4e6d-baa7-d5bf314941c0
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746442693 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stress_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c
_target_stress_rd.2746442693
Directory /workspace/9.i2c_target_stress_rd/latest

Test location /workspace/coverage/default/9.i2c_target_stress_wr.695549837
Short name T1176
Test name
Test status
Simulation time 37305458972 ps
CPU time 7.23 seconds
Started Jul 03 05:25:43 PM PDT 24
Finished Jul 03 05:25:51 PM PDT 24
Peak memory 217704 kb
Host smart-ec7210cc-61f2-44ac-a850-4aa55815bdd1
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695549837 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ
=i2c_target_stress_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_
target_stress_wr.695549837
Directory /workspace/9.i2c_target_stress_wr/latest

Test location /workspace/coverage/default/9.i2c_target_stretch.1137066283
Short name T1242
Test name
Test status
Simulation time 23878047032 ps
CPU time 1300.63 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:47:35 PM PDT 24
Peak memory 5123476 kb
Host smart-c8b07369-e540-4028-a976-ef528814149b
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137066283 -assert nopostproc +UVM_TESTNAME=i2c_base_test +UVM_TEST_SE
Q=i2c_target_stretch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.i2c_t
arget_stretch.1137066283
Directory /workspace/9.i2c_target_stretch/latest

Test location /workspace/coverage/default/9.i2c_target_timeout.585630742
Short name T772
Test name
Test status
Simulation time 2279845893 ps
CPU time 6.58 seconds
Started Jul 03 05:25:44 PM PDT 24
Finished Jul 03 05:25:52 PM PDT 24
Peak memory 218180 kb
Host smart-64b50e94-6555-4653-85b0-2a127a4d7bfb
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585630742 -assert nopostproc +UVM_TESTNAME=i2c_base
_test +UVM_TEST_SEQ=i2c_target_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.i2c_target_timeout.585630742
Directory /workspace/9.i2c_target_timeout/latest

Test location /workspace/coverage/default/9.i2c_target_tx_stretch_ctrl.3376861313
Short name T1335
Test name
Test status
Simulation time 141626357 ps
CPU time 2.88 seconds
Started Jul 03 05:25:53 PM PDT 24
Finished Jul 03 05:25:56 PM PDT 24
Peak memory 204848 kb
Host smart-c68792da-6aad-49c2-bb9c-ac1c721903b3
User root
Command /workspace/default/simv +i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376861313 -assert nopostproc +UVM_TESTNAME=i2c_bas
e_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.i2c_target_tx_stretch_ctrl.3376861313
Directory /workspace/9.i2c_target_tx_stretch_ctrl/latest
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