Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	7	53	88.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	60	7	53	88.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	982435	1			T1	3		T2	6040		T3	3
all_values[1]	982435	1			T1	3		T2	6040		T3	3
all_values[2]	982435	1			T1	3		T2	6040		T3	3
all_values[3]	982435	1			T1	3		T2	6040		T3	3
all_values[4]	982435	1			T1	3		T2	6040		T3	3
all_values[5]	982435	1			T1	3		T2	6040		T3	3
all_values[6]	982435	1			T1	3		T2	6040		T3	3
all_values[7]	982435	1			T1	3		T2	6040		T3	3
all_values[8]	982435	1			T1	3		T2	6040		T3	3
all_values[9]	982435	1			T1	3		T2	6040		T3	3
all_values[10]	982435	1			T1	3		T2	6040		T3	3
all_values[11]	982435	1			T1	3		T2	6040		T3	3
all_values[12]	982435	1			T1	3		T2	6040		T3	3
all_values[13]	982435	1			T1	3		T2	6040		T3	3
all_values[14]	982435	1			T1	3		T2	6040		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12085089

1

T1

39

T2

72765

T3

40

auto[1]

2651436

1

T1

6

T2

17835

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13424873

1

T1

45

T2

90600

T3

45

auto[1]

1311652

1

T48

3329

T133

245

T50

170

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	7	53	88.33	7

Automatically Generated Cross Bins for intr_cg_cc

Uncovered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[3]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[5] , all_values[6]]	[auto[1]]	[auto[0]]	--	--	2
[all_values[8]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[10]]	[auto[1]]	[auto[0]]	0	1	1
[all_values[13] , all_values[14]]	[auto[1]]	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103698	1			T1	1		T2	345		T3	1
all_values[0]	auto[0]	auto[1]	7055	1			T48	17		T133	12		T50	1
all_values[0]	auto[1]	auto[0]	803106	1			T1	2		T2	5695		T3	2
all_values[0]	auto[1]	auto[1]	68576	1			T48	261		T133	4		T50	11
all_values[1]	auto[0]	auto[0]	907131	1			T1	3		T2	6038		T3	3
all_values[1]	auto[0]	auto[1]	74579	1			T133	10		T50	9		T42	18486
all_values[1]	auto[1]	auto[0]	433	1			T2	2		T36	15		T43	3
all_values[1]	auto[1]	auto[1]	292	1			T133	6		T50	2		T42	7
all_values[2]	auto[0]	auto[0]	892536	1			T1	3		T2	6040		T3	3
all_values[2]	auto[0]	auto[1]	89652	1			T48	275		T133	9		T50	6
all_values[2]	auto[1]	auto[0]	51	1			T7	1		T17	1		T232	1
all_values[2]	auto[1]	auto[1]	196	1			T48	3		T133	8		T50	2
all_values[3]	auto[0]	auto[0]	892666	1			T1	3		T2	6040		T3	3
all_values[3]	auto[0]	auto[1]	89555	1			T48	274		T133	8		T50	8
all_values[3]	auto[1]	auto[1]	214	1			T48	2		T133	8		T50	4
all_values[4]	auto[0]	auto[0]	892647	1			T1	3		T2	6040		T3	3
all_values[4]	auto[0]	auto[1]	89580	1			T48	275		T133	12		T50	7
all_values[4]	auto[1]	auto[0]	12	1			T61	1		T235	1		T236	1
all_values[4]	auto[1]	auto[1]	196	1			T48	1		T133	5		T50	3
all_values[5]	auto[0]	auto[0]	892581	1			T1	3		T2	6040		T3	3
all_values[5]	auto[0]	auto[1]	89608	1			T48	276		T133	13		T50	7
all_values[5]	auto[1]	auto[1]	246	1			T48	2		T133	4		T50	3
all_values[6]	auto[0]	auto[0]	895584	1			T1	3		T2	6040		T3	3
all_values[6]	auto[0]	auto[1]	86635	1			T48	276		T133	12		T50	10
all_values[6]	auto[1]	auto[1]	216	1			T133	5		T50	2		T42	5
all_values[7]	auto[0]	auto[0]	865561	1			T1	2		T2	5886		T3	3
all_values[7]	auto[0]	auto[1]	86991	1			T48	233		T133	7		T50	7
all_values[7]	auto[1]	auto[0]	26703	1			T1	1		T2	154		T34	9
all_values[7]	auto[1]	auto[1]	3180	1			T48	45		T133	10		T50	4
all_values[8]	auto[0]	auto[0]	892259	1			T1	3		T2	6040		T3	3
all_values[8]	auto[0]	auto[1]	89962	1			T48	276		T133	7		T50	11
all_values[8]	auto[1]	auto[1]	214	1			T48	2		T133	7		T50	1
all_values[9]	auto[0]	auto[0]	203352	1			T1	2		T2	87		T3	2
all_values[9]	auto[0]	auto[1]	11202	1			T133	9		T50	11		T42	1411
all_values[9]	auto[1]	auto[0]	689510	1			T1	1		T2	5953		T3	1
all_values[9]	auto[1]	auto[1]	78371	1			T133	8		T50	1		T42	17082
all_values[10]	auto[0]	auto[0]	892248	1			T1	3		T2	6040		T3	3
all_values[10]	auto[0]	auto[1]	89988	1			T48	276		T133	7		T50	8
all_values[10]	auto[1]	auto[1]	199	1			T48	1		T133	6		T50	4
all_values[11]	auto[0]	auto[0]	2846	1			T1	1		T2	9		T3	1
all_values[11]	auto[0]	auto[1]	552	1			T48	9		T133	12		T50	1
all_values[11]	auto[1]	auto[0]	889799	1			T1	2		T2	6031		T3	2
all_values[11]	auto[1]	auto[1]	89238	1			T48	269		T133	5		T50	11
all_values[12]	auto[0]	auto[0]	896077	1			T1	3		T2	6040		T3	3
all_values[12]	auto[0]	auto[1]	86131	1			T48	277		T133	10		T50	8
all_values[12]	auto[1]	auto[0]	12	1			T237	1		T238	1		T239	1
all_values[12]	auto[1]	auto[1]	215	1			T48	1		T133	7		T50	4
all_values[13]	auto[0]	auto[0]	892228	1			T1	3		T2	6040		T3	3
all_values[13]	auto[0]	auto[1]	89973	1			T48	277		T133	6		T50	10
all_values[13]	auto[1]	auto[1]	234	1			T48	1		T133	11		T50	2
all_values[14]	auto[0]	auto[0]	893833	1			T1	3		T2	6040		T3	3
all_values[14]	auto[0]	auto[1]	88379	1			T133	9		T50	8		T42	18484
all_values[14]	auto[1]	auto[1]	223	1			T133	8		T50	4		T42	9