Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	60	0	60	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	15	0	15	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	60	0	60	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	982435	1			T1	3		T2	6040		T3	3
all_pins[1]	982435	1			T1	3		T2	6040		T3	3
all_pins[2]	982435	1			T1	3		T2	6040		T3	3
all_pins[3]	982435	1			T1	3		T2	6040		T3	3
all_pins[4]	982435	1			T1	3		T2	6040		T3	3
all_pins[5]	982435	1			T1	3		T2	6040		T3	3
all_pins[6]	982435	1			T1	3		T2	6040		T3	3
all_pins[7]	982435	1			T1	3		T2	6040		T3	3
all_pins[8]	982435	1			T1	3		T2	6040		T3	3
all_pins[9]	982435	1			T1	3		T2	6040		T3	3
all_pins[10]	982435	1			T1	3		T2	6040		T3	3
all_pins[11]	982435	1			T1	3		T2	6040		T3	3
all_pins[12]	982435	1			T1	3		T2	6040		T3	3
all_pins[13]	982435	1			T1	3		T2	6040		T3	3
all_pins[14]	982435	1			T1	3		T2	6040		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	12090378	1			T1	39		T2	72750		T3	40
values[0x1]	2646147	1			T1	6		T2	17850		T3	5
transitions[0x0=>0x1]	2645126	1			T1	6		T2	17848		T3	5
transitions[0x1=>0x0]	2643930	1			T1	5		T2	17847		T3	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	113987	1			T1	1		T2	344		T3	1
all_pins[0]	values[0x1]	868448	1			T1	2		T2	5696		T3	2
all_pins[0]	transitions[0x0=>0x1]	867820	1			T1	2		T2	5694		T3	2
all_pins[0]	transitions[0x1=>0x0]	72	1			T133	1		T50	1		T42	2
all_pins[1]	values[0x0]	981735	1			T1	3		T2	6038		T3	3
all_pins[1]	values[0x1]	700	1			T2	2		T36	15		T43	3
all_pins[1]	transitions[0x0=>0x1]	673	1			T2	2		T36	15		T43	3
all_pins[1]	transitions[0x1=>0x0]	121	1			T7	1		T17	1		T48	2
all_pins[2]	values[0x0]	982287	1			T1	3		T2	6040		T3	3
all_pins[2]	values[0x1]	148	1			T7	1		T17	1		T48	2
all_pins[2]	transitions[0x0=>0x1]	132	1			T7	1		T17	1		T48	2
all_pins[2]	transitions[0x1=>0x0]	86	1			T48	2		T133	3		T42	1
all_pins[3]	values[0x0]	982333	1			T1	3		T2	6040		T3	3
all_pins[3]	values[0x1]	102	1			T48	2		T133	3		T50	1
all_pins[3]	transitions[0x0=>0x1]	82	1			T48	2		T133	3		T42	1
all_pins[3]	transitions[0x1=>0x0]	97	1			T133	3		T61	1		T50	1
all_pins[4]	values[0x0]	982318	1			T1	3		T2	6040		T3	3
all_pins[4]	values[0x1]	117	1			T133	3		T61	1		T50	2
all_pins[4]	transitions[0x0=>0x1]	93	1			T133	3		T61	1		T50	2
all_pins[4]	transitions[0x1=>0x0]	109	1			T133	2		T50	1		T42	1
all_pins[5]	values[0x0]	982302	1			T1	3		T2	6040		T3	3
all_pins[5]	values[0x1]	133	1			T133	2		T50	1		T42	3
all_pins[5]	transitions[0x0=>0x1]	102	1			T133	2		T50	1		T42	1
all_pins[5]	transitions[0x1=>0x0]	78	1			T133	4		T75	3		T74	2
all_pins[6]	values[0x0]	982326	1			T1	3		T2	6040		T3	3
all_pins[6]	values[0x1]	109	1			T133	4		T42	2		T75	3
all_pins[6]	transitions[0x0=>0x1]	66	1			T133	2		T42	2		T75	3
all_pins[6]	transitions[0x1=>0x0]	32724	1			T1	1		T2	168		T36	219
all_pins[7]	values[0x0]	949668	1			T1	2		T2	5872		T3	3
all_pins[7]	values[0x1]	32767	1			T1	1		T2	168		T36	219
all_pins[7]	transitions[0x0=>0x1]	32734	1			T1	1		T2	168		T36	219
all_pins[7]	transitions[0x1=>0x0]	70	1			T48	1		T75	2		T255	1
all_pins[8]	values[0x0]	982332	1			T1	3		T2	6040		T3	3
all_pins[8]	values[0x1]	103	1			T48	1		T133	1		T75	3
all_pins[8]	transitions[0x0=>0x1]	72	1			T48	1		T133	1		T75	2
all_pins[8]	transitions[0x1=>0x0]	767763	1			T1	1		T2	5953		T3	1
all_pins[9]	values[0x0]	214641	1			T1	2		T2	87		T3	2
all_pins[9]	values[0x1]	767794	1			T1	1		T2	5953		T3	1
all_pins[9]	transitions[0x0=>0x1]	767767	1			T1	1		T2	5953		T3	1
all_pins[9]	transitions[0x1=>0x0]	55	1			T48	1		T133	2		T50	2
all_pins[10]	values[0x0]	982353	1			T1	3		T2	6040		T3	3
all_pins[10]	values[0x1]	82	1			T48	1		T133	2		T50	2
all_pins[10]	transitions[0x0=>0x1]	59	1			T48	1		T133	2		T42	2
all_pins[10]	transitions[0x1=>0x0]	975292	1			T1	2		T2	6031		T3	2
all_pins[11]	values[0x0]	7120	1			T1	1		T2	9		T3	1
all_pins[11]	values[0x1]	975315	1			T1	2		T2	6031		T3	2
all_pins[11]	transitions[0x0=>0x1]	975268	1			T1	2		T2	6031		T3	2
all_pins[11]	transitions[0x1=>0x0]	65	1			T133	3		T50	2		T42	2
all_pins[12]	values[0x0]	982323	1			T1	3		T2	6040		T3	3
all_pins[12]	values[0x1]	112	1			T17	1		T133	4		T256	1
all_pins[12]	transitions[0x0=>0x1]	94	1			T17	1		T133	3		T256	1
all_pins[12]	transitions[0x1=>0x0]	84	1			T133	4		T42	1		T75	1
all_pins[13]	values[0x0]	982333	1			T1	3		T2	6040		T3	3
all_pins[13]	values[0x1]	102	1			T133	5		T50	2		T42	2
all_pins[13]	transitions[0x0=>0x1]	77	1			T133	2		T50	2		T42	1
all_pins[13]	transitions[0x1=>0x0]	90	1			T133	2		T50	2		T42	6
all_pins[14]	values[0x0]	982320	1			T1	3		T2	6040		T3	3
all_pins[14]	values[0x1]	115	1			T133	5		T50	2		T42	7
all_pins[14]	transitions[0x0=>0x1]	87	1			T133	4		T50	1		T42	6
all_pins[14]	transitions[0x1=>0x0]	867224	1			T1	1		T2	5695		T3	1