Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	0	21	100.00
Crosses	90	0	90	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	15	0	15	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=14}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	90	0	90	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	476	1			T48	4		T133	14		T50	7
all_values[1]	476	1			T48	4		T133	14		T50	7
all_values[2]	476	1			T48	4		T133	14		T50	7
all_values[3]	476	1			T48	4		T133	14		T50	7
all_values[4]	476	1			T48	4		T133	14		T50	7
all_values[5]	476	1			T48	4		T133	14		T50	7
all_values[6]	476	1			T48	4		T133	14		T50	7
all_values[7]	476	1			T48	4		T133	14		T50	7
all_values[8]	476	1			T48	4		T133	14		T50	7
all_values[9]	476	1			T48	4		T133	14		T50	7
all_values[10]	476	1			T48	4		T133	14		T50	7
all_values[11]	476	1			T48	4		T133	14		T50	7
all_values[12]	476	1			T48	4		T133	14		T50	7
all_values[13]	476	1			T48	4		T133	14		T50	7
all_values[14]	476	1			T48	4		T133	14		T50	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3767

1

T48

38

T133

111

T50

44

auto[1]

3373

1

T48

22

T133

99

T50

61

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T48

19

T133

10

T50

10

auto[1]

5987

1

T48

41

T133

200

T50

95

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4178

1

T48

41

T133

110

T50

60

auto[1]

2962

1

T48

19

T133

100

T50

45

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	90	0	90	100.00
Automatically Generated Cross Bins	90	0	90	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	54	1			T133	1		T255	4		T74	1
all_values[0]	auto[0]	auto[0]	auto[1]	123	1			T48	3		T133	2		T42	3
all_values[0]	auto[0]	auto[1]	auto[0]	29	1			T75	4		T74	1		T257	1
all_values[0]	auto[0]	auto[1]	auto[1]	92	1			T133	7		T50	2		T42	2
all_values[0]	auto[1]	auto[0]	auto[1]	89	1			T48	1		T133	3		T50	1
all_values[0]	auto[1]	auto[1]	auto[1]	89	1			T133	1		T50	4		T42	3
all_values[1]	auto[0]	auto[0]	auto[0]	43	1			T48	3		T133	1		T75	1
all_values[1]	auto[0]	auto[0]	auto[1]	96	1			T133	2		T50	3		T42	1
all_values[1]	auto[0]	auto[1]	auto[0]	35	1			T48	1		T50	1		T74	1
all_values[1]	auto[0]	auto[1]	auto[1]	94	1			T133	5		T50	1		T42	3
all_values[1]	auto[1]	auto[0]	auto[1]	109	1			T133	5		T50	1		T42	7
all_values[1]	auto[1]	auto[1]	auto[1]	99	1			T133	1		T50	1		T75	1
all_values[2]	auto[0]	auto[0]	auto[0]	34	1			T50	2		T75	1		T74	1
all_values[2]	auto[0]	auto[0]	auto[1]	111	1			T48	1		T133	3		T50	1
all_values[2]	auto[0]	auto[1]	auto[0]	36	1			T50	2		T74	3		T258	1
all_values[2]	auto[0]	auto[1]	auto[1]	99	1			T133	3		T42	4		T75	1
all_values[2]	auto[1]	auto[0]	auto[1]	102	1			T48	1		T133	5		T50	2
all_values[2]	auto[1]	auto[1]	auto[1]	94	1			T48	2		T133	3		T42	2
all_values[3]	auto[0]	auto[0]	auto[0]	57	1			T48	2		T133	1		T75	4
all_values[3]	auto[0]	auto[0]	auto[1]	99	1			T133	3		T50	3		T42	3
all_values[3]	auto[0]	auto[1]	auto[0]	29	1			T255	2		T107	1		T79	1
all_values[3]	auto[0]	auto[1]	auto[1]	104	1			T48	1		T133	3		T50	2
all_values[3]	auto[1]	auto[0]	auto[1]	99	1			T133	5		T42	3		T74	2
all_values[3]	auto[1]	auto[1]	auto[1]	88	1			T48	1		T133	2		T50	2
all_values[4]	auto[0]	auto[0]	auto[0]	55	1			T48	1		T75	4		T79	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T48	1		T133	2		T50	1
all_values[4]	auto[0]	auto[1]	auto[0]	27	1			T48	1		T50	2		T75	1
all_values[4]	auto[0]	auto[1]	auto[1]	111	1			T133	7		T50	1		T42	6
all_values[4]	auto[1]	auto[0]	auto[1]	103	1			T133	1		T50	2		T42	2
all_values[4]	auto[1]	auto[1]	auto[1]	93	1			T48	1		T133	4		T50	1
all_values[5]	auto[0]	auto[0]	auto[0]	45	1			T102	2		T259	1		T253	3
all_values[5]	auto[0]	auto[0]	auto[1]	95	1			T133	3		T50	1		T42	4
all_values[5]	auto[0]	auto[1]	auto[0]	31	1			T50	2		T255	1		T74	2
all_values[5]	auto[0]	auto[1]	auto[1]	108	1			T48	1		T133	3		T50	1
all_values[5]	auto[1]	auto[0]	auto[1]	109	1			T48	3		T133	5		T50	1
all_values[5]	auto[1]	auto[1]	auto[1]	88	1			T133	3		T50	2		T75	2
all_values[6]	auto[0]	auto[0]	auto[0]	41	1			T48	1		T42	1		T255	2
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T133	6		T50	1		T42	2
all_values[6]	auto[0]	auto[1]	auto[0]	46	1			T48	1		T42	1		T255	2
all_values[6]	auto[0]	auto[1]	auto[1]	118	1			T48	1		T133	3		T50	3
all_values[6]	auto[1]	auto[0]	auto[1]	100	1			T48	1		T133	3		T50	1
all_values[6]	auto[1]	auto[1]	auto[1]	83	1			T133	2		T50	2		T75	2
all_values[7]	auto[0]	auto[0]	auto[0]	48	1			T74	1		T260	1		T261	3
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T48	1		T133	1		T50	3
all_values[7]	auto[0]	auto[1]	auto[0]	36	1			T50	1		T255	1		T74	3
all_values[7]	auto[0]	auto[1]	auto[1]	113	1			T48	1		T133	4		T50	1
all_values[7]	auto[1]	auto[0]	auto[1]	100	1			T48	2		T133	5		T50	2
all_values[7]	auto[1]	auto[1]	auto[1]	97	1			T133	4		T42	2		T75	2
all_values[8]	auto[0]	auto[0]	auto[0]	54	1			T133	3		T103	1		T259	1
all_values[8]	auto[0]	auto[0]	auto[1]	102	1			T48	1		T133	1		T50	2
all_values[8]	auto[0]	auto[1]	auto[0]	34	1			T74	1		T102	1		T257	1
all_values[8]	auto[0]	auto[1]	auto[1]	94	1			T48	1		T133	2		T42	1
all_values[8]	auto[1]	auto[0]	auto[1]	98	1			T48	1		T133	6		T50	1
all_values[8]	auto[1]	auto[1]	auto[1]	94	1			T48	1		T133	2		T50	4
all_values[9]	auto[0]	auto[0]	auto[0]	41	1			T48	2		T107	1		T253	3
all_values[9]	auto[0]	auto[0]	auto[1]	88	1			T133	3		T50	1		T42	4
all_values[9]	auto[0]	auto[1]	auto[0]	34	1			T48	2		T107	1		T102	1
all_values[9]	auto[0]	auto[1]	auto[1]	102	1			T133	5		T50	5		T42	3
all_values[9]	auto[1]	auto[0]	auto[1]	111	1			T133	3		T42	2		T75	3
all_values[9]	auto[1]	auto[1]	auto[1]	100	1			T133	3		T50	1		T42	2
all_values[10]	auto[0]	auto[0]	auto[0]	45	1			T48	1		T133	3		T107	1
all_values[10]	auto[0]	auto[0]	auto[1]	102	1			T133	1		T50	3		T42	2
all_values[10]	auto[0]	auto[1]	auto[0]	27	1			T133	1		T74	1		T257	1
all_values[10]	auto[0]	auto[1]	auto[1]	103	1			T48	2		T133	3		T42	3
all_values[10]	auto[1]	auto[0]	auto[1]	127	1			T133	4		T50	2		T42	4
all_values[10]	auto[1]	auto[1]	auto[1]	72	1			T48	1		T133	2		T50	2
all_values[11]	auto[0]	auto[0]	auto[0]	44	1			T42	1		T75	1		T102	1
all_values[11]	auto[0]	auto[0]	auto[1]	109	1			T48	1		T133	4		T50	4
all_values[11]	auto[0]	auto[1]	auto[0]	25	1			T75	3		T74	1		T103	1
all_values[11]	auto[0]	auto[1]	auto[1]	100	1			T48	1		T133	5		T50	1
all_values[11]	auto[1]	auto[0]	auto[1]	109	1			T48	2		T133	2		T50	1
all_values[11]	auto[1]	auto[1]	auto[1]	89	1			T133	3		T50	1		T42	4
all_values[12]	auto[0]	auto[0]	auto[0]	31	1			T107	3		T102	2		T259	1
all_values[12]	auto[0]	auto[0]	auto[1]	108	1			T48	2		T133	5		T42	3
all_values[12]	auto[0]	auto[1]	auto[0]	29	1			T75	1		T74	1		T107	1
all_values[12]	auto[0]	auto[1]	auto[1]	93	1			T48	1		T133	2		T50	3
all_values[12]	auto[1]	auto[0]	auto[1]	122	1			T48	1		T133	3		T42	4
all_values[12]	auto[1]	auto[1]	auto[1]	93	1			T133	4		T50	4		T42	1
all_values[13]	auto[0]	auto[0]	auto[0]	32	1			T107	1		T262	1		T259	1
all_values[13]	auto[0]	auto[0]	auto[1]	110	1			T48	3		T133	3		T50	1
all_values[13]	auto[0]	auto[1]	auto[0]	29	1			T75	2		T258	1		T107	1
all_values[13]	auto[0]	auto[1]	auto[1]	101	1			T133	1		T50	2		T42	1
all_values[13]	auto[1]	auto[0]	auto[1]	113	1			T48	1		T133	6		T42	4
all_values[13]	auto[1]	auto[1]	auto[1]	91	1			T133	4		T50	4		T42	4
all_values[14]	auto[0]	auto[0]	auto[0]	50	1			T48	2		T74	2		T259	4
all_values[14]	auto[0]	auto[0]	auto[1]	92	1			T133	3		T50	2		T42	1
all_values[14]	auto[0]	auto[1]	auto[0]	32	1			T48	2		T74	2		T259	1
all_values[14]	auto[0]	auto[1]	auto[1]	101	1			T133	5		T50	2		T42	3
all_values[14]	auto[1]	auto[0]	auto[1]	110	1			T133	4		T50	2		T42	2
all_values[14]	auto[1]	auto[1]	auto[1]	91	1			T133	2		T50	1		T42	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal